TW201731058A - 電子封裝件及其半導體基板與製法 - Google Patents

電子封裝件及其半導體基板與製法 Download PDF

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Publication number
TW201731058A
TW201731058A TW105105411A TW105105411A TW201731058A TW 201731058 A TW201731058 A TW 201731058A TW 105105411 A TW105105411 A TW 105105411A TW 105105411 A TW105105411 A TW 105105411A TW 201731058 A TW201731058 A TW 201731058A
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semiconductor substrate
substrate
package
conductive
substrate body
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TW105105411A
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English (en)
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TWI601259B (zh
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賴杰隆
葉懋華
李宏元
彭仕良
呂長倫
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矽品精密工業股份有限公司
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Priority to TW105105411A priority Critical patent/TWI601259B/zh
Priority to CN201610132896.8A priority patent/CN107123631B/zh
Priority to US15/149,576 priority patent/US9831191B2/en
Publication of TW201731058A publication Critical patent/TW201731058A/zh
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Publication of TWI601259B publication Critical patent/TWI601259B/zh

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  • Laminated Bodies (AREA)

Abstract

一種半導體基板，係包括：基板本體、複數貫穿該基板本體之導電穿孔、以及形成於該基板本體中而未貫穿該基板本體之至少一柱體，以於該半導體基板受熱時，該柱體能調整該基板本體於上、下側的伸縮量，使該半導體基板上、下側的熱變形量相等，而避免該半導體基板發生翹曲。

Description

電子封裝件及其半導體基板與製法
本發明係有關一種半導體封裝製程，尤指一種能提高產品良率之電子封裝件及其半導體基板與製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。目前應用於晶片封裝領域之技術，例如晶片尺寸構裝(Chip Scale Package，簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached，簡稱DCA)或多晶片模組封裝(Multi-Chip Module，簡稱MCM)等覆晶型態的封裝模組、或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊技術等。
第1圖係為習知半導體封裝件1之剖面示意圖，該半導體封裝件1係於一封裝基板11與半導體晶片10之間設置一矽中介板(Through Silicon interposer，簡稱TSI)13，該矽中介板13具有導電矽穿孔(Through-silicon via，簡稱TSV)130及形成於該導電矽穿孔130上之線路重佈結構(Redistribution layer，簡稱RDL)131，令該導電矽穿孔 130藉由複數導電元件16電性結合間距較大之封裝基板11之銲墊110，並以底膠15包覆該些導電元件16，而間距較小之半導體晶片10之電極墊100係藉由複數銲錫凸塊101電性結合該線路重佈結構131，再以底膠14包覆該些銲錫凸塊101。最後，形成一封裝膠體12於該封裝基板11上，以令該封裝膠體12包覆該半導體晶片10與該矽中介板13。
於後續製程中，於該封裝基板11下側形成複數銲球17，以供結合至一電路板(圖略)上。
惟，習知半導體封裝件1於製作過程中，尚未進行切單製程前，如第1’圖所示之整版面結構1’(其包含複數該半導體封裝件1)，當經過如回銲製程等高溫作業後，由於該半導體晶片10、封裝基板11、封裝膠體12與矽中介板13之間的熱膨脹係數(Coefficient of thermal expansion，簡稱CTE)差異(Mismatch)甚大，而使該整版面結構1’容易發生翹曲(warpage)，如上凸情況(如第1’圖所示)或下凹情況，導致切單後之半導體封裝件1之平面度不佳，以致於後續該半導體封裝件1接置於電路板上時，會發生不沾錫(Non wetting)之問題，而使電性連接不佳。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種半導體基板，係包括：一基板本體；複數導電穿孔，係形成於該基板本體中且貫穿該基板本體；以及至少一柱體，係 形成於該基板本體中且未貫穿該基板本體。
本發明復提供一種半導體基板之製法，係包括：提供一基板本體，且該基板本體形成有複數貫穿其中之導電穿孔；形成至少一盲孔於該基板本體上，其中，該盲孔未貫穿該基板本體；以及形成柱體於該盲孔中。
本發明亦提供一種半導體基板之製法，係包括：提供一基板本體；形成至少一盲孔與複數穿孔於該基板本體上，且該穿孔之深度大於該盲孔之深度；以及於該穿孔中形成導電穿孔，且於該盲孔中形成柱體，並使該導電穿孔貫穿該基板本體，而該柱體未貫穿該基板本體。
前述之半導體基板及其製法中，該基板本體係為含矽之板體。
前述之半導體基板及其製法中，該基板本體之表面係定義有一中央區與環繞該中央區之外圍區，且該些導電穿孔係位於該中央區，而該柱體係位於該外圍區。
前述之半導體基板及其製法中，該基板本體上形成有電性連接該導電穿孔之線路重佈結構。
前述之半導體基板及其製法中，該柱體係含有導電材。
本發明再提供一種電子封裝件，係包括：封裝基板；前述之半導體基板；電子元件，係設於該半導體基板上且電性連接該導電穿孔；以及封裝層，係形成於該封裝基板上以包覆該半導體基板與該電子元件。
本發明另提供一種電子封裝件之製法，係包括：提供 一前述之半導體基板；分別設置電子元件與封裝基板於該半導體基板之相對兩側，且該電子元件與封裝基板係電性連接該導電穿孔；以及形成封裝層於該封裝基板上，以令該封裝層包覆該電子元件與該半導體基板。
前述之製法中，該柱體形成之步驟係包括：形成盲孔於該半導體基板上；以及形成導電材於該盲孔中，以形成該柱體。
前述之製法中，該些導電穿孔與該柱體係分開製作；或者，該些導電穿孔與該柱體係同時製作。
前述之電子封裝件及其製法中，該半導體基板形成有一電性連接該導電穿孔之線路重佈結構，以令該電子元件結合於該線路重佈結構上、或者令該線路重佈結構結合該封裝基板。
由上可知，本發明之電子封裝件及其半導體基板與製法，係藉由該些柱體未貫穿該基板本體的設計，以於該半導體基板受熱時，該柱體能調整該基板本體於上、下側的伸縮量，使該半導體基板上、下側的熱變形量相等，以避免該半導體基板發生翹曲。
再者，由於該半導體基板能平衡上下側的伸縮量，故本發明之電子封裝件於經過高溫作業後，能避免其發生翹曲，因而於後續該電子封裝件接置於電路板上時，不會發生不沾錫之問題，進而能提升產品良率。
1‧‧‧半導體封裝件
1’‧‧‧整版面結構
10‧‧‧半導體晶片
100,400‧‧‧電極墊
101‧‧‧銲錫凸塊
11,41‧‧‧封裝基板
110,410‧‧‧銲墊
12‧‧‧封裝膠體
13‧‧‧矽中介板
130‧‧‧導電矽穿孔
131,21‧‧‧線路重佈結構
14,15,44,45‧‧‧底膠
16,22,25‧‧‧導電元件
17,43‧‧‧銲球
2,2’,3‧‧‧半導體基板
2a‧‧‧置晶側
2b‧‧‧中介側
20,30‧‧‧基板本體
20a‧‧‧第一表面
20b,30b‧‧‧第二表面
200‧‧‧導電穿孔
200a‧‧‧銅柱
200b,241‧‧‧絕緣材
210‧‧‧介電層
211‧‧‧線路層
220‧‧‧金屬層
221‧‧‧導電凸塊
23,33‧‧‧盲孔
24,34,54‧‧‧柱體
24a‧‧‧端面
240‧‧‧導電材
300‧‧‧穿孔
340‧‧‧銅塊
4,5‧‧‧電子封裝件
40‧‧‧電子元件
40a‧‧‧作用面
40b‧‧‧非作用面
411‧‧‧植球墊
42‧‧‧封裝層
A‧‧‧中央區
B‧‧‧外圍區
h,d‧‧‧深度
第1圖係為習知半導體封裝件之剖面示意圖； 第1’圖係為第1圖之立體示意圖；第2A至2C圖係本發明之半導體基板之製法之第一實施例的剖面示意圖；其中，第2C’圖係第2C圖之另一實施例；第3A至3D圖係本發明之半導體基板之製法之第二實施例的剖面示意圖；第4圖係本發明之電子封裝件之剖面示意圖；以及第5圖係第4圖之另一實施例。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2C圖係為本發明之半導體基板2之製法之第 一實施例的剖面示意圖。於本實施例中，係先製作導電穿孔，再製作柱體。
如第2A圖所示，提供一基板本體20，該基板本體20定義有相對之第一表面20a與第二表面20b，且該基板本體20中具有複數貫穿該第一與第二表面20a,20b(即連通該第一與第二表面20a,20b)之導電穿孔200。
於本實施例中，該基板本體20係為含矽之板體，例如，矽中介板(Through Silicon Interposer，簡稱TSI)或玻璃基板，且該導電穿孔200係為導電矽穿孔(Through-silicon via，簡稱TSV)，其中該導電穿孔200係為銅柱200a及環繞該銅柱200a之絕緣材200b所構成，但不以此為限。
再者，該導電穿孔200之兩端面係分別齊平該基板本體20之第一表面20a與第二表面20b。
又，該基板本體20之第一表面20a定義有一中央區A與環繞該中央區A之外圍區B，且該些導電穿孔200係位於該中央區A。
另外，可選擇性地於該基板本體20之第二表面20b上進行線路重佈層(Redistribution layer，簡稱RDL)製程，以形成一線路重佈結構21，且該線路重佈結構21電性連接各該導電穿孔200。具體地，該線路重佈結構21係包含相疊之至少一線路層211與至少一介電層210，且該線路層211電性連接該導電穿孔200。
此外，亦可選擇性地於最外層之線路層211上形成複 數導電元件22。具體地，該導電元件22係包含金屬層220、及設於該金屬層220上之導電凸塊221。例如，該導電凸塊221係含有銲錫材料，且該金屬層220係為凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)，其中該凸塊底下金屬層之構造與材質係因種類繁多而無特別限制。
如第2B圖所示，形成複數盲孔23於該基板本體20之第一表面20a之外圍區B上，其中，各該盲孔23未貫穿該基板本體20，亦即各該盲孔23未連通至該基板本體20之第二表面20b。
如第2C圖所示，形成柱體24於各該盲孔23中，且該柱體24之端面24a係齊平該基板本體20之第一表面20a。
於本實施例中，該柱體24係由絕緣材241及導電材240所構成。例如，先以熱氧化(thermal oxidation)方式形成一如氧化矽(SiO2)之絕緣材241於該盲孔23之壁面上，再以例如電鍍或沉積方式形成導電材240(如銅材)於各該盲孔23中。
再者，於形成該導電材240前，可先濺鍍如鈦材之黏著層與如銅材之種子層(seed layer)。然而，有關製作該柱體24之方式繁多，並不限於上述者。
又，於另一實施例中，如第2C’圖所示，可先製作該柱體24，再製作該線路重佈結構21，使該柱體24與該線路重佈結構21可位於該基板本體20之同一側(例如，兩者均位於該基板本體20之第一表面20a)。因此，應可理解地，該線路重佈結構21可選擇同時形成於該基板本體 20之第一表面20a及第二表面20b上或僅形成於該第一表面20a與該第二表面20b之其中一者上。
第3A至3D圖係為本發明之半導體基板3之製法之第二實施例的剖面示意圖。本實施例與第一實施例之差異在於柱體之製作，亦即本實施例係一同製作導電穿孔200與柱體34，故以下僅說明相異處，而不再贅述相同處。
如第3A圖所示，提供一基板本體30，該基板本體30定義有相對之第一表面20a與第二表面30b。接著，形成複數穿孔300於該基板本體20之第一表面20a之中央區A上，以及形成複數盲孔33於該基板本體20之第一表面20a之外圍區B上，且該穿孔300之深度h大於該盲孔33之深度d。
於本實施例中，係以蝕刻或機械方式形成該些穿孔300與該些盲孔33，且該些穿孔300與該些盲孔33均未貫穿該基板本體30。
如第3B圖所示，於各該穿孔300中形成導電穿孔200，且於各該盲孔33中形成柱體34。
於本實施例中，可先以熱氧化方式形成一如氧化矽之絕緣層於該穿孔300之壁面與該盲孔33之壁面上，再以例如電鍍或沉積方式形成金屬層(如銅材)於該穿孔300與盲孔33中及該基板本體30之第一表面20a上，之後以化學機械研磨(Chemical-Mechanical Polishing，簡稱CMP)方式移除該基板本體30之第一表面20a上之金屬層。於形成金屬層前，可先濺鍍如鈦材之黏著層與如銅材之種子層。
因此，該導電穿孔200係為銅柱200a及環繞該銅柱200a之絕緣材200b所構成，且該柱體34係為銅塊340及環繞該銅塊340之絕緣材200b所構成。
然而，有關製作該導電穿孔200與該柱體34之方式繁多，並不限於上述者。
如第3C圖所示，移除該基板本體30之第二表面30b之部分材質，以薄化該基板本體30而形成類似第2C圖之基板本體20，使該導電穿孔200貫穿該基板本體20，且各該柱體34未貫穿該基板本體20，亦即各該柱體34未連通至該基板本體20之第二表面20b。
於本實施例中，以研磨方式進行薄化製程，使該導電穿孔200之端面齊平該基板本體20之第二表面20b。
如第3D圖所示，可選擇性地形成一線路重佈結構21於該基板本體20之第一表面20a及/或第二表面20b上。
本發明之半導體基板2,3之製法係藉由該些柱體24,34未貫穿該基板本體20之設計，且金屬材的翹曲量遠大於矽材，以於該半導體基板2受熱時，該柱體24,34能調整該基板本體20於上、下側(即第一表面20a之側與第二表面20b之側)的伸縮量，使該半導體基板2,3上、下側的熱變形量相等，以避免該半導體基板2,3發生翹曲。
另外，應可理解地，上述各實施例中，該些柱體24,34可分佈於該基板本體20之不同側，亦即同一半導體基板中，部分柱體位於該基板本體20之第一表面20a，而部分柱體位於該基板本體20之第二表面20b。
本發明復提供一種半導體基板2,2’,3，係包括：一基板本體20、複數導電穿孔200以及複數柱體24,34。
所述之基板本體20係為含矽之板體，其具有相對之第一表面20a與第二表面20b。
所述之導電穿孔200係形成於該基板本體20中並貫穿該基板本體20。
所述之柱體24,34係包含導電材240(或銅塊340)，其形成於該基板本體20之第一表面20a及/或第二表面20b上而未貫穿該基板本體20。
於一實施例中，該基板本體20之第一表面20a或第二表面20b係定義有一中央區A與環繞該中央區A之外圍區B，且該些導電穿孔200係位於該中央區A，而該些柱體24,34係位於該外圍區B。
於一實施例中，該基板本體20之第一表面20a及/或第二表面20b上形成有一電性連接各該導電穿孔200之線路重佈結構21，且該線路重佈結構21未電性連接該柱體24,34。
第4圖係為本發明之電子封裝件4的剖面示意圖。於本實施例中，係應用如第2C圖所示之半導體基板2，但因該半導體基板2作為中介板，故以下將重新定義該半導體基板2。例如，該基板本體20之第一表面20a或第二表面20b之其中一者作為該半導體基板2之置晶側2a，而另一者則作為該半導體基板2之中介側2b。
如第4圖所示，設置一電子元件40於該半導體基板2 之置晶側2a上，且該電子元件40藉由該線路重佈結構21電性連接各該導電穿孔200。接著，將一封裝基板41結合至該半導體基板2之中介側2b上。之後，形成一封裝層42於該封裝基板41上，以令該封裝層42包覆該電子元件40與該半導體基板2。
於本實施例中，該柱體24係連通該半導體基板2之中介側2b而未連通該置晶側2a。而於另一實施例中，如第5圖所示，該柱體54亦可連通該半導體基板2之置晶側2a而未連通該中介側2b，其中，該柱體54之組成可參考上述各實施例。因此，可依設計需求，將部分柱體54形成於該置晶側2a，而部分柱體24形成於該中介側2b，如第5圖所示。
再者，該電子元件40係為主動元件、被動元件或其二者組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。例如，該電子元件40係為半導體晶片，其具有相對之作用面40a與非作用面40b，該作用面40a具有複數電極墊400，且該電子元件40係以其電極墊400結合該些導電元件22，再以底膠44包覆該些導電元件22。
又，形成該封裝層42之材質係為聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(expoxy)或封裝材。
另外，形成複數導電元件25於該半導體基板2之中介側2b上，以藉由該些導電元件25結合並電性連接該封裝 基板41上側之銲墊410，再以底膠45包覆該些導電元件25。具體地，該些導電元件25係接觸該些導電穿孔200而未接觸該柱體24，且該些導電元件25之組成可參考上述導電元件22。
於後續製程中，形成複數銲球43於該封裝基板41下側之植球墊411上，以供結合至一電路板(圖略)上。
本發明之電子封裝件4,5之製法中，主要藉由銅材的翹曲量遠大於矽材，以於該半導體基板2受熱時，該柱體24,54能調整該基板本體20於上下側的伸縮量，使該半導體基板2上下側的伸縮量能平衡對稱，從而避免發生翹曲。
因此，本發明之電子封裝件4,5於製作過程中，尚未進行切單製程前，當經過如回銲製程等高溫作業後，由於該半導體基板2能平衡上下側的伸縮量，故能避免整版面結構發生翹曲，因而於後續該電子封裝件4,5接置於電路板上時，不會發生不沾錫之問題，進而能提升產品良率。
本發明係提供一種電子封裝件4,5，係包括：一半導體基板2、一電子元件40、一封裝基板41以及一封裝層42。
所述之半導體基板2係為含矽之板體，其具有相對之置晶側2a與中介側2b，且該半導體基板2中具有複數柱體24,54及複數連通該置晶側2a與中介側2b之導電穿孔200，其中，該柱體24,54係含有金屬材並連通該置晶側2a或中介側2b但未貫穿該基板本體20。
所述之電子元件40係設於該半導體基板2之置晶側2a上且電性連接該導電穿孔200。
所述之封裝基板41係結合至該半導體基板2之中介側2b上且電性連接該導電穿孔200。
所述之封裝層42係形成於該封裝基板41上以包覆該半導體基板2與該電子元件40。
於一實施例中，該半導體基板2之置晶側2a或中介側2b係定義有一中央區A與環繞該中央區A之外圍區B，且該些導電穿孔20係位於該中央區A，而該柱體24,54係位於該外圍區B。
於一實施例中，該半導體基板2之置晶側2a上形成有一電性連接該導電穿孔200之線路重佈結構21，以令該電子元件40結合於該線路重佈結構21上並電性連接該線路重佈結構21，且該線路重佈結構21未電性連接該柱體24,54。
於一實施例中，該半導體基板2之中介側2b上形成有一電性連接該導電穿孔200之線路重佈結構21，以令該封裝基板41結合於該線路重佈結構21上並電性連接該線路重佈結構21，且該線路重佈結構21未電性連接該柱體24,54。
於一實施例中，該柱體24係連通該半導體基板2之中介側2b而未連通該置晶側2a。
於一實施例中，該柱體54係連通該半導體基板2之置晶側2a而未連通該中介側2b。
另一方面，本發明之柱體可設於該半導體基板之上側、下側或其組合，且該柱體之寬度、深度、數量、位置 亦可依據翹曲量而做調整，並不限於上述。
綜上所述，本發明之電子封裝件及其半導體基板與製法，係藉由該半導體基板具有未貫穿該基板本體之柱體，以於該半導體基板受熱時，該柱體能調整該基板本體於上下側的伸縮量，故當經高溫作業後，能避免電子封裝件發生翹曲，因而能提升產品良率。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧半導體基板
20‧‧‧基板本體
20a‧‧‧第一表面
20b‧‧‧第二表面
200‧‧‧導電穿孔
21‧‧‧線路重佈結構
22‧‧‧導電元件
23‧‧‧盲孔
24‧‧‧柱體
24a‧‧‧端面
240‧‧‧導電材
241‧‧‧絕緣材

Claims (26)

  1. 一種半導體基板，係包括：一基板本體；複數導電穿孔，係形成於該基板本體中且貫穿該基板本體；以及至少一柱體，係形成於該基板本體中且未貫穿該基板本體。
  2. 如申請專利範圍第1項所述之半導體基板，其中，該基板本體係為含矽之板體。
  3. 如申請專利範圍第1項所述之半導體基板，其中，該基板本體之表面係定義有一中央區與環繞該中央區之外圍區，且該些導電穿孔係位於該中央區，而該柱體係位於該外圍區。
  4. 如申請專利範圍第1項所述之半導體基板，其中，該基板本體上形成有電性連接該導電穿孔之線路重佈結構。
  5. 如申請專利範圍第1項所述之半導體基板，其中，該柱體係含有導電材。
  6. 一種半導體基板之製法，係包括：提供一基板本體，且該基板本體形成有複數貫穿其中之導電穿孔；形成至少一盲孔於該基板本體上，其中，該盲孔未貫穿該基板本體；以及形成柱體於該盲孔中。
  7. 一種半導體基板之製法，係包括： 提供一基板本體；形成至少一盲孔與複數穿孔於該基板本體上，且該穿孔之深度大於該盲孔之深度；以及於該穿孔中形成導電穿孔，且於該盲孔中形成柱體，並使該導電穿孔貫穿該基板本體，而該柱體未貫穿該基板本體。
  8. 如申請專利範圍第6或7項所述之半導體基板之製法，其中，該基板本體係為含矽之板體。
  9. 如申請專利範圍第6或7項所述之半導體基板之製法，其中，該基板本體之表面係定義有一中央區與環繞該中央區之外圍區，且該些導電穿孔係位於該中央區，而該柱體係位於該外圍區。
  10. 如申請專利範圍第6或7項所述之半導體基板之製法，其中，該基板本體上形成有電性連接該導電穿孔之線路重佈結構。
  11. 如申請專利範圍第6或7項所述之半導體基板之製法，其中，該柱體係含有導電材。
  12. 一種電子封裝件，係包括：封裝基板；半導體基板，係設於該封裝基板上並具有至少一未貫穿該半導體基板之柱體及複數貫穿該半導體基板之導電穿孔，且該封裝基板係電性連接該導電穿孔；電子元件，係設於該半導體基板上且電性連接該導電穿孔；以及 封裝層，係形成於該封裝基板上以包覆該半導體基板與該電子元件。
  13. 如申請專利範圍第12項所述之電子封裝件，其中，該半導體基板係為含矽之板體。
  14. 如申請專利範圍第12項所述之電子封裝件，其中，該半導體基板之表面係定義有一中央區與環繞該中央區之外圍區，且該些導電穿孔係位於該中央區，而該柱體係位於該外圍區。
  15. 如申請專利範圍第12項所述之電子封裝件，其中，該半導體基板形成有一電性連接該導電穿孔之線路重佈結構，以令該電子元件結合於該線路重佈結構上。
  16. 如申請專利範圍第12項所述之電子封裝件，其中，該半導體基板形成有一電性連接該導電穿孔之線路重佈結構，以令該線路重佈結構結合該封裝基板。
  17. 如申請專利範圍第12項所述之電子封裝件，其中，該柱體係含有導電材。
  18. 一種電子封裝件之製法，係包括：提供一半導體基板，其中該半導體基板形成有至少一未貫穿其中之柱體及複數貫穿其中之導電穿孔；分別設置電子元件與封裝基板於該半導體基板之相對兩側，且該電子元件與封裝基板係電性連接該導電穿孔；以及形成封裝層於該封裝基板上，以令該封裝層包覆該電子元件與該半導體基板。
  19. 如申請專利範圍第18項所述之電子封裝件之製法，其中，該半導體基板係為含矽之板體。
  20. 如申請專利範圍第18項所述之電子封裝件之製法，其中，該半導體基板之表面係定義有一中央區與環繞該中央區之外圍區，且該些導電穿孔係位於該中央區，而該柱體係位於該外圍區。
  21. 如申請專利範圍第18項所述之電子封裝件之製法，其中，該半導體基板形成有一電性連接該導電穿孔之線路重佈結構，以令該電子元件結合於該線路重佈結構上。
  22. 如申請專利範圍第18項所述之電子封裝件之製法，其中，該半導體基板形成有一電性連接該導電穿孔之線路重佈結構，以令該線路重佈結構結合該封裝基板。
  23. 如申請專利範圍第18項所述之電子封裝件之製法，其中，該柱體係含有導電材。
  24. 如申請專利範圍第18項所述之電子封裝件之製法，其中，該柱體形成之步驟係包括：形成盲孔於該半導體基板上；以及形成導電材於該盲孔中，以形成該柱體。
  25. 如申請專利範圍第18項所述之電子封裝件之製法，其中，該些導電穿孔與該柱體係分開製作。
  26. 如申請專利範圍第18項所述之電子封裝件之製法，其中，該些導電穿孔與該柱體係同時製作。
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