TW201739024A - 基板結構 - Google Patents

基板結構 Download PDF

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Publication number
TW201739024A
TW201739024A TW105113075A TW105113075A TW201739024A TW 201739024 A TW201739024 A TW 201739024A TW 105113075 A TW105113075 A TW 105113075A TW 105113075 A TW105113075 A TW 105113075A TW 201739024 A TW201739024 A TW 201739024A
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Taiwan
Prior art keywords
electrical contact
layer
substrate structure
insulating
substrate
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TW105113075A
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English (en)
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TWI669793B (zh
Inventor
梁芳瑜
張宏憲
賴顗喆
曾文聰
黃陳昱
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW105113075A priority Critical patent/TWI669793B/zh
Priority to CN201610326414.2A priority patent/CN107316842A/zh
Priority to US15/224,767 priority patent/US10199341B2/en
Publication of TW201739024A publication Critical patent/TW201739024A/zh
Application granted granted Critical
Publication of TWI669793B publication Critical patent/TWI669793B/zh

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Abstract

一種基板結構，係包括：具有電性接點之基板本體、形成於該基板本體上並外露該電性接點之絕緣層、以及形成於該絕緣層部分表面上之絕緣保護層，該絕緣保護層具有對應位於單一該電性接點之複數開口，其中，至少一該開口位於該電性接點之外圍，以於該基板結構經過高溫作業時，該絕緣保護層可藉由該些開口分散製程所產生之殘留應力。

Description

基板結構
本發明係有關一種基板結構，尤指一種能提高信賴性及產品良率之基板結構。
目前應用於晶片封裝領域之技術繁多，例如晶片尺寸構裝(Chip Scale Package，簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached，簡稱DCA)或多晶片模組封裝(Multi-Chip Module，簡稱MCM)等覆晶型態的封裝模組、或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊技術等。
第1圖係為習知3D IC晶片堆疊之半導體封裝件1之剖面示意圖。如圖所示，該半導體封裝件1具有一矽中介板(Through Silicon interposer，簡稱TSI)10，該矽中介板10具有具有相對之置晶側10b與轉接側10a、及連通該置晶側10b與轉接側10a之複數導電矽穿孔(Through-silicon via，簡稱TSV)100，且該置晶側10b上具有一電性連接該些導電矽穿孔100之線路重佈結構(Redistribution layer，簡稱RDL)11，以供間距較小之半導體晶片6之電極墊60係藉由複數銲錫凸塊61電性結合至該線路重佈結 構11上，再以底膠62包覆該些銲錫凸塊61，且於各該導電矽穿孔100上藉由複數如銲料凸塊之導電元件17電性結合間距較大之封裝基板7之銲墊70，之後形成封裝膠體8於該封裝基板7上，以包覆該半導體晶片6。
具體地，如第1’及1”圖所示，該矽中介板10之轉接側10a形成有一絕緣層12，且該絕緣層12具有開孔120以外露該導電矽穿孔100端面，且於該絕緣層12之局部表面上(約該絕緣層12之開孔120周圍)形成有一絕緣保護層15，以藉由該絕緣保護層15之開口150外露該導電矽穿孔100端面，再形成一凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)16於該開孔120與開口150中之導電矽穿孔100端面，以結合該導電元件17於該凸塊底下金屬層16上。
惟，前述習知半導體封裝件1中，當經過高溫作業時(例如，該導電元件17經回銲後銲接至該銲墊70上)，此時因熱所產生之殘留應力會集中在該些導電元件17與該些導電矽穿孔100間之交界面，如第1’圖所示之應力集中處k，使得該絕緣保護層15與該凸塊底下金屬層16(或該絕緣層12與該些導電矽穿孔100)之間會出現分離(peeling)或破裂(crack)之情形，因而降低該半導體封裝件1之信賴性及產品之良率。
再者，相同問題亦可能發生於該半導體晶片6與該線路重佈結構11之間的銲錫凸塊61上，致使該銲錫凸塊61與該線路重佈結構11之間會出現分離或破裂之情形，如第 1圖所示之應力集中處k’。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的問題。
鑑於上述習知技術之種種缺失，本發明提供一種基板結構，係包括：基板本體，係具有至少一電性接點；絕緣層，係形成於該基板本體上並外露該電性接點；以及絕緣保護層，係形成於該絕緣層之部分表面上，且該絕緣保護層具有對應於單一該電性接點之複數開口，其中，至少一該開口位於該電性接點之外圍。
前述之基板結構中，該電性接點係為導電柱或電性接觸墊。
前述之基板結構中，該基板本體上形成有線路層，使該絕緣層形成於該線路層上，且該電性接點係為該線路層之一部分。
前述之基板結構中，該開口之上視平面形狀係為封閉曲線或多邊形。
前述之基板結構中，復包括形成於至少一該開口中之金屬層。例如，該金屬層係接觸該電性接點。
前述之基板結構中，復包括形成於該絕緣保護層上之導電元件。
前述之基板結構中，至少一該開口外露出該絕緣層。
由上可知，本發明之基板結構，主要藉由該絕緣保護層具有位於該電性接點外圍之開口，以於經過如回銲製程 等高溫作業時，該絕緣保護層可分散因熱所產生之殘留應力，故相較於習知技術，本發明之基板結構能避免該絕緣保護層與該金屬層、或該絕緣層與該電性接點之間出現分離或破裂之情形，進而提高該基板結構之信賴性及產品之良率。
1‧‧‧半導體封裝件
10‧‧‧矽中介板
10a‧‧‧轉接側
10b‧‧‧置晶側
100‧‧‧導電矽穿孔
11‧‧‧線路重佈結構
12,22‧‧‧絕緣層
120,220‧‧‧開孔
15,25‧‧‧絕緣保護層
150,250,250’‧‧‧開口
16‧‧‧凸塊底下金屬層
17,27‧‧‧導電元件
2,2’,3‧‧‧基板結構
20‧‧‧基板本體
20a‧‧‧表面
200,200’,300‧‧‧電性接點
200”‧‧‧電性接觸墊
26‧‧‧金屬層
30‧‧‧介電層
31‧‧‧線路層
310‧‧‧導電盲孔
6‧‧‧半導體晶片
60‧‧‧電極墊
61‧‧‧銲錫凸塊
62‧‧‧底膠
7‧‧‧封裝基板
70‧‧‧銲墊
8‧‧‧封裝膠體
k,k’‧‧‧應力集中處
第1圖係為習知半導體封裝件之剖面示意圖；第1’圖係為第1圖的局部放大圖；第1”圖係為第1”圖之局部上視平面圖；第2A圖係為本發明之基板結構之剖視示意圖；第2B圖係為第2A圖之其它實施例之剖視示意圖；第3圖係為本發明之基板結構之另一實施例的剖視示意圖；以及第4、4’及4”圖係為第2A圖之不同態樣之局部上視平面圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功 效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A圖係為本發明之基板結構2之剖視示意圖。如第2A圖所示，該基板結構2係包含有一基板本體20、一絕緣層22以及一絕緣保護層25。
所述之基板本體20具有一表面20a，且於該表面20a結合有至少一電性接點200。於本實施例中，該基板本體20係為絕緣板、金屬板、或如晶圓、晶片、矽材、玻璃等之半導體板材。例如，該基板本體20係為矽中介板(TSI)或玻璃基板，其具有矽穿孔(TSV)，使該電性接點200係為導電柱。
於另一實施例中，如第2B圖所示之基板結構2’，該基板本體20係包含有一線路結構，其具有至少一介電層及至少一線路層，且該電性接點200’係為電性接觸墊，其設於最外層之介電層上並電性連接該線路層。
所述之絕緣層22係形成於該基板本體20之表面20a上並形成有一外露該電性接點200,200’之開孔220。
於本實施例中，該絕緣層22之材質可為氧化層或氮化層，如氧化矽(SiO2)或氮化矽(SixNy)。
再者，所述之絕緣層22係以單一該開孔220外露單一 該電性接點200,200’。
所述之絕緣保護層25係形成於該絕緣層22之部分表面上(即開孔220周圍)，且該絕緣保護層25具有對應於單一該電性接點200,200’之複數開口250,250’，其中，至少一該開口250’位於該電性接點200,200’之外圍。
於本實施例中，該絕緣保護層25之材質係為防銲材或介電材，例如聚亞醯胺(Polyimide，簡稱PI)、苯並環丁烯(Benezocy-clobutene，簡稱BCB)或聚對二唑苯(Polybenzoxazole，簡稱PBO)。
再者，如第2A圖所示，該絕緣保護層25係以單一該開口250對應該開孔220位置而外露單一該電性接點200，而其它開口250’外露該絕緣層22。
又，如第4、4’及4”圖所示，該些開口250,250’之上視平面形狀係為封閉曲線(如圓形、橢圓形)或多邊形(如矩形、三角形、規則多邊形或不規則多邊形等)。應可理解地，用以外露該電性接點200,200’之開口250,250’之上視平面形狀較佳為圓形，但亦可如第4”圖所示之矩形，使該絕緣保護層25之上視平面形狀呈柵欄狀。
另外，所述之基板結構2,2’復包括一形成於該開孔210及開口250,250’中之金屬層26，其接觸並電性連接該電性接點200,200’且延伸至該絕緣保護層25之部分表面上。具體地，該金屬層26形成於複數該開口250,250’中，且僅單一開口250中之金屬層26接觸及電性連接該電性接點200,200’。
於本實施例中，該金屬層26係為凸塊底下金屬層(Under Bump Metal，簡稱UBM)，且形成該金屬層26之材質係例如鈦/銅/鎳或鈦/鎳釩/銅，並可藉由濺鍍(sputter)或鍍覆(plating)配合曝光顯影之方式，進行圖案化製程，以形成該金屬層26。然而，該金屬層26之構造與材質係種類繁多，並不限於上述者。
再者，所述之基板結構2,2’復包括至少一形成於該絕緣保護層25上之導電元件27，其接觸結合於該金屬層26上，俾供結合半導體元件、封裝基板或電路板等電子裝置。具體地，該導電元件27係為銲球、金屬塊等，使該基板結構2,2’藉由該些導電元件27結合其它電子裝置(圖略)，例如，半導體晶圓、晶片、具有矽穿孔之中介板、封裝基板或線路板。
第3圖係為本發明之基板結構3之另一實施例的剖視示意圖。本實施例與上述實施例的差異在於新增線路層，其它構件大致相同，故以下僅說明相異處，而不再贅述相同處。
如第3圖所示，該基板本體20上形成有一線路層31，且該絕緣層22形成於該線路層31上，其中該線路層31具有至少一電性接點300。具體地，該基板本體20具有電性接觸墊200”，且於該基板本體20上形成有一外露該電性接觸墊200”之介電層30，再進行線路重佈層(Redistribution layer，簡稱RDL)製程，以於該介電層30上形成具有該電性接點300之線路層31，且該線路層31 具有至少一形成於該介電層30中之導電盲孔310，以電性連接該電性接觸墊200”。
於本實施例中，該絕緣層22係以單一該開孔220外露單一該電性接點300，且該絕緣保護層25之其中一開口250對應該開孔220位置而外露單一該電性接點300。
再者，相對於該電性接點300，該絕緣保護層之開口的形成位置與該金屬層之形成位置係可參照第2B圖所示之實施例進行配置。
綜上所述，本發明之基板結構2,2’,3係藉由該絕緣保護層25具有位於單一該電性接點200,200’,300外圍之複數開口250,250’，以當經過高溫作業時(例如，該導電元件27經回銲後銲接至半導體晶片或封裝基板時)，該絕緣保護層25可分散因熱所產生之殘留應力，故相較於習知技術，本發明之基板結構2,2’,3具有較小應力集中在該導電元件27與該電性接點200,200’,300間之交界面，因而能避免該絕緣保護層25與該金屬層26、或該絕緣層22與該電性接點200,200’,300之間出現分離或破裂之情形，進而提高該基板結構2,2’,3之信賴性及產品之良率。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧基板結構
20‧‧‧基板本體
20a‧‧‧表面
200‧‧‧電性接點
22‧‧‧絕緣層
220‧‧‧開孔
25‧‧‧絕緣保護層
250,250’‧‧‧開口
26‧‧‧金屬層
27‧‧‧導電元件

Claims (8)

  1. 一種基板結構，係包括：基板本體，係具有至少一電性接點；絕緣層，係形成於該基板本體上並外露該電性接點；以及絕緣保護層，係形成於該絕緣層之部分表面上，且該絕緣保護層具有對應於單一該電性接點之複數開口，其中，至少一該開口位於該電性接點之外圍。
  2. 如申請專利範圍第1項所述之基板結構，其中，該電性接點係為導電柱或電性接觸墊。
  3. 如申請專利範圍第1項所述之基板結構，其中，該基板本體上形成有線路層，使該絕緣層形成於該線路層上，且該電性接點係為該線路層之一部分。
  4. 如申請專利範圍第1項所述之基板結構，其中，該開口之上視平面形狀係為封閉曲線或多邊形。
  5. 如申請專利範圍第1項所述之基板結構，復包括形成於至少一該開口中之金屬層。
  6. 如申請專利範圍第5項所述之基板結構，其中，該金屬層係接觸該電性接點。
  7. 如申請專利範圍第1項所述之基板結構，復包括形成於該絕緣保護層上之導電元件。
  8. 如申請專利範圍第1項所述之基板結構，其中，至少一該開口外露出該絕緣層。
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