TWI463621B - 封裝基板結構及其製法 - Google Patents

封裝基板結構及其製法 Download PDF

Info

Publication number
TWI463621B
TWI463621B TW100140252A TW100140252A TWI463621B TW I463621 B TWI463621 B TW I463621B TW 100140252 A TW100140252 A TW 100140252A TW 100140252 A TW100140252 A TW 100140252A TW I463621 B TWI463621 B TW I463621B
Authority
TW
Taiwan
Prior art keywords
opening
dielectric layer
package substrate
sub
layer
Prior art date
Application number
TW100140252A
Other languages
English (en)
Other versions
TW201320269A (zh
Inventor
莊建隆
吳柏毅
李孟宗
姜亦震
Original Assignee
矽品精密工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW100140252A priority Critical patent/TWI463621B/zh
Priority to CN2011103843157A priority patent/CN103094243A/zh
Priority to US13/482,313 priority patent/US20130113095A1/en
Publication of TW201320269A publication Critical patent/TW201320269A/zh
Application granted granted Critical
Publication of TWI463621B publication Critical patent/TWI463621B/zh
Priority to US15/411,204 priority patent/US10192838B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
    • H01L2224/02125—Reinforcing structures
    • H01L2224/02126—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/024—Material of the insulating layers therebetween
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H01L2224/03614—Physical or chemical etching by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03622—Manufacturing methods by patterning a pre-deposited material using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H01L2224/05018—Shape in side view being a conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05562—On the entire exposed surface of the internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H01L2224/05582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H01L2224/10126—Bump collar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/053—Oxides composed of metals from groups of the periodic table
    • H01L2924/0544—14th Group
    • H01L2924/05442—SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/07—Polyamine or polyimide
    • H01L2924/07025—Polyimide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/206—Length ranges
    • H01L2924/2064—Length ranges larger or equal to 1 micron less than 100 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

封裝基板結構及其製法
本發明係有關於一種基板結構及其製法，尤指一種封裝基板結構及其製法。
傳統覆晶式(flip chip)半導體封裝技術主要係於晶片之電性接觸墊上形成銲料凸塊(solder bump)，再透過該銲料凸塊直接與封裝基板電性連接，相較於打線(wire bonding)方式來說，覆晶技術的電路路徑較短，具有較佳的電性品質，同時因可設計為晶背裸露形式，亦可提高晶片散熱性。
請參閱第1圖，係習知例如第5,937,320號美國專利之具有凸塊底下金屬層的基板結構之剖視圖，其覆晶技術係於晶片10上形成銲料凸塊12前，先於晶片10之電性接觸墊101上全面性地形成鈦層11a與銅層11b，並於該電性接觸墊101上方的銅層11b上形成銲料凸塊12，最後再蝕刻移除未被該銲料凸塊12所覆蓋之鈦層11a與銅層11b，以於該銲料凸塊12底下定義出凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)11，並藉由該凸塊底下金屬層11使該銲料凸塊12牢固地接置於該晶片10之電性接觸墊101上。
惟，習知使用層疊之鈦層11a與銅層11b以構成凸塊底下金屬層11時，由於該鈦層11a的蝕刻速度會大於銅層11b的蝕刻速度，因此該鈦層11a的側蝕情況嚴重，而造成如第1圖所示之顯著底切(undercut)結構，該底切結構將會使應力集中，因而容易在該點斷裂，導致整體信賴性不佳。
因此，如何避免上述習知技術中之種種問題，俾避免凸塊底下金屬層因過度側蝕而形成嚴重底切結構，進而提昇產品可靠度與良率，實已成為目前亟欲解決的課題。
有鑒於上述習知技術之缺失，本發明提供一種封裝基板結構，係包括：基板，其一表面具有至少一電性接觸墊；第一介電層，係形成於該基板之表面上，該第一介電層具有至少一第一開口與第二開口，其中，該第一開口係對應外露該電性接觸墊，該第二開口係對應設置於該第一開口之側周緣；凸塊底下金屬層，係對應形成於該電性接觸墊及該第一介電層上，且延伸至該第二開口的側壁上；以及銲料凸塊，係形成於該凸塊底下金屬層上。
本發明復提供一種封裝基板結構之製法，係包括：提供一表面具有至少一複數電性接觸墊的基板，該表面上形成有第一介電層，且該第一介電層具有至少一對應外露該電性接觸墊的第一開口；於該第一介電層上形成至少一第二開口，其中，第二開口係對應設置於該第一開口之周緣側；於該介電層、電性接觸墊上形成金屬層，且該金屬層延伸至該第二開口的側壁上；以及形成銲料凸塊於該金屬層上。
由上可知，因為本發明之金屬層的外緣係對應位於各該環形開口的傾斜內側壁上，亦即該凸塊底下金屬層的外緣係傾斜向下且其上形成有銲料凸塊，又蝕刻液本身並不易往上方流動與蝕刻，所以可大幅減低最終蝕刻時的側蝕現象，並避免產生過度底切結構，進而改善整體結構的信賴性與可靠度。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「水平」、「內」、「周緣」、「外緣」、「頂」、「底」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第2A至2F圖，係本發明之封裝基板結構及其製法的剖視圖，其中，第2F’圖係第2F圖之另一實施態樣。
首先，如第2A圖所示，準備一表面201具有複數電性接觸墊202的基板20，該表面201上形成有第一子介電層21a，並令該第一子介電層21a形成有複數對應外露各該電性接觸墊202的介電層開口210，於本實施例中，該基板20係為半導體晶圓，且該第一子介電層21a可為一鈍化保護層，防止元件表面接觸空氣而劣化，以保護晶圓表面，其材質係為氮化矽(SiN)或氧化矽(SiOx)，但不以此為限。
如第2B圖所示，於該電性接觸墊202與第一子介電層21a上形成第二子介電層21b，於本實施例中，該第二子介電層21b之厚度係大於10微米，並於該第二子介電層21b中形成複數頂寬底窄如倒置梯形之開口之第一開口211與環形之第二開口212，其中，各該第一開口211係對應外露各該電性接觸墊202，各該第二開口212係對應環繞各該第一開口211周緣且外露出該第一子介電層21a，該第二子介電層21b之材質可為聚亞醯胺(polyimide，簡稱PI)或苯環丁烯(bis-Benzo-Cyclo-Butene，簡稱BCB)，該第二開口212之底端寬度W1至少為10微米，該第二開口212之頂端寬度W2至少為20微米，亦即該第二開口212的一斜邊的水平投影寬度W3約為5微米，但不以此為限。
再者，本步驟中係可僅形成一介電層21以取代該第一子介電層21a與第二子介電層21b，且該第二開口212並不一定要是環形，即亦可為其他形狀。
如第2C圖所示，於該第二子介電層21b、電性接觸墊202與第一子介電層21a上形成金屬層23，該金屬層23之材質可為鈦/銅(Ti/Cu)，即該金屬層23係包括依序層疊形成之鈦層23a與銅層23b，但不以此為限。
如第2D圖所示，於該金屬層23上形成具有複數阻層開孔240的阻層24，各該阻層開孔240係對應各該電性接觸墊202，且各該阻層開孔240之孔壁係對應位於各該第二開口212的內側壁上，亦即靠近該第一開口211的側壁上；接著，於各該阻層開孔240中的金屬層23上電鍍形成銲料凸塊25。
如第2E圖所示，移除該阻層24，並可進行回銲步驟。
如第2F圖所示，以該銲料凸塊25做為遮罩，蝕刻移除未被該銲料凸塊25所覆蓋之金屬層23，以於該銲料凸塊25底下定義出剖視圖狀似海鷗的凸塊底下金屬層23’；其中，該金屬層23’係覆蓋該電性接觸墊202的外露部分、該第一開口211之側壁、該第一開口211與第二開口212之間的第二子介電層21b之表面、及該第二開口212靠近第一開口211側之部份側壁或全部側壁(未圖示此情況)。
於本發明之另一實施態樣，如第2F’圖所示，提供一基板20，其上設置有複數電性接觸墊203，該基板20上可以覆蓋一層外露該電性接觸墊203的鈍化保護層26，該鈍化保護層26係由氮化矽(SiN)或氧化矽(SiOx)所形成，於該電性接觸墊203與鈍化保護層26上形成有一第一子介電層21a，其中該第一子介電層21a之材質可為聚亞醯胺(polyimide，簡稱PI)或苯環丁烯(bis-Benzo-Cyclo-Butene，簡稱BCB)，於該第一子介電層21a中形成有複數個介電層開口210，該介電層開口210係對應外露該基板20上之電性接觸墊203。之後於該介電層開口210及電性接觸墊203上形成一金屬層(未圖示)，該金屬層可由濺鍍一導電種子層後再進行電鍍以形成，並再經由圖案化之製程而形成線路重新分佈層200，該線路重新分佈層200之材質可為鈦/銅、鈦/銅/鎳或鈦/鎳釩/銅，該線路重新分佈層200係電性連接至該電性接觸墊203並向周圍延伸而具有另一電性接觸墊202，以增加線路布局之彈性。於該線路重新分佈層200上更設置有第二子介電層21b，該第二子介電層21b材質可為聚亞醯胺(polyimide，簡稱PI)或苯環丁烯(bis-Benzo-Cyclo-Butene，簡稱BCB)，但不以此為限。於相同實施概念下，該第二子介電層21b具有第一開口211，該第一開口211係設置於該電性接觸墊202上且暴露出部份該電性接觸墊202。於本實施例中，該第二子介電層21b之厚度係大於10微米，並於該第二子介電層21b中形成複數頂寬底窄如倒置梯形之開口之第一開口211與環形之第二開口212，其中，各該第一開口211係對應外露各該電性接觸墊202，各該第二開口212係對應環繞各該第一開口211周緣且外露出該第一子介電層21a，該第二開口212之底端寬度W1至少為10微米，該第二開口212之頂端寬度W2至少為20微米，亦即該第二開口212的一斜邊的水平投影寬度W3約為5微米，但不以此為限。之後，於該第二子介電層21b與電性接觸墊202上形成金屬層23’，該金屬層23’覆蓋該電性接觸墊202於第一開口211暴露之部份、第一開口211與第二開口212間之第二子介電層21b、及第二開口212之側壁，該金屬層23’之材質可為鈦/銅(Ti/Cu)，即該金屬層23’係包括依序層疊形成之鈦層23a與銅層23b，但不以此為限。於該金屬層23’上形成有銲料凸塊25。於本實施例中，該銲料凸塊25係為一無鉛之銲料，經過回銲後覆蓋該電性接觸墊202、第一開口211與第二開口212間之第二子介電層21b及第二開口212之側壁之金屬層23’，以於該銲料凸塊25底下定義出剖視圖狀似海鷗的凸塊底下金屬層23’。
本發明復揭露一種封裝基板結構，係包括：基板20，其一表面201具有至少一電性接觸墊202；介電層21，係形成於該基板20之表面201上，該介電層21具有至少一第一開口211與第二開口212，其中，該第一開口211係對應外露該電性接觸墊202，該第二開口212係對應設置於該第一開口211之周緣；以及金屬層23’，係對應形成於各該電性接觸墊202及其周圍的介電層21上，且延伸至該第二開口212的側壁上。
於前述之封裝基板結構中，復包括銲料凸塊25，係形成於該金屬層23’上。
所述之封裝基板結構中，該第二開口212係環設於該第一開口211之周緣，且該金屬層23’係連續包覆該電性接觸墊202、該第一開口211之側壁、該第一開口211與第二開口212間之部份介電層21及該第二開口212之側壁。
本實施例之封裝基板結構中，該第一開口211係為圓形，該第二開口212係為環形，且該第一開口211與該第二開口212係共圓心；此外，該介電層21係包括第一子介電層21a與第二子介電層21b，該第一子介電層21a係形成於該基板20之表面上，該第二子介電層21b係形成於該第一子介電層21a上，且具有該第一開口211與第二開口212，該第二開口212係暴露出部份之該第一子介電層21a。
於前述之封裝基板結構中，該基板20可為半導體晶圓，該第一子介電層21a之材質可為氮化矽(SiN)，且該第二子介電層21b之材質可為聚亞醯胺(polyimide，簡稱PI)或苯環丁烯(bis-Benzo-Cyclo-Butene，簡稱BCB)。
於本實施例之封裝基板結構中，該第二開口212之底端寬度W1至少為10微米，且該第二開口212之頂端寬度W2至少為20微米。
依上述之封裝基板結構中，該第二開口212係為頂寬底窄者，且該凸塊底下金屬層23’之材質可為鈦/銅(Ti/Cu)。
要注意的是，本發明之封裝基板結構係可為具有凸塊底下金屬層的封裝基板結構；此外，本發明之結構最終可覆晶(flip chip)接置於另一封裝基板上，或應用於晶圓級晶片尺寸封裝(wafer level chip scale package，簡稱WLCSP)上。
綜上所述，相較於習知技術，由於本發明之金屬層的外緣係對應位於各該第二開口的傾斜內側壁上，且蝕刻液本身不易往上方流動與蝕刻，因此可大幅減低蝕刻時的側蝕現象，並避免產生過度底切結構，進而改善整體結構的信賴性與可靠度。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
10．．．晶片
101,202,203．．．電性接觸墊
11．．．凸塊底下金屬層
11a,23a．．．鈦層
11b,23b．．．銅層
12,25．．．銲料凸塊
20．．．基板
200．．．線路重新分佈層
201．．．表面
21．．．介電層
21a．．．第一子介電層
21b．．．第二子介電層
210．．．介電層開口
211．．．第一開口
212．．．第二開口
23,23’．．．金屬層
24．．．阻層
240．．．阻層開孔
26．．．鈍化保護層
W1,W2,W3．．．寬度
第1圖係習知之具有凸塊底下金屬層的基板結構之剖視圖；以及
第2A至2F圖係本發明之封裝基板結構及其製法的剖視圖，其中，第2F’圖係第2F圖之另一實施態樣。
20．．．基板
201．．．表面
202．．．電性接觸墊
21．．．介電層
21a．．．第一子介電層
21b．．．第二子介電層
210．．．介電層開口
211．．．第一開口
212．．．第二開口
23a．．．鈦層
23b．．．銅層
23’．．．金屬層
25．．．銲料凸塊
W1,W2,W3．．．寬度

Claims (20)

  1. 一種封裝基板結構，係包括：基板，其一表面具有至少一電性接觸墊；介電層，係形成於該基板之表面上，該介電層具有至少一第一開口與第二開口，其中，該第一開口係對應外露該電性接觸墊，該第二開口係對應設置於該第一開口之周緣；以及金屬層，係對應形成於該電性接觸墊及該介電層上，且延伸至該第二開口的部分側壁上。
  2. 如申請專利範圍第1項所述之封裝基板結構，復包括銲料凸塊，係形成於該金屬層上。
  3. 如申請專利範圍第1項所述之封裝基板結構，其中，該第二開口係環設於該第一開口之周緣。
  4. 如申請專利範圍第1項所述之封裝基板結構，其中，該金屬層係連續包覆該電性接觸墊、該第一開口之側壁、該第一開口與第二開口間之部份介電層及該第二開口之側壁。
  5. 如申請專利範圍第1項所述之封裝基板結構，其中，該第一開口係為圓形，該第二開口係為環形，且該第一開口與該第二開口係共圓心。
  6. 如申請專利範圍第1項所述之封裝基板結構，其中，該介電層係包括第一子介電層與第二子介電層，該第一子介電層係形成於該基板之表面上，該第二子介電層係形成於該第一子介電層上，且具有該第一開口與第二開 口，該第二開口係暴露出部份之該第一子介電層。
  7. 如申請專利範圍第6項所述之封裝基板結構，其中，該第一子介電層之材質係為氮化矽(SiN)，且該第二子介電層之材質係為聚亞醯胺(polyimide，簡稱PI)或苯環丁烯(bis-Benzo-Cyclo-Butene，簡稱BCB)。
  8. 如申請專利範圍第1項所述之封裝基板結構，其中，該第二開口之底端寬度至少為10微米。
  9. 如申請專利範圍第1項所述之封裝基板結構，其中，該第二開口之頂端寬度至少為20微米。
  10. 如申請專利範圍第1項所述之封裝基板結構，其中，該第二開口係為頂寬底窄者。
  11. 如申請專利範圍第1項所述之封裝基板結構，其中，該金屬層之材質係為鈦/銅。
  12. 一種封裝基板結構之製法，係包括：提供一表面具有至少一電性接觸墊的基板，該表面上形成有介電層，且該介電層具有至少一對應外露該電性接觸墊的第一開口；於該介電層上形成至少一第二開口，其中，第二開口係對應設置於該第一開口之周緣；於該介電層、電性接觸墊上形成金屬層，且該金屬層延伸至該第二開口的側壁上；以及形成銲料凸塊於該電性接觸墊上之金屬層上。
  13. 如申請專利範圍第12項所述之封裝基板結構之製法，其中，形成該金屬層與銲料凸塊之步驟係包括： 於該金屬層上形成具有複數阻層開孔的阻層，各該阻層開孔係對應各該電性接觸墊，且各該阻層開孔之孔壁係對應位於各該第二開口的內側壁上；於各該阻層開孔中的金屬層上形成銲料凸塊；移除該阻層；以及蝕刻移除未被該銲料凸塊所覆蓋之金屬層。
  14. 如申請專利範圍第13項所述之封裝基板結構之製法，復包括於移除該阻層後，進行回銲步驟。
  15. 如申請專利範圍第12項所述之封裝基板結構之製法，其中，該介電層係包括第一子介電層與第二子介電層，該第一子介電層係形成於該基板之表面上，該第二子介電層係形成於該第一子介電層上，且具有該第一開口與第二開口，該第二開口係暴露出部份之該第一子介電層。
  16. 如申請專利範圍第15項所述之封裝基板結構之製法，其中，該第一子介電層之材質係為氮化矽(SiN)，且該第二子介電層之材質係為聚亞醯胺(polyimide，簡稱PI)或苯環丁烯(bis-Benzo-Cyclo-Butene，簡稱BCB)。
  17. 如申請專利範圍第12項所述之封裝基板結構之製法，其中，該第二開口之底端寬度至少為10微米。
  18. 如申請專利範圍第12項所述之封裝基板結構之製法，其中，該第二開口之頂端寬度至少為20微米。
  19. 如申請專利範圍第12項所述之封裝基板結構之製法，其中，該第二開口係為頂寬底窄者。
  20. 如申請專利範圍第12項所述之封裝基板結構之製法，其中，該金屬層之材質係為鈦/銅。
TW100140252A 2011-11-04 2011-11-04 封裝基板結構及其製法 TWI463621B (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
TW100140252A TWI463621B (zh) 2011-11-04 2011-11-04 封裝基板結構及其製法
CN2011103843157A CN103094243A (zh) 2011-11-04 2011-11-28 封装基板结构及其制法
US13/482,313 US20130113095A1 (en) 2011-11-04 2012-05-29 Packaging substrate and fabrication method thereof
US15/411,204 US10192838B2 (en) 2011-11-04 2017-01-20 Fabrication method of packaging substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW100140252A TWI463621B (zh) 2011-11-04 2011-11-04 封裝基板結構及其製法

Publications (2)

Publication Number Publication Date
TW201320269A TW201320269A (zh) 2013-05-16
TWI463621B true TWI463621B (zh) 2014-12-01

Family

ID=48206642

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100140252A TWI463621B (zh) 2011-11-04 2011-11-04 封裝基板結構及其製法

Country Status (3)

Country Link
US (2) US20130113095A1 (zh)
CN (1) CN103094243A (zh)
TW (1) TWI463621B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9349665B2 (en) * 2013-01-18 2016-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of packaging of semiconductor devices
US9349700B2 (en) * 2013-04-24 2016-05-24 Stats Chippac, Ltd. Semiconductor device and method of forming stress-reduced conductive joint structures
US10163828B2 (en) * 2013-11-18 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and fabricating method thereof
US10008461B2 (en) 2015-06-05 2018-06-26 Micron Technology, Inc. Semiconductor structure having a patterned surface structure and semiconductor chips including such structures
TWI669793B (zh) * 2016-04-27 2019-08-21 矽品精密工業股份有限公司 基板結構
KR102658923B1 (ko) * 2016-09-12 2024-04-18 삼성전자주식회사 반도체 장치 및 반도체 패키지
KR102698828B1 (ko) 2019-12-26 2024-08-26 삼성전자주식회사 패키지 기판 및 이를 포함하는 반도체 패키지
CN118676110A (zh) * 2024-08-23 2024-09-20 甬矽半导体(宁波)有限公司 衬底布线结构及其制备方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200636885A (en) * 2005-04-11 2006-10-16 Siliconware Precision Industries Co Ltd Semiconductor device and fabrication method thereof

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW448524B (en) * 1997-01-17 2001-08-01 Seiko Epson Corp Electronic component, semiconductor device, manufacturing method therefor, circuit board and electronic equipment
US5937320A (en) 1998-04-08 1999-08-10 International Business Machines Corporation Barrier layers for electroplated SnPb eutectic solder joints
TWI288447B (en) * 2005-04-12 2007-10-11 Siliconware Precision Industries Co Ltd Conductive bump structure for semiconductor device and fabrication method thereof
CN100580897C (zh) * 2007-02-05 2010-01-13 百慕达南茂科技股份有限公司 平顶凸块结构的制造方法
KR20080085380A (ko) * 2007-03-19 2008-09-24 삼성전자주식회사 재배선층을 구비하는 반도체 패키지 및 그의 제조방법
US7622737B2 (en) * 2007-07-11 2009-11-24 International Business Machines Corporation Test structures for electrically detecting back end of the line failures and methods of making and using the same
JP2009064812A (ja) * 2007-09-04 2009-03-26 Panasonic Corp 半導体装置の電極構造およびその関連技術

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200636885A (en) * 2005-04-11 2006-10-16 Siliconware Precision Industries Co Ltd Semiconductor device and fabrication method thereof

Also Published As

Publication number Publication date
TW201320269A (zh) 2013-05-16
US20130113095A1 (en) 2013-05-09
US10192838B2 (en) 2019-01-29
CN103094243A (zh) 2013-05-08
US20170133337A1 (en) 2017-05-11

Similar Documents

Publication Publication Date Title
TWI463621B (zh) 封裝基板結構及其製法
TWI496207B (zh) 積體電路封裝結構及其製造方法
US10074584B2 (en) Method of forming a semiconductor component comprising a second passivation layer having a first opening exposing a bond pad and a plurality of second openings exposing a top surface of an underlying first passivation layer
US9515038B2 (en) Electrical connection for chip scale packaging
US10340226B2 (en) Interconnect crack arrestor structure and methods
US8193639B2 (en) Dummy metal design for packaging structures
TWI567900B (zh) 半導體裝置及封裝組件
WO2011058680A1 (ja) 半導体装置
TWI502691B (zh) 導電結構及其形成方法
US11335659B2 (en) Semiconductor chip with patterned underbump metallization and polymer film
JP5262277B2 (ja) 半導体装置及び基板の接合方法
TWI579937B (zh) 基板結構及其製法暨導電結構
CN105229781B (zh) 使用电介质桥接器的电镀方法和电镀结构
JP5280650B2 (ja) 半導体装置
JP4812673B2 (ja) 半導体装置
JP3915670B2 (ja) 半導体装置およびその製造方法
JP5656301B2 (ja) 半導体装置
TWI599006B (zh) 凸塊底層金屬化層結構及其形成方法和重佈金屬化層結構
JP7414563B2 (ja) 半導体装置
JP2011035349A (ja) 半導体装置およびその製造方法
JP2018073968A (ja) 半導体装置及びその製造方法
TWI449144B (zh) 半導體封裝件及其基板
JP2011023568A (ja) 半導体装置及びその製造方法
JP2011034988A (ja) 半導体装置