CN103094243A - 封装基板结构及其制法 - Google Patents

封装基板结构及其制法 Download PDF

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Publication number
CN103094243A
CN103094243A CN2011103843157A CN201110384315A CN103094243A CN 103094243 A CN103094243 A CN 103094243A CN 2011103843157 A CN2011103843157 A CN 2011103843157A CN 201110384315 A CN201110384315 A CN 201110384315A CN 103094243 A CN103094243 A CN 103094243A
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China
Prior art keywords
opening
dielectric layer
package substrate
sub
metal level
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庄建隆
吴柏毅
李孟宗
姜亦震
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN103094243A publication Critical patent/CN103094243A/zh
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Abstract

一种封装基板结构及其制法，该封装基板结构包括基板、介电层与金属层，该基板的一表面具有至少一电性接触垫，该介电层形成于该基板的表面上，该介电层具有至少一第一开口与第二开口，其中，该第一开口对应外露该电性接触垫，该第二开口对应设置于该第一开口的周缘，该金属层对应形成于该电性接触垫及该介电层上，且延伸至该第二开口的侧壁上。相比于现有技术，本发明可有效减轻凸块底下金属层的外缘的侧蚀现象。

Description

封装基板结构及其制法
技术领域
本发明有关于一种基板结构及其制法，尤指一种封装基板结构及其制法。
背景技术
传统倒装芯片(flip chip)半导体封装技术主要通过于芯片的电性接触垫上形成焊料凸块(solder bump)，再通过该焊料凸块直接与封装基板电性连接，相比于打线(wire bonding)方式来说，倒装芯片技术的电路路径较短，具有较佳的电性品质，同时因可设计为晶背裸露形式，也可提高芯片散热性。
请参阅图1，其为现有例如第5,937,320号美国专利的具有凸块底下金属层的基板结构的剖视图，倒装芯片技术通过于芯片10上形成焊料凸块12前，先于芯片10的电性接触垫101上全面性地形成钛层11a与铜层11b，并于该电性接触垫101上方的铜层11b上形成焊料凸块12，最后再蚀刻移除未被该焊料凸块12所覆盖的钛层11a与铜层11b，以于该焊料凸块12底下定义出凸块底下金属层(Under BumpMetallurgy，简称UBM)11，并借由该凸块底下金属层11使该焊料凸块12牢固地接置于该芯片10的电性接触垫101上。
然而，现有使用层叠的钛层11a与铜层11b以构成凸块底下金属层11时，由于该钛层11a的蚀刻速度会大于铜层11b的蚀刻速度，因此该钛层11a的侧蚀情况严重，而造成如图1所示的显著底切(undercut)结构，该底切结构将会使应力集中，因而容易在该点断裂，导致整体信赖性不佳。
因此，如何避免上述现有技术中的种种问题，以避免凸块底下金属层因过度侧蚀而形成严重底切结构，进而提升产品可靠度与良率，实已成为目前亟欲解决的课题。
发明内容
有鉴于上述现有技术的缺失，本发明的主要目的在于提供一种封装基板结构及其制法，以有效减轻凸块底下金属层的外缘的侧蚀现象。
本发明所揭示的封装基板结构包括：基板，其一表面具有至少一电性接触垫；第一介电层，其形成于该基板的表面上，该第一介电层具有至少一第一开口与第二开口，其中，该第一开口对应外露该电性接触垫，该第二开口对应设置于该第一开口的侧周缘；凸块底下金属层，其对应形成于该电性接触垫及该第一介电层上，且延伸至该第二开口的侧壁上；以及焊料凸块，其形成于该凸块底下金属层上。
本发明还提供一种封装基板结构的制法，其包括：提供一表面具有至少一多个电性接触垫的基板，该表面上形成有第一介电层，且该第一介电层具有至少一对应外露该电性接触垫的第一开口；于该第一介电层上形成至少一第二开口，其中，第二开口对应设置于该第一开口的周缘侧；于该介电层、电性接触垫上形成金属层，且该金属层延伸至该第二开口的侧壁上；以及形成焊料凸块于该金属层上。
由上可知，因为本发明的金属层的外缘对应位于各该环形开口的倾斜内侧壁上，也就是该凸块底下金属层的外缘倾斜向下且其上形成有焊料凸块，而且蚀刻液本身并不易往上方流动与蚀刻，所以可大幅减低最终蚀刻时的侧蚀现象，并避免产生过度底切结构，进而改善整体结构的信赖性与可靠度。
附图说明
图1为现有的具有凸块底下金属层的基板结构的剖视图。
图2A至图2F为本发明的封装基板结构及其制法的剖视图，其中，图2F’为图2F的另一实施例。
主要组件符号说明
10            芯片
101，202，203 电性接触垫
11            凸块底下金属层
11a，23a      钛层
11b，23b   铜层
12，25     焊料凸块
20         基板
200        线路重新分布层
201        表面
21         介电层
21a        第一子介电层
21b        第二子介电层
210        介电层开口
211        第一开口
212        第二开口
23，23’   金属层
24         阻层
240        阻层开孔
26         钝化保护层
W1，W2，W3 宽度。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“水平”、“内”、“周缘”、“外缘”、“顶”、“底”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
请参阅图2A至图2F，其为本发明的封装基板结构及其制法的剖视图，其中，图2F’为图2F的另一实施例。
首先，如图2A所示，准备一表面201具有多个电性接触垫202的基板20，该表面201上形成有第一子介电层21a，并令该第一子介电层21a形成有多个对应外露各该电性接触垫202的介电层开口210，于本实施例中，该基板20为半导体晶片，且该第一子介电层21a可为一钝化保护层，防止组件表面接触空气而劣化，以保护晶片表面，其材质为氮化硅(SiN)或氧化硅(SiOx)，但不以此为限。
如图2B所示，于该电性接触垫202与第一子介电层21a上形成第二子介电层21b，于本实施例中，该第二子介电层21b的厚度大于10微米，并于该第二子介电层21b中形成多个顶宽底窄如倒置梯形的开口的第一开口211与环形的第二开口212，其中，各该第一开口211对应外露各该电性接触垫202，各该第二开口212对应环绕各该第一开口211周缘且外露出该第一子介电层21a，该第二子介电层21b的材质可为聚亚醯胺(polyimide，简称PI)或苯环丁烯(bis-Benzo-Cyclo-Butene，简称BCB)，该第二开口212的底端宽度W1至少为10微米，该第二开口212的顶端宽度W2至少为20微米，也就是该第二开口212的一斜边的水平投影宽度W3约为5微米，但不以此为限。
此外，本步骤中可仅形成一介电层21以取代该第一子介电层21a与第二子介电层21b，且该第二开口212并不一定要是环形，也可为其它形状。
如图2C所示，于该第二子介电层21b、电性接触垫202与第一子介电层21a上形成金属层23，该金属层23的材质可为钛/铜(Ti/Cu)，即该金属层23包括依序层叠形成的钛层23a与铜层23b，但不以此为限。
如图2D所示，于该金属层23上形成具有多个阻层开孔240的阻层24，各该阻层开孔240对应各该电性接触垫202，且各该阻层开孔240的孔壁对应位于各该第二开口212的内侧壁上，也就是靠近该第一开口211的侧壁上；接着，于各该阻层开孔240中的金属层23上电镀形成焊料凸块25。
如图2E所示，移除该阻层24，并可进行回焊步骤。
如图2F所示，以该焊料凸块25做为屏蔽，蚀刻移除未被该焊料凸块25所覆盖的金属层23，以于该焊料凸块25底下定义出剖视图状似海鸥的凸块底下金属层23’；其中，该金属层23’覆盖该电性接触垫202的外露部分、该第一开口211的侧壁、该第一开口211与第二开口212之间的第二子介电层21b的表面、及该第二开口212靠近第一开口211侧的部份侧壁或全部侧壁(未图标此情况)。
于本发明的另一实施例，如图2F’所示，提供一基板20，其上设置有多个电性接触垫203，该基板20上可以覆盖一层外露该电性接触垫203的钝化保护层26，该钝化保护层26是由氮化硅(SiN)或氧化硅(SiOx)所形成，于该电性接触垫203与钝化保护层26上形成有一第一子介电层21a，其中该第一子介电层21a的材质可为聚亚醯胺(polyimide，简称PI)或苯环丁烯(bis-Benzo-Cyclo-Butene，简称BCB)，于该第一子介电层21a中形成有多个介电层开口210，该介电层开口210对应外露该基板20上的电性接触垫203。之后于该介电层开口210及电性接触垫203上形成一金属层(未图标)，该金属层可由溅镀一导电种子层后再进行电镀以形成，并再经由图案化的工艺而形成线路重新分布层200，该线路重新分布层200的材质可为钛/铜、钛/铜/镍或钛/镍钒/铜，该线路重新分布层200电性连接至该电性接触垫203并向周围延伸而具有另一电性接触垫202，以增加线路布局的弹性。于该线路重新分布层200上更设置有第二子介电层21b，该第二子介电层21b的材质可为聚亚醯胺(polyimide，简称PI)或苯环丁烯(bis-Benzo-Cyclo-Butene，简称BCB)，但不以此为限。于相同实施概念下，该第二子介电层21b具有第一开口211，该第一开口211设置于该电性接触垫202上且暴露出部份该电性接触垫202。于本实施例中，该第二子介电层21b的厚度大于10微米，并于该第二子介电层21b中形成多个顶宽底窄如倒置梯形的开口的第一开口211与环形的第二开口212，其中，各该第一开口211对应外露各该电性接触垫202，各该第二开口212对应环绕各该第一开口211周缘且外露出该第一子介电层21a，该第二开口212的底端宽度W1至少为10微米，该第二开口212的顶端宽度W2至少为20微米，也就是该第二开口212的一斜边的水平投影宽度W3约为5微米，但不以此为限。之后，于该第二子介电层21b与电性接触垫202上形成金属层23’，该金属层23’覆盖该电性接触垫202于第一开口211暴露的部份、第一开口211与第二开口212间的第二子介电层21b、及第二开口212的侧壁，该金属层23’的材质可为钛/铜(Ti/Cu)，即该金属层23’包括依序层叠形成的钛层23a与铜层23b，但不以此为限。于该金属层23’上形成有焊料凸块25。于本实施例中，该焊料凸块25为一无铅的焊料，经过回焊后覆盖该电性接触垫202、第一开口211与第二开口212间的第二子介电层21b及第二开口212的侧壁的金属层23’，以于该焊料凸块25底下定义出剖视图状似海鸥的凸块底下金属层23’。
本发明还揭露一种封装基板结构，包括：基板20，其一表面201具有至少一电性接触垫202；介电层21，其形成于该基板20的表面201上，该介电层21具有至少一第一开口211与第二开口212，其中，该第一开口211对应外露该电性接触垫202，该第二开口212对应设置于该第一开口211的周缘；以及金属层23’，其对应形成于各该电性接触垫202及其周围的介电层21上，且延伸至该第二开口212的侧壁上，于本实施例中，金属层23’仅包覆部份第二开口212靠近电性接触垫侧的内缘侧壁，并暴露出第二开口212的底面及与与靠近电性接触垫的相反另一侧的外侧壁，且金属层23’仅包覆第二开口212的内缘侧壁上半部，并暴露出内缘侧壁的下半部。
于前述的封装基板结构中，还包括焊料凸块25，其形成于该金属层23’上。
所述的封装基板结构中，该第二开口212环设于该第一开口211的周缘，且该金属层23’连续包覆该电性接触垫202、该第一开口211的侧壁、该第一开口211与第二开口212间的部份介电层21及该第二开口212的侧壁。
本实施例的封装基板结构中，该第一开口211为圆形，该第二开口212为环形，且该第一开口211与该第二开口212共圆心；此外，该介电层21包括第一子介电层21a与第二子介电层21b，该第一子介电层21a形成于该基板20的表面上，该第二子介电层21b形成于该第一子介电层21a上，且具有该第一开口211与第二开口212，该第二开口212暴露出部份的该第一子介电层21a。
于前述的封装基板结构中，该基板20可为半导体晶片，该第一子介电层21a的材质可为氮化硅(SiN)，且该第二子介电层21b的材质可为聚亚醯胺(polyimide，简称PI)或苯环丁烯(bis-Benzo-Cyclo-Butene，简称BCB)。
于本实施例的封装基板结构中，该第二开口212的底端宽度W1至少为10微米，且该第二开口212的顶端宽度W2至少为20微米。
依上述的封装基板结构中，该第二开口212为顶宽底窄，且该凸块底下金属层23’的材质可为钛/铜(Ti/Cu)。
要注意的是，本发明的封装基板结构可为具有凸块底下金属层的封装基板结构；此外，本发明的结构最终以倒装芯片(flip chip)技术接置于另一封装基板上，或应用于晶片级芯片尺寸封装(wafer levelchip scale package，简称WLCSP)上。
综上所述，相比于现有技术，由于本发明的金属层的外缘对应位于各该第二开口的倾斜内侧壁上，而且蚀刻液本身不易往上方流动与蚀刻，因此可大幅减低蚀刻时的侧蚀现象，并避免产生过度底切结构，进而改善整体结构的信赖性与可靠度。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (16)

1.一种封装基板结构，其包括：
基板，其一表面具有至少一电性接触垫；
介电层，其形成于该基板的表面上，该介电层具有至少一第一开口与第二开口，其中，该第一开口对应外露该电性接触垫，该第二开口对应设置于该第一开口的周缘；以及
金属层，其对应形成于该电性接触垫及该介电层上，且延伸至该第二开口的侧壁上。
2.根据权利要求1所述的封装基板结构，其特征在于，该封装基板结构还包括焊料凸块，其形成于该金属层上。
3.根据权利要求1所述的封装基板结构，其特征在于，该第二开口环设于该第一开口的周缘。
4.根据权利要求1所述的封装基板结构，其特征在于，该金属层连续包覆该电性接触垫、该第一开口的侧壁、该第一开口与第二开口间的部份介电层及该第二开口的侧壁。
5.根据权利要求1所述的封装基板结构，其特征在于，该第一开口为圆形，该第二开口为环形，且该第一开口与该第二开口为共圆心。
6.根据权利要求1所述的封装基板结构，其特征在于，该介电层包括第一子介电层与第二子介电层，该第一子介电层形成于该基板的表面上，该第二子介电层形成于该第一子介电层上，且具有该第一开口与第二开口，该第二开口暴露出部份的该第一子介电层。
7.根据权利要求1所述的封装基板结构，其特征在于，该第二开口的底端宽度至少为10微米。
8.根据权利要求1所述的封装基板结构，其特征在于，该第二开口的顶端宽度至少为20微米。
9.根据权利要求1所述的封装基板结构，其特征在于，该第二开口为顶宽底窄。
10.一种封装基板结构的制法，其包括：
提供一表面具有至少一电性接触垫的基板，该表面上形成有介电层，且该介电层具有至少一对应外露该电性接触垫的第一开口；
于该介电层上形成至少一第二开口，其中，第二开口对应设置于该第一开口的周缘；
于该介电层、电性接触垫上形成金属层，且该金属层延伸至该第二开口的侧壁上；以及
形成焊料凸块于该金属层上。
11.根据权利要求10所述的封装基板结构的制法，其特征在于，形成该金属层与焊料凸块的步骤包括：
于该金属层上形成具有多个阻层开孔的阻层，各该阻层开孔对应各该电性接触垫，且各该阻层开孔的孔壁对应位于各该第二开口的内侧壁上；
于各该阻层开孔中的金属层上形成焊料凸块；
移除该阻层；以及
蚀刻移除未被该焊料凸块所覆盖的金属层。
12.根据权利要求11所述的封装基板结构的制法，其特征在于，该制法还包括于移除该阻层后，进行回焊步骤。
13.根据权利要求10所述的封装基板结构的制法，其特征在于，该介电层包括第一子介电层与第二子介电层，该第一子介电层形成于该基板的表面上，该第二子介电层形成于该第一子介电层上，且具有该第一开口与第二开口，该第二开口暴露出部份的该第一子介电层。
14.根据权利要求10所述的封装基板结构的制法，其特征在于，该第二开口的底端宽度至少为10微米。
15.根据权利要求10所述的封装基板结构的制法，其特征在于，该第二开口的顶端宽度至少为20微米。
16.根据权利要求10所述的封装基板结构的制法，其特征在于，该第二开口为顶宽底窄。
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Families Citing this family (7)

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Publication number Priority date Publication date Assignee Title
US9349665B2 (en) * 2013-01-18 2016-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of packaging of semiconductor devices
US9349700B2 (en) * 2013-04-24 2016-05-24 Stats Chippac, Ltd. Semiconductor device and method of forming stress-reduced conductive joint structures
US10163828B2 (en) * 2013-11-18 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and fabricating method thereof
US10008461B2 (en) 2015-06-05 2018-06-26 Micron Technology, Inc. Semiconductor structure having a patterned surface structure and semiconductor chips including such structures
TWI669793B (zh) * 2016-04-27 2019-08-21 矽品精密工業股份有限公司 基板結構
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060226542A1 (en) * 2005-04-11 2006-10-12 Siliconware Precision Industries Co., Ltd. Semiconductor device and fabrication method thereof
CN101241865A (zh) * 2007-02-05 2008-08-13 百慕达南茂科技股份有限公司 平顶凸块结构及其制造方法
US20080230877A1 (en) * 2007-03-19 2008-09-25 Samsung Electronics Co., Ltd. Semiconductor package having wire redistribution layer and method of fabricating the same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW448524B (en) * 1997-01-17 2001-08-01 Seiko Epson Corp Electronic component, semiconductor device, manufacturing method therefor, circuit board and electronic equipment
US5937320A (en) 1998-04-08 1999-08-10 International Business Machines Corporation Barrier layers for electroplated SnPb eutectic solder joints
TWI288447B (en) * 2005-04-12 2007-10-11 Siliconware Precision Industries Co Ltd Conductive bump structure for semiconductor device and fabrication method thereof
US7622737B2 (en) * 2007-07-11 2009-11-24 International Business Machines Corporation Test structures for electrically detecting back end of the line failures and methods of making and using the same
JP2009064812A (ja) * 2007-09-04 2009-03-26 Panasonic Corp 半導体装置の電極構造およびその関連技術

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060226542A1 (en) * 2005-04-11 2006-10-12 Siliconware Precision Industries Co., Ltd. Semiconductor device and fabrication method thereof
CN101241865A (zh) * 2007-02-05 2008-08-13 百慕达南茂科技股份有限公司 平顶凸块结构及其制造方法
US20080230877A1 (en) * 2007-03-19 2008-09-25 Samsung Electronics Co., Ltd. Semiconductor package having wire redistribution layer and method of fabricating the same

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