CN107452693A - 封装结构 - Google Patents

封装结构 Download PDF

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Publication number
CN107452693A
CN107452693A CN201611024524.XA CN201611024524A CN107452693A CN 107452693 A CN107452693 A CN 107452693A CN 201611024524 A CN201611024524 A CN 201611024524A CN 107452693 A CN107452693 A CN 107452693A
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China
Prior art keywords
separator
encapsulating structure
rotating fields
layer
ubm
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Granted
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CN201611024524.XA
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CN107452693B (zh
Inventor
杨天中
苏安治
陈宪伟
王若梅
陈威宇
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
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Abstract

揭露封装结构、叠层封装器件及其形成方法。一种封装结构包括第一晶粒、重布线层结构、多个UBM接垫、多个接点以及分隔件。重布线层结构电性连接至第一晶粒。UBM接垫电性连接至重布线层结构。接点电性连接至UBM接垫。分隔件位于重布线层结构上方且环绕接点。

Description

封装结构
技术领域
本发明实施例是关于封装结构、叠层封装器件及其形成方法。
背景技术
近年来，由于各种电子组件(例如晶体管、二极管、电阻器、电容器等)的集成密度不断提升，半导体工业因而快速成长。这种集成密度的提升，大多是因为最小特征尺寸的持续缩小，因而允许将更多的组件整合在一特定的区域中。
相较于先前的封装件，这些尺寸较小的电子组件占据较小的面积，因而需要较小的封装件。用于半导体的封装件的类型的实例包括四方扁平封装(quad flat pack；QFP)、针格阵列(pin grid array；PGA)、球格阵列(ball grid array；BGA)、覆晶(flip chip；FC)、三维集成电路(three dimensional integrated circuit；3DIC)、晶圆级封装(waferlevel package；WLP)以及叠层封装(package on package；PoP)器件。在半导体晶圆级上将晶粒置放于晶粒上来制备一些三维集成电路。由于堆叠晶粒之间的内连线长度的减少，这些三维集成电路提供了改良的集成密度以及其他优势，例如较快的速度和较高的带宽(bandwidth)等。然而，仍存在许多与三维集成电路相关的挑战。
发明内容
根据本发明的一些实施例，一种封装结构包括第一晶粒、重布线层结构、多个凸点下金属(under-ball metallurgy；UBM)接垫、多个接点以及分隔件(separator)。重布线层结构电性连接至第一晶粒。UBM接垫电性连接至重布线层结构。接点电性连接至UBM接垫。分隔件位于重布线层结构上方且环绕接点。
附图说明
图1A至图1F为根据一些实施例所示出的叠层封装器件的形成方法的横截面示意图。
图2为图1B的简化上视图。
图3为图1E的区域A的放大图。
图4为根据一些实施例所示出的叠层封装器件的形成方法的流程图。
图5至图7为根据一些实施例所示出的叠层封装器件的横截面示意图。
图8A至图8F为根据其他实施例所示出的叠层封装器件的形成方法的横截面示意图。
图9为图8B的简化上视图。
图10为图8E的区域A的放大图。
图11为根据其他实施例所示出的叠层封装器件的形成方法的流程图。
图12至图15为根据其他实施例所示出的叠层封装器件的横截面示意图。
图16为根据又一些其他实施例所示出的叠层封装器件的形成方法的流程图。
图17至图21为根据又一些其他实施例所示出的叠层封装器件的横截面示意图。
具体实施方式
以下揭露内容提供许多不同的实施例或实例，用于实现所提供标的物的不同特征。以下所描述的构件及配置的具体实例是为了以简化的方式传达本揭露为目的。当然，这些仅仅为实例而非用以限制。举例来说，于以下描述中，在第一特征上方或在第一特征上形成第二特征可包括第二特征与第一特征形成为直接接触的实施例，且亦可包括第二特征与第一特征之间可形成有额外特征使得第二特征与第一特征可不直接接触的实施例。此外，本揭露在各种实例中可使用相同的器件符号和/或字母来指代相同或类似的部件。器件符号的重复使用是为了简单及清楚起见，且并不表示所欲讨论的各个实施例和/或配置本身之间的关系。
另外，为了易于描述附图中所示出的一个构件或特征与另一构件或特征的关系，本文中可使用例如「在…下」、「在…下方」、「下部」、「在…上」、「在…上方」、「上部」及类似术语的空间相对术语。除了附图中所示出的定向之外，所述空间相对术语意欲涵盖器件在使用或操作时的不同定向。设备可被另外定向(旋转90度或在其他定向)，而本文所用的空间相对术语相应地做出解释。
图1A至图1F为根据一些实施例所示出的叠层封装器件的形成方法的横截面示意图。
请参照图1A，提供载板C，其中载板C具有晶粒100以及多个集成扇出型穿孔(through integrated fan-out vias；through InFO vias)TIV，且集成扇出型穿孔TIV位于晶粒100侧边。在一些实施例中，集成扇出型穿孔TIV称为封装件穿孔(through packagevias；TPV)或界面穿孔(through interface vias)。在一些实施例中，载板C具有形成于其上的剥离层DB以及介电层101，且剥离层DB位于载板C与介电层101之间。在一些实施例中，载板C为玻璃衬底，形成于玻璃衬底上的剥离层DB为光热转换(light-to-heatconversion；LTHC)释放层，且形成于剥离层上的介电层101为聚合物层。举例来说，介电层101包括聚苯并恶唑(polybenzoxazole；PBO)、聚酰亚胺(polyimide；PI)、合适的有机或无机材料或类似物。在一些实施例中，晶粒100具有衬底100a、位于衬底100a上方的接垫100b、位于衬底100a上方且裸露出部分接垫100b的钝化层100c、位于钝化层100c上方且电性连接至接垫100b的接点100d，以及位于钝化层100c上方且位于接点100d侧边的保护层100e。在一些实施例中，接点100d包括锡凸块、金凸块、铜柱或类似物，且由电镀工艺所形成。在一些实施例中，保护层100e包括聚苯并恶唑(PBO)、聚酰亚胺(PI)、合适的有机或无机材料或类似物。在一些实施例中，集成扇出型穿孔TIV包括铜、镍、锡、其组合或类似物，且由电镀工艺所形成。在一些实施例中，取放晶粒100于载板C上之前，于载板C上形成集成扇出型穿孔TIV。在替代性实施例中，取放晶粒100于载板C上之后，于载板C上形成集成扇出型穿孔TIV。
请继续参照图1A，于载板C上方形成封装体102，以囊封晶粒100以及集成扇出型穿孔TIV。在一些实施例中，封装体102环绕晶粒100以及集成扇出型穿孔TIV，且裸露出集成扇出型穿孔TIV以及接点100d的表面。封装体102包括模制化合物(例如环氧树脂)、光敏材料(例如PBO)、聚酰亚胺(PI)或苯环丁烯(benzocyclobutene；BCB)、其组合或类似物。封装体102的形成方法包括：于载板C上形成封装体材料层(未示出)，且所述封装体材料层覆盖半导体晶粒100以及集成扇出型穿孔TIV；以及进行研磨工艺以移除部分所述封装体材料层，直到裸露出集成扇出型穿孔TIV以及接点100d的表面。
请参照图1B，于晶粒100上方形成重布线层结构117，且重布线层结构117电性连接至晶粒100。在一些实施例中，重布线层结构117包括交替堆叠的多个聚合物层104、108、112以及116以及多个重布线层106、110以及114。具体地说，重布线层106电性连接至接点100d以及集成扇出型穿孔TIV且穿过聚合物层104，重布线层110电性连接至重布线层106且穿过聚合物层108，重布线层114电性连接至重布线层110且穿过聚合物层112，以及聚合物层116覆盖重布线层114。在一些实施例中，聚合物层104、108、112以及116中的每一者包括光敏材料(例如PBO)、聚酰亚胺(PI)、苯环丁烯(BCB)、其组合或类似物。在一些实施例中，重布线层106、110以及114中的每一者包括铜、镍、钛、其组合或类似物，且由电镀工艺所形成。本发明实施例并不对聚合物层或重布线层的数目做限制。
请继续参照图1B，形成多个凸点下金属(UBM)接垫118以及分隔件119，其中分隔件119位于UBM接垫118侧边。UBM接垫118经配置以用于植球。于电磁干扰层(electromagneticinterference layer)的形成步骤期间，分隔件119配置成将一结构与固持所述结构的托盘分开，细节将详述于下。在一些实施例中，UBM接垫118以及分隔件119由相同材料所构成、提供为具有实质上相等的厚度，且于相同工艺步骤中同时形成。具体地说，UBM接垫118以及分隔件119中的每一者包括铜、镍、钛、其组合或类似物，且由电镀工艺所形成。在一些实施例中，UBM接垫118以及分隔件119由相同光掩模(photolithography reticle、photomask)所定义。也就是说，不需要用于定义分隔件119的额外光掩模。
然后，于UBM接垫118上方形成凸块、焊球或接点120，且接点120电性连接至UBM接垫118。在一些实施例中，接点120由具有低阻值的导电材料所构成，例如锡、铅、银、铜、镍、铋或其合金，且由合适的工艺所形成，例如蒸镀、电镀、落球(ball drop)、或网印(screenprinting)。在一些实施例中，分隔件119为环状且环绕最外面UBM接垫118或接点120，如图2的上视图所示。在一些实施例中，分隔件119处于浮动电位(floating potential)且电性绝缘于重布线层结构117以及接点120。
请参照图1C以及图1D，载板C从封装结构P1的背侧剥离，且另一封装结构P2接合至相同封装结构P1的相同背侧。
如图1C所示，载板C连同晶粒100、重布线层结构117，UBM接垫118、分隔件119以及接点120一起翻转，剥离层DB于光热作用下分解，接着，载板C从封装结构P1剥离。
如图1D所示，提供另一封装结构P2。在一些实施例中，封装结构P2具有衬底203以及安装于衬底203的一表面(例如，顶表面)上的晶粒201。打线207可用于提供晶粒201与位于衬底203的顶表面部分中的一组接合垫205之间的电性连接。于这些构件上方形成封装体209，以保护所述构件免于环境及外来污染。穿孔或集成扇出型穿孔(未示出)可用于提供接合垫205与位于衬底203的底表面部分中的另一组接合垫211之间的电性连接。接点214(例如焊料接点)可形成于衬底203的底表面上以电性连接至接合垫211。
将封装结构P2接合至封装结构P1，以形成接合结构(bonded structure)。在一些实施例中，封装结构P2的接点214对准并插入介电层101中的开口，且电性连接至封装结构P1的集成扇出型穿孔TIV。
然后，形成底胶层UF以填入封装结构P1与封装结构P2之间的空间，且底胶层UF环绕接点214。在一些实施例中，底胶层UF包括模制化合物(例如环氧树脂)，且使用点胶(dispensing)、注入(injecting)，和/或喷洒(spraying)技术来形成。
请参照图1E，将包括封装结构P1以及封装结构P2的接合结构置放于托盘(tray)T上，其中分隔件119抵靠托盘T的表面，并形成电磁干扰层EMI以覆盖封装结构P1以及封装结构P2的外表面或裸露出的表面。电磁干扰层EMI经配置以减少或避免电磁波的发射，且因此减低器件的噪声和/或器件的失效。在一些实施例中，形成电磁干扰层EMI以覆盖第二封装结构P2的顶面以及侧面，且电磁干扰层EMI电性连接至第一封装结构P1的重布线层结构117的重布线层106、110以及114。在一些实施例中，电磁干扰层EMI包括铝、铝合金、铜、铜合金、钛、氮化钛、钽、氮化钽、钨、金属硅化物、其组合或类似物，且由溅镀或合适的技术所形成。在一些实施例中，电磁干扰层EMI仅位于封装结构P1以及封装结构P2的裸露出的顶面以及侧面上方，而未延伸至封装结构P1下方。在替代性实施例中，电磁干扰层EMI可更延伸围绕封装结构P1的底角，并以逐渐减少的厚度从封装结构P1的外侧往内侧沿着聚合物层116的表面延伸，且此厚度相当小。也就是说，电磁干扰层EMI的很少一部分(即使有的话)形成为沿着聚合物层116的表面，且此部分如此薄而不会与托盘T接触。
请参照图1F，于形成电磁干扰层EMI之后，从托盘T取起本发明实施例的叠层封装器件1。
请注意，当形成电磁干扰层EMI时，本发明实施例的分隔件119扮演着将接合结构与托盘T分开的角色。于EMI形成步骤期间，此种分开有助于避免产生现有的EMI毛边(burr)，且因此改良器件效能。
具体地说，于现有的EMI形成步骤期间，将接合结构置放于EMI托盘上但没有两者间的分隔件，因此所形成的EMI层会沿着接合结构的外表面溅镀，且会连续不断地溅镀至托盘的表面上。在此情况下，当此接合结构从EMI托盘取起时，会产生现有的EMI毛边。此外，为了避免所形成的EMI层接触下封装结构的最外面接点，从下封装结构的边缘至其最外面接点的排除区(keep out zone；KOZ)通常大于约300μm。
然而，通过配置本发明实施例的位于托盘T与封装结构P1(如图1E以及图1F所示)之间的分隔件119，不会产生现有的EMI毛边，且用于EMI遮蔽(shielding)的排除区(KOZ)可大幅减少至100μm或小于100μm。
如图3中区域A的放大图所示，从最外面UBM接垫118至分隔件119的内边界的距离为“d”，分隔件119的宽度为“W”，分隔件119的高度为“H”，且从封装结构P1的边缘至分隔件119的外边界的距离为“D”。上述参数“d”、“W”、“D”以及“H”之间的比率必须在特定范围内方能达到所提及的效果。
此外，封装结构P1与托盘T之间的分开距离为“S”。在一些实施例中，分开距离(“S”)为从分隔件119的裸露出的表面至重布线层结构117的裸露出的表面的垂直距离。当封装结构P1与托盘T之间的分开距离(“S”)增加时，电磁干扰层EMI接触托盘T的机会变小。在一些实施例中，分开距离(“S”)等于分隔件119的高度(“H”)，如图3所示。
在一些实施例中，d与W的比率为约1:1至1:10。举例来说，d与W的比率可为约1、1/2、1/3、1/4、1/5、1/6、1/7、1/8、1/9、1/10，包括任意两个前述数值之间的任何范围。
在一些实施例中，d与H的比率为约1:1至1:10。举例来说，d与H的比率可为约1、1/2、1/3、1/4、1/5、1/6、1/7、1/8、1/9、1/10，包括任意两个前述数值之间的任何范围。
在一些实施例中，封装结构P1的边缘具有实质上垂直的轮廓，分隔件119的外边界未对齐于封装结构P1的边缘，且d与D的比率为约1:0.1至1:5。举例来说，d与D的比率的边缘可为约10、9、8、7、6、5、4、3、2、1、1/2、1/3、1/4、1/5、包括任意两个前述数值之间的任何范围。然而，本发明实施例并不以此为限。在替代性实施例中，封装结构P1-1/P1-2/P1-3的边缘具有阶梯状轮廓(例如单阶梯轮廓)，且分隔件119的外边界对齐于封装结构P1-1/P1-2/P1-3的相邻边缘，如图5至图7所示。也就是说，从封装结构P1-1/P1-2/P1-3的相邻边缘至分隔件119的外边界的距离(“D”)约为零。在又一些替代性实施例中，封装结构的边缘具有阶梯状轮廓(例如多阶梯轮廓)，且分隔件119的外边界对齐于封装结构的阶梯状边缘的邻接部分。
在一些实施例中，修改图1B的步骤使得所形成的聚合物层116裸露出重布线层114的边缘部分，并执行类似于图1C至图1F中所描述的步骤。因此，如图5所示，提供了包括封装结构P1-1以及封装结构P2的叠层封装器件2，其中分隔件119的外边界对齐于封装结构P1-1的重布线层结构117的聚合物层116的边缘，且电磁干扰层EMI电性连接至重布线层结构117的重布线层106、110以及114。如图5所示，分开距离(“S”)为从分隔件119的裸露出的表面至重布线层结构117的重布线层114的裸露出的表面的垂直距离，且分开距离(“S”)大于分隔件119高度(“H”)。
在一些实施例中，修改图1B的步骤使得所形成的聚合物层116、重布线层114以及聚合物层112均裸露出重布线层110的边缘部分，并执行类似于图1C至图1F中所描述的步骤。因此，如图6所示，提供了包括封装结构P1-2以及封装结构P2的叠层封装器件3，其中分隔件119的外边界对齐于封装结构P1-2的重布线层结构117的聚合物层116、重布线层114以及聚合物层112的边缘，且电磁干扰层EMI电性连接至重布线层结构117的重布线层106以及110。如图6所示，分开距离(“S”)为从分隔件119的裸露出的表面至重布线层结构117的重布线层110的裸露出的表面的垂直距离，且分开距离(“S”)大于分隔件119的高度(“H”)。
在一些实施例中，改图1B的步骤使得所形成的聚合物层116、重布线层114、聚合物层112、重布线层110以及聚合物层108均裸露出重布线层106的边缘部分，并执行类似于图1C至图1F中所描述的步骤。因此，如图7所示，提供了包括封装结构P1-3以及封装结构P2的叠层封装器件4，其中分隔件119的外边界对齐于封装结构P1-3的重布线层结构117的聚合物层116、重布线层114、聚合物层112、重布线层110以及聚合物层108的边缘，且电磁干扰层EMI电性连接至重布线层结构117的重布线层106。如图7所示，分开距离(“S”)为从分隔件119的裸露出的表面至重布线层结构117的重布线层106的裸露出的表面的垂直距离，且分开距离(“S”)大于分隔件119的高度(“H”)。
上述图1A至图1F的工艺步骤可参照图4的流程图精简说明如下。
于步骤300，于第一晶粒(例如，晶粒100)上方形成重布线层结构117，其中重布线层结构117电性连接至第一晶粒，如图1A、图1B以及图5至图7所示。于步骤302，形成多个UBM接垫118以及分隔件119，其中分隔件119环绕UBM接垫118，且UBM接垫118电性连接至重布线层结构117，如图1B以及图5至图7所示。于步骤304，于UBM接垫118上方形成多个接点120，且因此提供第一封装结构(例如，封装结构P1/P1-1/P1-2/P1-3)，如图1B、图1C以及图5至图7所示。于步骤306，将包括第二晶粒(例如，晶粒201)的第二封装结构(例如，封装结构P2)接合至第一封装结构，如图1D以及图5至图7所示。于步骤308中，形成电磁干扰层EMI以覆盖第一封装结构以及第二封装结构的裸露出的顶面以及侧面，如图1E、图1F以及图5至图7所示。由此完成本发明实施例的叠层封装器件1/2/3/4。
在上述的实施例中，分隔件以及UBM接垫于相同工艺步骤中同时形成，但本发明实施例并不限于此。在替代性实施例中，分隔件以及UBM接垫可于不同工艺步骤中分开形成。举例来说，可于形成UBM接垫的步骤之后或之前，形成分隔件。
图8A至图8F为根据其他实施例所示出的叠层封装器件的形成方法的横截面示意图。图9为图8B的简化上视图。图10为图8E的区域A的放大图。图11为根据其他实施例所示出的叠层封装器件的形成方法的流程图。
图8A至图8F的方法与图1A至图1F的方法之间的差异在于：分隔件的形成方法。差异处将详述如下，相同处则不再赘述。
请参照图8A、图11以及图12至图15，于步骤500中，于第一晶粒(例如，晶粒100)上方形成重布线层结构117，其中重布线层结构117电性连接至第一晶粒。
在一些实施例中，重布线层结构117的边缘具有实质上垂直的轮廓，如图8A以及图12所示。在替代性实施例中，可依先前描述方式修改形成重布线层结构117的步骤，使重布线层结构117的边缘具有阶梯状轮廓，且依工艺需要裸露出重布线层114、110或106的表面，如图13至图15所示。
然后，于步骤502中，于重布线层结构117上方形成多个UBM接垫118，其中UBM接垫118电性连接至重布线层结构117。接着，于步骤504中，于UBM接垫118上方形成多个接点120。
请参照图8B、图8C、图11以及图12至图15，于步骤506中，于形成接点120的步骤之后，形成环绕接点120的分隔件400，且因此提供第一封装结构(例如，封装结构P1-4/P1-5/P1-6/P1-7/P1-8)。如图9的上视图所示，分隔件400为环状且环绕最外面UBM接垫118或接点120。在一些实施例中，分隔件400为聚合物坝(polymer dam)，其包括模制化合物(例如环氧树脂)、光敏材料(例如PBO)、聚酰亚胺(PI)或苯环丁烯(BCB)、其组合或类似物。使用点胶、注入，和/或喷洒技术来形成分隔件400。在一些实施例中，分隔件400具有圆顶状或半球状。
在一些实施例中，分隔件400的外边界未对齐于封装结构P1-4的边缘，如图8B所示。在替代性实施例中，分隔件400的外边界对齐于封装结构P1-5/P1-6/P1-7/P1-8的边缘，如图12至图15所示。如图12所示，分隔件400的外边界对齐于封装结构P1-5的实质上垂直的边缘。如图13至图15所示，分隔件400的外边界对齐于封装结构P1-6/P1-7/P1-8的阶梯状边缘的邻接部分。封装结构P1-6/P1-7/P1-8的阶梯状边缘与封装结构P1-1/P1-2/P1-3的阶梯状边缘类似，故细节于此不再赘述。
请参照图8D、图11以及图12至图15，于步骤508中，将包括第二晶粒(例如，晶粒201)的第二封装结构(例如，封装结构P2)接合至第一封装结构。
请参照图8E、图8F、图11以及图12至图15，于步骤510中，形成电磁干扰层EMI以覆盖第一封装结构以及第二封装结构的裸露出的顶面以及侧面。由此形成本发明实施例的叠层封装器件5/6/7/8/9。图10中区域A的放大图示出参数“d”、“W”、“D”以及“H”的涵义。上述参数之间的比率与图3中所述的比率类似，故细节于此不再赘述。
请注意，在图12的叠层封装器件6中，虽然分隔件400的外边界对齐于封装结构P1-5的笔直边缘，但由于分隔件400具有圆顶状，所形成的电磁干扰层EMI很难沿着分隔件400的表面延伸，因此，所形成的电磁干扰层EMI于EMI形成步骤期间不会与托盘接触。
在上述实施例中，是以分隔件为金属分隔件或聚合物分隔件为例来说明，但不用于限定本发明实施例。在一些实施例中，分隔件可为包含导体材料以及绝缘材料的复合分隔件。
图16为根据又一些其他实施例所示出的叠层封装器件的形成方法的流程图。图17至图21为根据又一些其他实施例所示出的叠层封装器件的横截面示意图。
于步骤600中，于第一晶粒(例如，晶粒100)上方形成重布线层结构117，其中重布线层结构117电性连接至第一晶粒。于步骤602中，形成多个UBM接垫118以及第一分隔件(例如，分隔件119)，其中第一分隔件环绕UBM接垫118，且UBM接垫118电性连接至重布线层结构117。于步骤604中，于UBM接垫120上方形成多个接点120。于步骤606中，于形成接点120的步骤之后，于第一分隔件(例如，分隔件119)上形成第二分隔件(例如，分隔件400)，且因此提供第一封装结构(例如，封装结构P1-9/P1-10/P1-11/P1-12/P1-13)。于步骤608中，将包括第二晶粒(例如，晶粒201)的第二封装结构(例如，封装结构P2)接合至第一封装结构。于步骤610中，形成电磁干扰层EMI以覆盖第一封装结构以及第二封装结构的裸露出的顶面以及侧面。由此形成本发明实施例的叠层封装器件10/11/12/13/14。上述参数“d”、“W”、“D”以及“H”之间的比率范围与图3中所述的比率范围类似，故细节于此不再赘述。
叠层封装器件10/11/12/13/14(如图17至图21所示)与叠层封装器件5/6/7/8/9(如图8F以及图12至图15所示)类似，且其差异处在于：叠层封装器件10/11/12/13/14中的分隔件为双层结构，其包括由金属所构成的分隔件119以及由聚合物所构成的分隔件400；而叠层封装器件5/6/7/8/9中的分隔件400为单层结构，其包括由聚合物所构成的分隔件400。于EMI形成步骤期间，叠层封装器件10/11/12/13/14中的双层分隔件可提供下封装结构与托盘之间的较大分开距离(“S”)，以避免产生现有的EMI毛边(burr)，且因此改良器件效能。
在一些实施例中，本发明实施例提供封装结构P1/P1-1/P1-2/P1-3/P1-4/P1-5/P1-6/P1-7/P1-8/P1-9/P1-10/P1-11/P1-12/P1-13，其包括晶粒100、重布线层结构117、多个UBM接垫118、多个接点120以及分隔件119/400。封装结构P1/P1-1/P1-2/P1-3/P1-4/P1-5/P1-6/P1-7/P1-8/P1-9/P1-10/P1-11/P1-12/P1-1具有第一侧(例如，前侧)以及与第一侧相对的第二侧(例如，背侧)。重布线层结构117电性连接至晶粒100。UBM接垫118电性连接至重布线层结构117。接点120电性连接至UBM接垫118且由封装结构的第一侧裸露出。具体地说，一个UBM接垫118位于重布线层结构117与每一个接点120之间。分隔件119/400位于封装结构的第一侧上且位于最外面接点120侧边。具体地说，分隔件119/400位于重布线层结构117上方且环绕最外面接点120。
在封装结构P1/P1-1/P1-2/P1-3中，分隔件119包括金属。在封装结构P1-4/P1-5/P1-6/P1-7/P1-8中，分隔件400包括聚合物。在封装结构P1-9/P1-10/P1-11/P1-12/P1-13中，分隔部件包括由金属所构成的分隔件119以及由聚合物所构成的分隔件400。
在一些实施例中，本发明实施例更提供叠层封装器件1/2/3/4/5/6/7/8/9/10/11/12/13/14，其包括封装结构P2、封装结构P1/P1-1/P1-2/P1-3/P1-4/P1-5/P1-6/P1-7/P1-8/P1-9/P1-10/P1-11/P1-12/P1-13以及电磁干扰层EMI，其中封装结构P2接合于且堆叠于封装结构P1/P1-1/P1-2/P1-3/P1-4/P1-5/P1-6/P1-7/P1-8/P1-9/P1-10/P1-11/P1-12/P1-13上，电磁干扰层EMI覆盖封装结构P2的顶面以及侧面并电性连接至封装结构P1/P1-1/P1-2/P1-3/P1-4/P1-5/P1-6/P1-7/P1-8/P1-9/P1-10/P1-11/P1-12/P1-13的重布线层结构117的重布线层106、110以及114中的至少一个。
基于上述，在本发明实施例的叠层封装器件中，于重布线层结构上方形成分隔件，且分隔件环绕封装结构的接点。分隔件扮演着将叠层封装器件与托盘分开的角色，所述托盘于EMI形成步骤期间固持住所述叠层封装器件。以此方式，不会产生现有的EMI毛边，且EMI遮蔽的排除区(KOZ)可为大幅减少。
根据本发明的一些实施例，一种封装结构包括第一晶粒、重布线层结构、多个UBM接垫、多个接点以及分隔件。重布线层结构电性连接至第一晶粒。UBM接垫电性连接至重布线层结构。接点电性连接至UBM接垫。分隔件位于重布线层结构上方且环绕接点。
在上述封装结构中，所述分隔件包括金属、聚合物或其组合。
在上述封装结构中，从最外面UBM接垫至所述分隔件的内边界的距离为“d”，所述分隔件的宽度为“W”，且d与W的比率为约1:1至1:10。
在上述封装结构中，从最外面UBM接垫至所述分隔件的内边界的距离为“d”，所述分隔件的高度为“H”，且d与H的比率为约1:1至1:10。
在上述封装结构中，从最外面UBM接垫至所述分隔件的内边界的距离为“d”，从所述封装结构的边缘至所述分隔件的外边界的距离为“D”，且d与D的比率为约1:0.1至1:5。
在上述封装结构中，所述分隔件为环状且环绕最外面接点。
在上述封装结构中，所述封装结构的边缘具有阶梯状轮廓。
在上述封装结构中，所述分隔件处于浮动电位。
根据本发明的一些替代性实施例，一种叠层封装器件包括第一封装结构、第二封装结构以及电磁干扰层。第一封装结构，具有第一侧以及与所述第一侧相对的第二侧，且包括第一晶粒、重布线层结构、多个接点以及分隔件。重布线层结构电性连接至所述第一晶。多个接点电性连接至所述重布线层结构且由所述第一侧裸露出。分隔件位于所述第一封装结构的所述第一侧上，且位于所述接点侧边。第二封装结构位于所述第一封装结构的所述第二侧上方。电磁干扰层覆盖所述第二封装结构的顶面以及侧面，且电性连接至所述第一封装结构的所述重布线层结构。
在上述叠层封装器件中，所述分隔件包括金属、聚合物或其组合。
在上述叠层封装器件中，所述第一封装结构还包括位于所述重布线层结构的顶面的多个UBM接垫，且所述多个接点连接至所述多个UBM接垫。
在上述叠层封装器件中，从最外面UBM接垫至所述分隔件的内边界的距离为“d”，所述分隔件的宽度为“W”，且d与W的比率为约1:1至1:10。
在上述叠层封装器件中，从最外面UBM接垫至所述分隔件的内边界的距离为“d”，所述分隔件的高度为“H”，且d与H的比率为约1:1至1:10。
在上述叠层封装器件中，从最外面UBM接垫至所述分隔件的内边界的距离为“d”，从所述第一封装结构的边缘至所述分隔件的外边界的距离为“D”，且d与D的比率为约1:0.1至1:5。
在上述叠层封装器件中，所述分隔件的外边界对齐于所述第一封装结构的边缘。
在上述叠层封装器件中，所述第一封装结构的边缘具有阶梯状轮廓。
根据本发明的另一些替代性实施例，一种封装结构的形成方法包括以下步骤。于第一晶粒上方形成重布线层结构，其中所述重布线层结构电性连接至所述第一晶粒。形成多个UBM接垫以及第一分隔件，其中所述第一分隔件环绕所述UBM接垫，且所述多个UBM接垫电性连接至所述重布线层结构。于所述多个UBM接垫上方形成多个接点。
在上述形成方法中，还包括于形成所述多个接点的步骤之后，于所述第一分隔件上形成第二分隔件。
在上述形成方法中，所述第一分隔件包括金属，且所述第二分隔件包括聚合物。
在上述形成方法中，所述多个UBM接垫以及所述第一分隔件由相同光掩模所定义。
以上概述了数个实施例的特征，使所属领域的一般技术人员可更佳了解本揭露的态样。所属领域的一般技术人员应理解，其可轻易地使用本揭露作为设计或修改其他工艺与结构的依据，以实行本文所介绍的实施例的相同目的和/或达到相同优点。所属领域的一般技术人员还应理解，这种等效的配置并不悖离本揭露的精神与范畴，且所属领域的一般技术人员在不悖离本揭露的精神与范畴的情况下可对本文做出各种改变、置换以及变更。

Claims (1)

1.一种封装结构，其特征在于包括：
第一晶粒；
重布线层结构，电性连接至所述第一晶粒；
多个凸点下金属接垫，电性连接至所述重布线层结构；
多个接点，电性连接至所述多个凸点下金属接垫；以及
分隔件，位于所述重布线层结构上方且环绕所述接点。
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