CN110783294A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN110783294A
CN110783294A CN201910527925.4A CN201910527925A CN110783294A CN 110783294 A CN110783294 A CN 110783294A CN 201910527925 A CN201910527925 A CN 201910527925A CN 110783294 A CN110783294 A CN 110783294A
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China
Prior art keywords
conductive
die
semiconductor
dam
semiconductor die
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CN201910527925.4A
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Inventor
卢贯中
苏安治
叶德强
黄立贤
林岳霆
叶名世
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN110783294A publication Critical patent/CN110783294A/zh
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Abstract

提供一种半导体装置及其制造方法。所述半导体装置包括封装结构、第一管芯、第一围阻结构、预填充层及多个导电端子。封装结构包括附接区、位于附接区周围的排除区。第一管芯设置在附接区中的封装结构上且电连接到封装结构。第一围阻结构设置在封装结构的排除区内且环绕第一管芯。预填充层设置在封装结构与第一管芯之间且设置在第一围阻结构与第一管芯之间，其中预填充层被限制在第一围阻结构内。导电端子设置在封装结构上，分布在封装结构的排除区周围且电连接到封装结构。

Description

半导体装置及其制造方法
技术领域
本发明的实施例是有关于一种半导体装置及其制造方法，特别是有关于一种包括用围阻结构来限制预填充层的半导体装置及其制作方法。
背景技术
近年来，由于各种电子组件(例如晶体管、二极管、电阻器、电容器等)的集成密度持续提高，半导体工业已经历快速成长。在很大程度上，集成密度的这种提高来自于最小特征大小(minimum feature size)的不断减小，这使得更多组件能够集成到给定区域中。这些较小的电子组件也需要与先前的封装相比占据较小面积的较小的封装。半导体装置封装的类型的实例包括三维集成电路(three-dimensional integrated circuit，3DIC)、晶片级封装(wafer level package，WLP)及层叠封装(package on package，PoP)装置等。一些半导体装置是通过以半导体晶片级将芯片放置在彼此之上来制备的。半导体装置提供提高的集成密度及其他优点(例如更快的速度及更高的频宽)，这是因为堆叠芯片之间的内连线的长度减小。然而，存在与半导体装置相关的许多挑战。
发明内容
根据一些实施例，一种半导体装置包括封装结构、第一管芯、第一围阻结构、预填充层及多个导电端子。所述封装结构包括附接区、位于所述附接区周围的排除区。所述第一管芯设置在所述封装结构上及所述附接区中且电连接到所述封装结构。所述第一围阻结构设置在所述封装结构的所述排除区内且环绕所述第一管芯。所述预填充层设置在所述封装结构与所述第一管芯之间且设置在所述第一围阻结构与所述第一管芯之间，其中所述预填充层被限制在所述第一围阻结构内。所述导电端子设置在所述封装结构上，分布在所述封装结构的所述排除区周围且电连接到所述封装结构。
根据一些实施例，一种半导体装置包括第一管芯、密封所述第一管芯的绝缘密封体、设置在所述绝缘密封体及所述第一管芯上的重布线结构、与所述第一管芯相对地设置在所述重布线结构上且经由所述重布线结构电耦合到所述第一管芯的第二管芯、填充在所述第二管芯与所述重布线结构之间的预填充层、以及设置在所述重布线结构上的第一围阻结构。所述预填充层设置在所述第一围阻结构与所述第二管芯之间且被所述第一围阻结构包围。
根据一些实施例，提供一种半导体装置的制造方法包括提供封装结构，其中所述封装结构包括第一区、环绕所述第一区的第二区以及位于所述第一区与所述第二区之间的第三区。在所述第三区内的所述封装结构上形成第一围阻结构。设置半导体管芯于所述封装结构的所述第一区上且预填充层在其之间，其中所述第一围阻结构阻挡所述预填充层向外流动。在所述封装结构上设置第一屏蔽结构以覆盖所述第一围阻结构及所述半导体管芯，其中所述封装结构的所述第二区被所述第一屏蔽结构暴露出。在所述封装结构的被所述第一屏蔽结构暴露出的所述第二区中形成导电端子。
附图说明
结合附图阅读以下详细说明，会最好地理解本公开的各个方面。要注意的是，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的尺寸。
图1及图2是示出根据本公开一些示例性实施例的半导体结构的制造方法中的各个阶段的示意性剖视图。
图3到图8是示出图2所示虚线区A且示出根据本公开一些示例性实施例的形成导电端子以及在半导体结构上设置半导体管芯的方法中的各个阶段的放大的示意性剖视图。
图9是根据本公开一些示例性实施例的图8的简化的示意性俯视图。
图10及图11是示出根据本公开一些示例性实施例的半导体装置的制造方法中的各个阶段的示意性剖视图。
图12是示出根据本公开一些示例性实施例的半导体结构的示意性剖视图。
图13到图18是示出图12所示虚线区B且示出根据本公开一些示例性实施例的形成导电端子以及在半导体结构上设置半导体管芯的方法中的各个阶段的放大的示意性剖视图。
图19及图20是示出根据本公开一些示例性实施例的半导体装置的制造方法中的各个阶段的示意性剖视图。
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本公开。当然，这些仅为实例而非旨在进行限制。举例来说，在以下说明中，在第二特征之上或第二特征上形成第一特征可包括其中第一特征与第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成附加特征从而使得第一特征与第二特征可不直接接触的实施例。另外，本公开在各种实例中可重复使用参考编号和/或字母。此种重复使用是为了简明及清晰起见，且自身并不表示所论述的各个实施例和/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“在…之下(beneath)”、“在…下方(below)”、“下部的(lower)”、“在…上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。装置可具有其他取向(旋转90度或处于其他取向)，且本文中所用的空间相对性描述语可同样相应地进行解释。
另外，为易于说明，本文中可能使用例如“第一”、“第二”等用语来阐述图中所例示的相似的或不同的元件或特征，且可根据存在的次序或说明的上下文而互换地使用。
本公开也可包括其他特征及工艺。举例来说，可包括测试结构，以帮助对三维(three-dimensional，3D)封装或3DIC装置进行验证测试。所述测试结构可包括例如在重布线层(redistribution layer)中或在衬底上形成的测试垫，以使得能够对3D封装或3DIC进行测试、对探针和/或探针卡(probe card)进行使用等。可对中间结构以及最终结构执行验证测试。另外，本文中所公开的结构及方法可结合包括对已知良好管芯(known good die)进行中间验证的测试方法来使用，以提高良率并降低成本。
图1及图2是示出根据本公开一些示例性实施例的半导体结构的制造方法中的各个阶段的示意性剖视图。在示例性实施例中，所述制造方法是晶片级封装工艺的部分。可在半导体结构中封装一种或多种类型的集成电路管芯以形成例如系统芯片(system on achip，SoC)装置。参照图1，提供临时载体C且在临时载体C上提供第一半导体管芯110以及位于第一半导体管芯110旁边的多个导电元件120。在一些实施例中，在临时载体C上形成剥离层C1。临时载体C可为玻璃载体、陶瓷载体或类似载体。剥离层C1可由聚合物系材料(例如光热转换(light to heat conversion，LTHC)材料)形成，所述聚合物系材料可与临时载体C一起从将在随后工艺中形成的上覆结构移除。在一些实施例中，在临时载体C上设置多于一个半导体管芯。举例来说，第一半导体管芯110包括选自以下的一种或多种类型的芯片：数字芯片(digital chip)、模拟芯片(analog chip)或混合信号芯片、应用专用集成电路(application-specific integrated circuit，ASIC)芯片、传感器芯片、存储器芯片或逻辑芯片和/或其他电子装置。
在一些实施例中，第一半导体管芯110包括半导体衬底110a、位于半导体衬底110a之上的接触垫110b、位于半导体衬底110a之上且暴露出接触垫110b的部分的钝化层110c、位于钝化层110c之上且电连接到接触垫110b的管芯连接件110d以及位于钝化层110c之上且位于管芯连接件110d旁边的保护层110e。在一些实施例中，管芯连接件110d包括导电柱或通孔、焊料凸块、金凸块、铜柱或类似连接件，并且通过电镀工艺或其他合适的沉积工艺形成。上面分布有管芯连接件110d以用于进一步的电连接的表面可被称为第一半导体管芯110的有源表面。在一些实施例中，保护层110e包含聚苯并恶唑(polybenzoxazole，PBO)、聚酰亚胺(polyimide，PI)、合适的有机材料或无机材料或类似材料。在一些实施例中，在拾取第一半导体管芯110并将第一半导体管芯110放置在临时载体C上之前，在临时载体C上形成导电元件120。在替代实施例中，在拾取第一半导体管芯110并将第一半导体管芯110放置在临时载体C上之后，在临时载体C上设置导电元件120。导电元件120的材料包括铜、镍、焊料、其组合或类似材料。在一些实施例中，通过电镀工艺或其他合适的沉积工艺来形成导电元件120。在一些替代实施例中，省略导电元件120。应理解的是，导电元件120的数目及位置是可变化的且可视需要进行修改。
继续参照图1，在临时载体C之上形成绝缘密封体130以在侧向上密封第一半导体管芯110及导电元件120。绝缘密封体130可暴露出导电元件120的顶表面以及第一半导体管芯110的管芯连接件110d的顶表面以进行进一步的电连接。绝缘密封体130包含模塑化合物(例如环氧树脂)、感光材料(例如聚苯并恶唑(PBO)、聚酰亚胺(PI)或苯并环丁烯(benzocyclobutene，BCB))、其组合或者其他合适的电绝缘材料。形成绝缘密封体130的方法包括在临时载体C上形成绝缘材料(未示出)以覆盖第一半导体管芯110及导电元件120以及执行研磨工艺、化学机械抛光(chemical mechanical polishing，CMP)工艺或其他平坦化工艺以部分地移除绝缘材料直到暴露出导电元件120的顶表面以及第一半导体管芯110的管芯连接件110d的顶表面为止。在研磨工艺之后，可选地执行清洁步骤例如以清洁及移除从研磨工艺产生的残留物。然而，本公开并非仅限于此，所述平坦化步骤可通过任何其他合适的技术来执行。在形成绝缘密封体130及平坦化工艺之后，导电元件120穿透过绝缘密封体130，其中导电元件120的顶表面被暴露出。在一些实施例中，导电元件120可被称为绝缘体穿孔(through insulator via，TIV)。
参照图2，在第一半导体管芯110之上形成重布线结构140且重布线结构140电连接到第一半导体管芯110。在一些实施例中，重布线结构140基于电路设计要求而包括至少一个图案化介电层(例如141、143、145及147)以及至少一个图案化导电层(例如142、144及146)。图案化导电层(例如142、144及146)可包括导电特征(例如线路、通孔及接垫)且可通过图案化及金属化技术(例如光刻、刻蚀、CMP、薄膜沉积、镀覆、镶嵌处理等)或其他合适的工艺形成。图案化导电层142实体连接到且电连接到第一半导体管芯110的管芯连接件110d以及导电元件120。图案化导电层142可穿透过图案化介电层141。图案化导电层144电连接到图案化导电层142且穿透过图案化介电层143。图案化导电层146电连接到图案化导电层144且穿透过图案化介电层145且图案化介电层147覆盖图案化导电层146。图案化介电层141、143、145及147的材料可包括感光材料，例如聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)、其组合或类似材料。图案化导电层142、144及146的材料可包括铜、镍、钛、其组合或类似材料且通过电镀工艺或其他合适的沉积工艺形成。应理解的是，本公开不限制图案化介电层或图案化导电层的数目。
参照图2，重布线结构140包括位于图案化介电层147上的多个第一导电特征148及多个第二导电特征149，所述多个第二导电特征149位于第一导电特征148旁边。在一些实施例中，位于图案化介电层147上且连接到下伏的图案化导电层146的第一导电特征148及第二导电特征149可被视为重布线结构140的另一图案化导电层。在一些实施例中，第一导电特征148及第二导电特征149中的每一者的材料包括铜、镍、钛、其组合或类似材料且可通过电镀工艺或其他合适的沉积工艺形成。第一导电特征148及第二导电特征149可包括微凸块、导电接垫、金属化图案、焊料连接件和/或类似导电特征。在一些实施例中，第一导电特征148包括用于进行随后植球工艺的凸块下金属(under-ball metallurgy，UBM)接垫。在一些实施例中，第一导电特征148由铜制成。在替代实施例中，第一导电特征148可为由包括钛、镍、铜、金、钯、其合金或类似材料的材料制成的多层式接垫。在一些实施例中，第二导电特征149包括用于电连接其他半导体管芯/装置的微凸块接垫。在一些实施例中，与第一导电特征148相比，第二导电特征149的大小较小使得能够实现第二导电特征149的精细节距并实现高密度连接。在一些实施例中，第一导电特征148与第二导电特征149由相同的光刻掩模版(lithography reticle)或光掩模(photomask)界定。在替代实施例中，第一导电特征148与第二导电特征149依序形成或者由不同的图案化工艺形成。
在形成重布线结构140之后，在临时载体C上形成包括第一导电特征148及第二导电特征149的半导体结构(即封装结构)100A，如图2所示。在一些实施例中，形成在半导体结构100A的最外侧OS处的重布线结构140可包括第一区、环绕第一区的第二区以及位于第一区与第二区之间的第三区，其中半导体管芯或半导体装置在第一区位移或定位。在一些实施例中，第一区被称为管芯/装置附接区DAZ，而第二区及第三区被称为球/凸块安装区BMZ及排除区(keep-out zone)KOZ。在一些实施例中，管芯/装置附接区DAZ可被指定用于安装一个或多个半导体管芯。在一些实施例中，球/凸块安装区BMZ可被指定用于安装外部连接件(例如导电凸块、球栅阵列(ball grid array，BGA)球或焊球)，排除区KOZ插设在管芯/装置附接区DAZ与球/凸块安装区BMZ之间。之后将在其他实施例中更详细地论述这些区。举例来说，第二导电特征149形成在管芯附接区DAZ中且第一导电特征148形成在植球区BMZ中。在一些实施例中，第二导电特征149中最外部的一个第二导电特征149的边缘以及第一导电特征148中相邻的一个第一导电特征148的最近边缘附近的区可被视为排除区KOZ。
图3到图8是示出图2所示虚线区A且示出根据本公开一些示例性实施例的形成导电端子以及在半导体结构上设置半导体管芯的方法中的各个阶段的放大的示意性剖视图。参照图3及图4，在排除区KOZ(例如紧密环绕管芯/装置附接区DAZ的区)内的半导体结构100A的最外侧OS上形成第一围阻结构(containment structure)150。第一围阻结构150的材料可包括聚合物(例如环氧树脂(epoxy resin)、酚醛树脂(phenolic resin))、阻焊剂(solder resist)、粘合剂、金属或其他合适的障壁材料(barrier material)。在一些替代实施例中，第一围阻结构150可由导电膏(例如导电颗粒与粘结剂(binder)的混合物)制成。根据所应用的材料而定，采用合适的工艺(例如印刷(printing)、点胶(dispensing)、喷涂(spraying)或其他适用的沉积工艺)来形成第一围阻结构150。在一些实施例中，在重布线结构140上覆盖包括第一开孔AP1的第一图案化掩模PM1。第一图案化掩模PM1可为具有与排除区KOZ的位置对应的第一开孔AP1的钢板(stencil)(例如金属片材)。在一些实施例中，第一开孔AP1定位在靠近排除区KOZ内的第二导电特征149的最外部的一个第二导电特征149的边缘。第一图案化掩模PM1的第一开孔AP1可形成为封闭环(例如矩形环状、环状、多边形环状或类似形状)的图案。
举例来说，第一图案化掩模PM1直接抵靠第一导电特征148及第二导电特征149以接近图案化介电层147的顶表面147a且第一图案化掩模PM1与图案化介电层147的顶表面147a在空间上彼此分离。接下来，可在图案化介电层147的顶表面147a上或者在第一图案化掩模PM1的平面部分上形成障壁材料IM。在一些实施例中，障壁材料IM包括环氧助焊剂(epoxy flux)或其他合适的材料。环氧助焊剂可包括环氧树脂及助焊剂组分。在替代实施例中，障壁材料IM可为导电膏。举例来说，一个或多个工具TL(例如刮板(squeegee)、刀片(blade)或刷具(wiper))可来回地刷过第一图案化掩模PM1以在第一图案化掩模PM1的第一开孔AP1中涂上障壁材料IM。在一些实施例中，向第一图案化掩模PM1的第一开孔AP1中点上(dispense)预定量的障壁材料IM且通过表面张力(surface tension)形成圆形表面。
在一些实施例中，障壁材料IM被作为半流体被涂上。然后，将第一图案化掩模PM1移除，包围第二导电特征149的障壁材料IM余留在图案化介电层147的顶表面147a上。随后，可执行固化工艺以使障壁材料IM凝固从而形成第一围阻结构150。在一些实施例中，使障壁材料IM固化的条件包括使障壁材料IM经受约100℃到约180℃的温度达约60分钟。在某些实施例中，固化温度介于约150℃与约160℃之间达约30分钟。应理解的是，固化条件可根据设计要求而进行调整，固化条件并非仅限于此。
第一围阻结构150可被形成为呈各种横截面形状的挡坝结构或挡墙结构。在一些实施例中，第一围阻结构150实质上是环形壁结构。尽管图4示出第一围阻结构150的圆形(凸起)顶表面，然而第一围阻结构150的顶表面可具有其他形状，包括平坦表面、凹陷表面等。第一围阻结构150可包括介于约20微米(μm)到约30μm范围内的宽度W1。第一围阻结构150的高度H1可介于约20μm到约30μm的范围内。第一围阻结构150的最佳大小(例如宽度W1、高度H1等)与各种因素相关，所述各种因素包括第二导电特征149的大小以及随后安装组件的大小。在一些实施例中，第一围阻结构150的高度H1小于图案化介电层147的顶表面147a上的每一第一导电特征148的厚度(或每一第二导电特征149的厚度)。在替代实施例中，第一围阻结构150的高度H1实质上等于或大于图案化介电层147的顶表面147a上的每一第一导电特征148的厚度(或每一第二导电特征149的厚度)。应理解的是，在本说明通篇中陈述的值仅为实例且可改变成不同的值。
参照图5，在管芯/装置附接区DAZ内的图案化介电层147的顶表面147a上形成预填充(pre-fill)材料PF以覆盖第二导电特征149。预填充材料PF可包含聚合物、环氧树脂或合适的粘合材料。举例来说，在重布线结构140上覆盖包括第二开孔AP2的第二图案化掩模PM2。第二开孔AP2可暴露出形成在管芯/装置附接区DAZ中的第二导电特征149。第二开孔AP2的大小可根据随后安装的组件(例如图6所示第二半导体管芯170)的大小而定。举例来说，第二图案化掩模PM2的开口面积对随后安装的组件的表面积的比介于约45％到约65％的范围内。第二图案化掩模PM2可抵靠球/凸块安装区BMZ中的第一导电特征148且可覆盖排除区KOZ中的第一围阻结构150。接下来，在第二图案化掩模PM2之上以及第二开孔AP2内部涂上预填充材料PF且可使用工具TL除掉过量的预填充材料PF。然后，移除第二图案化掩模PM2，预填充材料PF留在图案化介电层147上且覆盖第二导电特征149。
参照图6，在第二导电特征149上设置第二半导体管芯170以电连接半导体结构100A。举例来说，拾取第二半导体管芯170且将第二半导体管芯170放置在第二导电特征149及预填充材料PF之上。第二半导体管芯170可位于第一半导体管芯110(图2所示)之上且与第一半导体管芯110对齐。作为另外一种选择，第二半导体管芯170可与绝缘密封体130和/或导电元件120(图2所示)对齐。在一些实施例中，第二半导体管芯170包括导电连接件172，在设置第二半导体管芯170之后，导电连接件172分布在管芯/装置附接区DAZ内。第二半导体管芯170经由导电连接件172电连接到第二导电特征149。导电连接件172可包括导电接垫/导电柱、焊料凸块、其组合或类似材料。在一个实施例中，导电连接件172可通过在第二导电特征149之上印刷焊料材料形成。可在重布线结构140上设置一个或多个第二半导体管芯170。应注意，出于例示目的在图中存在单个第二半导体管芯170，但本文不限制要安装在重布线结构140上的第二半导体管芯170的数目且可基于设计要求而变化。在一些实施例中，可由一个或多个第二半导体管芯170来对一个或多个第一半导体管芯110进行编程(program)。举例来说，可使用第二半导体管芯170来对相应的半导体装置的性能进行微调。在一些实施例中，第二半导体管芯170是离散的无源装置，所述离散的无源装置未形成在其中形成有有源装置(例如晶体管及二极管)的相同管芯中。在一些实施例中，第二半导体管芯170可为硅系(silicon based)的(或陶瓷系的)且其中具有无源装置。举例来说，第二半导体管芯170中可不形成有有源装置。第二半导体管芯170可包括电容器、电阻器、电感器和/或类似装置。第二半导体管芯170可为集成无源装置(integrated passive device，IPD)、表面安装装置(surface mount device，SMD)或其他合适的封装组件。
在一些实施例中，当安装第二半导体管芯170时，第二导电特征149上的预填充材料PF可被挤压以从管芯/装置附接区DAZ向外延伸到排除区KOZ，从而形成预填充层160。举例来说，在设置第二半导体管芯170期间，过量的预填充材料PF可流出至管芯/装置附接区DAZ外，接着预填充材料PF的流动可向外扩散直到抵达第一围阻结构150，使得预填充层160可与第一围阻结构150实体接触。在替代实施例中，点上(dispense)少量的预填充材料，以使得在设置第二半导体管芯170之后，预填充层160分布在管芯/装置附接区DAZ内，而不会向外扩散到排除区KOZ且可不与第一围阻结构150接触。在设置第二半导体管芯170之后，第二半导体管芯170的导电连接件172与下伏的第二导电特征149实体连接且电连接。插设在第二半导体管芯170与重布线结构140之间的预填充层160可密封导电连接件172以及下伏的第二导电特征149。可对第一围阻结构150的大小进行设定，以阻挡预填充材料PF向外扩散出排除区KOZ。在一些实施例中，第一围阻结构150使第二半导体管芯170之下的预填充层160能够定位在排除区KOZ内且使预填充层160填充于被第一围阻结构150包围的区域。
参照图7及图8，在第一导电特征148上形成导电端子180以电连接半导体结构100A。导电端子180可与第二半导体管芯170相邻地设置。在一些实施例中，多个导电端子180排列在与球/凸块安装区BMZ内的第一导电特征148的位置对应的位置处。导电端子180实体连接及电连接到重布线结构140的第一导电特征148以使第二半导体管芯170及第一半导体管芯110电耦合到导电端子180。在一些实施例中，导电端子180由具有低电阻率的导电材料(例如焊料、铜、铝、金、镍、银、钯、锡、其合金或类似材料)制成。导电端子180可为球栅阵列(BGA)连接件、焊球、金属柱或类似装置。
在一些实施例中，导电端子180通过在开始时通过例如着球(ball drop)、蒸镀(evaporation)、电镀、印刷或类似方法等方法形成焊料层来形成。举例来说，植球工艺可包括以下步骤。在图案化介电层147的顶表面147a之上设置包括穿孔TH1的屏蔽结构S1以覆盖第二半导体管芯170、下伏的预填充层160及第一围阻结构150。屏蔽结构S1的穿孔TH1可暴露出球/凸块安装区BMZ中的第一导电特征148。在一些实施例中，屏蔽结构S1包括上部盖体S1a以及连接到上部盖体S1a的侧壁S1b以覆盖第二半导体管芯170以及第一围阻结构150内的下伏的预填充层160，侧壁S1b可使第一导电特征148与相邻的第一围阻结构150在空间上隔离。举例来说，第一围阻结构150可为实质上环绕预填充层160及上覆的第二半导体管芯170的矩形障壁结构，具有挡墙结构(retaining wall structure)(例如包括从顶部面板及分区面板制作的矩形框架)的屏蔽结构S1可在处理期间保护第一围阻结构150。
在设置屏蔽结构S1之后，在设置导电球之前使用印刷工艺或其他合适的工艺来向第一导电特征148上涂上助焊剂材料FM。接下来，在屏蔽结构S1之上放置导电球(例如焊球、金球、铜球、镍球或类似球)。举例来说，导电球可经受震动以使得导电球坠落到屏蔽结构S1的穿孔TH1中且导电球的位置可被屏蔽结构S1的穿孔TH1所局限。在一些实施例中，导电球可被直接放置在助焊剂材料FM上。随后，移除屏蔽结构S1并执行回焊工艺。在一些实施例中，执行回焊工艺以在第一导电特征148(例如作为UBM接垫)上形成导电端子180。举例来说，回焊工艺有助于将导电球牢固地结合到下伏的第一导电特征148，并且在回焊工艺之后，可能看不到助焊剂材料FM。在一些实施例中，可通过在第二导电特征149及第一导电特征148上印刷焊料材料以及之后的回焊来同时形成第二半导体管芯170的导电连接件172及导电端子180。在替代实施例中，在将第二半导体管芯170设置在重布线结构140的第二导电特征149上之前，可在第一导电特征148上形成导电端子180。
图9是根据本公开一些示例性实施例的图8的简化的示意性俯视图。参照图8及图9，可对排除区KOZ的大小进行设定，使得在导电端子180与第二半导体管芯170的导电连接件172之间存在足够的空间。在一些实施例中，排除区KOZ可包括一区，在所述区中，导电端子180中的一者的边缘与第二半导体管芯170的边缘间隔开排除距离D1。在一些实施例中，第一围阻结构150设置在第二半导体管芯170的每一侧壁与所述多个导电端子180中相邻的一个导电端子180的最近边缘之间。在一些实施例中，第二半导体管芯170的每一侧壁到相邻的导电端子180的最近边缘之间的排除距离D1可实质上相等。在一些其他实施例中，根据布线(layout)要求而定，从第二半导体管芯170的侧壁中的一者到导电端子180中相邻的一个导电端子180的最近边缘可存在不同的排除距离。
在一些实施例中，由于在半导体结构100A上能安装有更多第二半导体管芯170，第二半导体管芯170的侧壁到相邻的导电端子180的最近边缘之间的排除距离D1可期望为较小。在一些实施例中，排除距离D1与第一围阻结构150的宽度W1的比例介于约5到约7.5的范围内。应理解的是，在本文通篇中陈述的值仅为实例且可改变成不同的值。为防止在第二导电特征149上所涂的预填充材料PF外流或者甚至影响在第一导电特征148上所涂的助焊剂材料FM，在排除区KOZ中形成的第一围阻结构150可限制预填充材料PF的流动，从而防止过量的预填充材料PF流出而造成内连线缺陷及检查故障，因此排除区KOZ的大小要求可减小且导电端子180的分布密度可因此增大。
图10及图11是示出根据本公开一些示例性实施例的半导体装置的制造方法中的各个阶段的示意性剖视图。参照图10及图11，在安装第二半导体管芯170及形成导电端子180之后，可将临时载体C与绝缘密封体130、第一半导体管芯110及导电元件120分离。在一些实施例中，通过以紫外光或激光来辐照设置在临时载体C之上的剥离层C1来剥离临时载体C，以暴露出半导体结构100A的表面100s。半导体结构100A的表面100s具有被绝缘密封体130暴露出的导电元件120的部分以进行进一步的电连接。举例来说，可在半导体结构100A上堆叠多个集成电路封装，以在堆叠式封装(package-on-package，POP)结构中提供附加的功能。
在一些实施例中，在半导体结构100A的表面100s上设置装置封装200以形成半导体装置SD1。装置封装200为例如存储器装置(例如静态随机存取存储器(static randomaccess memory，SRAM)、动态随机存取存储器(dynamic random access memory，DRAM)等)或其他合适的半导体装置。装置封装200可堆叠在半导体结构100A之上且经由外部端子210电连接到半导体结构100A。在一些实施例中，装置封装200的外部端子210实体连接及电连接到导电元件120，使装置封装200电耦合到第一半导体管芯110及第二半导体管芯170。在一些实施例中，在半导体结构100A与装置封装200之间形成底胶UF。底胶UF可被点(dispense)成覆盖至少外部端子210以用于保护。在一些实施例中，底胶UF可覆盖半导体结构100A的表面100s且可包绕装置封装200的至少底部部分。在一些实施例中，接着执行单体化(切割)工艺以沿切割线(未示出)切穿至少底部填充材料UF、绝缘密封体130及重布线结构140来形成各别的且分离的半导体装置SD1。在一些实施例中，所述单体化工艺包括机械锯切或激光切割的晶片切割工艺。
图12是示出根据本公开一些示例性实施例的半导体结构的示意性剖视图。在如图1及图2中所述的前述制造工艺之后，可制作出图12所示半导体结构100B。半导体结构100A与半导体结构100B之间的差异在于重布线结构。参照图12，重布线结构340的图案化导电层346电连接到图案化导电层144且穿透过图案化介电层145，并且图案化介电层347部分地覆盖图案化导电层346。图案化导电层346可包括第一导电特征346a及第二导电特征346b。举例来说，图案化介电层347包括第一开口OP1及第二开口OP2。第一开口OP1可暴露出下伏的第一导电特征346a且第二开口OP2可暴露出下伏的第二导电特征347b，以进行进一步的电连接。
图13到图18是示出图12所示虚线区B且示出根据本公开一些示例性实施例的形成导电端子以及在半导体结构上设置半导体管芯的方法中的各个阶段的放大的示意性剖视图。参照图13，在图案化介电层347的顶表面347a上覆盖包括第三开孔AP3及第四开孔AP4的第三图案化掩模PM3。在一些实施例中，第三图案化掩模PM3可为具有实质上对应于至少球/凸块安装区BMZ的第三开孔AP3以及对应于排除区KOZ的位置的第四开孔AP4的钢板(例如金属片材)。在一些其他实施例中，第三开孔AP3的部分设置在球/凸块安装区BMZ与排除区KOZ的交界处以暴露出这两个区。举例来说，第三开孔AP3可部分地暴露出图案化导电层346的第一导电特征346a。在一些实施例中，第三图案化掩模PM3覆盖图案化介电层347的第二开口OP2。图13中的虚线框示出对应于第三图案化掩模PM3、图案化介电层347及下伏的第一导电特征346a的俯视图。举例来说，就第一导电特征346a的可被图案化介电层347的第一开口OP1触及地显露的所述部分来说，第三图案化掩模PM3覆盖第一导电特征346a的中间部分MP且第三图案化掩模PM3的第三开孔AP3暴露出第一导电特征346a的外围部分PP。
在一些实施例中，第三图案化掩模PM3的第三开孔AP3可与图案化介电层347的第一开口OP1连通且可暴露出图案化介电层347的顶表面347a及侧壁347b(例如连接到顶表面347a及第一导电特征346a)。在一些实施例中，第四开孔AP4定位在靠近图案化介电层347的第二开口OP2中最外部的一个第二开口OP2。第三开孔AP3和/或第四开孔AP4可形成为封闭环(例如矩形环状、环状、多边形环状等)的图案。在设置第三图案化掩模PM3来直接抵靠图案化介电层347的顶表面347a之后，可在图案化介电层347的顶表面347a上形成障壁材料IM。举例来说，一个或多个工具TL(例如刮板(squeegee)、刀片(blade)或刷具(wiper))可来回地刷过第三图案化掩模PM3以在第三图案化掩模PM3的第三开孔AP3及第四开孔AP4中涂上障壁材料IM。
参照图14，移除第三图案化掩模PM3，分别包围第一开口OP1及第二开口OP2的两组障壁材料IM余留在图案化介电层347的顶表面347a上。在一些实施例中，障壁材料IM作为半流体被涂上，涂上在图案化介电层347的顶表面347a上的障壁材料IM的部分可向下流动，以覆盖图案化介电层347的侧壁347b并抵达第一导电特征346a的被图案化介电层347的第一开口OP1显露出的至少外围部分PP。可执行固化工艺以使障壁材料IM凝固从而在这些第二开口OP2周围形成第一围阻结构350A且也在第一开口OP1中的每一者周围形成第二围阻结构350B。图14中的虚线框示出对应于第二围阻结构350B、图案化介电层347及下伏的第一导电特征346a的俯视图。尽管图14示出因表面张力而引起的第一围阻结构350A及第二围阻结构350B的圆形(凸起)顶表面，但第一围阻结构350A及第二围阻结构350B的顶表面可具有其他形状，包括平坦表面、凹陷表面等。应理解，图中所示单个第二围阻结构350B仅用作例示性实例，可在第一导电特征346a的部分(或每一者)上形成多个第二围阻结构350B以进行随后的植球工艺。
所述固化工艺可为与图3及图4中所述的工艺相似的工艺，并可根据设计要求来调整固化条件以形成第一围阻结构350A及第二围阻结构350B。第一围阻结构350A连接到图案化介电层347的顶表面347a，第二围阻结构350B可与图案化介电层347的顶表面347a及侧壁347b实体接触且还与第一导电特征346a的被图案化介电层347的第一开口OP1显露出的外围部分PP实体接触。第一导电特征346a的中间部分MP被第二围阻结构350B以及图案化介电层347的第一开口OP1暴露出。在一些实施例中，第一围阻结构350A及第二围阻结构350B由电隔离材料制成。在一些替代实施例中，第一围阻结构350A与第二围阻结构350B由不同的材料以及使用不同的图案化掩模制成。举例来说，第二围阻结构350B可由导电材料(例如焊料、铜等)制成且第一围阻结构350A可由电绝缘材料制成。在替代实施例中，第一围阻结构350A与第二围阻结构350B二者由导电膏制成。
参照图15，在图案化介电层347的顶表面347a之上设置第一屏蔽结构S2，以覆盖排除区KOZ及球/凸块安装区BMZ中的第一围阻结构350A及第二围阻结构350B。第一屏蔽结构S2可包括暴露出管芯/装置附接区DAZ内的图案化介电层347的第二开口OP2的穿孔TH2。在一些实施例中，第一屏蔽结构S2包括上部盖体S2a及连接到上部盖体S2a的侧壁S2b。被第一屏蔽结构S2覆盖的第一围阻结构350A及第二围阻结构350B在空间上与上部盖体S2a及侧壁S2b分离。在设置第一屏蔽结构S2之后，在第一屏蔽结构S2的穿孔TH2中涂上预填充材料PF，使得在管芯/装置附接区DAZ内并在图案化介电层347的顶表面347a上及在图案化介电层347的第二开口OP2内部形成预填充材料PF以覆盖第二导电特征346b。
参照图16，在第二导电特征346b上形成预填充材料PF之后，第二半导体管芯370可设置在第二导电特征346b上且预填充层360形成在其之间。在一些实施例中，当设置第二半导体管芯370时，第二导电特征149上的预填充材料PF可被挤压以从管芯/装置附接区DAZ向外延伸到排除区KOZ，从而形成预填充层360。第二半导体管芯370的导电连接件372可对应地连接到第二导电特征346b。在一些实施例中，第二半导体管芯370的导电连接件372的底部部分可被图案化介电层347密封且导电连接件372的顶部部分可被预填充层360密封。在一些实施例中，预填充材料PF的流动可向外扩散直到抵达第一围阻结构350，以使预填充层360可与第一围阻结构350实体接触。在替代实施例中，点上(dispense)少量的预填充材料PF，以使得在设置第二半导体管芯370之后，预填充层360分布在管芯/装置附接区DAZ内且可不与第一围阻结构350A接触。在一些实施例中，在第一围阻结构350A的外边缘与第二围阻结构350B中相邻的一个第二围阻结构350B的最近边缘之间存在足够的距离R1。举例来说，距离R1介于约80μm到约100μm的范围内。
参照图17及图18，在图案化介电层347的顶表面347a之上设置第二屏蔽结构S3以覆盖第一围阻结构350A、第二半导体管芯370及下伏的预填充层360。第二屏蔽结构S3可包括暴露出第二围阻结构350B的穿孔TH3。在一些实施例中，第二屏蔽结构S3包括上部盖体S3a及连接到上部盖体S3a的侧壁S3b。被第二屏蔽结构S3覆盖的第一围阻结构350A及第二半导体管芯370在空间上与上部盖体S3a及侧壁S3b分离。在一些实施例中，侧壁S3b可设置在第一围阻结构350A与第二围阻结构350B之间，以在其之间间隔开。在设置第二屏蔽结构S3之后，在设置导电球之前使用印刷工艺或其他合适的工艺在被第二围阻结构350B及图案化介电层347暴露出的图案化导电层346的第一导电特征346a上形成助焊剂材料FM。接下来，在第二屏蔽结构S3之上设置导电球且使导电球坠落到第二屏蔽结构S3的穿孔TH3中以形成导电端子380。
随后，移除第二屏蔽结构S3，并对导电端子380以及第二半导体管芯370的导电连接件372选择性地执行回焊工艺以增强附接。导电端子380的形成可与图7及图8所述工艺相似，为简洁起见省略详细说明。在一些实施例中，导电端子380可由焊料材料制成，而第二围阻结构350B可限制焊料材料的流动且可防止焊料材料向外扩散而干涉彼此或者防止污染半导体结构100B的相邻的部分。在预填充材料朝球/凸块安装区BMZ溢出(overflow)之前，第一围阻结构350A可阻挡预填充材料。图18中的虚线框示出对应于导电端子350及第二围阻结构350B的俯视图。在一些实施例中，第二围阻结构350B(例如为环形的(annularshape)或环形圈的(ring shape))可围绕导电端子350。下伏的第二围阻结构350B可为各种形状，例如环形、环形圈、矩形、方形、多边形、椭圆形、钻石形状或其他合适的形状。
图19及图20是示出根据本公开一些示例性实施例的半导体装置的制造方法中的各个阶段的示意性剖视图。参照图19，在安装第二半导体管芯370及形成导电端子380之后，可将临时载体C与绝缘密封体130、第一半导体管芯110及导电元件120分离。临时载体C的移除可与图10所述工艺相似，为简洁起见省略详细说明。在一些实施例中，执行单体化(切割)工艺以沿切割线(未示出)切穿绝缘密封体130及重布线结构340来形成各别的及分离的半导体装置。可在系统芯片(SOC)、集成电路上系统(system on integrated circuit，SOIC)装置或其他适用的封装装置上形成第一围阻结构350A和/或第二围阻结构350B。上面形成有第一围阻结构350A和/或第二围阻结构350B的此种封装装置可与印刷配线板或印刷电路板(printed circuit board，PCB)实体耦合及电耦合，以形成电子总成。电子总成可为例如计算机、无线通信装置、计算机相关外围设备(computer-related peripherals)、娱乐装置或类似装置等电子系统的部分。
参照图20，可在半导体结构100B的相对侧处分别安装装置封装200及封装组件400，并且可将装置封装200及封装组件400电连接到半导体结构100B。在一些实施例中，装置封装200的外部端子210实体连接及电连接到导电元件120，使得装置封装200电耦合到第一半导体管芯110及第二半导体管芯370。可在半导体结构100B与装置封装200之间形成底胶UF以进行保护。半导体结构100B可经由导电端子380连接到封装组件400。第二半导体管芯370可插设在封装组件400与半导体结构100B之间。封装组件400可为例如印刷电路板(PCB)、装置封装、中介层(interposer)或另一些类型的封装组件。在一些实施例中，封装组件400可包括构建在封装组件400内部的导电内连线结构410(例如包括垫、导电迹线、通孔或类似结构)。导电端子380可接合到封装组件400中的导电内连线结构410以在其之间进行电连接。
根据一些实施例，一种半导体装置包括封装结构、第一管芯、第一围阻结构、预填充层及多个导电端子。所述封装结构包括附接区、位于所述附接区周围的排除区。所述第一管芯设置在所述封装结构上及所述附接区中且电连接到所述封装结构。所述第一围阻结构设置在所述封装结构的所述排除区内且环绕所述第一管芯。所述预填充层设置在所述封装结构与所述第一管芯之间且设置在所述第一围阻结构与所述第一管芯之间，其中所述预填充层被限制在所述第一围阻结构内。所述导电端子设置在所述封装结构上，分布在所述封装结构的所述排除区周围且电连接到所述封装结构。
在一些实施例中，所述封装结构还包括第二管芯、在侧向上密封所述第二管芯的绝缘密封体、以及设置在所述绝缘密封体及所述第二管芯上且电连接到所述第二管芯及所述多个导电端子的重布线结构。在一些实施例中，所述第一围阻结构设置在所述第一管芯的侧壁与所述多个导电端子中相邻的一个导电端子的最近边缘之间。在一些实施例中，所述封装结构的所述排除区的距离与所述第一围阻结构的宽度的比例介于约5到约7.5的范围内。在一些实施例中，所述的半导体装置还包括第二围阻结构，其设置在所述封装结构上且环绕所述多个导电端子中的至少一者，其中所述第二围阻结构夹置在所述多个导电端子中的所述至少一者与所述封装结构之间。在一些实施例中，所述封装结构还包括覆盖所述图案化导电层且暴露出所述图案化导电层的部分的图案化介电层，其中所述第二围阻结构设置在所述图案化介电层及所述图案化导电层上且覆盖所述图案化介电层的侧壁。
根据一些实施例，一种半导体装置包括第一管芯、密封所述第一管芯的绝缘密封体、设置在所述绝缘密封体及所述第一管芯上的重布线结构、与所述第一管芯相对地设置在所述重布线结构上且经由所述重布线结构电耦合到所述第一管芯的第二管芯、填充在所述第二管芯与所述重布线结构之间的预填充层、以及设置在所述重布线结构上的第一围阻结构。所述预填充层设置在所述第一围阻结构与所述第二管芯之间且被所述第一围阻结构包围。
在一些实施例中，所述的半导体装置还包括设置在所述重布线结构上且电连接到所述重布线结构的导电端子，其中所述第一围阻结构设置在所述第二管芯与所述导电端子之间。在一些实施例中，所述重布线结构包括图案化介电层及嵌置在所述图案化介电层中的图案化导电层，且所述导电端子设置在所述图案化介电层上且连接到所述图案化导电层。在一些实施例中，所述的半导体装置还包括设置在所述图案化介电层及所述图案化导电层上且覆盖所述图案化介电层的侧壁的第二围阻结构。在一些实施例中，所述第二围阻结构环绕所述导电端子且夹置在所述导电端子、所述重布线结构的所述图案化介电层及所述图案化导电层中。在一些实施例中，所述第一围阻结构及所述第二围阻结构由电绝缘材料制成。在一些实施例中，所述第一围阻结构及所述第二围阻结构中的至少一者由导电膏制成。
根据一些实施例，提供一种半导体装置的制造方法包括提供封装结构，其中所述封装结构包括第一区、环绕所述第一区的第二区以及位于所述第一区与所述第二区之间的第三区。在所述第三区内的所述封装结构上形成第一围阻结构。设置半导体管芯于所述封装结构的所述第一区上且预填充层在其之间，其中所述第一围阻结构阻挡所述预填充层向外流动。在所述封装结构上设置第一屏蔽结构以覆盖所述第一围阻结构及所述半导体管芯，其中所述封装结构的所述第二区被所述第一屏蔽结构暴露出。在所述封装结构的被所述第一屏蔽结构暴露出的所述第二区中形成导电端子。
在一些实施例中，所述封装结构包括多个导电特征，所述多个导电特征形成在所述封装结构的最外侧上，所述方法还包括在印刷所述第一围阻结构之前，在所述封装结构上设置第一图案化掩膜来抵靠所述多个导电特征并暴露出所述封装结构在所述第三区中的一部分。在一些实施例中，所述预填充层是在设置所述半导体管芯之前形成的，所述方法还包括在形成所述预填充层时，设置第二图案化掩模来抵靠所述多个导电特征的一部分、暴露出所述多个导电特征的另一部分且在空间上与所述第一围阻结构分离、以及在所述多个导电特征被所述第二图案化掩模暴露出的所述部分上形成预填充材料。在一些实施例中，所述的方法还包括在设置所述半导体管芯时，所述预填充材料被挤压从所述第一区向外延伸以形成所述预填充层。在一些实施例中，所述封装结构包括形成在所述封装结构的最外侧上的图案化介电层，所述方法还包括在印刷所述第一围阻结构时，在所述第二区中与在所述图案化介电层的表面上印刷第二围阻结构且延伸以覆盖所述图案化介电层的侧壁。在一些实施例中，所述方法还包括在印刷所述第一围阻结构及所述第二围阻结构时，设置第三图案化掩模来抵靠所述封装结构的所述图案化介电层且暴露出所述封装结构的所述第二区的部分及所述第三区的部分。在一些实施例中，所述预填充层是在将所述半导体管芯设置在所述封装结构的所述第一区上之前形成的，所述方法还包括在形成所述预填充层时，在所述封装结构上设置第二屏蔽结构以覆盖所述第一围阻结构及所述第二围阻结构且暴露出所述封装结构的所述第一区。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本公开的各个方面。所属领域中的技术人员应理解，其可容易地使用本公开作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的和/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本公开的精神及范围，而且他们可在不背离本公开的精神及范围的条件下在本文中作出各种改变、代替及变更。
[符号的说明]
100A、100B：半导体结构
100s：表面
110：第一半导体管芯
110a：半导体衬底
110b：接触垫
110c：钝化层
110d：管芯连接件
110e：保护层
120：导电元件
130：绝缘密封体
140、340：重布线结构
141、143、145、147、347：图案化介电层
142、144、146、346：图案化导电层
147a、347a：顶表面
148、346a：第一导电特征
149、346b：第二导电特征
150、350A：第一围阻结构
160、360：预填充层
170、370：第二半导体管芯
172、372：导电连接件
180、380：导电端子
200：装置封装
210：外部端子
347b：第二导电特征/侧壁
350B：第二围阻结构
400：封装组件
410：导电内连线结构
A、B：虚线区
AP1：第一开孔
AP2：第二开孔
AP3：第三开孔
AP4：第四开孔
BMZ：球/凸块安装区
C：临时载体
C1：剥离层
D1：排除距离
DAZ：管芯/装置附接区
FM：助焊剂材料
H1：高度
IM：障壁材料
KOZ：排除区
MP：中间部分
OP1：第一开口
OP2：第二开口
OS：最外侧
PF：预填充材料
PM1：第一图案化掩模
PM2：第二图案化掩模
PM3：第三图案化掩模
PP：外围部分
R1：距离
S1：屏蔽结构
S1a、S2a、S3a：上部盖体
S1b、S2b、S3b：侧壁
S2：第一屏蔽结构
S3：第二屏蔽结构
SD1：半导体装置
TH1、TH2、TH3：穿孔
TL：工具
UF：底胶
W1：宽度。

Claims (1)

1.一种半导体装置，其特征在于，包括：
封装结构，包括附接区以及位于所述附接区周围的排除区；
第一管芯，设置在所述封装结构上及所述附接区中且电连接到所述封装结构；
第一围阻结构，设置在所述封装结构的所述排除区内且环绕所述第一管芯；
预填充层，设置在所述封装结构与所述第一管芯之间且设置在所述第一围阻结构与所述第一管芯之间，其中所述预填充层被限制在所述第一围阻结构内；以及
多个导电端子，设置在所述封装结构上，分布在所述封装结构的所述排除区周围且电连接到所述封装结构。
CN201910527925.4A 2018-07-31 2019-06-18 半导体装置及其制造方法 Pending CN110783294A (zh)

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