TW202008545A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW202008545A
TW202008545A TW108120471A TW108120471A TW202008545A TW 202008545 A TW202008545 A TW 202008545A TW 108120471 A TW108120471 A TW 108120471A TW 108120471 A TW108120471 A TW 108120471A TW 202008545 A TW202008545 A TW 202008545A
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Taiwan
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conductive
die
semiconductor
patterned
layer
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TW108120471A
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English (en)
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盧貫中
蘇安治
葉德強
黃立賢
林岳霆
葉名世
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台灣積體電路製造股份有限公司
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Publication of TW202008545A publication Critical patent/TW202008545A/zh

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Abstract

提供一種半導體裝置及其製造方法。所述半導體裝置包括封裝結構、第一晶粒、第一圍阻結構、預填充層及多個導電端子。封裝結構包括附接區、位於附接區周圍的排除區。第一晶粒設置在附接區中的封裝結構上且電性地連接到封裝結構。第一圍阻結構設置在封裝結構的排除區內且環繞第一晶粒。預填充層設置在封裝結構與第一晶粒之間且設置在第一圍阻結構與第一晶粒之間，其中預填充層被限制在第一圍阻結構內。導電端子設置在封裝結構上，分佈在封裝結構的排除區周圍且電性地連接到封裝結構。

Description

半導體裝置及其製造方法
本發明的實施例是有關於一種半導體裝置及其製造方法，特別是有關於一種包括用圍阻結構來限制預填充層的半導體裝置及其製作方法。
近年來，由於各種電子元件（例如電晶體、二極體、電阻器、電容器等）的積體密度持續提高，半導體工業已經歷快速成長。在很大程度上，積體密度的這種提高來自於最小特徵尺寸（minimum feature size）的不斷減小，這使得更多元件能夠整合到給定區域中。這些較小的電子元件也需要與先前的封裝相比佔據較小面積的較小的封裝。半導體裝置封裝的類型的實例包括三維積體電路（three-dimensional integrated circuit，3DIC）、晶圓級封裝（wafer level package，WLP）及堆疊封裝（package on package，PoP）裝置等。一些半導體裝置是藉由以半導體晶圓級將晶圓放置在彼此之上來製備的。半導體裝置提供提高的機體密度及其他優點（例如更快的速度及更高的頻寬），這是因為堆疊晶圓之間的內連線的長度減小。然而，存在與半導體裝置相關的許多挑戰。
根據一些實施例，一種半導體裝置包括封裝結構、第一晶粒、第一圍阻結構、預填充層及多個導電端子。所述封裝結構包括附接區、位於所述附接區周圍的排除區。所述第一晶粒設置在所述封裝結構上及所述附接區中且電性地連接到所述封裝結構。所述第一圍阻結構設置在所述封裝結構的所述排除區內且環繞所述第一晶粒。所述預填充層設置在所述封裝結構與所述第一晶粒之間且設置在所述第一圍阻結構與所述第一晶粒之間，其中所述預填充層被限制在所述第一圍阻結構內。所述導電端子設置在所述封裝結構上，分佈在所述封裝結構的所述排除區周圍且電性地連接到所述封裝結構。
根據一些實施例，一種半導體裝置包括第一晶粒、密封所述第一晶粒的絕緣密封體、設置在所述絕緣密封體及所述第一晶粒上的重佈線結構、與所述第一晶粒相對地設置在所述重佈線結構上且經由所述重佈線結構電性耦合到所述第一晶粒的第二晶粒、填充在所述第二晶粒與所述重佈線結構之間的預填充層、以及設置在所述重佈線結構上的第一圍阻結構。所述預填充層設置在所述第一圍阻結構與所述第二晶粒之間且被所述第一圍阻結構包圍。
根據一些實施例，提供一種半導體裝置的製造方法包括提供封裝結構，其中所述封裝結構包括第一區、環繞所述第一區的第二區以及位於所述第一區與所述第二區之間的第三區。在所述第三區內的所述封裝結構上形成第一圍阻結構。設置半導體晶粒於所述封裝結構的所述第一區上且預填充層在其之間，其中所述第一圍阻結構阻擋所述預填充層向外流動。在所述封裝結構上設置第一遮罩結構以覆蓋所述第一圍阻結構及所述半導體晶粒，其中所述封裝結構的所述第二區被所述第一遮罩結構暴露出。在所述封裝結構的被所述第一遮罩結構暴露出的所述第二區中形成導電端子。
以下公開內容提供許多不同的實施例或實例以用於實施本發明的實施例的不同特徵。以下闡述元件及配置形式的具體實例以簡化本公開內容。當然，這些僅為實例而並非旨在進行限制。舉例來說，以下說明中將第一特徵形成在第二特徵“之上”或第二特徵“上”可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本公開內容可能在各種實例中重複使用參考編號及/或字母。這種重複使用是出於簡明及清晰的目的，而自身並不表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“之下（beneath）”、“下面（below）”、“下部的（lower）”、“上方（above）”、“上部的（upper）”等空間相對性用語來闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。設備可具有其他取向（例如，旋轉90度或處於其他取向）且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
另外，為易於說明，本文中可能使用例如“第一”、“第二”等用語來闡述圖中所示出的相似或不同的元件或特徵且可依據存在的次序或說明的上下文而互換地使用。
其他特徵和製程也可能包括在內。例如可以包括測試結構以說明3D封裝或3DIC裝置的驗證測試。測試結構可以包括，例如形成在重佈線層（redistribution layer）中或基底上的測試接墊，其允許測試3D封裝或3DIC，探針及/或探針卡（probe card）的使用等。驗證測試可以在中間結構以及最終結構上進行。另外，本文公開的結構和方法可以與包含已知良好晶粒（known good die）的中間驗證的測試方法結合使用，以增加良率並降低成本。
圖1及圖2是示出根據本公開一些示例性實施例的半導體結構的製造方法中的各個階段的示意性剖視圖。在示例性實施例中，所述製造方法是晶圓級封裝製程的部分。可在半導體結構中封裝一種或多種類型的積體電路晶粒以形成例如系統晶片（system on a chip，SoC）裝置。參照圖1，提供臨時載體C且在臨時載體C上提供第一半導體晶粒110以及位於第一半導體晶粒110旁邊的多個導電元件120。在一些實施例中，在臨時載體C上形成剝離層C1。臨時載體C可為玻璃載體、陶瓷載體或類似載體。剝離層C1可由聚合物系材料（例如光熱轉換（light to heat conversion，LTHC）材料）形成，所述聚合物系材料可與臨時載體C一起從將在隨後製程中形成的上覆結構移除。在一些實施例中，在臨時載體C上設置多於一個半導體晶粒。舉例來說，第一半導體晶粒110包括選自以下的一種或多種類型的晶片：數位晶片（digital chip）、類比晶片（analog chip）或混合訊號晶片、應用專用積體電路（application-specific integrated circuit，ASIC）晶片、感測器晶片、記憶體晶片或邏輯晶片及/或其他電子裝置。
在一些實施例中，第一半導體晶粒110包括半導體基板110a、位於半導體基板110a之上的接觸墊110b、位於半導體基板110a之上且暴露出接觸墊110b的部分的鈍化層110c、位於鈍化層110c之上且電性地連接到接觸墊110b的晶粒連接件110d以及位於鈍化層110c之上且位於晶粒連接件110d旁邊的保護層110e。在一些實施例中，晶粒連接件110d包括導電柱或通孔、焊料凸塊、金凸塊、銅柱或類似連接件，並且藉由電鍍製程或其他合適的沉積製程形成。上面分佈有晶粒連接件110d以用於進一步的電性地連接的表面可被稱為第一半導體晶粒110的主動表面。在一些實施例中，保護層110e包含聚苯並惡唑（polybenzoxazole，PBO）、聚醯亞胺（polyimide，PI）、合適的有機材料或無機材料或類似材料。在一些實施例中，在拾取第一半導體晶粒110並將第一半導體晶粒110放置在臨時載體C上之前，在臨時載體C上形成導電元件120。在替代實施例中，在拾取第一半導體晶粒110並將第一半導體晶粒110放置在臨時載體C上之後，在臨時載體C上設置導電元件120。導電元件120的材料包括銅、鎳、焊料、其組合或類似材料。在一些實施例中，藉由電鍍製程或其他合適的沉積製程來形成導電元件120。在一些替代實施例中，省略導電元件120。應理解的是，導電元件120的數目及位置是可變化的且可視需要進行修改。
繼續參照圖1，在臨時載體C之上形成絕緣密封體130以在側向上密封第一半導體晶粒110及導電元件120。絕緣密封體130可暴露出導電元件120的頂表面以及第一半導體晶粒110的晶粒連接件110d的頂表面以進行進一步的電性地連接。絕緣密封體130包含模塑化合物（例如環氧樹脂）、感光材料（例如聚苯並惡唑（PBO）、聚醯亞胺（PI）或苯並環丁烯（benzocyclobutene，BCB））、其組合或者其他合適的電絕緣材料。形成絕緣密封體130的方法包括在臨時載體C上形成絕緣材料（未示出）以覆蓋第一半導體晶粒110及導電元件120以及執行研磨製程、化學機械拋光（chemical mechanical polishing，CMP）製程或其他平坦化製程以部分地移除絕緣材料直到暴露出導電元件120的頂表面以及第一半導體晶粒110的晶粒連接件110d的頂表面為止。在研磨製程之後，可選地執行清潔步驟例如以清潔及移除從研磨製程產生的殘留物。然而，本公開並非僅限於此，所述平坦化步驟可藉由任何其他合適的技術來執行。在形成絕緣密封體130及平坦化製程之後，導電元件120穿透過絕緣密封體130，其中導電元件120的頂表面被暴露出。在一些實施例中，導電元件120可被稱為絕緣體穿孔（through insulator via，TIV）。
參照圖2，在第一半導體晶粒110之上形成重佈線結構140且重佈線結構140電性地連接到第一半導體晶粒110。在一些實施例中，重佈線結構140基於電路設計要求而包括至少一個圖案化介電層（例如141、143、145及147）以及至少一個圖案化導電層（例如142、144及146）。圖案化導電層（例如142、144及146）可包括導電特徵（例如線路、通孔及接墊）且可藉由圖案化及金屬化技術（例如微影、蝕刻、CMP、薄膜沉積、鍍覆、鑲嵌處理等）或其他合適的製程形成。圖案化導電層142物理性地連接到且電性地連接到第一半導體晶粒110的晶粒連接件110d以及導電元件120。圖案化導電層142可穿透過圖案化介電層141。圖案化導電層144電性地連接到圖案化導電層142且穿透過圖案化介電層143。圖案化導電層146電性地連接到圖案化導電層144且穿透過圖案化介電層145且圖案化介電層147覆蓋圖案化導電層146。圖案化介電層141、143、145及147的材料可包括感光材料，例如聚苯並惡唑（PBO）、聚醯亞胺（PI）、苯並環丁烯（BCB）、其組合或類似材料。圖案化導電層142、144及146的材料可包括銅、鎳、鈦、其組合或類似材料且藉由電鍍製程或其他合適的沉積製程形成。應理解的是，本公開不限制圖案化介電層或圖案化導電層的數目。
參照圖2，重佈線結構140包括位於圖案化介電層147上的多個第一導電特徵148及多個第二導電特徵149，所述多個第二導電特徵149位於第一導電特徵148旁邊。在一些實施例中，位於圖案化介電層147上且連接到下伏的圖案化導電層146的第一導電特徵148及第二導電特徵149可被視為重佈線結構140的另一圖案化導電層。在一些實施例中，第一導電特徵148及第二導電特徵149中的每一者的材料包括銅、鎳、鈦、其組合或類似材料且可藉由電鍍製程或其他合適的沉積製程形成。第一導電特徵148及第二導電特徵149可包括微凸塊、導電接墊、金屬化圖案、焊料連接件及/或類似導電特徵。在一些實施例中，第一導電特徵148包括用於進行隨後植球製程的凸塊下金屬（under-ball metallurgy，UBM）接墊。在一些實施例中，第一導電特徵148由銅製成。在替代實施例中，第一導電特徵148可為由包括鈦、鎳、銅、金、鈀、其合金或類似材料的材料製成的多層式接墊。在一些實施例中，第二導電特徵149包括用於電性地連接其他半導體晶粒/裝置的微凸塊接墊。在一些實施例中，與第一導電特徵148相比，第二導電特徵149的尺寸較小使得能夠實現第二導電特徵149的精細間距並實現高密度連接。在一些實施例中，第一導電特徵148與第二導電特徵149由相同的微影光罩（lithography reticle）或光罩（photomask）界定。在替代實施例中，第一導電特徵148與第二導電特徵149依序形成或者由不同的圖案化製程形成。
在形成重佈線結構140之後，在臨時載體C上形成包括第一導電特徵148及第二導電特徵149的半導體結構（即封裝結構）100A，如圖2所示。在一些實施例中，形成在半導體結構100A的最外側OS處的重佈線結構140可包括第一區、環繞第一區的第二區以及位於第一區與第二區之間的第三區，其中半導體晶粒或半導體裝置在第一區位移或定位。在一些實施例中，第一區被稱為晶粒/裝置附接區DAZ，而第二區及第三區被稱為球/凸塊安裝區BMZ及排除區（keep-out zone）KOZ。在一些實施例中，晶粒/裝置附接區DAZ可被指定用於安裝一個或多個半導體晶粒。在一些實施例中，球/凸塊安裝區BMZ可被指定用於安裝外部連接件（例如導電凸塊、球柵陣列（ball grid array，BGA）球或焊球），排除區KOZ插設在晶粒/裝置附接區DAZ與球/凸塊安裝區BMZ之間。之後將在其他實施例中更詳細地論述這些區。舉例來說，第二導電特徵149形成在晶粒附接區DAZ中且第一導電特徵148形成在植球區BMZ中。在一些實施例中，第二導電特徵149中最外部的一個第二導電特徵149的邊緣以及第一導電特徵148中相鄰的一個第一導電特徵148的最近邊緣附近的區可被視為排除區KOZ。
圖3到圖8是示出圖2所示虛線區A且示出根據本公開一些示例性實施例的形成導電端子以及在半導體結構上設置半導體晶粒的方法中的各個階段的放大的示意性剖視圖。參照圖3及圖4，在排除區KOZ（例如緊密環繞晶粒/裝置附接區DAZ的區）內的半導體結構100A的最外側OS上形成第一圍阻結構（containment structure）150。第一圍阻結構150的材料可包括聚合物（例如環氧樹脂（epoxy resin）、酚醛樹脂（phenolic resin））、阻焊劑（solder resist）、黏合劑、金屬或其他合適的障壁材料（barrier material）。在一些替代實施例中，第一圍阻結構150可由導電膏（例如導電顆粒與黏接劑（binder）的混合物）製成。根據所應用的材料而定，採用合適的製程（例如印刷（printing）、點膠（dispensing）、噴塗（spraying）或其他適用的沉積製程）來形成第一圍阻結構150。在一些實施例中，在重佈線結構140上覆蓋包括第一開孔AP1的第一圖案化遮罩PM1。第一圖案化遮罩PM1可為具有與排除區KOZ的位置對應的第一開孔AP1的鋼板（stencil）（如金屬片材）。在一些實施例中，第一開孔AP1定位在靠近排除區KOZ內的第二導電特徵149的最外部的一個第二導電特徵149的邊緣。第一圖案化遮罩PM1的第一開孔AP1可形成為封閉環（如矩形環狀、環狀、多邊形環狀或類似形狀）的圖案。
舉例來說，第一圖案化遮罩PM1直接抵靠第一導電特徵148及第二導電特徵149以接近圖案化介電層147的頂表面147a且第一圖案化遮罩PM1與圖案化介電層147的頂表面147a在空間上彼此分離。接下來，可在圖案化介電層147的頂表面147a上或者在第一圖案化遮罩PM1的平面部分上形成障壁材料IM。在一些實施例中，障壁材料IM包括環氧助焊劑（epoxy flux）或其他合適的材料。環氧助焊劑可包括環氧樹脂及助焊劑組分。在替代實施例中，障壁材料IM可為導電膏。舉例來說，一個或多個工具TL（例如刮板（squeegee）、刀片（blade）或刷具（wiper））可來回地刷過第一圖案化遮罩PM1以在第一圖案化遮罩PM1的第一開孔AP1中塗上障壁材料IM。在一些實施例中，向第一圖案化遮罩PM1的第一開孔AP1中點上（dispense）預定量的障壁材料IM且藉由表面張力（surface tension）形成圓形表面。
在一些實施例中，障壁材料IM被作為半流體被塗上。然後，將第一圖案化遮罩PM1移除，包圍第二導電特徵149的障壁材料IM餘留在圖案化介電層147的頂表面147a上。隨後，可執行固化製程以使障壁材料IM凝固從而形成第一圍阻結構150。在一些實施例中，使障壁材料IM固化的條件包括使障壁材料IM經受約100℃到約180℃的溫度達約60分鐘。在某些實施例中，固化溫度介於約150℃與約160℃之間達約30分鐘。應理解的是，固化條件可根據設計要求而進行調整，固化條件並非僅限於此。
第一圍阻結構150可被形成為呈各種剖面形狀的擋壩結構或擋牆結構。在一些實施例中，第一圍阻結構150實質上是環形壁結構。儘管圖4示出第一圍阻結構150的圓形（凸起）頂表面，然而第一圍阻結構150的頂表面可具有其他形狀，包括平坦表面、凹陷表面等。第一圍阻結構150可包括介於約20微米（μm）到約30 μm範圍內的寬度W1。第一圍阻結構150的高度H1可介於約20 μm到約30 μm的範圍內。第一圍阻結構150的最佳尺寸（例如寬度W1、高度H1等）與各種因素相關，所述各種因素包括第二導電特徵149的尺寸以及隨後安裝元件的尺寸。在一些實施例中，第一圍阻結構150的高度H1小於圖案化介電層147的頂表面147a上的每一第一導電特徵148的厚度（或每一第二導電特徵149的厚度）。在替代實施例中，第一圍阻結構150的高度H1實質上等於或大於圖案化介電層147的頂表面147a上的每一第一導電特徵148的厚度（或每一第二導電特徵149的厚度）。應理解的是，在本說明通篇中陳述的值僅為實例且可改變成不同的值。
參照圖5，在晶粒/裝置附接區DAZ內的圖案化介電層147的頂表面147a上形成預填充（pre-fill）材料PF以覆蓋第二導電特徵149。預填充材料PF可包含聚合物、環氧樹脂或合適的黏合材料。舉例來說，在重佈線結構140上覆蓋包括第二開孔AP2的第二圖案化遮罩PM2。第二開孔AP2可暴露出形成在晶粒/裝置附接區DAZ中的第二導電特徵149。第二開孔AP2的尺寸可根據隨後安裝的元件（例如圖6所示第二半導體晶粒170）的尺寸而定。舉例來說，第二圖案化遮罩PM2的開口面積對隨後安裝的組件的表面積的比介於約45%到約65%的範圍內。第二圖案化遮罩PM2可抵靠球/凸塊安裝區BMZ中的第一導電特徵148且可覆蓋排除區KOZ中的第一圍阻結構150。接下來，在第二圖案化遮罩PM2之上以及第二開孔AP2內部塗上預填充材料PF且可使用工具TL除掉過量的預填充材料PF。然後，移除第二圖案化遮罩PM2，預填充材料PF留在圖案化介電層147上且覆蓋第二導電特徵149。
參照圖6，在第二導電特徵149上設置第二半導體晶粒170以電性地連接半導體結構100A。舉例來說，拾取第二半導體晶粒170且將第二半導體晶粒170放置在第二導電特徵149及預填充材料PF之上。第二半導體晶粒170可位於第一半導體晶粒110（圖2所示）之上且與第一半導體晶粒110對齊。作為另外一種選擇，第二半導體晶粒170可與絕緣密封體130及/或導電元件120（圖2所示）對齊。在一些實施例中，第二半導體晶粒170包括導電連接件172，在設置第二半導體晶粒170之後，導電連接件172分佈在晶粒/裝置附接區DAZ內。第二半導體晶粒170經由導電連接件172電性地連接到第二導電特徵149。導電連接件172可包括導電接墊/導電柱、焊料凸塊、其組合或類似材料。在一個實施例中，導電連接件172可藉由在第二導電特徵149之上印刷焊料材料形成。可在重佈線結構140上設置一個或多個第二半導體晶粒170。應注意，出於例示目的在圖中存在單個第二半導體晶粒170，但本文不限制要安裝在重佈線結構140上的第二半導體晶粒170的數目且可基於設計要求而變化。在一些實施例中，可由一個或多個第二半導體晶粒170來對一個或多個第一半導體晶粒110進行程式設計（program）。舉例來說，可使用第二半導體晶粒170來對相應的半導體裝置的性能進行微調。在一些實施例中，第二半導體晶粒170是離散的被動裝置，所述離散的被動裝置未形成在其中形成有主動裝置（例如電晶體及二極體）的相同晶粒中。在一些實施例中，第二半導體晶粒170可為矽系（silicon based）的（或陶瓷系的）且其中具有被動裝置。舉例來說，第二半導體晶粒170中可不形成有主動裝置。第二半導體晶粒170可包括電容器、電阻器、電感器及/或類似裝置。第二半導體晶粒170可為整合型被動裝置（integrated passive device，IPD）、表面安裝裝置（surface mount device，SMD）或其他合適的封裝組件。
在一些實施例中，當安裝第二半導體晶粒170時，第二導電特徵149上的預填充材料PF可被擠壓以從晶粒/裝置附接區DAZ向外延伸到排除區KOZ，從而形成預填充層160。舉例來說，在設置第二半導體晶粒170期間，過量的預填充材料PF可流出至晶粒/裝置附接區DAZ外，接著預填充材料PF的流動可向外擴散直到抵達第一圍阻結構150，使得預填充層160可與第一圍阻結構150物理性地接觸。在替代實施例中，點上（dispense）少量的預填充材料，以使得在設置第二半導體晶粒170之後，預填充層160分佈在晶粒/裝置附接區DAZ內，而不會向外擴散到排除區KOZ且可不與第一圍阻結構150接觸。在設置第二半導體晶粒170之後，第二半導體晶粒170的導電連接件172與下伏的第二導電特徵149物理性地連接且電性地連接。插設在第二半導體晶粒170與重佈線結構140之間的預填充層160可密封導電連接件172以及下伏的第二導電特徵149。可對第一圍阻結構150的尺寸進行設定，以阻擋預填充材料PF向外擴散出排除區KOZ。在一些實施例中，第一圍阻結構150使第二半導體晶粒170之下的預填充層160能夠定位在排除區KOZ內且使預填充層160填充於被第一圍阻結構150包圍的區域。
參照圖7及圖8，在第一導電特徵148上形成導電端子180以電性地連接半導體結構100A。導電端子180可與第二半導體晶粒170相鄰地設置。在一些實施例中，多個導電端子180排列在與球/凸塊安裝區BMZ內的第一導電特徵148的位置對應的位置處。導電端子180物理性地連接及電性地連接到重佈線結構140的第一導電特徵148以使第二半導體晶粒170及第一半導體晶粒110電性耦合到導電端子180。在一些實施例中，導電端子180由具有低電阻率的導電材料（例如焊料、銅、鋁、金、鎳、銀、鈀、錫、其合金或類似材料）製成。導電端子180可為球柵陣列（BGA）連接件、焊球、金屬柱或類似裝置。
在一些實施例中，導電端子180藉由在開始時藉由例如著球（ball drop）、蒸鍍（evaporation）、電鍍、印刷或類似方法等方法形成焊料層來形成。舉例來說，植球製程可包括以下步驟。在圖案化介電層147的頂表面147a之上設置包括穿孔TH1的遮罩結構S1以覆蓋第二半導體晶粒170、下伏的預填充層160及第一圍阻結構150。遮罩結構S1的穿孔TH1可暴露出球/凸塊安裝區BMZ中的第一導電特徵148。在一些實施例中，遮罩結構S1包括上部蓋體S1a以及連接到上部蓋體S1a的側壁S1b以覆蓋第二半導體晶粒170以及第一圍阻結構150內的下伏的預填充層160，側壁S1b可使第一導電特徵148與相鄰的第一圍阻結構150在空間上隔離。舉例來說，第一圍阻結構150可為實質上環繞預填充層160及上覆的第二半導體晶粒170的矩形障壁結構，具有擋牆結構（retaining wall structure）（例如包括從頂部面板及分區面板製作的矩形框架）的遮罩結構S1可在處理期間保護第一圍阻結構150。
在設置遮罩結構S1之後，在設置導電球之前使用印刷製程或其他合適的製程來向第一導電特徵148上塗上助焊劑材料FM。接下來，在遮罩結構S1之上放置導電球（例如焊球、金球、銅球、鎳球或類似球）。舉例來說，導電球可經受震動以使得導電球墜落到遮罩結構S1的穿孔TH1中且導電球的位置可被遮罩結構S1的穿孔TH1所侷限。在一些實施例中，導電球可被直接放置在助焊劑材料FM上。隨後，移除遮罩結構S1並執行回焊製程。在一些實施例中，執行回焊製程以在第一導電特徵148（例如作為UBM接墊）上形成導電端子180。舉例來說，回焊製程有助於將導電球牢固地結合到下伏的第一導電特徵148，並且在回焊製程之後，可能看不到助焊劑材料FM。在一些實施例中，可藉由在第二導電特徵149及第一導電特徵148上印刷焊料材料以及之後的回焊來同時形成第二半導體晶粒170的導電連接件172及導電端子180。在替代實施例中，在將第二半導體晶粒170設置在重佈線結構140的第二導電特徵149上之前，可在第一導電特徵148上形成導電端子180。
圖9是根據本公開一些示例性實施例的圖8的簡化的示意性俯視圖。參照圖8及圖9，可對排除區KOZ的尺寸進行設定，使得在導電端子180與第二半導體晶粒170的導電連接件172之間存在足夠的空間。在一些實施例中，排除區KOZ可包括一區，在所述區中，導電端子180中的任一者的邊緣與第二半導體晶粒170的邊緣間隔開排除距離D1。在一些實施例中，第一圍阻結構150設置在第二半導體晶粒170的每一側壁與所述多個導電端子180中相鄰的一個導電端子180的最近邊緣之間。在一些實施例中，第二半導體晶粒170的每一側壁到相鄰的導電端子180的最近邊緣之間的排除距離D1可實質上相等。在一些其他實施例中，根據佈線（layout）要求而定，從第二半導體晶粒170的側壁中的任一者到導電端子180中相鄰的一個導電端子180的最近邊緣可存在不同的排除距離。
在一些實施例中，由於在半導體結構100A上能安裝有更多第二半導體晶粒170，第二半導體晶粒170的側壁到相鄰的導電端子180的最近邊緣之間的排除距離D1可期望為較小。在一些實施例中，排除距離D1與第一圍阻結構150的寬度W1的比例介於約5到約7.5的範圍內。應理解的是，在本文通篇中陳述的值僅為實例且可改變成不同的值。為防止在第二導電特徵149上所塗的預填充材料PF外流或者甚至影響在第一導電特徵148上所塗的助焊劑材料FM，在排除區KOZ中形成的第一圍阻結構150可限制預填充材料PF的流動，從而防止過量的預填充材料PF流出而造成內連線缺陷及檢查故障，因此排除區KOZ的尺寸要求可減小且導電端子180的分佈密度可因此增大。
圖10及圖11是示出根據本公開一些示例性實施例的半導體裝置的製造方法中的各個階段的示意性剖視圖。參照圖10及圖11，在安裝第二半導體晶粒170及形成導電端子180之後，可將臨時載體C與絕緣密封體130、第一半導體晶粒110及導電元件120分離。在一些實施例中，藉由以紫外光或雷射來輻照設置在臨時載體C之上的剝離層C1來剝離臨時載體C，以暴露出半導體結構100A的表面100s。半導體結構100A的表面100s具有被絕緣密封體130暴露出的導電元件120的部分以進行進一步的電性地連接。舉例來說，可在半導體結構100A上堆疊多個積體電路封裝，以在堆疊式封裝（package-on-package，POP）結構中提供附加的功能。
在一些實施例中，在半導體結構100A的表面100s上設置裝置封裝200以形成半導體裝置SD1。裝置封裝200為例如記憶體裝置（例如靜態隨機存取記憶體（static random access memory，SRAM）、動態隨機存取記憶體（dynamic random access memory，DRAM）等）或其他合適的半導體裝置。裝置封裝200可堆疊在半導體結構100A之上且經由外部端子210電性地連接到半導體結構100A。在一些實施例中，裝置封裝200的外部端子210物理性地連接及電性地連接到導電元件120，使裝置封裝200電性耦合到第一半導體晶粒110及第二半導體晶粒170。在一些實施例中，在半導體結構100A與裝置封裝200之間形成底膠UF。底膠UF可被點（dispense）成覆蓋至少外部端子210以用於保護。在一些實施例中，底膠UF可覆蓋半導體結構100A的表面100s且可包繞裝置封裝200的至少底部部分。在一些實施例中，接著執行單體化（切割）製程以沿切割線（未示出）切穿至少底部填充材料UF、絕緣密封體130及重佈線結構140來形成各別的且分離的半導體裝置SD1。在一些實施例中，所述單體化製程包括機械鋸切或雷射切割的晶圓切割製程。
圖12是示出根據本公開一些示例性實施例的半導體結構的示意性剖視圖。在如圖1及圖2中所述的前述製造製程之後，可製作出圖12所示半導體結構100B。半導體結構100A與半導體結構100B之間的差異在於重佈線結構。參照圖12，重佈線結構340的圖案化導電層346電性地連接到圖案化導電層144且穿透過圖案化介電層145，並且圖案化介電層347部分地覆蓋圖案化導電層346。圖案化導電層346可包括第一導電特徵346a及第二導電特徵346b。舉例來說，圖案化介電層347包括第一開口OP1及第二開口OP2。第一開口OP1可暴露出下伏的第一導電特徵346a且第二開口OP2可暴露出下伏的第二導電特徵347b，以進行進一步的電性地連接。
圖13到圖18是示出圖12所示虛線區B且示出根據本公開一些示例性實施例的形成導電端子以及在半導體結構上設置半導體晶粒的方法中的各個階段的放大的示意性剖視圖。參照圖13，在圖案化介電層347的頂表面347a上覆蓋包括第三開孔AP3及第四開孔AP4的第三圖案化遮罩PM3。在一些實施例中，第三圖案化遮罩PM3可為具有實質上對應於至少球/凸塊安裝區BMZ的第三開孔AP3以及對應於排除區KOZ的位置的第四開孔AP4的鋼板（例如金屬片材）。在一些其他實施例中，第三開孔AP3的部分設置在球/凸塊安裝區BMZ與排除區KOZ的交界處以暴露出這兩個區。舉例來說，第三開孔AP3可部分地暴露出圖案化導電層346的第一導電特徵346a。在一些實施例中，第三圖案化遮罩PM3覆蓋圖案化介電層347的第二開口OP2。圖13中的虛線框示出對應於第三圖案化遮罩PM3、圖案化介電層347及下伏的第一導電特徵346a的俯視圖。舉例來說，就第一導電特徵346a的可被圖案化介電層347的第一開口OP1觸及地顯露的所述部分來說，第三圖案化遮罩PM3覆蓋第一導電特徵346a的中間部分MP且第三圖案化遮罩PM3的第三開孔AP3暴露出第一導電特徵346a的周邊部分PP。
在一些實施例中，第三圖案化遮罩PM3的第三開孔AP3可與圖案化介電層347的第一開口OP1連通且可暴露出圖案化介電層347的頂表面347a及側壁347b（例如連接到頂表面347a及第一導電特徵346a）。在一些實施例中，第四開孔AP4定位在靠近圖案化介電層347的第二開口OP2中最外部的一個第二開口OP2。第三開孔AP3及/或第四開孔AP4可形成為封閉環（例如矩形環狀、環狀、多邊形環狀等）的圖案。在設置第三圖案化遮罩PM3來直接抵靠圖案化介電層347的頂表面347a之後，可在圖案化介電層347的頂表面347a上形成障壁材料IM。舉例來說，一個或多個工具TL（例如刮板（squeegee）、刀片（blade）或刷具（wiper））可來回地刷過第三圖案化遮罩PM3以在第三圖案化遮罩PM3的第三開孔AP3及第四開孔AP4中塗上障壁材料IM。
參照圖14，移除第三圖案化遮罩PM3，分別包圍第一開口OP1及第二開口OP2的兩組障壁材料IM餘留在圖案化介電層347的頂表面347a上。在一些實施例中，障壁材料IM作為半流體被塗上，塗上在圖案化介電層347的頂表面347a上的障壁材料IM的部分可向下流動，以覆蓋圖案化介電層347的側壁347b並抵達第一導電特徵346a的被圖案化介電層347的第一開口OP1顯露出的至少周邊部分PP。可執行固化製程以使障壁材料IM凝固從而在這些第二開口OP2周圍形成第一圍阻結構350A且也在第一開口OP1中的每一者周圍形成第二圍阻結構350B。圖14中的虛線框示出對應於第二圍阻結構350B、圖案化介電層347及下伏的第一導電特徵346a的俯視圖。儘管圖14示出因表面張力而引起的第一圍阻結構350A及第二圍阻結構350B的圓形（凸起）頂表面，但第一圍阻結構350A及第二圍阻結構350B的頂表面可具有其他形狀，包括平坦表面、凹陷表面等。應理解，圖中所示單一個第二圍阻結構350B僅用作例示性實例，可在第一導電特徵346a的部分（或每一者）上形成多個第二圍阻結構350B以進行隨後的植球製程。
所述固化製程可為與圖3及圖4中所述的製程相似的製程，並可根據設計要求來調整固化條件以形成第一圍阻結構350A及第二圍阻結構350B。第一圍阻結構350A連接到圖案化介電層347的頂表面347a，第二圍阻結構350B可與圖案化介電層347的頂表面347a及側壁347b物理性地接觸且還與第一導電特徵346a的被圖案化介電層347的第一開口OP1顯露出的周邊部分PP物理性地接觸。第一導電特徵346a的中間部分MP被第二圍阻結構350B以及圖案化介電層347的第一開口OP1暴露出。在一些實施例中，第一圍阻結構350A及第二圍阻結構350B由電性隔離材料製成。在一些替代實施例中，第一圍阻結構350A與第二圍阻結構350B由不同的材料以及使用不同的圖案化遮罩製成。舉例來說，第二圍阻結構350B可由導電材料（例如焊料、銅等）製成且第一圍阻結構350A可由電絕緣材料製成。在替代實施例中，第一圍阻結構350A與第二圍阻結構350B二者由導電膏製成。
參照圖15，在圖案化介電層347的頂表面347a之上設置第一遮罩結構S2，以覆蓋排除區KOZ及球/凸塊安裝區BMZ中的第一圍阻結構350A及第二圍阻結構350B。第一遮罩結構S2可包括暴露出晶粒/裝置附接區DAZ內的圖案化介電層347的第二開口OP2的穿孔TH2。在一些實施例中，第一遮罩結構S2包括上部蓋體S2a及連接到上部蓋體S2a的側壁S2b。被第一遮罩結構S2覆蓋的第一圍阻結構350A及第二圍阻結構350B在空間上與上部蓋體S2a及側壁S2b分離。在設置第一遮罩結構S2之後，在第一遮罩結構S2的穿孔TH2中塗上預填充材料PF，使得在晶粒/裝置附接區DAZ內並在圖案化介電層347的頂表面347a上及在圖案化介電層347的第二開口OP2內部形成預填充材料PF以覆蓋第二導電特徵346b。
參照圖16，在第二導電特徵346b上形成預填充材料PF之後，第二半導體晶粒370可設置在第二導電特徵346b上且預填充層360形成在其之間。在一些實施例中，當設置第二半導體晶粒370時，第二導電特徵149上的預填充材料PF可被擠壓以從晶粒/裝置附接區DAZ向外延伸到排除區KOZ，從而形成預填充層360。第二半導體晶粒370的導電連接件372可對應地連接到第二導電特徵346b。在一些實施例中，第二半導體晶粒370的導電連接件372的底部部分可被圖案化介電層347密封且導電連接件372的頂部部分可被預填充層360密封。在一些實施例中，預填充材料PF的流動可向外擴散直到抵達第一圍阻結構350，以使預填充層360可與第一圍阻結構350物理性地接觸。在替代實施例中，點上（dispense）少量的預填充材料PF，以使得在設置第二半導體晶粒370之後，預填充層360分佈在晶粒/裝置附接區DAZ內且可不與第一圍阻結構350A接觸。在一些實施例中，在第一圍阻結構350A的外邊緣與第二圍阻結構350B中相鄰的一個第二圍阻結構350B的最近邊緣之間存在足夠的距離R1。舉例來說，距離R1介於約80 μm到約100 μm的範圍內。
參照圖17及圖18，在圖案化介電層347的頂表面347a之上設置第二遮罩結構S3以覆蓋第一圍阻結構350A、第二半導體晶粒370及下伏的預填充層360。第二遮罩結構S3可包括暴露出第二圍阻結構350B的穿孔TH3。在一些實施例中，第二遮罩結構S3包括上部蓋體S3a及連接到上部蓋體S3a的側壁S3b。被第二遮罩結構S3覆蓋的第一圍阻結構350A及第二半導體晶粒370在空間上與上部蓋體S3a及側壁S3b分離。在一些實施例中，側壁S3b可設置在第一圍阻結構350A與第二圍阻結構350B之間，以在其之間間隔開。在設置第二遮罩結構S3之後，在設置導電球之前使用印刷製程或其他合適的製程在被第二圍阻結構350B及圖案化介電層347暴露出的圖案化導電層346的第一導電特徵346a上形成助焊劑材料FM。接下來，在第二遮罩結構S3之上設置導電球且使導電球墜落到第二遮罩結構S3的穿孔TH3中以形成導電端子380。
隨後，移除第二遮罩結構S3，並對導電端子380以及第二半導體晶粒370的導電連接件372選擇性地執行回焊製程以增強附接。導電端子380的形成可與圖7及圖8所述製程相似，為簡潔起見省略詳細說明。在一些實施例中，導電端子380可由焊料材料製成，而第二圍阻結構350B可限制焊料材料的流動且可防止焊料材料向外擴散而干涉彼此或者防止污染半導體結構100B的相鄰的部分。在預填充材料朝球/凸塊安裝區BMZ溢出（overflow）之前，第一圍阻結構350A可阻擋預填充材料。圖18中的虛線框示出對應於導電端子350及第二圍阻結構350B的俯視圖。在一些實施例中，第二圍阻結構350B（例如為環形的（annular shape）或環形圈的（ring shape））可圍繞導電端子350。下伏的第二圍阻結構350B可為各種形狀，例如環形、環形圈、矩形、方形、多邊形、橢圓形、鑽石形狀或其他合適的形狀。
圖19及圖20是示出根據本公開一些示例性實施例的半導體裝置的製造方法中的各個階段的示意性剖視圖。參照圖19，在安裝第二半導體晶粒370及形成導電端子380之後，可將臨時載體C與絕緣密封體130、第一半導體晶粒110及導電元件120分離。臨時載體C的移除可與圖10所述製程相似，為簡潔起見省略詳細說明。在一些實施例中，執行單體化（切割）製程以沿切割線（未示出）切穿絕緣密封體130及重佈線結構340來形成各別的及分離的半導體裝置。可在系統晶圓（SOC）、積體電路上系統（system on integrated circuit，SOIC）裝置或其他適用的封裝裝置上形成第一圍阻結構350A及/或第二圍阻結構350B。上面形成有第一圍阻結構350A及/或第二圍阻結構350B的此種封裝裝置可與印刷配線板或印刷電路板（printed circuit board，PCB）物理性地耦合及電性耦合，以形成電子總成。電子總成可為例如電腦、無線通訊裝置、電腦相關周邊設備（computer-related peripherals）、娛樂裝置或類似裝置等電子系統的部分。
參照圖20，可在半導體結構100B的相對側處分別安裝裝置封裝200及封裝組件400，並且可將裝置封裝200及封裝元件400電性地連接到半導體結構100B。在一些實施例中，裝置封裝200的外部端子210物理性地連接及電性地連接到導電元件120，使得裝置封裝200電性耦合到第一半導體晶粒110及第二半導體晶粒370。可在半導體結構100B與裝置封裝200之間形成底膠UF以進行保護。半導體結構100B可經由導電端子380連接到封裝元件400。第二半導體晶粒370可插設在封裝元件400與半導體結構100B之間。封裝元件400可為例如印刷電路板（PCB）、裝置封裝、中介層（interposer）或另一些類型的封裝組件。在一些實施例中，封裝元件400可包括構建在封裝元件400內部的導電內連線結構410（例如包括墊、導電跡線、通孔或類似結構）。導電端子380可接合到封裝組件400中的導電內連線結構410以在其之間進行電性地連接。
根據一些實施例，一種半導體裝置包括封裝結構、第一晶粒、第一圍阻結構、預填充層及多個導電端子。所述封裝結構包括附接區、位於所述附接區周圍的排除區。所述第一晶粒設置在所述封裝結構上及所述附接區中且電性地連接到所述封裝結構。所述第一圍阻結構設置在所述封裝結構的所述排除區內且環繞所述第一晶粒。所述預填充層設置在所述封裝結構與所述第一晶粒之間且設置在所述第一圍阻結構與所述第一晶粒之間，其中所述預填充層被限制在所述第一圍阻結構內。所述導電端子設置在所述封裝結構上，分佈在所述封裝結構的所述排除區周圍且電性地連接到所述封裝結構。
在一些實施例中，所述封裝結構還包括第二晶粒、在側向上密封所述第二晶粒的絕緣密封體、以及設置在所述絕緣密封體及所述第二晶粒上且電性地連接到所述第二晶粒及所述多個導電端子的重佈線結構。在一些實施例中，所述第一圍阻結構設置在所述第一晶粒的側壁與所述多個導電端子中相鄰的一個導電端子的最近邊緣之間。在一些實施例中，所述封裝結構的所述排除區的距離與所述第一圍阻結構的寬度的比例介於約5到約7.5的範圍內。在一些實施例中，所述的半導體裝置還包括第二圍阻結構，其設置在所述封裝結構上且環繞所述多個導電端子中的至少一者，其中所述第二圍阻結構夾置在所述多個導電端子中的所述至少一者與所述封裝結構之間。在一些實施例中，所述封裝結構還包括覆蓋所述圖案化導電層且暴露出所述圖案化導電層的部分的圖案化介電層，其中所述第二圍阻結構設置在所述圖案化介電層及所述圖案化導電層上且覆蓋所述圖案化介電層的側壁。
根據一些實施例，一種半導體裝置包括第一晶粒、密封所述第一晶粒的絕緣密封體、設置在所述絕緣密封體及所述第一晶粒上的重佈線結構、與所述第一晶粒相對地設置在所述重佈線結構上且經由所述重佈線結構電性耦合到所述第一晶粒的第二晶粒、填充在所述第二晶粒與所述重佈線結構之間的預填充層、以及設置在所述重佈線結構上的第一圍阻結構。所述預填充層設置在所述第一圍阻結構與所述第二晶粒之間且被所述第一圍阻結構包圍。
在一些實施例中，所述的半導體裝置還包括設置在所述重佈線結構上且電性地連接到所述重佈線結構的導電端子，其中所述第一圍阻結構設置在所述第二晶粒與所述導電端子之間。在一些實施例中，所述重佈線結構包括圖案化介電層及嵌置在所述圖案化介電層中的圖案化導電層，且所述導電端子設置在所述圖案化介電層上且連接到所述圖案化導電層。在一些實施例中，所述的半導體裝置還包括設置在所述圖案化介電層及所述圖案化導電層上且覆蓋所述圖案化介電層的側壁的第二圍阻結構。在一些實施例中，所述第二圍阻結構環繞所述導電端子且夾置在所述導電端子、所述重佈線結構的所述圖案化介電層及所述圖案化導電層中。在一些實施例中，所述第一圍阻結構及所述第二圍阻結構由電絕緣材料製成。在一些實施例中，所述第一圍阻結構及所述第二圍阻結構中的至少一者由導電膏製成。
根據一些實施例，提供一種半導體裝置的製造方法包括提供封裝結構，其中所述封裝結構包括第一區、環繞所述第一區的第二區以及位於所述第一區與所述第二區之間的第三區。在所述第三區內的所述封裝結構上形成第一圍阻結構。設置半導體晶粒於所述封裝結構的所述第一區上且預填充層在其之間，其中所述第一圍阻結構阻擋所述預填充層向外流動。在所述封裝結構上設置第一遮罩結構以覆蓋所述第一圍阻結構及所述半導體晶粒，其中所述封裝結構的所述第二區被所述第一遮罩結構暴露出。在所述封裝結構的被所述第一遮罩結構暴露出的所述第二區中形成導電端子。
在一些實施例中，所述封裝結構包括多個導電特徵，所述多個導電特徵形成在所述封裝結構的最外側上，所述方法還包括在印刷所述第一圍阻結構之前，在所述封裝結構上設置第一圖案化掩膜來抵靠所述多個導電特徵並暴露出所述封裝結構在所述第三區中的一部分。在一些實施例中，所述預填充層是在設置所述半導體晶粒之前形成的，所述方法還包括在形成所述預填充層時，設置第二圖案化遮罩來抵靠所述多個導電特徵的一部分、暴露出所述多個導電特徵的另一部分且在空間上與所述第一圍阻結構分離、以及在所述多個導電特徵被所述第二圖案化遮罩暴露出的所述部分上形成預填充材料。在一些實施例中，所述的方法還包括在設置所述半導體晶粒時，所述預填充材料被擠壓從所述第一區向外延伸以形成所述預填充層。在一些實施例中，所述封裝結構包括形成在所述封裝結構的最外側上的圖案化介電層，所述方法還包括在印刷所述第一圍阻結構時，在所述第二區中與在所述圖案化介電層的表面上印刷第二圍阻結構且延伸以覆蓋所述圖案化介電層的側壁。在一些實施例中，所述方法還包括在印刷所述第一圍阻結構及所述第二圍阻結構時，設置第三圖案化遮罩來抵靠所述封裝結構的所述圖案化介電層且暴露出所述封裝結構的所述第二區的部分及所述第三區的部分。在一些實施例中，所述預填充層是在將所述半導體晶粒設置在所述封裝結構的所述第一區上之前形成的，所述方法還包括在形成所述預填充層時，在所述封裝結構上設置第二遮罩結構以覆蓋所述第一圍阻結構及所述第二圍阻結構且暴露出所述封裝結構的所述第一區。
雖然本發明的實施例已以實施例揭露如上，然其並非用以限定本發明的實施例，任何所屬技術領域中具有通常知識者，在不脫離本發明的實施例的精神和範圍內，當可作些許的更動與潤飾，故本發明的實施例的保護範圍當視後附的申請專利範圍所界定者為準。
100A、100B‧‧‧半導體結構 100s‧‧‧表面 110‧‧‧第一半導體晶粒 110a‧‧‧半導體基板 110b‧‧‧接觸墊 110c‧‧‧鈍化層 110d‧‧‧晶粒連接件 110e‧‧‧保護層 120‧‧‧導電元件 130‧‧‧絕緣密封體 140、340‧‧‧重佈線結構 141、143、145、147、347‧‧‧圖案化介電層 142、144、146、346‧‧‧圖案化導電層 147a、347a‧‧‧頂表面 148、346a‧‧‧第一導電特徵 149、346b‧‧‧第二導電特徵 150、350A‧‧‧第一圍阻結構 160、360‧‧‧預填充層 170、370‧‧‧第二半導體晶粒 172、372‧‧‧導電連接件 180、380‧‧‧導電端子 200‧‧‧裝置封裝 210‧‧‧外部端子 347b‧‧‧第二導電特徵/側壁 350B‧‧‧第二圍阻結構 400‧‧‧封裝組件 410‧‧‧導電內連線結構 A、B‧‧‧虛線區 AP1‧‧‧第一開孔 AP2‧‧‧第二開孔 AP3‧‧‧第三開孔 AP4‧‧‧第四開孔 BMZ‧‧‧球/凸塊安裝區 C‧‧‧臨時載體 C1‧‧‧剝離層 D1‧‧‧排除距離 DAZ‧‧‧晶粒/裝置附接區 FM‧‧‧助焊劑材料 H1‧‧‧高度 IM‧‧‧障壁材料 KOZ‧‧‧排除區 MP‧‧‧中間部分 OP1‧‧‧第一開口 OP2‧‧‧第二開口 OS‧‧‧最外側 PF‧‧‧預填充材料 PM1‧‧‧第一圖案化遮罩 PM2‧‧‧第二圖案化遮罩 PM3‧‧‧第三圖案化遮罩 PP‧‧‧周邊部分 R1‧‧‧距離 S1‧‧‧遮罩結構 S1a、S2a、S3a‧‧‧上部蓋體 S1b、S2b、S3b‧‧‧側壁 S2‧‧‧第一遮罩結構 S3‧‧‧第二遮罩結構 SD1‧‧‧半導體裝置 TH1、TH2、TH3‧‧‧穿孔 TL‧‧‧工具 UF‧‧‧底膠 W1‧‧‧寬度
為讓本發明的實施例的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 圖1及圖2是示出根據本公開一些示例性實施例的半導體結構的製造方法中的各個階段的示意性剖視圖。 圖3到圖8是示出圖2所示虛線區A且示出根據本公開一些示例性實施例的形成導電端子以及在半導體結構上設置半導體晶粒的方法中的各個階段的放大的示意性剖視圖。 圖9是根據本公開一些示例性實施例的圖8的簡化的示意性俯視圖。 圖10及圖11是示出根據本公開一些示例性實施例的半導體裝置的製造方法中的各個階段的示意性剖視圖。 圖12是示出根據本公開一些示例性實施例的半導體結構的示意性剖視圖。 圖13到圖18是示出圖12所示虛線區B且示出根據本公開一些示例性實施例的形成導電端子以及在半導體結構上設置半導體晶粒的方法中的各個階段的放大的示意性剖視圖。 圖19及圖20是示出根據本公開一些示例性實施例的半導體裝置的製造方法中的各個階段的示意性剖視圖。
100A‧‧‧半導體結構
110‧‧‧第一半導體晶粒
120‧‧‧導電元件
130‧‧‧絕緣密封體
140‧‧‧重佈線結構
148‧‧‧第一導電特徵
149‧‧‧第二導電特徵
150‧‧‧第一圍阻結構
160‧‧‧預填充層
170‧‧‧第二半導體晶粒
180‧‧‧導電端子
200‧‧‧裝置封裝
210‧‧‧外部端子
BMZ‧‧‧球/凸塊安裝區
DAZ‧‧‧晶粒/裝置附接區
KOZ‧‧‧排除區
SD1‧‧‧半導體裝置
UF‧‧‧底膠

Claims (1)

  1. 一種半導體裝置，包括： 封裝結構，包括附接區以及位於所述附接區周圍的排除區； 第一晶粒，設置在所述封裝結構上及所述附接區中且電性地連接到所述封裝結構； 第一圍阻結構，設置在所述封裝結構的所述排除區內且環繞所述第一晶粒； 預填充層，設置在所述封裝結構與所述第一晶粒之間且設置在所述第一圍阻結構與所述第一晶粒之間，其中所述預填充層被限制在所述第一圍阻結構內；以及 多個導電端子，設置在所述封裝結構上，分佈在所述封裝結構的所述排除區周圍且電性地連接到所述封裝結構。
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