WO2023050093A1 - 芯片封装结构及其封装方法、通信装置 - Google Patents

芯片封装结构及其封装方法、通信装置 Download PDF

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Publication number
WO2023050093A1
WO2023050093A1 PCT/CN2021/121468 CN2021121468W WO2023050093A1 WO 2023050093 A1 WO2023050093 A1 WO 2023050093A1 CN 2021121468 W CN2021121468 W CN 2021121468W WO 2023050093 A1 WO2023050093 A1 WO 2023050093A1
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WO
WIPO (PCT)
Prior art keywords
chip
packaging
bumps
layer
underfill
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PCT/CN2021/121468
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English (en)
French (fr)
Inventor
郭晨鸣
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2021/121468 priority Critical patent/WO2023050093A1/zh
Priority to CN202180099627.5A priority patent/CN117529801A/zh
Publication of WO2023050093A1 publication Critical patent/WO2023050093A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor

Definitions

  • the present application relates to the technical field of semiconductors, and in particular to a chip packaging structure, a packaging method thereof, and a communication device.
  • the chip packaging structure After the high-density bumps of the chip structure are bonded to the packaging substrate, due to the large difference in coefficient of thermal expansion (CTE) between the chip structure and the packaging substrate, when the operating temperature changes, Warpage and stress are easily generated between the packaging substrate and the chip structure.
  • CTE coefficient of thermal expansion
  • an underfill is formed between the chip structure and the packaging substrate.
  • the thermal expansion coefficient difference between the chip structure and the package substrate is relatively large, and the die corner of the chip structure brings a greater stress risk to the underfill.
  • the temperature of the chip package structure is constantly changing during use, resulting in repeated warping of the chip package structure, resulting in repeated squeezes between the corners of the chip structure and the underfill.
  • the repeated extrusion between the corners of the high-modulus chip structure and the low-modulus underfill due to internal stress, expansion, shrinkage, etc. causes the underfill to break and the chip packaging structure to fail.
  • the ratio of the size of the chip structure to the size of the packaging substrate gradually increases, and the above problems become more prominent.
  • Embodiments of the present application provide a chip packaging structure, a packaging method thereof, and a communication device, which are used to solve the problem of failure of the chip packaging structure.
  • a chip packaging structure includes a packaging substrate, a chip structure disposed on the packaging substrate, a molding layer wrapping at least the side of the chip structure, and an underfill glue.
  • the chip structure includes a plurality of bumps on the surface, and the bumps are electrically connected to the packaging substrate; the plastic sealing layer wraps the side of the chip structure, or also wraps the top surface of the chip structure, but does not wrap the bumps; the plastic sealing layer is close to the package
  • the outer bottom of the substrate has a chamfer; the underfill encloses the bump and at least part of the chamfered surface of the chamfer.
  • the embodiment of the present application provides that the chip structure in the chip package structure does not need to have chamfers, and there is no need to reserve a wide dicing line area on the wafer.
  • the actual size of the chip structure is similar to the size of the functional area of the chip structure. Problems such as chip structure damage and wafer waste caused by chamfering on the structure reduce the cost of the chip structure.
  • the chamfering on the plastic encapsulation layer will not affect the chip structure such as cracks, there is no need to have a sintering groove on the plastic encapsulation layer, and there is no need to reserve a safety distance, which can reduce the dicing line area.
  • the size of the plastic packaging layer does not need to be too large, and the size of the chip packaging structure will not be excessively increased. That is to say, after the chamfer on the chip structure is transferred to the plastic encapsulation layer, it can not only relieve the concentrated stress between the sharp corner of the chip structure and the underfill, but also avoid the problem of cracks in the underfill due to the concentrated stress. It can also reduce the cost of the chip packaging structure and solve a series of problems caused by cutting the chip structure. It overcomes the limitation of the chip structure under the chip package with large size and high area ratio, solves the problem of stress concentration at the corners of the chip structure under the large-size chip package, and avoids the failure of the chip package structure under high temperature.
  • the corners of the chip structure are wrapped by the plastic encapsulation layer, and the plastic encapsulation layer is in direct contact with the underfill, which can avoid cracking or warping caused by the direct contact between the corners of the chip structure and the underfill.
  • the chip structure can be cut due to dicing deviation and the problem of cracking the chip structure can be avoided.
  • the underfill overflows from the bottom of the molding layer, overflows the chamfer and wraps the sides of the molding layer.
  • the material of the molding layer includes epoxy resin.
  • the plastic encapsulation layer is used as a stress transition layer between the chip structure and the underfill.
  • the hardness of the epoxy resin is smaller than that of the chip structure. It is easier to form a chamfer on the epoxy resin than to form a chamfer on the chip structure, and it is less harmful to tool wear. Low.
  • the chip structure is: a chip, and bumps are arranged on the chip.
  • the chip structure is not limited, and the application range is wide.
  • the chip structure includes: an interconnection transfer layer; a plurality of via holes penetrating through the interconnection transfer layer; a chip disposed on the interconnection transfer layer and electrically connected to one end of the via hole; the via hole The other end is provided with bumps.
  • the chip structure is not limited, and the application range is wide.
  • the second aspect of the embodiment of the present application provides a packaging method for a chip packaging structure.
  • the chip packaging method includes: forming a plastic sealing film on a carrier board on which a plurality of chip modules are placed; Board, the plastic film wraps at least the side of the chip module; remove the carrier board to expose the contacts; form bumps on the contacts, and the bumps are electrically connected to the contacts; form multiple chamfers on the bottom surface of the plastic film near the bumps Groove, the chamfered groove is located at the gap of the chip module; cut along the cutting line; wherein, the cutting line is located at the gap of the chip module, and the position of the chamfered groove coincides with the position of the cutting line; the assembly structure obtained by cutting is passed through the bump It is electrically connected with the package substrate; an underfill glue is formed between the assembly structure and the package substrate, and the underfill glue is wrapped around the periphery of the plastic packaging film.
  • a plastic sealing film is wrapped around the periphery of the chip structure that does not need to be chamfered, and then the plastic sealing film is cut to form a structure in which the chip structure is wrapped with a plastic sealing layer. Since there is no need to form chamfers on the chip structure, and there is no need to reserve a wide dicing line area on the wafer, the actual size of the finally formed chip structure is similar to the size of the functional area of the chip structure. Therefore, problems such as chip structure damage and wafer waste caused by forming chamfers on the chip structure can be avoided, and the manufacturing cost of the chip structure can be reduced.
  • the process of cutting chamfering grooves on the plastic encapsulation layer to form chamfers will not cause cracks or other effects on the chip structure.
  • the third aspect of the embodiments of the present application provides a communication device, including a printed circuit board and the chip package structure according to any one of the first aspect; the chip package structure is arranged on the printed circuit board and coupled with the printed circuit board.
  • the communication device provided in the third aspect of the embodiment of the present application includes the chip packaging structure in any one of the first aspects, and its beneficial effects are the same as those of the chip packaging structure, and will not be repeated here.
  • FIG. 1 is a schematic structural diagram of a base station provided in an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a chip package structure carried on a PCB provided by an embodiment of the present application;
  • FIG. 3A is a schematic structural diagram of a chip packaging structure provided by an embodiment of the present application.
  • FIG. 3B is a schematic structural diagram of a chip structure provided by an embodiment of the present application.
  • FIG. 3C is a schematic structural diagram of another chip structure provided by the embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another chip packaging structure provided by the embodiment of the present application.
  • FIG. 5 is a schematic flowchart of a packaging method for a chip packaging structure provided in an embodiment of the present application
  • 6A-6P are schematic diagrams of the packaging process of a chip packaging structure provided by the embodiment of the present application.
  • FIG. 7A is a schematic structural diagram of another chip packaging structure provided by the embodiment of the present application.
  • FIG. 7B is a schematic structural diagram of another chip structure provided by the embodiment of the present application.
  • FIG. 7C is a schematic structural diagram of another chip structure provided by the embodiment of the present application.
  • FIG. 7D is a schematic structural diagram of another chip structure provided by the embodiment of the present application.
  • FIG. 8A is a schematic structural diagram of another chip structure provided by the embodiment of the present application.
  • FIG. 8B is a schematic structural diagram of another chip structure provided by the embodiment of the present application.
  • FIG. 9A is a schematic structural diagram of another chip packaging structure provided by the embodiment of the present application.
  • FIG. 9B is a schematic structural diagram of another chip packaging structure provided by the embodiment of the present application.
  • FIG. 9C is a schematic structural diagram of another chip packaging structure provided by the embodiment of the present application.
  • FIG. 9D is a schematic structural diagram of another chip packaging structure provided by the embodiment of the present application.
  • FIG. 9E is a schematic structural diagram of another chip packaging structure provided by the embodiment of the present application.
  • FIG. 10A is a schematic structural diagram of another chip packaging structure provided by the embodiment of the present application.
  • FIG. 10B is a schematic structural diagram of another chip packaging structure provided by the embodiment of the present application.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more elements are in direct physical or electrical contact.
  • the term “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited by the context herein.
  • Exemplary embodiments are described in the embodiments of the present application with reference to cross-sectional views and/or plan views and/or equivalent circuit diagrams that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations in shape from the drawings as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • An embodiment of the present application provides a communication device, and the communication device may be a terminal device, a processor and a server in a data center, or a network device.
  • the terminal device is used to provide users with one or more of voice services and data connectivity services, and a terminal is an entity on the user side for receiving signals, or sending signals, or receiving signals and sending signals .
  • a terminal device may also be called user equipment (UE), access terminal, subscriber unit, subscriber station, mobile station, remote station, remote terminal, mobile device, user terminal, wireless communication device, user agent, or user device.
  • the terminal device can be a mobile station (mobile station, MS), a subscriber unit (subscriber unit), a drone, an Internet of things (internet of things, IoT) device, a station in a wireless local area network (wireless local area networks, WLAN).
  • IoT Internet of things
  • WLAN wireless local area network
  • ST cellular phone
  • smart phone smart phone
  • cordless phone wireless data card
  • tablet computer session initiation protocol (session initiation protocol, SIP) phone
  • wireless local loop wireless local loop, WLL
  • PDA personal digital assistant
  • MTC machine type communication terminal
  • handheld device with wireless communication function
  • the terminal device may also be a terminal in a next-generation communication system, for example, a terminal device in a future evolving public land mobile network (public land mobile network, PLMN), a terminal device in a new radio (new radio, NR) communication system, etc. .
  • PLMN public land mobile network
  • NR new radio
  • a network device is an entity on the network side for sending signals, or receiving signals, or sending signals and receiving signals.
  • the network device may be a device deployed in a radio access network (radio access network, RAN) to provide a wireless communication function for a terminal, for example, it may be a base station.
  • Radio access network radio access network
  • Network devices may be various forms of macro base stations, micro base stations (also called small cells), relay stations, access points (access points, APs), etc., and may also include various forms of control nodes, such as network controllers.
  • the control node may be connected to multiple base stations, and configure resources for multiple terminals covered by the multiple base stations.
  • the names of the equipment with base station functions may be different.
  • GSM global system for mobile communication
  • CDMA code division multiple access
  • BTS base transceiver station
  • WCDMA wideband code division multiple access
  • NodeB base station
  • LTE system can be called evolved base station (evolved NodeB, eNB or eNodeB)
  • NR communication system can be called next generation base station node (next generation node base station, gNB)
  • the network device may also be a wireless controller in a cloud radio access network (cloud radio access network, CRAN) scenario, a network device in a future evolving public land mobile network, a transmission and reception point (TRP), etc.
  • CRAN cloud radio access network
  • TRP transmission and reception point
  • the network device 1 may include one or more radio frequency units, such as a remote radio unit (remote radio unit, RRU) and one or more baseband units (baseband unit, BBU ) (also known as digital unit (DU)).
  • a remote radio unit remote radio unit
  • BBU baseband unit
  • DU digital unit
  • the RRU may be called a transceiver unit, a transceiver, a transceiver circuit, or a transceiver, etc., and may include at least one antenna 2 and a radio frequency unit 3 .
  • the RRU part is mainly used for transmitting and receiving radio frequency signals and converting radio frequency signals and baseband signals, for example, for sending the first indication information in the above method embodiments.
  • the RRU and the BBU may be physically set together or physically separated, for example, a distributed base station.
  • the BBU is the control center of the network equipment, and can also be called a processing unit, which is mainly used to complete baseband processing functions, such as channel coding, multiplexing, modulation, and spread spectrum.
  • the BBU can be composed of one or more single boards, and multiple single boards can jointly support a wireless access network (such as an LTE network) with a single access indication, or can separately support wireless access networks of different access standards. Access network (such as LTE network, 5G network or other networks).
  • the BBU also includes a memory 4 and a processor 5, the memory 4 is used to store necessary instructions and data.
  • the processor 5 is used to control the network equipment to perform necessary actions.
  • the memory 4 and the processor 5 may serve one or more single boards. That is to say, memory and processors can be set independently on each single board. It may also be that multiple single boards share the same memory and processor.
  • necessary circuits can also be set on each single board. Necessary circuits such as memory 4 and processor 5 are packaged on a single board as a chip package structure. Wherein, the single board may be, for example, a printed circuit board (printed circuit board, PCB).
  • the chip package structure 100 is carried on a PCB. Normally, the chip structure 12 with functional circuits is electrically connected to the packaging substrate 11, and then electrically connected to the PCB through the packaging substrate 11.
  • the flip chip package is the chip structure 12 obtained by grinding and cutting the wafer.
  • the surface provided with the bumps 121 faces the packaging substrate 11, so that the bumps 121 are aligned with the pads on the packaging substrate 11, and then the chip structure 12 and the packaging substrate 11 are welded through soldering processes such as reflow soldering. Interconnected package form.
  • the high-density bumps 121 and the packaging substrate 11 will form a tight bond through welding, and the thermal expansion coefficients between the chip structure 12 and the packaging substrate 11 will not match.
  • the combined structure with a strong thermal expansion coefficient mismatch will cause warpage or internal stress during the temperature change of the subsequent thermal process.
  • an underfill 14 is formed between the chip structure 12 and the packaging substrate 11 .
  • the encapsulated chip structure 12 is protected from failure during reliability testing and high-temperature manufacturing process by the surrounding protection of the underfill glue 14 .
  • the underfill glue 14 in the above chip package structure 100 can alleviate the problems caused by the warping of the chip structure 12 and the package substrate 11 .
  • the development of advanced nodes is relatively slow, which requires increasing the size of key chips. Greater computing power.
  • the corners of the chip structure 12 will bring greater stress risk to the underfill 14 .
  • the surface of the chip structure 12 close to the packaging substrate 11 has a sintering groove (far laser) 30, and the bottom side of the chip structure 12 has a chamfer 131.
  • the corners in contact with the underfill 14 are changed from sharp corners to chamfers by using the chamfer 131 structure cut at the die corner, and the corner of the chip structure 12 After smoothing, the concentrated stress between the corners of the chip structure and the underfill 14 can be relieved, and the problem of cracks in the underfill 14 due to the concentrated stress can be avoided.
  • the aforementioned chamfered chip structure 12 can alleviate the problems caused by the aforementioned stress and cracks, it will bring new problems during the process of preparing the chip structure 12 .
  • the process of preparing the chip structure 12 includes: forming a wafer (wafer) 10 comprising a plurality of chip structures 12, and the plurality of chip structures 12 are separated by dicing line regions; A sealing ring (seal ring) 20 and a sintering groove 30, the sintering groove 30 is located in the kerf zone, and is positioned at the periphery of the seal ring 20; then an auxiliary ring is formed between adjacent sintering grooves 30 (that is, the middle position of the kerf zone). groove; then use a dicing knife to form a chamfer groove 40 at the auxiliary groove; then use a dicing knife to cut through the wafer 10 in the middle of the chamfer groove 40 to form a chip structure 12 .
  • a certain width needs to be reserved for the chamfering groove. For example, for a chamfer of 45°, a width of about 100 ⁇ m needs to be reserved.
  • the width of the dicing line region is not less than 234 ⁇ m, which wastes more of the wafer 10 , which increases the manufacturing cost of the chip structure 12 , and further increases the cost of the chip package structure 100 .
  • the logic region of the wafer 10 usually includes an extremely low-k material (extreme low-K material, ELK).
  • ELK extremely low-K material
  • the porous structure of the extremely low dielectric constant material causes cracks to be formed on the surface of the chamfered groove 40 during the process of forming the chamfered groove 40 .
  • a heat-affected zone (hat affected zone, HAZ) will be formed around the sintering tank 30, as shown in Figure 3C, the heat-affected zone will cause the irregular topography of the sintering tank 30 surface to bring unknown stress risk.
  • the dicing knife cannot directly contact the wafer 10 during the dicing process, which affects the cutting effect and causes the wafer 10 to crack.
  • the introduction of the sintering groove 30 cannot completely avoid the risk of cracks when the chamfer groove 40 is formed on the wafer 10 .
  • the chamfered surface cut out on the wafer 10 is not smooth, which brings the problem of local stress concentration; The middle will cause greater wear to the angle knife, shortening the service life of the tool.
  • the embodiment of the present application also provides a chip packaging structure.
  • the underfill glue 14 has a chamfer 131 on the outside of the bottom of the plastic encapsulation layer 13 .
  • the embodiment of the present application provides a packaging method for a chip packaging structure, including:
  • the chip module 12 ′ refers to the structure of the chip structure 12 before the bumps 121 are formed. That is to say, after the bumps 12 are formed on the chip module 12 ′, the chip structure 12 shown in FIG. 4 can be obtained.
  • a plurality of chip modules 12 ′ are arranged on the carrier board 21 at intervals of a certain distance.
  • a plurality of chip modules 12 ′ are arrayed on the carrier board 21 .
  • FIG. 6B is a cross-sectional view along the A1-A2 direction in FIG. 6A.
  • the bottom surface of the chip module 12' has a plurality of contacts 122, and the signals of the external structure are transmitted to the inside of the chip module 12' through the contacts 122. .
  • the bottom surface of the chip module 12 ′ with a plurality of contacts 122 faces the carrier 21 .
  • the carrier board 21 is used to carry a plurality of chip modules 12 ′, and the material of the carrier board 21 is not limited in the embodiment of the present application.
  • the material forming the carrier 21 may include silicon, silicon oxide, glass, ceramics, polymer, metal or other materials having similar functions and being compatible with subsequent packaging processes.
  • the shape of the carrier 21 may be a wafer circle, square or any other shape, and the shape of the carrier 21 in FIG. 6A is only a schematic representation.
  • the carrier 21 is cleaned to remove impurities on the surface of the carrier 21 and improve the adhesion and coplanarity of the carrier 21 .
  • the chip module 12' is placed on the carrier 21 and fixedly connected to the carrier 21, so that the chip module 12' will not move on the carrier 21 in subsequent processes.
  • the chip module 12 ′ is connected to the carrier board 21 through a connection layer 22 .
  • connection layer 22 needs to be formed on the carrier 21 first.
  • connection layer 22 is an adhesive layer.
  • the material of the connecting layer 22 may be an adhesive such as ultraviolet curing (ultra violet, UV) glue or light-to-heat conversion (light-to-heat conversion, LTHC) material.
  • connection layer 22 is adhered on the carrier board 21 first. Then, the chip modules 12 ′ are adhered on the connection layer 22 , so as to realize the fixed placement of multiple chip modules 12 ′ on the carrier board 21 .
  • the connecting layer 22 is a sacrificial layer.
  • connection layer 22 is a buffer layer film (buffer layer).
  • connection layer 22 is a dielectric layer.
  • connection layer 22 does not limit the material of the connection layer 22 , and may be any material with any performance and function. Materials that can connect the chip module 12' to the carrier 21 and are compatible with subsequent packaging processes can be used in this application.
  • the obtained chip module 12 ′ can be directly placed on the carrier board 21 .
  • the wafer including a plurality of chip modules 12' needs to be diced.
  • a wafer without bumping (bumping) obtained from a fab is subjected to standard wafer thinning (backside grinding, BG), laser groove sintering (laser groove, LG) ) and dicing (die saw, DS) and other processes for grinding and cutting to obtain the chip module 12'.
  • standard wafer thinning backside grinding, BG
  • laser groove sintering laser groove, LG
  • dicing die saw, DS
  • plastic packaging layer 13 in the chip packaging structure 100 shown in FIG. 4 can be obtained after cutting the plastic packaging film 13 ′.
  • the embodiment of the present application does not limit the forming process and material of the plastic sealing film 13 ′.
  • the plastic sealing film 13 ′ is formed on the carrier 21 by using an injection molding process.
  • the material forming the plastic sealing film 13' may include epoxy resin, for example: the material of the plastic sealing film 13' is epoxy molding compound (EMC), chip underfill (under fill, UF), chip bonding material ( Adhesive material (AD), thermal interface material (TIM), etc.
  • the embodiment of the present application does not limit the structure of the plastic sealing film 13', the formed plastic sealing film 13' is arranged on the carrier board 21, and according to the layout of the chip module 12', the thickness of the plastic sealing film 13' is set reasonably, so that the plastic sealing film 13' 13' wraps at least the side of the chip module 12'. Wherein, there is no limitation on whether the plastic sealing film 13' covers the top surface of the chip module 12'.
  • the plastic sealing film 13' wraps the side of the chip module 12', exposing the top surface of the chip module 12' (set opposite to the bottom surface with the contacts 122), which is beneficial to the chip module 12' Surface heat dissipation.
  • the plastic sealing film 13 ′ exposing the top surface of the chip module 12 ′ is directly formed on the carrier 21 and the chip module 12 ′.
  • This method of directly forming the plastic sealing film 13' has fewer process steps, high manufacturing efficiency, and is conducive to heat dissipation on the surface of the chip module 12'.
  • a plastic sealing film 13' can be formed on the surface of the carrier 21 and the chip module 12' first, and the plastic sealing film 13' wraps the side and top surface of the chip module 12', and then the plastic sealing film The surface of 13' away from the carrier 21 is subjected to a grinding process to expose the top surface of the chip module 12'.
  • the manner of grinding the plastic sealing film 13 ′ may adopt a chemical mechanical polishing (CMP) process to grind the plastic sealing film 13 ′.
  • CMP chemical mechanical polishing
  • the plastic sealing film 13 ′ wraps the side and top surface of the chip module 12 ′.
  • the process of removing the carrier 21 may be a grinding process or a thinning process to expose the contacts 122 on the bottom surface of the chip module 12'.
  • the carrier plate 21 may be removed by mechanical polishing, chemical mechanical planarization, wet etching or dry etching.
  • the carrier 21 may be removed by removing the connection layer 22 between the carrier 21 and the chip module 12', so as to expose the contacts 122 on the surface of the chip module 12'.
  • the bumps 121 are electrically connected with the contacts 122 to obtain the chip structure 12 . It can be understood that the contact 122 on the surface of the chip module 12' is equivalent to an under bump metalization (UBM).
  • UBM under bump metalization
  • the bumps 121 may be structures made of metal solder such as solder balls, bumps, Cu pillars, and controlled collapse chip connection bumps (C4 bumps). Certainly, the material and shape of the bumps 121 are not limited in the embodiment of the present application, and the manufacturing process of the bumps 121 is also different according to the structure of the bumps 121 .
  • the structures of the bumps 121 are solder balls, they can be prepared by processes such as coating, exposure, development, solder paste printing, and ball planting.
  • the structure of the bump 121 when the structure of the bump 121 is a copper pillar, it can be prepared by processes such as coating, exposure, development, curing, sputtering, electroplating, etching, and reflow.
  • different preparation processes can be selected to form bumps 121 with different structures.
  • the chamfer groove 40 is located at the gap of the chip structure 12 , that is, the scribe line area.
  • the process of forming the chamfered groove 40 may be to use a cutting knife with an inclined side to cut the bottom surface of the plastic film 13 ′ near the bump 121 to form the chamfered groove 40 .
  • an auxiliary groove can be formed first, so as to reduce the loss of the cutting blade.
  • cutting knives of different shapes and angles can be selected to form chamfered grooves 40 of different shapes, thereby obtaining chamfers 131 of different shapes.
  • the groove wall of the chamfered groove 40 may be a straight surface or a curved surface. That is to say, the final chamfered surface can be a straight surface or a curved surface.
  • the angle range of the chamfering groove 40 may be 30°-70°, for example, the angle of the chamfering groove 40 may be 45°, 60° or 63°, which corresponds to the inclination angle of the side of the cutting knife.
  • the number and length of the chamfered grooves are not limited in the embodiment of the present application. According to the different chamfers required to be included in the plastic sealing layer 13 to be formed, the structure of the chamfering groove 40 formed on the plastic sealing film 13 ′ is different.
  • chamfer grooves 40 that run through the entire column are formed at the gaps of the multi-row chip structures 12 .
  • each row of chip structures 12 is sequentially arranged along the first direction X.
  • the finally formed part of the plastic encapsulation layer 13 only has chamfers on one side (for example, the plastic encapsulation layer 13 wrapping the chip structure 12-1 in FIG.
  • chamfer grooves 40 that run through the entire row and column are formed at the gaps between the multi-row chip structures 12 and the multi-row chip structures 12 .
  • each row of chip structures 12 is sequentially arranged along the second direction Y.
  • the finally formed part of the plastic encapsulation layer 13 only has chamfers on three sides (for example, the plastic encapsulation layer 13 wrapping the chip structure 12-3 in FIG.
  • each plastic encapsulation layer 13 it is only necessary to ensure that the periphery of each chip structure 12 is formed with chamfered grooves 40 . That is to say, it is desired that several sides of the plastic sealing layer 13 have chamfers, and several sides of the chip structure 12 are formed with chamfering grooves 40, and the chamfering on the plastic sealing layer 13 corresponds to the structure of the chamfering grooves 40 on the plastic sealing film 13'.
  • the assembly structure 12 ′′ includes a chip structure 12 , a plastic encapsulation layer 13 and bumps 121 , the bumps 121 are electrically connected to the contacts 122 , and the surface of the plastic encapsulation layer 13 near the bumps 121 has a chamfer 131 .
  • the criss-crossing dicing lines are located at the gaps of the chip structures 12, and the positions of the chamfering grooves 40 coincide with the positions of the dicing lines. That is, it can be understood that when cutting, the cutting is performed centering on the intersection line of the two groove walls of the chamfered groove 40 .
  • a cutting knife is used to cut along a cutting line as shown in FIG. 6N to form a plurality of mutually separated assembly structures 12 ′′.
  • S4 may be executed first, and then S5 and S6 are executed. It is also possible to execute S5 first, and then execute S4 and S6.
  • the embodiment of the present application does not limit the structure of the package substrate 11 , as long as the package substrate 11 can transmit signals from the upper surface to the lower surface.
  • the packaging substrate 11 includes multiple signal wire layers, an insulating layer is disposed between adjacent signal wire layers, and adjacent signal wire layers are coupled through via holes on the insulating layers to realize signal transmission.
  • the ways of bonding the bumps 121 to the package substrate 11 to realize the electrical connection are also different, which is not limited in the embodiment of the present application, and the electrical connection between the bumps 121 and the package substrate 11 can be realized. Can.
  • an underfill glue 14 is formed between the assembly structure 12 ′′ and the packaging substrate 11 .
  • underfill 14 is arranged between the assembly structure 12" and the packaging substrate 11 to wrap the bump 121; and from The bottom of the assembled structure 12 ′′ overflows to cover at least part of the chamfered surface a of the chamfer 131 .
  • the underfill 14 is disposed between the assembly structure 12 ′′ and the packaging substrate 11 , and wrapped around the periphery of the plastic layer 13 .
  • the embodiment of the present application does not limit the extent to which the underfill 14 covers the periphery of the plastic layer 13 . It can be set as needed.
  • the underfill 14 is wrapped to the chamfered surface a of the chamfer 131 on the plastic encapsulation layer 13 .
  • the underfill 14 overflows from the bottom of the molding layer 13 , overflows the chamfer 131 and wraps the side b of the molding layer 13 .
  • the underfill 14 can be wrapped to half the height of the side b of the plastic sealing layer 13 , can also be wrapped to the entire side b of the plastic sealing layer 13 , and of course can be wrapped to any height of the side b of the plastic sealing layer 13 .
  • the side b of the plastic encapsulation layer 13 refers to the surface intersecting the top surface c (the surface away from the packaging substrate 11 ) of the plastic encapsulation layer 13 .
  • the side surface of the plastic sealing layer 13 does not directly intersect the bottom surface d, and a chamfered surface a is provided between the side surface b and the bottom surface d. That is to say, in the embodiment of the present application, the chamfered surface a is not part of the side b of the plastic encapsulation layer 13 . Since the height of the side b of the underfill 14 wrapping the plastic encapsulation layer 13 is higher, the underfill 14 can withstand greater stress and can resist stress risks. Therefore, in the embodiment of the present application, the underfill 14 is wrapped to the side b of the plastic encapsulation layer 13 , which can increase the risk of stress resistance of the underfill 14 .
  • steps S1-S8 can be removed as needed, and it is not limited that every step must be included. Certain steps can also be added as needed, and are not limited to only include the above steps.
  • the packaging method of the chip packaging structure wraps the plastic sealing film 13' around the chip structure 12 that does not need to be chamfered, and then cuts the plastic sealing film 13' to form a plastic sealing layer 13 wrapped around the chip structure 12. structure. Since there is no need to form chamfers on the chip structure 12 , and it is not necessary to reserve a wide dicing line area on the wafer 10 , the actual size of the finally formed chip structure 12 is similar to the size of the functional area of the chip structure 12 . Therefore, problems such as damage to the chip structure 12 and waste of the wafer 10 caused by forming chamfers on the chip structure 12 can be avoided, and the manufacturing cost of the chip structure 12 can be reduced.
  • the process of cutting the chamfer groove 40 on the plastic encapsulation layer 13 to form the chamfer 131 will not affect the chip structure 12 such as cracks.
  • the sintering groove 30 on the plastic sealing layer 13 There is no need to form the sintering groove 30 on the plastic sealing layer 13, and it is not necessary to reserve a safety distance, so the scribe line area can be reduced. Therefore, the finally formed assembly structure 12 ′′ of the outer periphery of the chip structure 12 wrapped with the plastic encapsulation layer 13 is not much different from the size of the chip structure 12, and the size of the chip package structure will not be excessively increased.
  • the chip structure 12 After the chamfer is transferred to the plastic encapsulation layer 13, it can not only relieve the concentrated stress between the sharp corner of the chip structure 12 and the underfill 14, but also avoid the problem of cracks in the underfill 14 due to the concentrated stress. It can also reduce the chip packaging The cost of the structure, and solve a series of problems caused by the need to cut the chip structure 12. Overcome the limitation of the chip structure under the large-size chip package, and solve the problem of the chip structure 12 sides under the chip package with large size and high area ratio. Corner stress concentration problem, to avoid chip package structure failure under high temperature.
  • the plastic encapsulation layer 13 wraps the periphery of the chip structure 12 , and the plastic encapsulation layer 13 is in direct contact with the underfill 14 . Since the thermal expansion coefficient difference between the plastic encapsulation compound forming the plastic encapsulation layer 13 and the underfill 14 , and the thermal expansion coefficient difference between the chip structure 12 and the plastic encapsulation layer 13 are smaller than the thermal expansion coefficient between the chip structure 12 and the underfill 14 difference. Therefore, the plastic encapsulation layer 13 acts as a stress transition layer, which can improve the stress caused by thermal expansion and contraction between the chip structure 12 and the underfill 14, thereby reducing the concentrated stress on the underfill 14 at the corners of the chip structure 12. , so as to avoid the failure of the chip package structure due to the underfill glue 14 being ruptured by the concentrated stress, and realize the release of the stress in the chip package structure 100 .
  • the material of the plastic encapsulation layer 13 is softer and easier to cut than the material of the wafer 10 , and the chamfered surface a formed is smoother, which avoids local stress concentration caused by the uneven chamfered surface a.
  • the loss of the tool is also small in the process of forming the chamfer 131 , which prolongs the service life of the tool and further reduces the preparation cost.
  • the chip packaging method provided by the embodiment of the present application can be applied to flip chip ball grid array packaging (flip chip ball grid array, FCBGA), flip chip grid array packaging (flip chip land grid array, FCLGA), flip chip Chip pin grid array package (flip chip pin grid array, FCPGA), a wide range of applications.
  • the preparation process can be realized by using the existing chip structure recombination process, injection molding process and chamfering groove cutting process, the process is simple, the cost is low, and the technology is mature.
  • the following embodiments illustrate the chip packaging structure provided in the embodiments of the present application, and the chip packaging structure can be prepared by using the above packaging method for the chip packaging structure.
  • the chip packaging structure 100 includes: a packaging substrate 11 , a chip structure 12 , a plastic packaging layer 13 and an underfill glue 14 .
  • the chip structure 12 includes a plurality of bumps 121 located on the surface (near the bottom surface of the packaging substrate 11), the chip structure 12 is arranged on the packaging substrate 11, and the bumps 121 are electrically connected to the packaging substrate 11 to realize the connection between the chip structure 12 and the packaging substrate. 11 electrical connections.
  • the embodiment of the present application does not limit the specific structure of the chip structure 12 , as long as the chip structure 12 includes a chip and can realize the electrical connection between the chip and the packaging substrate 11 .
  • the chip structure 12 mainly includes a chip module 12 ′ and bumps 121 .
  • the chip module 12 ′ includes an interconnection layer (for example, it can be understood as an interposer) 123 , a plurality of via holes 124 and a chip 125 .
  • an interconnection layer for example, it can be understood as an interposer
  • a plurality of via holes 124 penetrate through the interconnection transfer layer 123 , for example, the end surfaces of the via holes 124 are flush with the surface of the interconnection transfer layer 123 .
  • the embodiment of the present application does not limit the material of the interconnection transfer layer 123, for example, it may be an inorganic non-metallic material.
  • the material of the interconnection transfer layer 123 may be, for example, silicon, and the formed chip structure 12 may be understood as a 2.5D chip-on-wafer-on-substrate (CoWoS) structure.
  • CoWoS chip-on-wafer-on-substrate
  • the material of the interconnection transfer layer 123 may be glass, for example, and the formed chip structure 12 may be understood as a 2.5D package (chip on glass-on-substrate, CoGoS) structure.
  • the material of the interconnection transfer layer may be, for example, ceramics
  • the formed chip structure 12 may be understood as a 2.5D package (chip on ceramics-on-substrate, CoCoS) structure with a ceramic through-hole interposer.
  • the embodiment of the present application does not limit the material of the via hole 124 , and the via hole 124 can be any conductive material.
  • the via hole 124 can be fabricated by, for example, a through silicon via (TSV) technology or an electroplating process.
  • TSV through silicon via
  • the chip 125 is disposed on the interconnection transfer layer 123 (for example, on the first surface), and is electrically connected to the first end of the via hole 124 .
  • the bumps 121 are also disposed on the interconnection transfer layer 123 (on the second surface opposite to the first surface), and are electrically connected to the second end of the via hole 124 .
  • the second end of the via hole 124 can be understood as the contact 122 of the chip structure 12 .
  • the active surface of the chip 125 is disposed facing the interconnection transfer layer 123 .
  • the structure of the transfer point exposed to the active surface of the chip 125 is also different.
  • the transition points exposed to the active surface of the chip 125 are pads.
  • the transfer point exposed to the active surface of the chip 125 is a conductive bump.
  • the transition points exposed to the active surface of the chip 125 are solder balls.
  • the embodiment of the present application does not limit the manner in which the chip 125 is electrically connected to the first end of the via hole 124 .
  • the electrical connection between the two can be realized by bonding.
  • the embodiment of the present application does not limit the number of chips 125 included in the chip structure 12 , and in some embodiments, the chip structure 12 includes one chip 125 .
  • the chip structure 12 includes a plurality of chips 125 .
  • multiple chips 125 are arranged side by side on the interconnection transfer layer 123 .
  • a plurality of chips 125 are stacked and disposed on the interconnection transfer layer 123 .
  • the embodiment of the present application does not limit the structure of the chip 125 included in the chip structure 12 , and in some embodiments, the chip 125 may be a bare chip (also called a grain or a particle) (die). It can be understood that what is obtained by cutting the wafer is a bare chip.
  • the chip 125 may also be a packaged chip obtained by packaging a bare chip.
  • the plurality of chips 125 can all be bare chips; the plurality of chips 125 can also be all packaged chips; the plurality of chips 125 can also be partially bare Chips, partly packaged chips.
  • the embodiment of the present application does not limit the structure and material of the bump 121 .
  • the bumps 121 can be metal solders such as solder balls, bumps, Cu pillars, and controlled collapse chip connection bumps (C4bump). .
  • the bumps 121 with different structures can be obtained by adjusting the process of step S4 in the method for preparing the packaging structure.
  • the chip module 12 ′ includes a chip 125 and bumps 121 .
  • the embodiment of the present application does not limit the number of chips 125 included in the chip structure 12 , for example, as shown in FIG. 8A , the chip structure 12 includes one chip 125 .
  • the chip structure 12 includes a plurality of stacked chips 125 .
  • the chip 125 may be a bare chip or a packaged chip, which is not limited in this embodiment of the present application.
  • the bump 121 is arranged on the chip 125, for example, the bump 121 is arranged on the active surface of the chip 125, and the pad exposed to the active surface of the chip 125 is used as the contact 122 in the chip structure 12, and the bump 121 is electrically connected. sexual connection.
  • the bumps 121 can be, for example, solder balls, bumps, copper pillars, and metal solder such as C4.
  • the chip module 12' in FIGS. 7B-7D and FIGS. 8A and 8B is the chip module 12' placed on the carrier board 21 in step S1 of the manufacturing method of the above-mentioned chip packaging structure. After the bumps 121 are formed on the chip module 12', the chip structure 12 in the embodiment of the present application can be obtained.
  • the plastic encapsulation layer 13 wraps at least the side of the chip structure 12 and exposes the bumps 121 .
  • the plastic encapsulation layer 13 wraps the sides of the chip structure 12 and covers the top surface of the chip structure 12 (the surface away from the packaging substrate 11 ).
  • the plastic encapsulation layer 13 wraps the sides of the chip structure 12 and exposes the top surface of the chip structure 12 .
  • the plastic sealing layer 13 with different wrapping degrees can be obtained.
  • the outer bottom of the molding layer 13 has a chamfer 131 .
  • the chamfer surface a of the chamfer 131 is a plane.
  • the chamfered surface a of the chamfered corner 131 is a curved surface.
  • the embodiment of the present application does not limit the size of the angle ⁇ of the chamfer 131 , and the range of the chamfer angle ⁇ may be 30°-70°.
  • chamfer angle ⁇ can be 45°, 60° or 63°.
  • the chamfer angle ⁇ can be understood as the angle between the chamfer surface a and the bottom surface of the plastic encapsulation layer 13 .
  • the side of the chamfered surface a of the chamfer near the bottom of the plastic encapsulation layer 13 has no distance from the chip structure 12 .
  • the size of the plastic encapsulation layer 13 is smaller, which can reduce the size of the chip packaging structure 100 .
  • the side of the chamfered surface a near the bottom of the plastic encapsulation layer 13 has a distance from the chip structure 12 (or understood as Horizontal margin) h1; the side of the chamfered chamfered surface a that is close to the top of the plastic encapsulation layer 13 (the side away from the package substrate 11 ) has a distance (or be understood as a vertical margin) h2 from the chip structure 12 .
  • the side of the chamfered surface a near the bottom of the plastic encapsulation layer 13 (the side close to the packaging substrate 11 ) has a distance h1 from the chip structure 12 , and the chamfer The side of the chamfered surface a near the top of the plastic sealing layer 13 is in direct contact with the top of the plastic sealing layer 13 without spacing.
  • the corners of the chip structure 12 can be wrapped by the plastic encapsulation layer 13 , and the plastic encapsulation layer 13 is in direct contact with the underfill 14 . In this way, cracking or warping caused by direct contact between the corners of the chip structure 12 and the underfill 14 can be avoided.
  • the process of performing the above step S6 when cutting along the dicing line, the problem of cutting the chip structure 12 due to cutting deviation and causing the chip structure 12 to be broken can be avoided.
  • the chamfer 131 is only provided at the four corners of the bottom of the molding layer 13 .
  • the chamfer 131 is arranged around the outer bottom of the plastic encapsulation layer 13 .
  • step S5 by adjusting the process of step S5 in the manufacturing method of the above packaging structure, the chamfers 131 arranged at different positions can be obtained.
  • the embodiment of the present application does not limit the material of the plastic encapsulation layer 13 , and the plastic encapsulation layer 13 serves as a stress transition layer between the chip structure 12 and the underfill 14 . Therefore, the stress exerted by the plastic encapsulation layer 13 on the underfill 14 should be less than the stress exerted by the chip structure 12 on the underfill 14 .
  • the hardness of the plastic encapsulation layer 13 is smaller than that of the chip structure 12 .
  • the modulus of the plastic encapsulation layer 13 is smaller than the modulus of the chip structure 12 , but close to the modulus of the underfill 14 .
  • the material of the plastic encapsulation layer 13 is based on epoxy resin, and is subjected to doping treatment to obtain the desired material.
  • the material of the plastic sealing layer 13 can be, for example, epoxy molding compound, underfill glue, adhesive material or heat conduction medium material.
  • the chip structure 12 is disposed on the packaging substrate 11 and is electrically connected to the packaging substrate 11 through bumps 121 .
  • the underfill 14 is disposed in the gap between the chip structure 12 and the packaging substrate 11 , and is wrapped around the outer periphery of the plastic sealing layer 13 .
  • the embodiment of the present application does not limit the wrapping degree of the underfill 14 to the plastic sealing layer 13 , and it can be reasonably set according to the process and requirements.
  • the underfill 14 is wrapped to the side b of the plastic encapsulation layer 13 .
  • the underfill 14 can be wrapped to half the height of the side b of the plastic sealing layer 13 , can also be wrapped around the entire side b of the plastic sealing layer 13 , and of course can be wrapped at any height of the side b of the plastic sealing layer 13 .
  • the underfill 14 is wrapped to the side b of the plastic encapsulation layer 13 , which can increase the risk of stress resistance of the underfill 14 .
  • the underfill 14 is wrapped to the chamfered surface a of the chamfer 131 .
  • the underfill glue 14 wrapping to the chamfered surface a of the chamfer 131 can protect the bumps 121 and stabilize the chip structure 12 .
  • the preparation process time is short and the production capacity is increased.
  • step S8 By adjusting the process of step S8 in the above method for preparing the packaging structure, the underfill 14 with different wrapping degrees can be obtained.
  • the chip packaging structure includes a packaging substrate 11, a chip structure 12 arranged on the packaging substrate 11, a plastic sealing layer 13 that wraps at least the side of the chip structure 12, and a package between the chip structure 12 and the packaging substrate 11. Between, and the underfill glue 14 wrapped around the periphery of the plastic encapsulation layer 13 .
  • the chip structure 12 includes a plurality of bumps 121 on the surface, and the bumps 121 are electrically connected to the packaging substrate 11; the plastic sealing layer 13 wraps the side of the chip structure 12, exposing the bumps 121, and the plastic sealing layer 13 is close to the bottom of the packaging substrate 11
  • the outside has a chamfer 131 .
  • the actual size of the chip structure 12 is close to the size of the chip structure 12 functional areas, therefore, it is possible to avoid pouring on the chip structure 12.
  • the damage of the chip structure 12 and the waste of the wafer 10 caused by corners can reduce the cost of the chip structure 12 .
  • the chamfer 131 on the plastic encapsulation layer 13 will not have any impact on the chip structure 12 such as cracks, and there is no need to have a sintering groove 30 on the plastic encapsulation layer 13, and there is no need to reserve a safety distance, and the dicing line area can be reduced. Therefore, the size of the plastic encapsulation layer 13 does not need to be too large, and the size of the chip packaging structure will not be excessively increased. That is to say, after the chamfer on the chip structure 12 is transferred to the plastic encapsulation layer 13, not only the concentrated stress between the sharp corner of the chip structure 12 and the underfill 14 can be relieved, but also the underfill 14 can be prevented from being damaged due to the concentrated stress.
  • the plastic encapsulation layer 13 wraps the periphery of the chip structure 12 , and the plastic encapsulation layer 13 is in direct contact with the underfill 14 . Since the thermal expansion coefficient difference between the plastic encapsulation compound forming the plastic encapsulation layer 13 and the underfill 14 , and the thermal expansion coefficient difference between the chip structure 12 and the plastic encapsulation layer 13 are smaller than the thermal expansion coefficient between the chip structure 12 and the underfill 14 difference. Therefore, the plastic encapsulation layer 13 acts as a stress transition layer, which can improve the stress caused by thermal expansion and contraction between the chip structure 12 and the underfill 14, thereby reducing the concentrated stress on the underfill 14 at the corners of the chip structure 12. , so as to avoid the failure of the chip package structure due to the underfill glue 14 being ruptured by the concentrated stress, and realize the release of the stress in the chip package structure 100 .
  • the material of the plastic encapsulation layer 13 is softer and easier to cut than the material of the wafer 10 , and the chamfered surface formed is smoother, which avoids local stress concentration caused by the uneven chamfered surface.

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Abstract

本申请实施例提供一种芯片封装结构及其封装方法、通信装置，涉及半导体技术领域，用于解决芯片封装结构失效的问题。芯片封装结构，包括：封装基板；芯片结构，包括位于表面的多个凸点；芯片结构设置在封装基板上，凸点与封装基板电性连接；塑封层，至少包裹芯片结构的侧面；塑封层靠近封装基板的底部外侧具有倒角；底部填充胶，包裹凸点以及倒角的至少部分倒角面。

Description

芯片封装结构及其封装方法、通信装置 技术领域
本申请涉及半导体技术领域，尤其涉及一种芯片封装结构及其封装方法、通信装置。
背景技术
随着电子技术的发展，通信装置的功能不断的区域丰富化、全面化，使得高阶芯片演进迭代需求与日俱增，芯片的集成度持续的增加，多芯片集成合封成为趋势。由于堆叠的芯片数量增加，导致芯片封装结构尺寸的增大。然而超大尺寸的芯片封装，给应力与工艺上带来极大的挑战。
芯片封装结构中芯片结构的高密度的凸点与封装基板的键合后，由于芯片结构与封装基板之间存在较大的热膨胀系数(coefficient of thermal expansion，CTE)差异，导致使用温度变化时，封装基板和芯片结构之间容易产生翘曲(warpage)和应力(stress)。为了保护凸点、提高芯片结构与封装基板的稳固性，在芯片结构与封装基板之间形成底部填充胶(under fill)。然而，一方面，在封装键合过程中，芯片结构和封装基板之间的热膨胀系数差异较大，芯片结构边角(die corner)对底部填充胶(under fill)带来较大的应力风险。另一方面，封装形成的芯片封装结构在后续使用过程中，由于使用时温度是不断变化的，导致芯片封装结构出现反复的翘曲，从而会出现芯片结构边角与底部填充胶之间反复挤压的情况，高模量的芯片结构边角与低模量的底部填充胶之间由于内部应力、膨胀、收缩等原因产生的反复挤压导致底部填充胶断裂，芯片封装结构失效。
而随着与封装基板合封的芯片结构尺寸的不断增大，导致芯片结构的尺寸和封装基板的尺寸之比(die-substrate size ratio)逐渐增大，上述问题就更为凸显。
发明内容
本申请实施例提供一种芯片封装结构及其封装方法、通信装置，用于解决芯片封装结构失效的问题。
为达到上述目的，本申请采用如下技术方案：
本申请实施例的第一方面，提供一种芯片封装结构，芯片封装结构包括封装基板、设置在封装基板上的芯片结构、至少包裹芯片结构侧面的塑封层(molding)以及底部填充胶。其中，芯片结构包括位于表面的多个凸点，凸点与封装基板电性连接；塑封层包裹芯片结构的侧面，或者还包裹芯片结构的顶面，但不会包裹凸点；塑封层靠近封装基板的底部外侧具有倒角；底部填充胶包裹凸点以及倒角的至少部分倒角面。
本申请实施例提供芯片封装结构中的芯片结构无需具有倒角，无需预留晶圆上较宽的切割道区，芯片结构的实际尺寸和芯片结构功能区的尺寸相近，因此，可以避免在芯片结构上倒角所带来的芯片结构损坏和晶圆浪费等问题，降低芯片结构的成本。而且，在塑封层上的倒角不会对芯片结构产生裂痕等影响，塑封层上无需具有烧结槽， 也无需预留安全距离，可缩小切割道区。因此，塑封层的尺寸无需过大，不会过分增大芯片封装结构的尺寸。也就是说，将芯片结构上的倒角转移到塑封层上后，不仅可以缓解芯片结构的尖角与底部填充胶之间的集中应力，可避免底部填充胶因为集中应力而出现裂纹的问题。还可以降低芯片封装结构的成本，和解决因切割芯片结构所带来的一系列问题。克服了大尺寸、高面积占比的芯片封装下芯片结构的限制，解决了大尺寸芯片封装下的芯片结构边角应力集中问题，避免芯片封装结构高温下失效。
在一些实施例中，倒角的倒角面中靠近塑封层底部的一侧，与芯片结构之间具有间距。芯片结构的边角被塑封层包裹起来，塑封层与底部填充胶直接接触，能够避免芯片结构的边角与底部填充胶直接接触造成的裂开或翘曲。同时，沿切割道进行切割时，能够避免因为切割偏移而切到芯片结构，导致芯片结构破裂的问题。
在一些实施例中，底部填充胶从塑封层的底部溢出，漫过倒角并包裹塑封层的侧面。底部填充胶包裹塑封层的侧面高度越高，底部填充胶能够承受的应力就越大，越能抵抗应力风险。
在一些实施例中，塑封层的材料包括环氧树脂。塑封层作为芯片结构与底部填充胶之间的应力过渡层，环氧树脂的硬度小于芯片结构的硬度，在环氧树脂上形成倒角，比在芯片结构上形成倒角容易，且对刀具损耗低。
在一些实施例中，芯片结构为：芯片，芯片上设置有凸点。对芯片结构不做限定，适用范围广。
在一些实施例中，芯片结构包括：互联转接层；多个导通孔，贯穿互联转接层；芯片，设置在互联转接层上，与导通孔的一端电性连接；导通孔的另一端上设置有凸点。对芯片结构不做限定，适用范围广。
本申请实施例的第二方面，提供一种芯片封装结构的封装方法，芯片封装方法包括：在放置有多个芯片模块的载板上形成塑封膜；芯片模块具有多个触点的表面朝向载板，塑封膜至少包裹芯片模块的侧面；去除载板，露出触点；在触点上形成凸点，凸点与触点电性连接；在塑封膜靠近凸点的底面上形成多个倒角槽，倒角槽位于芯片模块的间隙处；沿切割道进行切割；其中，切割道位于芯片模块的间隙处，倒角槽的位置与切割道的位置重合；将切割得到的组装结构通过凸点与封装基板电性连接；在组装结构与封装基板之间形成底部填充胶，底部填充胶包裹在塑封膜的外围。
本申请实施例提供的芯片封装结构的封装方法，在无需形成倒角的芯片结构的外围包裹塑封膜，然后对塑封膜进行切割，以形成芯片结构外围包裹塑封层的结构。由于芯片结构上无需形成倒角，无需在晶圆上预留较宽的切割道区，最终形成的芯片结构的实际尺寸和芯片结构功能区的尺寸相近。因此，可以避免在芯片结构上形成倒角所带来的芯片结构损坏和晶圆浪费等问题，降低芯片结构的制备成本。而且，在塑封层上切割倒角槽，以形成倒角的过程，不会对芯片结构产生裂痕等影响。不需要在塑封层上形成烧结槽，也不需要预留安全距离，可缩小切割道区。因此，最终形成的芯片结构外围包裹塑封层的组装结构，和芯片结构的尺寸相差不大，不会过分增大芯片封装结构的尺寸。也就是说，将芯片结构上的倒角转移到塑封层上后，不仅可以缓解芯片结构的尖角与底部填充胶之间的集中应力，可避免底部填充胶因为集中应力而出现裂纹的问题。还可以降低芯片封装结构的成本，和解决因需要切割芯片结构所带来 的一系列问题。克服了大尺寸、高面积占比的芯片封装下芯片结构的限制，解决了大尺寸芯片封装下的芯片结构边角应力集中问题，避免芯片封装结构高温下失效。
本申请实施例的第三方面，提供一种通信装置，包括印刷线路板和第一方面任一项的芯片封装结构；芯片封装结构设置在印刷线路板上，与印刷线路板耦接。
本申请实施例第三方面提供的通信装置，包括第一方面任一项的芯片封装结构，其有益效果与芯片封装结构的有益效果相同，此处不再赘述。
附图说明
图1为本申请实施例提供的一种基站的结构示意图；
图2为本申请实施例提供的一种芯片封装结构承载于PCB的结构示意图；
图3A为本申请实施例提供的一种芯片封装结构的结构示意图；
图3B为本申请实施例提供的一种芯片结构的结构示意图；
图3C为本申请实施例提供的又一种芯片结构的结构示意图；
图4为本申请实施例提供的又一种芯片封装结构的结构示意图；
图5为本申请实施例提供的一种芯片封装结构的封装方法的流程示意图；
图6A-图6P为本申请实施例提供的一种芯片封装结构的封装过程示意图；
图7A为本申请实施例提供的又一种芯片封装结构的结构示意图；
图7B为本申请实施例提供的又一种芯片结构的结构示意图；
图7C为本申请实施例提供的又一种芯片结构的结构示意图；
图7D为本申请实施例提供的又一种芯片结构的结构示意图；
图8A为本申请实施例提供的又一种芯片结构的结构示意图；
图8B为本申请实施例提供的又一种芯片结构的结构示意图；
图9A为本申请实施例提供的又一种芯片封装结构的结构示意图；
图9B为本申请实施例提供的又一种芯片封装结构的结构示意图；
图9C为本申请实施例提供的又一种芯片封装结构的结构示意图；
图9D为本申请实施例提供的又一种芯片封装结构的结构示意图；
图9E为本申请实施例提供的又一种芯片封装结构的结构示意图；
图10A为本申请实施例提供的又一种芯片封装结构的结构示意图；
图10B为本申请实施例提供的又一种芯片封装结构的结构示意图。
附图标记：
1-通信装置；2-天线；3-射频单元；4-存储器；5-处理器；100-芯片封装结构；10-晶圆；20-密封环；30-烧结槽；40-倒角槽；11-封装基板；12-芯片结构；12＇-芯片模块；12”-组装结构；121-凸点；122-触点；123-互联转接层；124-导通孔；125-芯片；13-塑封层；13＇-塑封膜；131-倒角；a-倒角面；14-底部填充胶；21-载板；22-连接层。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，本申请实施例中，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中， 除非另有说明，“多个”的含义是两个或两个以上。
本申请实施例中，“上”、“下”、“左”以及“右不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
在本申请实施例中，除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例性地”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
在本申请实施例中，“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
本申请实施例中参照作为理想化示例性附图的剖视图和/或平面图和/或等效电路图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本申请实施例提供一种通信装置，通信装置可以是终端设备、数据中心中的处理器和服务器或者网络设备等。
其中，终端设备用于向用户提供语音服务和数据连通性服务中的一种或多种，终端是用户侧的一种用于接收信号，或者，发送信号，或者，接收信号和发送信号的实体。终端设备还可以称为用户设备(user equipment，UE)、接入终端、用户单元、用户站、移动站、远方站、远程终端、移动设备、用户终端、无线通信设备、用户代理或用户装置。终端设备可以是移动站(mobile station，MS)、用户单元(subscriber unit)、无人机、物联网(internet of things，IoT)设备、无线局域网(wireless local area networks，WLAN)中的站点(station，ST)、蜂窝电话(cellular phone)、智能电话(smart phone)、无绳电话、无线数据卡、平板型电脑、会话启动协议(session initiation protocol，SIP)电话、无线本地环路(wireless local loop，WLL)站、个人数字助理(personal digital assistant，PDA)设备、膝上型电脑(laptop computer)、机器类型通信(machine type  communication，MTC)终端、具有无线通信功能的手持设备、计算设备或连接到无线调制解调器的其它处理设备、车载设备、可穿戴设备(也可以称为穿戴式智能设备)。终端设备还可以为下一代通信系统中的终端，例如，未来演进的公共陆地移动网络(public land mobile network，PLMN)中的终端设备，新无线电(new radio，NR)通信系统中的终端设备等。
网络设备为网络侧的一种用于发送信号，或者，接收信号，或者，发送信号和接收信号的实体。网络设备可以为部署在无线接入网(radio access network，RAN)中为终端提供无线通信功能的装置，例如可以为基站。网络设备可以为各种形式的宏基站，微基站(也称为小站)，中继站，接入点(access point，AP)等，也可以包括各种形式的控制节点，如网络控制器。所述控制节点可以连接多个基站，并为所述多个基站覆盖下的多个终端配置资源。在采用不同的无线接入技术的系统中，具备基站功能的设备的名称可能会有所不同。例如，全球移动通信系统(global system for mobile communication，GSM)或码分多址(code division multiple access，CDMA)网络中可以称为基站收发信台(base transceiver station，BTS)，宽带码分多址(wideband code division multiple access，WCDMA)中可以称为基站(NodeB)，LTE系统中可以称为演进型基站(evolved NodeB，eNB或eNodeB)，NR通信系统中可以称为下一代基站节点(next generation node base station，gNB)，本申请对基站的具体名称不作限定。网络设备还可以是云无线接入网络(cloud radio access network，CRAN)场景下的无线控制器、未来演进的公共陆地移动网络中的网络设备、传输接收节点(transmission and reception point，TRP)等。
示例一种网络设备的结构，如图1所示，网络设备1可包括一个或多个射频单元，如远端射频单元(remote radio unit，RRU)和一个或多个基带单元(baseband unit，BBU)(也可称为数字单元(digital unit，DU))。
该RRU可以称为收发单元、收发机、收发电路、或者收发器等等，其可以包括至少一个天线2和射频单元3。该RRU部分主要用于射频信号的收发以及射频信号与基带信号的转换，例如，用于发送上述方法实施例中第一指示信息。该RRU与BBU可以是物理上设置在一起，也可以物理上分离设置的，例如，分布式基站。
该BBU为网络设备的控制中心，也可以称为处理单元，主要用于完成基带处理功能，如信道编码，复用，调制，扩频等等。
在一些实施例中，该BBU可以由一个或多个单板构成，多个单板可以共同支持单一接入指示的无线接入网(如LTE网络)，也可以分别支持不同接入制式的无线接入网(如LTE网，5G网或其它网)。该BBU还包括存储器4和处理器5，该存储器4用于存储必要的指令和数据。该处理器5用于控制网络设备进行必要的动作。该存储器4和处理器5可以服务于一个或多个单板。也就是说，可以每个单板上单独设置存储器和处理器。也可以是多个单板共用相同的存储器和处理器。此外每个单板上还可以设置有必要的电路。而存储器4和处理器5等必要电路作为芯片封装结构封装于单板上。其中，单板例如可以是印刷电路板(printed circuit board，PCB)。
其中，如图2所示，芯片封装结构100承载于PCB上。通常情况下，具有功能电路的芯片结构12与封装基板11电性连接，然后通过封装基板11与PCB实现电性连 接。
而芯片结构12与封装基板11的电性连接，以倒装芯片封装(flip chip)为例，倒装芯片封装是通过将晶圆(wafer)磨划切割后得到的芯片结构12，通过翻转倒装的工艺，将设置有凸点121的面朝向封装基板11，使凸点121与封装基板11上的焊盘形成对位，随后经历回流焊等焊接工艺实现芯片结构12和封装基板11焊接的互联的封装形式。而高密度的凸点121与封装基板11通过焊接将形成紧密的结合，会出现芯片结构12和封装基板11间的热膨胀系数不匹配。而有较强的热膨胀系数不匹配的组合结构会在后续热制程的温度变化过程中产生的翘曲变化或内部应力。
为了在封装后续工艺中的高温制程(如植球回流焊、上板回流焊)中保护凸点121结构以及封装基板11表面的绝缘阻挡层(solder resist，SR)结构，如图2所示，在芯片结构12和封装基板11之间形成底部填充胶14。通过底部填充胶14的包围保护来防止封装后的芯片结构12在可靠性测试和高温制程的过程中发生失效。
然而，上述芯片封装结构100中底部填充胶14虽然能够缓解芯片结构12和封装基板11翘曲带来的问题。但是由于服务器、高性能处理器(CPU)、网络互连交换机等高性能设备对核心芯片的计算能力不断提高，而先进节点的发展速度相对较慢，这就需要通过增加关键芯片的尺寸来实现更强的计算能力。随着芯片结构的尺寸和封装基板的尺寸之比(die-substrate size ratio)的增大，芯片结构12边角会对底部填充胶14带来更大的应力风险。在芯片封装结构的使用过程中，不断的温度变化带来的反复翘曲，在芯片结构12边角处高模量的尖角与较软的底部填充胶14之间，出现由于内部应力、膨胀、收缩等原因产生反复挤压拉扯，将会使底部填充胶14最终断裂失效。而芯片结构12的面积占比越大，这种失效风险也随之越高。
基于此，为了解决芯片封装结构100应力和裂痕的问题，在一些实施例中，如图3A所示，提供一种芯片封装结构100，主要包括封装载板11，芯片结构12以及底部填充胶14，芯片结构12靠近封装基板11的表面具有烧结槽(far laser)30，且芯片结构12的底部侧面具有倒角131。
在这种芯片封装结构100中，利用在芯片边角(die corner)处切割出的倒角131结构，与底部填充胶14接触的顶角由尖角变成倒角，芯片结构12的顶角平滑后，可缓解芯片结构边角与底部填充胶14之间的集中应力，可避免底部填充胶14因为集中应力而出现裂纹的问题。
然而，上述带有倒角的芯片结构12虽然能够缓解上述应力和裂痕的问题引出问题，但是在制备得到芯片结构12的过程中，会带来新的问题。
如图3B所示，制备芯片结构12的过程，包括：形成包含有多个芯片结构12的晶圆(wafer)10，多个芯片结构12通过切割道区间隔开；然后在晶圆10上形成密封环(seal ring)20和烧结槽30，烧结槽30位于切割道区，且位于密封环20的外围；然后在相邻烧结槽30之间(也就是切割道区的中间位置处)形成辅助凹槽；然后用切割刀在辅助凹槽处形成倒角槽40；然后采用划片刀在倒角槽40的中间处切穿晶圆10，形成芯片结构12。
然而，制备上述芯片结构12的过程中，为了避免倒角槽切割(bevel cut)过程中产生的裂痕扩展到密封环20以及密封环20以内的逻辑区，需在密封环20与待形成倒 角槽40的区域之间形成烧结槽30。其中，考虑到工艺等因素，在烧结槽30与倒角槽40之间需要留有12μm左右的安全距离，在烧结槽30与密封环20之间需要留有25μm左右的安全距离。烧结槽30的宽度为30μm左右。根据芯片结构12上倒角角度的不同，倒角槽也需预留一定的宽度。例如，45°的倒角，需要预留100μm左右的宽度。这就导致切割道区的宽度不小于234μm，对晶圆10的浪费较多，从而导致芯片结构12的制备成本增加，进而导致芯片封装结构100的成本增加。
而且，由于晶圆10(材料例如为Si)的硬度较大，晶圆10的逻辑区通常包括极低介电常数材料(extreme low-K material，ELK)。而极低介电常数材料的多孔结构导致形成倒角槽40的过程中会在倒角槽40表面形成裂痕。形成烧结槽30的过程中会在烧结槽30周围形成热影响区(hat affected zone，HAZ)，如图3C所示，热影响区导致烧结槽30表面产生的不规则形貌会带来未知的应力风险。此外，由于晶圆10中金属层的金属在切割过程中会粘附在切割刀表面，导致在切割过程中切割刀无法与晶圆10直接接触，影响切割效果，导致晶圆10发生裂开。另外，引入烧结槽30也不能完全避免在晶圆10上形成倒角槽40时带来裂痕的风险。
又由于晶圆10较为坚硬，一方面，在晶圆10上切割出来的倒角面不平整，带来局部应力集中的问题，另一方面，为了保持倒角的角度稳定，在切割倒角过程中会对角度刀产生较大的磨损，缩短了刀具的使用寿命。
基于此，为了解决上述芯片封装结构制备成本高等问题，本申请实施例还提供一种芯片封装结构，如图4所示，芯片封装结构100主要包括封装基板11、芯片结构12、塑封层13以及底部填充胶14，塑封层13的底部外侧具有倒角131。
如图5所示，本申请实施例提供一种芯片封装结构的封装方法，包括：
S1、如图6A所示，将多个芯片模块12＇放置在载板21上。
此处释明的是，如图4所示，芯片模块12＇是指芯片结构12未形成凸点121前的结构。也就是说，芯片模块12＇上形成凸点12后，即可得到图4所示的芯片结构12。
示例的，将多个芯片模块12＇以一定距离间隔排布在载板21上。例如，将多个芯片模块12＇阵列排布在载板21上。
其中，如图6B所示，图6B为沿图6A中A1-A2向的剖视图，芯片模块12＇的底面具有多个触点122，外部结构的信号经触点122传输至芯片模块12＇内部。芯片模块12＇具有多个触点122的底面朝向载板21。
如图6A所示，载板21用于承载多个芯片模块12＇，本申请实施例对载板21的材料不做限定。示例性的，形成载板21的材料可以包括硅、氧化硅、玻璃、陶瓷、聚合物、金属或者其它具有相似功能且兼容后续封装工艺的材料。另外，载板21的形状可以为晶圆形、方形或其他任意形状，图6A中载板21的形状仅为一种示意。
在一些实施例中，将芯片模块12＇放置于载板21上之前，先对载板21进行清洗，以清除载板21表面的杂质，提高载板21的粘结力以及共面度。
在一些实施例中，芯片模块12＇放置于载板21上，与载板21固定连接，以使芯片模块12＇在后续工艺中在载板21上不会发生移动。
如图6B所示，芯片模块12＇与载板21之间通过连接层22进行连接。
基于此，如图6C所示，将芯片模块12＇放置在载板21上之前，需先在载板21上形成连接层22。
关于连接层22的材料，在一些实施例中，连接层22为粘附层薄膜(adhesive layer)。
即，芯片模块12＇与载板21粘结。例如，连接层22的材料为可以是紫外光固化(ultra violet，UV)胶或者光热转换(light-to-heat conversion，LTHC)材料等黏合剂(adhesive)。
示例的，如图6C所示，先将连接层22黏附在载板21上。然后将芯片模块12＇黏附在连接层22上，以实现将多个芯片模块12＇固定放置在载板21上。
在另一些实施例中，连接层22为牺牲层薄膜(sacrificial layer)。
在又一些实施例中，连接层22为缓冲层薄膜(buffer layer)。
在又一些实施例中，连接层22为介电层薄膜(dielectric layer)。
本申请实施例对连接层22的材料不做限定，可以是任意性能，任意功能的材料。能够将芯片模块12＇与载板21连接，且能与后续封装工艺兼容的材料均可应用于本申请中。
应当明白的是，在可以直接获取芯片模块12＇的情况下，可以将获取的芯片模块12＇直接拿来放置在载板21上。在无法直接获取芯片模块12＇的情况下，还需将包括多个芯片模块12＇的晶圆进行切割。
示例的，如图6D所示，将从晶圆厂获取的未形成凸点(bumping)的晶圆，通过标准的晶圆减薄(backside grinding，BG)、激光凹槽烧结(laser groove，LG)和划片(die saw，DS)等工艺进行磨划切割，获取芯片模块12＇。
S2、如图6E所示，在放置有多个芯片模块12＇的载板21上形成塑封膜13＇。
此处释明的是，塑封膜13＇在切割后即可得到图4所示的芯片封装结构100中的塑封层13。
本申请实施例对塑封膜13＇的形成工艺和形成材料不做限定，示例性的，利用注塑工艺在载板21上形成塑封膜13＇。形成塑封膜13＇的材料可以包括环氧树脂，例如：塑封膜13＇的材料为环氧塑封料(epoxy molding compound，EMC)、芯片底部填充胶(under fill，UF)、芯片粘结料(adhesive material，AD)、导热介质材料(thermal interface material，TIM)等。
本申请实施例对塑封膜13＇的结构不做限定，形成的塑封膜13＇设置在载板21上，且根据芯片模块12＇的布局，合理设置塑封膜13＇的厚度，以使得塑封膜13＇至少包裹芯片模块12＇的侧面即可。其中，对塑封膜13＇是否覆盖芯片模块12＇的顶面不做限定。
在一些实施例中，如图6E所示，塑封膜13＇包裹芯片模块12＇的侧面，露出芯片模块12＇的顶面(与具有触点122的底面相对设置)，有利于芯片模块12＇表面散热。
关于形成图6E所示的塑封膜13＇的方法，示例性的，如图6E所示，在载板21和芯片模块12＇上直接形成露出芯片模块12＇顶面的塑封膜13＇。
这种直接形成塑封膜13＇的方式，工艺步骤少，制备效率高，且有利于芯片模块12＇表面散热。
或者，示例性的，如图6F所示，可以先在载板21和芯片模块12＇的表面形成塑封膜13＇，塑封膜13＇包裹芯片模块12＇的侧面和顶面，然后对塑封膜13＇远离载板21的表面进行研磨(grinding)处理，以露出芯片模块12＇的顶面。
其中，对塑封膜13＇进行研磨处理的方式，例如可以采用化学机械平坦化(chemical mechanical polishing，CMP)工艺对塑封膜13＇进行研磨处理。
在另一些实施例中，如图6G所示，塑封膜13＇包裹芯片模块12＇的侧面和顶面。
这样一来，无需采用CMP工艺对塑封膜13＇进行研磨处理，可减少工艺步骤。
S3、如图6H所示，去除载板21，露出触点122。
示例性的，去除载板21的工艺可以是采用研磨工艺或者减薄工艺进行去除，以露出芯片模块12＇底面的触点122。例如，可以采用机械研磨、化学机械平坦化工艺、湿法刻蚀或者干法刻蚀去除载板21。
或者，示例性的，可以通过去除载板21与芯片模块12＇之间的连接层22去除载板21，以露出芯片模块12＇表面的触点122。
S4、如图6I所示，在触点122上形成凸点121。
其中，凸点121与触点122电性连接，以得到芯片结构12。可以理解的是，芯片模块12＇表面的触点122相当于球下金属层(under bump metalization，UBM)。
凸点121可以是焊球(solder ball)、凸起(bump)、铜柱(Cu pillar)以及可控塌陷芯片连接凸块(controlled collapse chip connection bump，C4bump)等由金属焊料构成的结构。当然，本申请实施例中对凸点121的材料和形状不做限定，根据凸点121结构的不同，凸点121的制备工艺也不同。
示例性的，凸点121的结构为焊球时，可以通过涂覆、曝光、显影、锡膏印刷、植球等工艺制备。
或者，示例性的，凸点121的结构为铜柱时，可以通过涂覆、曝光、显影、固化、溅射、电镀、刻蚀、回流等工艺制备。
根据需要，可以选取不同的制备工艺，以形成不同结构的凸点121。
S5、如图6J所示，在塑封膜13＇靠近凸点121的底面上形成多个倒角槽40。
其中，倒角槽40位于芯片结构12的间隙处，也就是切割道区。形成倒角槽40的工艺可以是利用具有倾斜侧面的切割刀在塑封膜13＇靠近凸点121的底面上切割，形成倒角槽40。另外，根据需要，在形成倒角槽40之前，可先形成辅助凹槽，以减小对切割刀的损耗。
根据需要，可以选取不同形状、不同角度的切割刀，以形成不同形状的倒角槽40，从而得到不同形状的倒角131。
示例的，倒角槽40的槽壁可以是直面，也可以是曲面。也就是说，最终形成的倒角面可以是直面，也可以是曲面。
示例的，倒角槽40的角度范围可以是30°-70°，例如：倒角槽40的角度可以是45°、60°或者63°，与切割刀的侧面倾斜角度对应。
本申请实施例中对倒角槽的数量和长度不做限定。根据待形成的塑封层13所需包含的倒角的不同，塑封膜13＇上形成的倒角槽40的结构不同。
示例性的，如图6K所示，在多列芯片结构12的间隙处形成贯穿整列的倒角槽40。 其中，每列芯片结构12沿第一方向X依次排布。
这样一来，最终形成的部分塑封层13仅在一侧具有倒角(例如包裹图6K中芯片结构12-1的塑封层13)，部分塑封层13在两侧均具有倒角(例如包裹图6K中芯片结构12-2的塑封层13)。
示例性的，如图6L所示，在多列芯片结构12的间隙处和多行芯片结构12的间隙处形成贯穿整行整列的倒角槽40。其中，每行芯片结构12沿第二方向Y依次排布。
这样一来，最终形成的部分塑封层13仅在三侧具有倒角(例如包裹图6L中芯片结构12-3的塑封层13)，部分塑封层13在四侧均具有倒角(例如包裹图6L中芯片结构12-4的塑封层13)。
可以理解的是，若希望得到每个塑封层13的四侧均具有倒角，只需保证每个芯片结构12的外围均形成有倒角槽40即可。也就是说，希望得到塑封层13的几侧具有倒角，芯片结构12的几侧形成有倒角槽40，塑封层13上的倒角与塑封膜13＇上的倒角槽40结构对应即可。
S6、如图6M所示，沿切割道进行切割，形成组装结构12”。
此处需要释明的是，组装结构12”包括芯片结构12、塑封层13以及凸点121，凸点121与触点122电性连接，塑封层13靠近凸点121的表面具有倒角131。
其中，横纵交错的切割道位于芯片结构12的间隙处，倒角槽40的位置与切割道的位置重合。也就是可以理解为，切割的时候，是以倒角槽40两个槽壁的交叉线为中心进行切割的。
例如，采用切割刀，沿如图6N所示的切割道进行切割，形成多个相互分立的组装结构12”。
需要说明的是，本申请实施例对S4的顺序不做限定，可以先执行S4，再执行S5和S6。也可以先执行S5，再执行S4和S6。
S7、如图6N所示，将切割得到的组装结构12”通过凸点121与封装基板11电性连接。
本申请实施例对封装基板11的结构不做限定，封装基板11能够实现将信号从上表面传输至下表面即可。例如，封装基板11包括多层信号线层，相邻信号线层之间设置有绝缘层，相邻信号线层通过绝缘层上的过孔耦接，以实现信号的传输。
根据凸点121结构的不同，凸点121与封装基板11键合以实现电性连接的方式也不同，本申请实施例对此不做限定，能够实现凸点121与封装基板11电性连接即可。
S8、如图6O所示，在组装结构12”与封装基板11之间形成底部填充胶14。
在组装结构12”与封装基板11之间填充底部填充胶(under fill)，形成底部填充胶14，底部填充胶14设置在组装结构12”与封装基板11之间，包裹凸点121；且从组装结构12”的底部溢出，包裹倒角131的至少部分倒角面a。
或者理解为，底部填充胶14设置在组装结构12”与封装基板11之间，且包裹在塑封层13的外围。本申请实施例对底部填充胶14覆盖塑封层13外围的程度不做限定，根据需要可以设置即可。
示例性的，如图6O所示，底部填充胶14包裹至塑封层13上倒角131的倒角面a。
这样一来，制备工艺时间短，提升产能。
或者，示例性的，如图6P所示，底部填充胶14从塑封层13的底部溢出，漫过倒角131并包裹塑封层13的侧面b。
其中，底部填充胶14可以包裹至塑封层13侧面b的一半高度，也可以包裹塑封层13的全部侧面b，当然也可以时候包裹至塑封层13侧面b的任意高度处。
可以理解的是，塑封层13的侧面b，是指与塑封层13的顶面c(远离封装基板11的表面)相交的面。且塑封层13的侧面与底面d没有直接相交，侧面b与底面d之间设置有倒角面a。也就是说，本申请实施例中，倒角面a不属于塑封层13侧面b的一部分。由于底部填充胶14包裹塑封层13的侧面b高度越高，底部填充胶14能够承受的应力就越大，越能抵抗应力风险。因此，本申请实施例将底部填充胶14包裹至塑封层13的侧面b，可提高底部填充胶14的抗应力风险。
本申请实施例提供的上述封装方法，并不做任何步骤顺序的限制，可以根据需要合理调整。
此外，上述S1-S8的步骤，可以根据需要去除其中的某些步骤，并不限定为每个步骤都必须包含。也可以根据需要增加某些步骤，不限定为仅包含上述步骤。
本申请实施例提供的芯片封装结构的封装方法，在无需形成倒角的芯片结构12的外围包裹塑封膜13＇，然后对塑封膜13＇进行切割，以形成芯片结构12外围包裹塑封层13的结构。由于芯片结构12上无需形成倒角，无需在晶圆10上预留较宽的切割道区，最终形成的芯片结构12的实际尺寸和芯片结构12功能区的尺寸相近。因此，可以避免在芯片结构12上形成倒角所带来的芯片结构12损坏和晶圆10浪费等问题，降低芯片结构12的制备成本。而且，在塑封层13上切割倒角槽40，以形成倒角131的过程，不会对芯片结构12产生裂痕等影响。不需要在塑封层13上形成烧结槽30，也不需要预留安全距离，可缩小切割道区。因此，最终形成的芯片结构12外围包裹塑封层13的组装结构12”，和芯片结构12的尺寸相差不大，不会过分增大芯片封装结构的尺寸。也就是说，将芯片结构12上的倒角转移到塑封层13上后，不仅可以缓解芯片结构12的尖角与底部填充胶14之间的集中应力，可避免底部填充胶14因为集中应力而出现裂纹的问题。还可以降低芯片封装结构的成本，和解决因需要切割芯片结构12所带来的一系列问题。克服了大尺寸的芯片封装下芯片结构的限制，解决了大尺寸、高面积占比芯片封装下的芯片结构12边角应力集中问题，避免芯片封装结构高温下失效。
另外，塑封层13包裹芯片结构12的外围，塑封层13直接与底部填充胶14接触。由于形成塑封层13的塑封料与底部填充胶14之间的热膨胀系数差异，以及芯片结构12与塑封层13之间的热膨胀系数差异，均小于芯片结构12与底部填充胶14之间的热膨胀系数差异。因此，塑封层13作为应力过渡层，可以改善芯片结构12与底部填充胶14之间热胀冷缩过程中带来的应力，进而减小芯片结构12边角处对底部填充胶14的集中应力，从而避免因为底部填充胶14受到集中应力断裂而导致芯片封装结构失效的问题，实现芯片封装结构100中应力的释放。
此外，塑封层13的材质相较于晶圆10的材质更为柔软且极易进行切割，形成的倒角面a更为光滑，避免了不平整的倒角面a带来的局部应力集中。且在形成倒角131 的过程中对刀具的损耗也小，延长刀具的使用寿命，进一步减小了制备成本。
再者，本申请实施例提供的芯片封装方法可以应用到倒装芯片球栅阵列封装(flip chip ball grid array，FCBGA)、倒装芯片栅格阵列封装(flip chip land grid array，FCLGA)、倒装芯片引脚网格阵列封装(flip chip pin grid array，FCPGA)上，应用范围广。而且，在制备过程中是利用现有的芯片结构重组工艺、注塑工艺以及倒角槽切割工艺即可实现，流程简单，成本低廉，技术成熟。
下面实施例对本申请实施例提供的芯片封装结构进行说明，芯片封装结构可以采用上述芯片封装结构的封装方法制备得到。
基于此，如图7A所示，芯片封装结构100包括：封装基板11、芯片结构12、塑封层13以及底部填充胶14。
芯片结构12包括位于表面(靠近封装基板11的底面)的多个凸点121，芯片结构12设置在封装基板11上，凸点121与封装基板11电性连接，以实现芯片结构12与封装基板11的电性连接。
本申请实施例对芯片结构12的具体结构不做限定，芯片结构12中包含芯片，且能够实现芯片与封装基板11的电性连接即可。
如图7B所示，芯片结构12主要包括芯片模块12＇和凸点121。
在一些实施例中，芯片模块12＇包括互联转接层(例如可以理解为interposer)123、多个导通孔124以及芯片125。
多个导通孔124贯穿互联转接层123，示例的，导通孔124的端面与互联转接层123的表面平齐。
本申请实施例对互联转接层123的材料不做限定，例如可以是无机非金属材料。
在一些实施例中，互联转接层123的材料例如可以是硅，构成的芯片结构12可以理解为是硅通孔中介层2.5D封装(chip-on-wafer-on-substrate，CoWoS)结构。
在另一些实施例中，互联转接层123的材料例如可以是玻璃，构成的芯片结构12可以理解为是玻璃通孔中介层2.5D封装(chip on glass-on-substrate，CoGoS)结构。
在又一些实施例中，互联转接层的材料例如可以是陶瓷，构成的芯片结构12可以理解为是陶瓷通孔中介层2.5D封装(chip on ceramics-on-substrate，CoCoS)结构。
另外，本申请实施例对导通孔124的材料不做限定，导通孔124是任意导电材料即可。导通孔124例如可以通过硅通孔技术(through silicon via，TSV)技术、或者电镀工艺制备得到。
如图7B所示，芯片125设置在互联转接层123上(例如第一表面上)，与导通孔124的第一端电性连接。凸点121也设置在互联转接层123上(与第一表面相对的第二表面上)，与导通孔124的第二端电性连接。
在这种情况下，导通孔124的第二端可以理解为是芯片结构12的触点122。
在一些实施例中，为了简化芯片125与互联转接层123的电性连接的方式，如图7B所示，芯片125的有源面朝向互联转接层123设置。
其中，根据芯片125结构的不同，暴露于芯片125有源面的转接点的结构也不同。示例的，暴露于芯片125有源面的转接点为焊盘(pad)。或者，示例的，暴露于芯片125有源面的转接点为导电柱(bump)。或者，示例的，暴露于芯片125有源面的转 接点为焊球。基于此，本申请实施例对芯片125与导通孔124的第一端电性连接的方式不做限定。例如，可以通过键合的方式实现二者的电性连接。
本申请实施例对芯片结构12包括的芯片125的数量不做限定，在一些实施例中，芯片结构12包括一个芯片125。
在另一些实施例中，如图7C所示，芯片结构12包括多个芯片125。
示例的，如图7C所示，多个芯片125并排设置在互联转接层123上。
或者，示例的，如图7D所示，多个芯片125堆叠后，设置在互联转接层123上。
本申请实施例对芯片结构12中包括的芯片125的结构不做限定，在一些实施例中，芯片125可以是裸芯片(也可以称为晶粒或颗粒)(die)。可以理解的是，对晶圆进行切割得到的即为裸芯片。
在另一些实施例中，芯片125也可以是将裸芯片进行封装后得到的封装后的芯片。
可以理解的是，在芯片结构12包括多个芯片125的情况下，多个芯片125可以全部是裸芯片；多个芯片125也可以全部是封装后的芯片；多个芯片125也可以部分是裸芯片，部分是封装后的芯片。
关于凸点121的结构，本申请实施例对凸点121的结构、材料不做限定。
在一些实施例中，凸点121可以是焊球(solder ball)、凸起(bump)、铜柱(Cu pillar)以及可控塌陷芯片连接凸块(controlled collapse chip connection bump，C4bump)等金属焊料。
其中，通过调整上述封装结构的制备方法中步骤S4的工艺，即可得到不同结构的凸点121。
关于芯片结构12的结构，在另一种实施例中，如图8A所示，芯片模块12＇包括芯片125和凸点121。
本申请实施例对芯片结构12包括的芯片125的数量不做限定，示例性的，如图8A所示，芯片结构12包括一个芯片125。
或者，示例的，如图8B所示，芯片结构12包括多个堆叠设置的芯片125。
其中，芯片125可以是裸芯片，也可以是封装后的芯片，本申请实施例对此不做限定。
凸点121设置在芯片125上，例如，凸点121设置在芯片125的有源面上，暴露于芯片125的有源面的焊盘作为芯片结构12中的触点122，与凸点121电性连接。
凸点121，例如可以是焊球、凸起、铜柱以及C4等金属焊料。
其中，图7B-图7D和图8A、图8B中的芯片模块12＇，即为上述芯片封装结构的制备方法的步骤S1中放置到载板21上的芯片模块12＇。在芯片模块12＇上形成凸点121之后，即可得到本申请实施例中的芯片结构12。
关于芯片封装结构100中的塑封层13，如图7A所示，塑封层13至少包裹芯片结构12的侧面，且露出凸点121。
在一些实施例中，如图7A所示，塑封层13包裹芯片结构12的侧面，且覆盖芯片结构12的顶面(远离封装基板11的表面)。
这样一来，制备工艺简单，效率高。
在另一些实施例中，如图9A所示，塑封层13包裹芯片结构12的侧面，且露出 芯片结构12的顶面。
这样一来，有利于芯片结构12的表面散热。
其中，通过调整上述封装结构的制备方法中步骤S2的工艺，即可得到不同包裹程度的塑封层13。
在此基础上，如图9A所示，塑封层13的底部外侧具有倒角131。
关于倒角131的结构，在一些实施例中，如图9A所示，倒角131的倒角面a为平面。
在另一些实施例中，如图9B所示，倒角131的倒角面a为曲面。
本申请实施例对此不做限定，根据需要合理设置即可。
另外，本申请实施例对倒角131角度α的大小不做限定，倒角角度α范围可以是30°-70°。例如：倒角角度α可以是45°、60°或者63°。倒角角度α，可以理解为是倒角面a与塑封层13底面的夹角。
其中，在执行上述步骤S5的过程中，通过设定切割刀侧面的倾斜角度和侧面的形状，即可制备得不同结构的倒角131。
在一些实施例中，如图9C所示，塑封层13中，倒角的倒角面a中靠近塑封层13底部(靠近封装基板11一侧)的一侧，与芯片结构12之间没有间距。
这样一来，塑封层13的尺寸较小，可减小芯片封装结构100的尺寸。
在另一些实施例中，如图9A所示，倒角的倒角面a中靠近塑封层13底部(靠近封装基板11一侧)的一侧，与芯片结构12之间具有间距(或者理解为水平余量)h1；倒角的倒角面a中靠近塑封层13顶部(远离封装基板11一侧)的一侧，与芯片结构12之间具有间距(或者理解为竖直余量)h2。
也就是说，塑封层13的倒角131与芯片结构12之间具有水平距离，倒角131并未直接切割到芯片结构12的边缘。
在另一些实施例中，如图9D所示，倒角的倒角面a中靠近塑封层13底部(靠近封装基板11一侧)的一侧，与芯片结构12之间具有间距h1，倒角的倒角面a中靠近塑封层13顶部的一侧直接与塑封层13的顶部接触，没有间距。
通过在塑封层13的倒角131与芯片结构12之间具有一定的水平距离h1，可以使芯片结构12的边角被塑封层13包裹起来，塑封层13与底部填充胶14直接接触。这样一来，能够避免芯片结构12的边角与底部填充胶14直接接触造成的裂开或翘曲。同时，在执行上述步骤S6的过程中，沿切割道进行切割时，能够避免因为切割偏移而切到芯片结构12，导致芯片结构12破裂的问题。
关于倒角131的设置位置，在一些实施例中，如图10A所示，倒角131仅在塑封层13底部的四角处设置。
由于塑封层13底部的四角处对底部填充胶14施加的应力最大，因此，在塑封层13底部的四角处形成倒角131，即可减小塑封层13对底部填充胶14施加的应力，降低底部填充胶14破裂的风险。
在另一些实施例中，如图10B所示，倒角131绕塑封层13的底部外侧一圈设置。
这样一来，制备工艺简单，易于实现。
其中，通过调整上述封装结构的制备方法中步骤S5的工艺，即可得到设置于不同 位置的倒角131。
本申请实施例对塑封层13的材料不做限定，塑封层13作为芯片结构12与底部填充胶14之间的应力过渡层。因此，塑封层13对底部填充胶14施加的应力，小于芯片结构12对底部填充胶14施加的应力即可。
例如，塑封层13的硬度小于芯片结构12的硬度。例如，塑封层13的模量小于芯片结构12的模量，但接近底部填充胶14的模量。
示例的，塑封层13的材料以环氧树脂为基底，进行掺杂处理，得到所需的材料。
塑封层13的材料，例如可以是环氧塑封料、底部填充胶、粘结料或者导热介质材料。
关于芯片封装结构100中的底部填充胶14，如图7A所示，芯片结构12设置在封装基板11上，通过凸点121与封装基板11电性连接。芯片结构12与封装基板11之间存在间隙，底部填充胶14设置在芯片结构12与封装基板11之间的间隙处，且包裹在塑封层13的外围。
本申请实施例对底部填充胶14对塑封层13的包裹程度不做限定，根据工艺和需求合理设置即可。
在一些实施例中，如图9A所示，底部填充胶14包裹至塑封层13的侧面b。
其中，底部填充胶14可以包裹至塑封层13侧面b的一半高度，也可以包裹塑封层13的全部侧面b，当然也可以包裹塑封层13侧面b的任意高度处。
底部填充胶14包裹塑封层13的侧面高度越高，底部填充胶14能够承受的应力就越大，越能抵抗应力风险。因此，本申请实施例将底部填充胶14包裹至塑封层13的侧面b，可提高底部填充胶14的抗应力风险。在另一些实施例中，如图9E所示，底部填充胶14包裹至倒角131的倒角面a。
底部填充胶14包裹至倒角131的倒角面a，即可对凸点121起到保护作用，对芯片结构12起到稳固作用。制备工艺时间短，提升产能。
通过调整上述封装结构的制备方法中步骤S8的工艺，即可得到不同包裹程度的底部填充胶14。
本申请实施例提供的芯片封装结构，芯片封装结构包括封装基板11、设置在封装基板11上的芯片结构12、至少包裹芯片结构12侧面的塑封层13以及设置在芯片结构12与封装基板11之间，且包裹在塑封层13外围的底部填充胶14。其中，芯片结构12包括位于表面的多个凸点121，凸点121与封装基板11电性连接；塑封层13包裹芯片结构12的侧面，露出凸点121，塑封层13靠近封装基板11的底部外侧具有倒角131。由于无需具有倒角的芯片结构12，无需预留晶圆10上较宽的切割道区，芯片结构12的实际尺寸和芯片结构12功能区的尺寸相近，因此，可以避免在芯片结构12上倒角所带来的芯片结构12损坏和晶圆10浪费等问题，降低芯片结构12的成本。
而且，在塑封层13上的倒角131不会对芯片结构12产生裂痕等影响，塑封层13上无需具有烧结槽30，也无需预留安全距离，可缩小切割道区。因此，塑封层13的尺寸无需过大，不会过分增大芯片封装结构的尺寸。也就是说，将芯片结构12上的倒角转移到塑封层13上后，不仅可以缓解芯片结构12的尖角与底部填充胶14之间的集中应力，可避免底部填充胶14因为集中应力而出现裂纹的问题。还可以降低芯片封装结 构的成本，和解决因切割芯片结构12所带来的一系列问题。克服了大尺寸的芯片封装下芯片结构的限制，解决了大尺寸、高面积占比芯片封装下的芯片结构12边角应力集中问题，避免芯片封装结构高温下失效。
塑封层13包裹芯片结构12的外围，塑封层13直接与底部填充胶14接触。由于形成塑封层13的塑封料与底部填充胶14之间的热膨胀系数差异，以及芯片结构12与塑封层13之间的热膨胀系数差异，均小于芯片结构12与底部填充胶14之间的热膨胀系数差异。因此，塑封层13作为应力过渡层，可以改善芯片结构12与底部填充胶14之间热胀冷缩过程中带来的应力，进而减小芯片结构12边角处对底部填充胶14的集中应力，从而避免因为底部填充胶14受到集中应力断裂而导致芯片封装结构失效的问题，实现芯片封装结构100中应力的释放。
此外，塑封层13的材质相较于晶圆10的材质更为柔软且极易进行切割，形成的倒角面更为光滑，避免了不平整的倒角面带来的局部应力集中。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (8)

  1. 一种芯片封装结构，其特征在于，包括：
    封装基板；
    芯片结构，包括位于表面的多个凸点；所述芯片结构设置在所述封装基板上，所述凸点与所述封装基板电性连接；
    塑封层(molding)，至少包裹所述芯片结构的侧面；所述塑封层靠近所述封装基板的底部外侧具有倒角；
    底部填充胶，包裹所述凸点以及所述倒角的至少部分倒角面。
  2. 根据权利要求1所述的芯片封装结构，其特征在于，所述倒角的倒角面中靠近所述塑封层底部的一侧，与所述芯片结构之间具有间距。
  3. 根据权利要求1或2所述的芯片封装结构，其特征在于，所述底部填充胶从所述塑封层的底部溢出，漫过所述倒角并包裹所述塑封层的侧面。
  4. 根据权利要求1-3任一项所述的芯片封装结构，其特征在于，所述塑封层的材料包括环氧树脂。
  5. 根据权利要求1-4任一项所述的芯片封装结构，其特征在于，所述芯片结构为：
    芯片，所述芯片上设置有所述凸点。
  6. 根据权利要求1-4任一项所述的芯片封装结构，其特征在于，所述芯片结构包括：
    互联转接层；
    多个导通孔，贯穿所述互联转接层；
    芯片，设置在所述互联转接层上，与所述导通孔的一端电性连接；所述导通孔的另一端上设置有所述凸点。
  7. 一种芯片封装结构的封装方法，其特征在于，包括：
    在放置有多个芯片模块的载板上形成塑封膜；所述芯片模块具有多个触点的表面朝向所述载板，所述塑封膜至少包裹所述芯片模块的侧面；
    去除所述载板，露出所述触点；
    在所述触点上形成凸点，所述凸点与所述触点电性连接；
    在所述塑封膜靠近所述凸点的底面上形成多个倒角槽，所述倒角槽位于所述芯片模块的间隙处；
    沿切割道进行切割；其中，所述切割道位于所述芯片模块的间隙处，所述倒角槽的位置与所述切割道的位置重合；
    将切割得到的组装结构通过所述凸点与封装基板电性连接；
    在所述组装结构与所述封装基板之间形成底部填充胶，所述底部填充胶包裹在所述塑封膜的外围。
  8. 一种通信装置，其特征在于，包括印刷线路板和权利要求1-6任一项所述的芯片封装结构；所述芯片封装结构设置在所述印刷线路板上，与所述印刷线路板耦接。
PCT/CN2021/121468 2021-09-28 2021-09-28 芯片封装结构及其封装方法、通信装置 WO2023050093A1 (zh)

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