CN107154386A - 电子封装件及半导体基板 - Google Patents

电子封装件及半导体基板 Download PDF

Info

Publication number
CN107154386A
CN107154386A CN201610152388.6A CN201610152388A CN107154386A CN 107154386 A CN107154386 A CN 107154386A CN 201610152388 A CN201610152388 A CN 201610152388A CN 107154386 A CN107154386 A CN 107154386A
Authority
CN
China
Prior art keywords
semiconductor substrate
substrate
packing piece
electronic packing
protrusion structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201610152388.6A
Other languages
English (en)
Other versions
CN107154386B (zh
Inventor
陈仕卿
彭仕良
赖杰隆
潘嘉伟
吕长伦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN107154386A publication Critical patent/CN107154386A/zh
Application granted granted Critical
Publication of CN107154386B publication Critical patent/CN107154386B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

一种电子封装件及半导体基板，该电子封装件包括：一具有侧面的基板本体、以及自该侧面向外延伸的突出结构，使该半导体基板通过该突出结构分散于制造方法中所产生的应力，以避免该半导体基板发生破裂或脱层的问题。

Description

电子封装件及半导体基板
技术领域
本发明有关一种半导体封装件，特别是指一种能提高产品合格率的电子封装件及所应用的半导体基板。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。目前应用于芯片封装领域的技术繁多，例如芯片尺寸构装(Chip Scale Package，简称CSP)、芯片直接贴附封装(Direct Chip Attached，简称DCA)或多芯片模组封装(Multi-Chip Module，简称MCM)等覆晶型封装模组、或将芯片立体堆迭化整合为三维集成电路(3D IC)芯片堆迭模组。
图1为现有3D IC式半导体封装件1的剖面示意图。如图1所示，将多个半导体芯片11通过多个焊锡凸块110设于一硅中介板(Through Silicon interposer，简称TSI)10上，且形成一封装层12于该硅中介板10上，以包覆该半导体芯片11，其中该硅中介板10具有多个导电硅穿孔(Through-silicon via，简称TSV)100及形成于该导电硅穿孔100上并电性连接这些焊锡凸块110的线路重布层(Redistribution layer，简称RDL)101，以令该硅中介板10通过这些导电硅穿孔100与多个导电元件130结合至一封装基板13上，并以底胶14包覆这些导电元件130。
然而，现有半导体封装件1中，该硅中介板10的四个角落皆为直角，如图1’所示，故该硅中介板10于封装后，会因应力集中而在各角落形成较大的芯片角落应力(Die CornerStress)，使其与该封装层12之间会产生强大的应力，如图1’所示的虚线圆圈处S，导致该硅中介板10会沿四个角落处发生破裂(Crack)、或因热膨胀系数(Coefficient of thermalexpansion，简称CTE)不匹配(mismatch)而与该封装层12分离，即产生脱层(delaminating)问题，造成该硅中介板10无法有效电性连接该半导体芯片11或无法通过可靠度测试，致使产品的合格率不佳。
此外，于封装后，该硅中介板10的四个角落与该底胶14之间也会产生强大应力，如图1所示的虚线圆圈处K，导致该硅中介板10会沿四个角落处发生破裂或与该底胶14发生分离，致使产品的合格率不佳。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明提供一种电子封装件及半导体基板，以避免该半导体基板发生破裂或脱层的问题。
本发明的半导体基板，其包括：一基板本体，其具有至少一侧面；以及至少一突出结构，其自该基板本体的侧面向外延伸。
本发明还提供一种电子封装件，其包括：半导体基板，其包含有一基板本体及自该基板本体的侧面向外延伸的至少一突出结构；电子元件，其设于该半导体基板上；以及封装层，其形成于该半导体基板上以包覆该电子元件。
前述的电子封装件中，该半导体基板具有多个线路，以令该电子元件电性连接该线路。
前述的电子封装件中，还包括封装基板，其接置于该半导体基板用于设有该电子元件的另一侧上。又包括形成于该封装基板与该半导体基板间的底胶。
前述的电子封装件及半导体基板中，该基板本体具有多个该侧面，其交会形成有角落，以令该突出结构形成于该角落上。
前述的电子封装件及半导体基板中，该突出结构与该基板本体一体成形。
前述的电子封装件及半导体基板中，该突出结构的轮廓由直线、曲线或其二者的组合所构成。
前述的电子封装件及半导体基板中，该突出结构包含有一连接该基板本体侧面的颈部与一连接该颈部的头部。
由上可知，本发明的电子封装件及半导体基板中，主要通过该突出结构的设计，以分散该半导体基板与该封装层(或底胶)之间的应力，使该半导体基板消除应力集中于角落的问题，故能避免该半导体基板于封装后发生破裂或脱层等问题，因而能提高产品合格率。
此外，该突出结构自该基板本体的侧面向外延伸，故该突出结构不会占用该基板本体的原本预定区域(如布设线路或设置电极垫的区域)，使该半导体基板的原本预定可用区域与性能均不受影响。
附图说明
图1为现有半导体封装件的剖面示意图；
图1’为图1的半导体封装件省略底胶的上视示意图；
图2为本发明的半导体基板的上视示意图；
图2’为图2的另一实施例；
图2A至图2D为图2的不同实施例的局部放大图；
图3为本发明的半导体基板的制法的上视示意图；
图4为本发明的电子封装件的剖面示意图；以及
图5为本发明的电子封装件的制法的上视示意图。
符号说明：
1 半导体封装件
10 硅中介板
100 导电硅穿孔
101 线路重布层
11 半导体芯片
110 焊锡凸块
12,42 封装层
13,43 封装基板
130,402,430 导电元件
14,44 底胶
2,2’,40 半导体基板
20,20’,40’ 基板本体
20a,20a’,40c 侧面
20b 角落
21 突出结构
21a 颈部
21b 头部
210,210’ 直线
211 曲线
3,5 整版面板块
30,50 预切割道
30’,50’ 切割道
30”,50” 预切割道材质
4 电子封装件
40a 第一表面
40b 第二表面
400 导电穿孔
401 线路重布结构
41 电子元件
41a 作用面
41b 非作用面
410 电极垫
W 宽度
S,K 虚线圆圈处。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2为本发明的半导体基板2的上视示意图。如图2所示，所述的半导体基板2包括有一基板本体20以及多个突出结构21。
所述的基板本体20为含硅的板体，例如，硅中介板(Through SiliconInterposer，简称TSI)、主动芯片、被动芯片或玻璃基板。
于本实施例中，该基板本体20具有四个侧面20a，如图2所示的矩形轮廓。
所述的突出结构21自该基板本体20的侧面20a向外延伸。
于本实施例中，该基板本体20的四个侧面20a于其交会处形成有四个角落20b，以令各该突出结构21对应形成于各该角落20b上。
此外，该突出结构21包含有一连接该基板本体20的颈部21a与一连接该颈部21a的头部21b，且该突出结构21的轮廓由直线210,210’、曲线211或其二者的组合所构成，如图2A至图2D所示。具体地，如图2A及图2D所示，该颈部21a呈钝角多边形；如图2B及图2C所示，该颈部21a呈圆弧形。因此，本实施例的突出结构21由圆弧及/或多边形所构成。需注意，如图2A及图2D所示，该颈部21a的单一侧至多十条直线210，以避免变成弧状。
又，于其它实施例中，如图2’所示的半导体基板2’，该基板本体20’仅具有一侧面20a’，如圆形轮廓，且该突出结构21的位置可依需求形成于该侧面20a’的任一处上。
另外，该半导体基板2的制法如图3所示，先提供一整版面板块3，且该整版面板块3包含多个基板本体20及多个预切割道30，且该预切割道30的宽度W约为80至120微米(μm)，再于这些预切割道30上形成光阻层后，以干式蚀刻方式，如反应性离子蚀刻(Reactive IonEtching，简称RIE)或等离子(Plasma)方式，形成多个突出结构21及切割道30’，之后移除该光阻层，再沿这些切割道30’进行切单制造方法以分离各该半导体基板2，最后移除该半导体基板2周围的预切割道材质30”。因此，该突出结构21与该基板本体20一体成形。
本发明的半导体基板2,2’通过该突出结构21的设计，以分散该半导体基板2,2’于后续封装制造方法中所产生的应力，使该半导体基板2,2’消除应力集中于角落的问题，故能避免该半导体基板2,2’于封装后发生破裂或脱层的问题，因而能提高产品合格率。
此外，该突出结构21凸出于该基板本体20,20’的侧面20a,20a’外，亦即该突出结构21只占用预切割道30的区域，故该突出结构21不会占用该基板本体20,20’的原本预定区域(如布设线路或设置电极垫的区域)，使该基板本体20,20’的原本预定可用面积与性能皆完全不受影响。
图4为本发明的电子封装件4的剖面示意图。如图4所示，所述的电子封装件4包括有一半导体基板40、至少一电子元件41以及一封装层42。
所述的半导体基板40如图2所述的结构，其基板本体40’定义有相对的第一表面40a与第二表面40b，且该半导体基板40的侧面40c邻接该第一表面40a与第二表面40b，使该突出结构21自该侧面40c向外延伸。
于本实施例中，该半导体基板40具有多个线路。例如，该基板本体40’中具有多个贯穿该第一与第二表面40a,40b(即连通该第一与第二表面40a,40b)的导电穿孔400。具体地，该导电穿孔400为导电硅穿孔(Through-silicon via，简称TSV)，且该导电穿孔400的两端面分别齐平该基板本体40’的第一表面40a与第二表面40b。
此外，该半导体基板40的线路也可形成于该基板本体40’的第一表面40a上。例如，进行线路重布层(Redistribution layer，简称RDL)制造方法，以形成一线路重布结构401，且该线路重布结构401电性连接各该导电穿孔400。
所述的电子元件41设于该半导体基板40上，且该电子元件41为主动元件、被动元件或其二者组合等，其中，该主动元件为例如半导体芯片，且该被动元件为例如电阻、电容及电感。
于本实施例中，该电子元件41为半导体芯片，其具有相对的作用面41a与非作用面41b，该作用面41a具有多个电极垫410，使该电子元件41以其电极垫410通过含焊锡材料的导电元件402结合于该线路重布结构401上。
所述的封装层42形成于该半导体基板40上以包覆这些电子元件41与这些导电元件402。
于本实施例中，形成该封装层42的材质为聚酰亚胺(polyimide，简称PI)、干膜(dry film)、环氧树脂(expoxy)或封装材。
于另一实施例中，该电子封装件4亦可包括一封装基板43，其设于该半导体基板40用于设有该电子元件41的另一侧上(即该基板本体40’的第二表面40b上)。具体地，该封装基板43通过多个导电元件430结合并电性连接该半导体基板40的导电穿孔400，再形成底胶44于该封装基板43与该半导体基板40之间以包覆这些导电元件430，并于后续制造方法中，形成多个焊球(图略)于该封装基板43下侧，以供该电子封装件4结合至一电路板(图略)上。
另外，该电子封装件4的制法如图5所示(图未示封装层42)，先提供一整版面板块5，该整版面板块5包含多个基板本体40’及多个预切割道50，且该基板本体40’上设有该电子元件41；接着，于这些预切割道50上以蚀刻方式形成多个突出结构21及切割道50’，之后沿这些切割道50’进行切单制造方法以分离各该半导体基板40，最后移除该电子封装件4周围的预切割道材质50”。或者，先于该整版面板块5形成多个突出结构21及切割道50’，再于该基板本体40’上设置电子元件41。
需注意，干式蚀刻无法蚀刻该封装层42，故可先形成这些突出结构21及切割道50’，再形成该封装层42。应可理解地，也可先形成该封装层42，再以其它方式形成这些突出结构21及切割道50’。
本发明的电子封装件4通过该突出结构21的设计，以消除该半导体基板40的应力集中，故于封装后，该半导体基板40不会沿角落处发生破裂，且能避免因热膨胀系数(CTE)不匹配而与该封装层42(或底胶44)发生分离的问题，因而该半导体基板40得以与该电子元件41及封装基板43保持正常电性连接，并能通过可靠度测试，致能提高产品合格率。
此外，该突出结构21凸出于该基板本体40’的使用区域外，亦即该突出结构21只占用该预切割道50的区域，故该突出结构21不会占用该基板本体40’的原本预定区域(如布设线路或设置电极垫的区域)，使该半导体基板40的可用面积与性能皆完全不受影响，亦即该基板本体40’的线路布设空间或设置该电子元件41的区域不受影响。
综上所述，本发明的电子封装件及半导体基板中，通过该突出结构消除应力集中的问题，以提升产品合格率，且该半导体基板的原本可用区域与性能均不受影响。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (13)

1.一种半导体基板，其特征为，该半导体基板包括：
一基板本体，其具有至少一侧面；以及
至少一突出结构，其自该基板本体的侧面向外延伸。
2.如权利要求1所述的半导体基板，其特征为，该基板本体具有多个该侧面，其交会形成有角落，以令该突出结构形成于该角落上。
3.如权利要求1所述的半导体基板，其特征为，该突出结构与该基板本体一体成形。
4.如权利要求1所述的半导体基板，其特征为，该突出结构的轮廓由直线、曲线或其二者的组合所构成。
5.如权利要求1所述的半导体基板，其特征为，该突出结构包含有一连接该基板本体侧面的颈部与一连接该颈部的头部。
6.一种电子封装件，其特征为，该电子封装件包括：
半导体基板，其包含有一基板本体及自该基板本体的侧面向外延伸的至少一突出结构；
电子元件，其设于该半导体基板上；以及
封装层，其形成于该半导体基板上以包覆该电子元件。
7.如权利要求6所述的电子封装件，其特征为，该基板本体具有多个该侧面，其交会形成有角落，以令该突出结构形成于该角落上。
8.如权利要求6所述的电子封装件，其特征为，该半导体基板具有多个线路，以令该电子元件电性连接该线路。
9.如权利要求6所述的电子封装件，其特征为，该突出结构与该基板本体一体成形。
10.如权利要求6所述的电子封装件，其特征为，该突出结构的轮廓由直线、曲线或其二者的组合所构成。
11.如权利要求6所述的电子封装件，其特征为，该突出结构包含有一连接该侧面的颈部与一连接该颈部的头部。
12.如权利要求6所述的电子封装件，其特征为，该电子封装件还包括封装基板，其接置于该半导体基板相对设有该电子元件的另一侧上。
13.如权利要求12所述的电子封装件，其特征为，该电子封装件还包括形成于该封装基板与该半导体基板间的底胶。
CN201610152388.6A 2016-03-04 2016-03-17 电子封装件及半导体基板 Active CN107154386B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW105106680A TWI611577B (zh) 2016-03-04 2016-03-04 電子封裝件及半導體基板
TW105106680 2016-03-04

Publications (2)

Publication Number Publication Date
CN107154386A true CN107154386A (zh) 2017-09-12
CN107154386B CN107154386B (zh) 2020-01-10

Family

ID=59722267

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610152388.6A Active CN107154386B (zh) 2016-03-04 2016-03-17 电子封装件及半导体基板

Country Status (3)

Country Link
US (1) US9899309B2 (zh)
CN (1) CN107154386B (zh)
TW (1) TWI611577B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116314040A (zh) * 2023-05-24 2023-06-23 深圳和美精艺半导体科技股份有限公司 一种承载基板及其制造方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3449502B1 (en) 2016-04-26 2021-06-30 Linear Technology LLC Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
US20210257335A1 (en) 2020-02-19 2021-08-19 Nanya Technology Corporation Semiconductor package and method of manufacturing the same
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6329960A (ja) * 1986-07-23 1988-02-08 Hitachi Micro Comput Eng Ltd 樹脂封止型半導体装置用リ−ドフレ−ム
CN102468257A (zh) * 2010-11-11 2012-05-23 日月光半导体制造股份有限公司 晶圆级半导体封装件及其制造方法
CN102931156A (zh) * 2012-10-08 2013-02-13 日月光半导体制造股份有限公司 半导体芯片的构造及制作方法
CN104617088A (zh) * 2013-11-05 2015-05-13 矽品精密工业股份有限公司 半导体封装件及其制法与基板暨封装结构
CN104701196A (zh) * 2013-12-09 2015-06-10 矽品精密工业股份有限公司 半导体封装件的制法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6940176B2 (en) * 2002-05-21 2005-09-06 United Microelectronics Corp. Solder pads for improving reliability of a package
US8039365B2 (en) * 2006-07-11 2011-10-18 Stats Chippac Ltd. Integrated circuit package system including wafer level spacer
SG143098A1 (en) * 2006-12-04 2008-06-27 Micron Technology Inc Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
JP2013058547A (ja) * 2011-09-07 2013-03-28 Toshiba Corp 半導体装置
WO2014009997A1 (ja) * 2012-07-11 2014-01-16 三菱電機株式会社 半導体装置およびその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6329960A (ja) * 1986-07-23 1988-02-08 Hitachi Micro Comput Eng Ltd 樹脂封止型半導体装置用リ−ドフレ−ム
CN102468257A (zh) * 2010-11-11 2012-05-23 日月光半导体制造股份有限公司 晶圆级半导体封装件及其制造方法
CN102931156A (zh) * 2012-10-08 2013-02-13 日月光半导体制造股份有限公司 半导体芯片的构造及制作方法
CN104617088A (zh) * 2013-11-05 2015-05-13 矽品精密工业股份有限公司 半导体封装件及其制法与基板暨封装结构
CN104701196A (zh) * 2013-12-09 2015-06-10 矽品精密工业股份有限公司 半导体封装件的制法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116314040A (zh) * 2023-05-24 2023-06-23 深圳和美精艺半导体科技股份有限公司 一种承载基板及其制造方法

Also Published As

Publication number Publication date
CN107154386B (zh) 2020-01-10
TW201733109A (zh) 2017-09-16
TWI611577B (zh) 2018-01-11
US20170256481A1 (en) 2017-09-07
US9899309B2 (en) 2018-02-20

Similar Documents

Publication Publication Date Title
CN107154386A (zh) 电子封装件及半导体基板
TWI631676B (zh) 電子封裝件及其製法
CN106935563B (zh) 电子封装件及其制法与基板结构
CN106206509B (zh) 电子封装件及其制法与基板结构
CN106469712B (zh) 电子封装结构及其制法
JP2010056139A (ja) 積層型半導体装置
TWI669789B (zh) 電子封裝件
US10037970B2 (en) Multiple interconnections between die
TW201306209A (zh) 半導體裝置及其封裝方法以及用於半導體裝置的封裝
CN107305870A (zh) 电子封装件及基板结构
CN108074904A (zh) 电子封装件及其制法
KR102065648B1 (ko) 반도체 패키지
CN108074905A (zh) 电子装置及其制法与基板结构
CN107123631A (zh) 电子封装件及其半导体基板与制法
TW201642428A (zh) 矽中介層與其製作方法
TWI790945B (zh) 電子封裝件及其製法
CN108305866A (zh) 电子封装件的制法
CN108538790A (zh) 基板结构及其制法与电子封装件
TW201216439A (en) Chip stacked structure
TWM521807U (zh) 封裝結構及其中介板
CN107123629B (zh) 封装结构
US12033871B2 (en) Method for forming semiconductor die package with ring structure comprising recessed parts
KR20160010968A (ko) 반도체 패키지 및 그 제조 방법
US11973061B2 (en) Chip package including stacked chips and chip couplers
US20240055363A1 (en) Semiconductor device, method of manufacturing semiconductor device, and method of disposing alignment mark

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant