TW201519402A - 半導體封裝件及其製法與基板暨封裝結構 - Google Patents

半導體封裝件及其製法與基板暨封裝結構 Download PDF

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Publication number
TW201519402A
TW201519402A TW102140073A TW102140073A TW201519402A TW 201519402 A TW201519402 A TW 201519402A TW 102140073 A TW102140073 A TW 102140073A TW 102140073 A TW102140073 A TW 102140073A TW 201519402 A TW201519402 A TW 201519402A
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Taiwan
Prior art keywords
substrate
semiconductor package
fabricating
cleaning
package according
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TW102140073A
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English (en)
Inventor
徐逐崎
王隆源
江政嘉
施嘉凱
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矽品精密工業股份有限公司
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Priority to TW102140073A priority Critical patent/TW201519402A/zh
Priority to CN201310577966.7A priority patent/CN104617088B/zh
Priority to US14/133,868 priority patent/US20150123287A1/en
Publication of TW201519402A publication Critical patent/TW201519402A/zh

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Abstract

一種半導體封裝件之製法，係先藉由複數支撐元件疊放第二基板於第一基板上，且該第二基板具有至少一貫通之清理孔，再進行清理該支撐元件之作業，並利用該清理孔清理該第二基板與該第一基板之間的空間。本發明復提供該半導體封裝件、基板及封裝結構。

Description

半導體封裝件及其製法與基板暨封裝結構
本發明係關於一種半導體封裝件，更詳言之，本發明係有關於一種提升可靠度的半導體封裝件及其製法與基板暨封裝結構。
隨著近年來可攜式電子產品的蓬勃發展，各類相關產品逐漸朝向高密度、高性能以及輕、薄、短、小之趨勢而走，各態樣的堆疊封裝(package on package，PoP)也因而配合推陳出新，以期能符合輕薄短小與高密度的要求。
習知堆疊式半導體封裝件係包括兩相疊之第一封裝結構與第二封裝結構、及黏固該第一封裝結構與第二封裝結構之封裝膠體。該第一封裝結構係包含第一基板、及電性結合該第一基板之第一半導體元件。該第二封裝結構係包含第二基板、及電性結合該第二基板之第二半導體元件。該第二基板藉由銲錫球疊設且電性連接於該第一基板上，且該封裝膠體形成於該第一基板與第二基板之間以包覆該些銲錫球。
於製作習知堆疊式半導體封裝件之過程中，如第1A至1B圖所示，係將一第二基板12以複數銲錫球13覆晶結合至第一封裝結構1a上，該第一封裝結構1a係包括設有複數半導體元件10之第一基板11，且該些銲錫球13上具有助銲劑(flux)。接著，以去離子水(DI water)進行清理作業以清除助銲劑。之後，電性結合複數第二半導體元件(圖略)於該第二基板12上。
惟，該第二基板12係覆蓋於該第一基板11上，因而於進行清理作業時，會由上方及側方朝第二基板12與該些銲錫球13清洗助銲劑(如第1B及1B’圖所示之箭頭方向X,Z)，故於進行清理作業後，助銲劑f會因去離子水之帶動而殘留於該第一封裝結構1a上方，如第1B圖所示，致使當該第一封裝結構1a進行熱傳導時，會發生爆板(popcorn)情況，因而造成堆疊式半導體封裝件發生分層(delamination)，即該第二基板12與該第一封裝結構1a分離。
此外，由於第一基板11、第二基板12與銲錫球13之間的熱膨脹係數(Coefficient of thermal expansion,CTE)不同，故於覆晶結合及形成封裝膠體時，該第一基板11與第二基板12易產生翹曲現象，使該些銲錫球13與第一基板11或第二基板12間的界面不斷脹縮拉扯而造成斷裂，因而導致短路。
因此，如何解決習知技術之種種缺失，實為目前各界亟欲解決之技術問題。
為解決上述習知技術之種種問題，本發明遂揭露一種半導體封裝件，係包括：第一基板；以及第二基板，係藉由複數支撐元件設於該第一基板上，且該第二基板之邊緣具有至少一缺口。
前述之半導體封裝件中，該缺口係為彎折形、弧形、直線形或多邊形。
本發明復揭露一種半導體封裝件之製法，係包括：提供第一基板；藉由複數支撐元件置放第二基板於該第一基板上，且該第二基板具有至少一貫通之清理孔；以及進行清理作業，係藉由該清理孔清理該第二基板與該第一基板之間的空間。
前述之製法中，該清理作業復清理該支撐元件。
前述之製法中，該清理作業係藉由液體進行清理，例如，水。
前述之製法中，該第二基板係包含複數基板單元，且該清理孔係位於該基板單元之邊緣。例如，該第二基板復包括間隔部，係位於各該基板單元之間，以連結各該基板單元，致使該清理孔係位於該間隔部，其中，該間隔部係為切割路徑。
前述之製法中，該清理孔係為十字形、圓形、條狀或多邊形。
前述之半導體封裝件及其製法中，該第一基板上具有至少一半導體元件。
前述之半導體封裝件及其製法中，該支撐元件係為導電元件，例如含有銲錫材料及助銲劑。
前述之半導體封裝件及其製法中，復包括設置至少一電子元件於該第二基板上。
前述之半導體封裝件及其製法中，復包括形成封裝膠體於該第二基板與該第一基板之間，例如，該封裝膠體係填充滿該第二基板與該第一基板之間的空間。
本發明亦提供一種基板，如前述之第二基板，係包括：複數基板單元；以及間隔部，係位於各該基板單元之間，以連結各該基板單元，且該間隔部上具有至少一貫通之清理孔。
前述之基板中，該清理孔係為十字形、圓形、條狀或多邊形。
前述之基板中，該間隔部係為切割路徑。
另外，本發明又提供一種封裝結構，係包括：基板，係包含複數基板單元及位於各該基板單元之間以連結各該基板單元的間隔部，該間隔部上具有至少一貫通之清理孔；以及電子元件，係設於該基板上。
前述之封裝結構中，該電子元件係為半導體元件。
前述之封裝結構中，該清理孔係為十字形、圓形、條狀或多邊形。
前述之封裝結構中，該間隔部係為切割路徑。
由上可知，本發明之半導體封裝件及其製法與其基板暨封裝結構，係藉由該些清理孔之設計，使液體能經由該 些清理孔流至該第一與第二基板之間的空間而增加清洗水流的面積，以於進行該清理作業時，液體能由內向外清洗如助銲劑之殘渣，故相較於習知技術，本發明於清理作業結束後，於該第一封裝結構上方不會有殘留物。因此，當該第一基板或半導體元件進行熱傳導時，不會發生爆板情況，因而該半導體封裝件不會發生分層之問題。
再者，藉由該些清理孔可分散熱應力，以於覆晶結合及形成封裝膠體時，能避免該第一基板與第二基板發生翹曲現象，故能減少該些支撐元件與第一基板或第二基板間的界面脹縮拉扯，以避免該些支撐元件發生斷裂而導致短路之問題。
1a,2a‧‧‧第一封裝結構
10,20‧‧‧半導體元件
11,21‧‧‧第一基板
12,22‧‧‧第二基板
13‧‧‧銲錫球
14‧‧‧第二半導體元件
2‧‧‧半導體封裝件
2b‧‧‧第二封裝結構
22’‧‧‧基板區塊
22a‧‧‧基板單元
22b,22b’‧‧‧間隔部
220,220’‧‧‧清理孔
23‧‧‧支撐元件
24‧‧‧電子元件
25‧‧‧封裝膠體
26,26’‧‧‧基板
260,260’‧‧‧缺口
29‧‧‧承載件
f‧‧‧助銲劑
S‧‧‧空間
第1A至1B圖係顯示習知半導體封裝件之製法之剖面示意圖；其中，第1B’圖係為第1B圖之上視示意圖；以及第2A至2E圖係本發明之半導體封裝件之製法之剖面示意圖；其中，第2B圖係為第2C圖之上視示意圖，第2B’圖係為第2B圖之另一實施例，2C’圖係為第2B圖之局部放大圖，第2E’及2E’’圖係為第2E圖之不同態樣之局部上視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2E圖係本發明之半導體封裝件2之製法的示意圖。
如第2A圖所示，提供一第一封裝結構2a，該第一封裝結構2a係包含第一基板21及覆晶結合於該第一基板21上之至少一半導體元件20，且該第一基板21係設於承載件29上。接著，藉由複數支撐元件23置放至少一第二基板22於該第一基板21上。
於本實施例中，該第一基板21係為未切單之整版面結構，其上具有複數個半導體元件20，且該第二基板22亦為未切單之整版面結構，如第2B圖所示，其包含四個基板區塊22’。
再者，該基板區塊22’係包含對應該半導體元件20之複數基板單元22a、及位於各該基板單元22a之間以連 結各該基板單元22a的間隔部22b，使每一基板區塊22’係覆蓋十六個半導體元件20，如第2B圖所示。
又，該支撐元件23係為導電元件，具體地，該導電元件係含有銲錫材料與助銲劑。
另外，該第一基板21及第二基板22均為線路板，且有關線路板之種類繁多，於圖中係簡略繪示，並不限於此。
如第2B及2B’圖所示，形成複數貫通之清理孔220,220’於該第二基板22上。
於本實施例中，該清理孔220,220’係對應該半導體元件20之位置而位於該基板單元22a之邊緣，例如，位於該間隔部22b上。
再者，該清理孔220,220’係為十字形(如第2B圖所示)、圓形(如第2B’圖所示)、條狀或多邊形。
如第2C及2C’圖所示，進行清理作業，係由上方及側方朝該第二基板22與該些支撐元件23清洗助銲劑，且利用該些清理孔220清理該第二基板22與該第一基板21之間的空間S。
於本實施例中，係藉由液體(如第2C’圖所示之箭頭方向L)進行該清理作業，該液體係為水，例如去離子水。
本發明之製法係藉由該些清理孔220,220’之設計，使液體能經由該些清理孔220,220’流至該第二基板22與該第一基板21之間的空間S而增加清洗水流的面積，以於進行該清理作業時，液體能由內向外清洗助銲劑(如第2C圖所示之箭頭方向Y)，而降低助銲劑殘留的可能性，故 於清理作業結束後，助銲劑會因液體之沖洗而不會殘留於該第一封裝結構2a上方。因此，當後續該第一封裝結構2a進行熱傳導時，不會發生爆板情況，因而有效避免堆疊式半導體封裝件2發生分層之問題。
如第2D圖所示，設置複數電子元件24於該第二基板22上，以令該電子元件24與該第二基板22構成第二封裝結構2b，且形成封裝膠體25於該基板單元22a與該第一基板21之間。
於本實施例中，單一該基板單元22a上係設有複數該電子元件24。
再者，該電子元件24可為如半導體晶片之主動元件、或如電阻、電容、電感之被動元件。
又，該電子元件24係以覆晶方式電性連接該第二基板22(或該基板單元22a)；或者，亦可以打線方式電性連接該第二基板22(或該基板單元22a)。
另外，該封裝膠體25係填充滿該第二基板22與該第一基板21之間的空間。
如第2E及2E’圖所示，進行切單製程，並移除該承載件29。
於本實施例中，該切單製程係沿該間隔部22b作為切割路徑，以移除部分該間隔部22b，使該清理孔220成為缺口260，該基板單元22a與保留的部分該間隔部22b’係成為位於該第一基板21上方之另一基板26。
再者，該缺口260,260’之形狀係依清理孔220,220’ 之形狀而定，例如，第2E’圖之彎折形缺口260係依第2B圖之十字形清理孔220、或第2E”圖之弧形缺口260’係依第2B’圖之圓形清理孔220’。因此，該缺口可為彎折形、弧形、直線形或多邊形。
另外，於其它實施例中，亦可以一併移除全部該間隔部22b與清理孔220,220’。
本發明之製法係藉由該些清理孔220,220’之設計以分散熱應力，因而於覆晶結合及形成封裝膠體25時，能避免該第一基板21與第二基板22發生翹曲現象，故能減少該些支撐元件23與第一基板21或第二基板22間的界面之脹縮拉扯，以避免該些支撐元件23發生斷裂而導致短路之問題。
本發明亦提供一種基板(如第2B圖所示之第二基板22)，係包括：複數基板單元22a、以及間隔部22b。
所述之間隔部22b係位於各該基板單元22a之間，以連結各該基板單元22a，且該間隔部22b上具有至少一貫通之清理孔220,220’。
於一實施例中，該清理孔220,220’係為十字形、圓形、條狀或多邊形。
於一實施例中，該間隔部22b係為切割路徑。
本發明復提供一種封裝結構(如第2D圖所示之第二封裝結構2b)，其包括：第二基板22、以及設於該第二基板22上之電子元件24。
所述之第二基板22係包含複數基板單元22a、及位於 各該基板單元22a之間以連結各該基板單元22a的間隔部22b，且該間隔部22b上具有至少一貫通之清理孔220,220’。
於一實施例中，該清理孔220,220’係為十字形、圓形、條狀或多邊形。
於一實施例中，該間隔部22b係為切割路徑。
於一實施例中，該電子元件24係為半導體元件。
本發明另提供一種半導體封裝件2，如第2E圖所示，其包括：相疊之第一基板21與另一基板26(可視為第二基板)、以及設於該第一基板21與另一基板26之間的封裝膠體25。
所述之第一基板21上具有至少一半導體元件20。
所述之基板26係藉由複數支撐元件23疊設於該第一基板21上，且該基板26之邊緣具有至少一缺口260,260’，而該缺口260,260’係為彎折形、弧形、直線形或多邊形。
於一實施例中，所述之封裝膠體25係填充滿該基板26與該第一基板21之間的空間S。
於一實施例中，該支撐元件23係為導電元件，例如，該導電元件係含有銲錫材料與助銲劑。
於一實施例中，該半導體封裝件2復包括至少一電子元件24，係設於該基板26上。
綜上所述，本發明之半導體封裝件及其製法與基板暨封裝結構中，主要藉由該些清理孔能使液體流至該第一與 第二基板之間的空間，以於進行該清理作業時，液體能將助銲劑移除，故於清理作業結束後，助銲劑不會殘留於該第一基板上方。
再者，藉由該些清理孔能分散熱應力，以避免該第一基板與第二基板發生翹曲現象，故能避免該些支撐元件發生斷裂之問題。
上述該些實施樣態僅例示性說明本發明之功效，而非用於限制本發明，任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述該些實施態樣進行修飾與改變。此外，在上述該些實施態樣中之元件的數量僅為例示性說明，亦非用於限制本發明。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
22’‧‧‧基板區塊
22a‧‧‧基板單元
220‧‧‧清理孔

Claims (32)

  1. 一種半導體封裝件之製法，係包括：提供第一基板；藉由複數支撐元件置放第二基板於該第一基板上，且該第二基板具有至少一貫通之清理孔；以及進行清理作業，以藉由該清理孔清理該第二基板與該第一基板之間的空間。
  2. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該第一基板上具有至少一半導體元件。
  3. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該第二基板係包含複數基板單元，且該清理孔係位於該基板單元之邊緣。
  4. 如申請專利範圍第1項所述之半導體封裝件之製法，復包括間隔部，係位於各該基板單元之間，以連結各該基板單元。
  5. 如申請專利範圍第4項所述之半導體封裝件之製法，其中，該間隔部係為切割路徑。
  6. 如申請專利範圍第4項所述之半導體封裝件之製法，其中，該清理孔係位於該間隔部。
  7. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該清理孔係為十字形、圓形、條狀或多邊形。
  8. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該支撐元件係為導電元件。
  9. 如申請專利範圍第8項所述之半導體封裝件之製法， 其中，該導電元件係含有銲錫材料。
  10. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，該導電元件係含有助銲劑。
  11. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該清理作業復清理該支撐元件。
  12. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該清理作業係藉由液體進行清理。
  13. 如申請專利範圍第12項所述之半導體封裝件之製法，其中，該液體係為水。
  14. 如申請專利範圍第1項所述之半導體封裝件之製法，復包括設置至少一電子元件於該第二基板上。
  15. 如申請專利範圍第1項所述之半導體封裝件之製法，復包括形成封裝膠體於該第二基板與該第一基板之間。
  16. 如申請專利範圍第15項所述之半導體封裝件之製法，其中，該封裝膠體係填充滿該第二基板與該第一基板之間的空間。
  17. 一種基板，係包括：複數基板單元；以及間隔部，係位於各該基板單元之間，以連結各該基板單元，且該間隔部上具有至少一貫通之清理孔。
  18. 如申請專利範圍第17項所述之基板，其中，該間隔部係為切割路徑。
  19. 如申請專利範圍第17項所述之基板，其中，該清理孔 係為十字形、圓形、條狀或多邊形。
  20. 一種封裝結構，係包括：基板，係包含複數基板單元及位於各該基板單元之間以連結各該基板單元的間隔部，該間隔部上具有至少一貫通之清理孔；以及電子元件，係設於該基板上。
  21. 如申請專利範圍第20項所述之封裝結構，其中，該間隔部係為切割路徑。
  22. 如申請專利範圍第20項所述之封裝結構，其中，該清理孔係為十字形、圓形、條狀或多邊形。
  23. 如申請專利範圍第20項所述之封裝結構，其中，該電子元件係為半導體元件。
  24. 一種半導體封裝件，係包括：第一基板；以及第二基板，係藉由複數支撐元件設於該第一基板上，且該第二基板之邊緣具有至少一缺口。
  25. 如申請專利範圍第24項所述之半導體封裝件，其中，該第一基板上具有至少一半導體元件。
  26. 如申請專利範圍第24項所述之半導體封裝件，其中，該缺口係為彎折形、弧形、直線形或多邊形。
  27. 如申請專利範圍第24項所述之半導體封裝件，其中，該支撐元件係為導電元件。
  28. 如申請專利範圍第27項所述之半導體封裝件，其中，該導電元件係含有銲錫材料。
  29. 如申請專利範圍第28項所述之半導體封裝件，其中，該導電元件係含有助銲劑。
  30. 如申請專利範圍第24項所述之半導體封裝件，復包括設置至少一電子元件於該第二基板上。
  31. 如申請專利範圍第24項所述之半導體封裝件，復包括形成封裝膠體於該第二基板與該第一基板之間。
  32. 如申請專利範圍第31項所述之半導體封裝件，其中，該封裝膠體係填充滿該第二基板與該第一基板之間的空間。
TW102140073A 2013-11-05 2013-11-05 半導體封裝件及其製法與基板暨封裝結構 TW201519402A (zh)

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