CN1459854A - 增加封装体可靠性的焊垫结构 - Google Patents

增加封装体可靠性的焊垫结构 Download PDF

Info

Publication number
CN1459854A
CN1459854A CN03100349A CN03100349A CN1459854A CN 1459854 A CN1459854 A CN 1459854A CN 03100349 A CN03100349 A CN 03100349A CN 03100349 A CN03100349 A CN 03100349A CN 1459854 A CN1459854 A CN 1459854A
Authority
CN
China
Prior art keywords
substrate
welding pad
pad structure
presumptive area
welding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN03100349A
Other languages
English (en)
Other versions
CN1242472C (zh
Inventor
陈国明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Publication of CN1459854A publication Critical patent/CN1459854A/zh
Application granted granted Critical
Publication of CN1242472C publication Critical patent/CN1242472C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0613Square or rectangular array
    • H01L2224/06131Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0613Square or rectangular array
    • H01L2224/06134Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0614Circular array, i.e. array with radial symmetry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/06179Corner adaptations, i.e. disposition of the bonding areas at the corners of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81192Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/094Array of pads or lands differing from one another, e.g. in size, pitch or thickness; Using different connections on the pads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/09418Special orientation of pads, lands or terminals of component, e.g. radial or polygonal orientation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04Soldering or other types of metallurgic bonding
    • H05K2203/0465Shape of solder, e.g. differing from spherical shape, different shapes due to different solder pads
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

一种增加封装体可靠性的焊垫结构,该封装体包含有一基板或/及晶片,该焊垫结构包含有复数个第一焊垫设于该基板或/及晶片表面,以及至少一第二焊垫设于该基板或/及晶片表面的一预定区域;其中各该第一焊垫具有一第一直径,且该第二焊垫具有一大于该第一直径的第二直径,因此该第二焊垫可以在该基板或/及晶片承受较大的热应力;由于本发明于基板或/及晶片的高应力区域设置具有较大尺寸的焊垫,且这些具有较大尺寸的焊垫可以承受较强的机械强度并且提供较佳的抗热应力能力,因此本发明封装体焊垫结构可以有效改善整个封装体的可靠性;另,本发明利用焊垫制程中光阻图案的开口大小来控制基板或/及晶片上的焊垫尺寸,因此不需增加额外的制程及设备或变更原有制程,即可达到改善封装体可靠性的目的。

Description

增加封装体可靠性的焊垫结构
技术领域
本发明关于一种封装体的焊垫结构(solder pad),特别是一种增加封装体可靠性的焊垫结构。
背景技术
在现今的半导体封装技术中,高效率电子元件通常都利用焊锡球(solderballs)或是焊锡凸块(solder bumps)来达到彼此之间电性和机械性连接的目的。举例来说,超大型集成电路(very large scale integration,VLSI)便是利用焊锡球或是焊锡凸块而与一电路板(circuit board)或其他次级的封装基底(packaging substrate)相连接。这种连接技术称为覆晶接合(flip-chip,FC)。覆晶接合属于面积阵列式(area array)的接合,因此能应用于极高密度的构装连线制程。简单来说,覆晶接合的观念先在IC晶片的焊垫上长成焊锡凸块,然后再将IC晶片置放到构装基板上并完成接垫对位后,并以回焊(reflow)热处理配合焊锡熔融时的表面张力效应使焊锡成球,进而完成IC晶片与构装基板的接合。这种方式不仅可突破传统打线技术的数目限制,适合多脚数元件封装,而且电性效能也因具有较短的内连线(connection pass)而大幅提升。
请参考图1,图1为习知一封装体结构示意图。如图1所示,一封装体10包含有一晶片12与一基板18,晶片12上包含有复数个凸块焊垫14分别连接至复数个相对应的凸块结构(solder bump)16,并且经由凸块结构16连接至基板18表面。晶片12与基板18之间设有一底部密封层(underfilllayer)20,用来填满晶片12与基板18之间的空隙,以使晶片12与基板18紧密结合。
在习知封装技术中,基板18可由塑胶(有机)或陶瓷等材料构成,其中陶瓷基板的价格昂贵,且来源有限,因此相对具有价格低廉、来源取得容易等优点的塑胶基板即成为封装材料的主流。然而使用塑胶基板却也使得封装体经常遭遇到热应力不均匀的问题,举例来说,晶片12的热膨胀系数约为2.7ppm/℃,而塑胶基板18的热膨胀系数约为17ppm/℃,因此当外界环境的温度发生变化时,晶片12与塑胶基板18即可能因为热膨胀系数不匹配而导致封装体结构变形,甚至导致产品失效。
请参考图2A与图2B,图2A与图2B为封装体因外界温度变化而产生的形变结果示意图。如图2A所示,当外界温度上升时,由于塑胶基板18的热膨胀系数大于晶片12的热膨胀系数,因此封装体10可能因塑胶基板18过度膨胀而造成结构向上弯曲。相反地,如图2B所示,当外界温度下降时,由于塑胶基板18收缩程度大于晶片12,因此可能造成封装体10结构向下弯曲。值得注意的是,由于晶片12边缘区域为一高应力区域,因此在温度变化时会较晶片12中心区域产生严重形变,甚至使封装体结构产生裂缝(crack)等缺陷。
为了避免封装体因热应力而产生形变,习知方法改变连接晶片12与基板18的凸块焊垫(solder bump pad)14的设置位置,亦即利用凸块16位置来调整晶片12以及基板18承受应力的分布情形。请参考图3与图4,图3与图4为设置于晶片表面的凸块焊垫的示意图。一般而言,凸块焊垫以一矩阵排列方式设置于晶片上,为说明凸块焊垫设置位置与晶片承受应力的关系,在图3与图4中均仅显示设于晶片表面高应力区域(矩阵边缘)的凸块焊垫结构。如图3所示,晶片12上的凸块焊垫14以一矩型排列方式设置于晶片12上,当外界温度发生变化时,最大的热应力通常是产生离晶片12中心点最远处的位置(maximum distance to neutral point,max DNP),例如晶片12的四个角落上的凸块焊垫22的位置上即承受较大的热应力,因此凸块焊垫22的位置是封装体内最容易产生裂缝(crack)的部位。如图4所示,习知解决上述问题的方法是直接将承受较大热应力的凸块焊垫22移除,亦即避免在晶片12的角落区域设置焊垫以及凸块等结构,此为一般所称的角落凸块设计原则(bump corner design rule)。
由于习知方法仅移除设于晶片12四个角落的凸块焊垫14,晶片12上其他高应力区域的凸块焊垫14并未加以去除,例如图4所示的凸块焊垫24仍须承受较大的热应力,因此随着晶片12尺寸愈大,上述方法根本无法有效改善热应力所衍生的问题,进而使得封装体的可靠性大为降低。
发明内容
本发明的目的是提供一种封装体焊垫结构,以改善封装体的可靠性。
依据本发明的目的,该封装体包含有一基板或/及晶片,该焊垫结构包含有复数个第一焊垫设于该基板或/及晶片表面,以及至少一第二焊垫设于该基板或/及晶片表面的一预定区域。其中各该第一焊垫具有一第一直径,且该第二焊垫具有一大于该第一直径的第二直径,因此该第二焊垫可以在该基板或/及晶片进行一热制程时承受较大的热应力以及拥有较佳的可靠性。
由于本发明于基板或/及晶片的高应力区域设置具有较大尺寸的焊垫,且这些具有较大尺寸的焊垫可以承受较强的机械强度并且提供较佳的抗热应力能力,因此本发明封装体焊垫结构可以有效改善整个封装体的可靠性。此外,本发明利用焊垫制程中光阻图案的开口大小来控制基板或/及晶片上的焊垫尺寸,因此并不需要增加额外的制程及设备或变更原有制程,即可达到改善封装体可靠性的目的。
附图说明
图1为习知一封装体的结构示意图;
图2A与图2B为习知封装体结构因外界温度变化而产生的形变结果示意图;
图3与图4为习知焊垫结构的示意图;
图5为本发明的第一实施例的焊垫结构示意图;
图6为本发明的第二实施例的焊垫结构示意图;
图7为本发明的第三实施例的焊垫结构示意图;
图8为本发明的第四实施例的焊垫结构示意图;
图9为本发明的第五实施例的焊垫结构示意图;
图10为本发明的第六实施例的焊垫结构示意图;
图11为本发明的第七实施例的焊垫结构示意图;
图12为本发明一封装体结构示意图。
图示的符号说明:
10封装体         12晶片        14凸块焊垫    16凸块结构
18基板或/及晶片  20底部密封层  22凸块焊垫    24凸块焊垫
30基板或/及晶片  32第一焊垫    34第二焊垫    40封装体
42晶片           44基板        46印刷电路板  48第一表面
50第二表面       52凸块焊垫    54凸块结构
56底部密封层     58锡球焊垫    60锡球结构
具体实施方式
请参考图5至图11,图5至图11为本发明焊垫结构的实施例。本发明的特点是于一基板或/及晶片的高应力区域设置具有较大尺寸的焊垫,以使封装体高应力区域可以承受较强的机械强度并且提供较佳的抗热应力能力。如图5所示的第一实施例,一基板或/及晶片30的表面上设有复数个第一焊垫32以及复数个第二焊垫34。其中,第一焊垫32以阵列排列的方式设于基板或/及晶片30的中心区域,具有较大直径的第二焊垫34则是设在第一焊垫32所排成阵列的角落区域。为了确保封装体于焊接过程的可靠性,所有第一焊垫32与第二焊垫34应具有相同或近似高度。
请参考图6,图6为本发明的第二实施例的焊垫结构示意图。如图6所示,一基板或/及晶片30的表面上设有复数个第一焊垫32以及复数个第二焊垫34。其中,第一焊垫32以阵列排列的方式设于基板30的中心区域,而具有较大直径的第二焊垫34则是设在第一焊垫32所排成阵列的角落区域,包括阵列的四个顶点位置以及顶点周围位置。为了确保封装体于焊接过程的可靠性,所有第一焊垫32与第二焊垫34应具有相同或近似高度。
请参考图7,图7为本发明的第三实施例的焊垫结构示意图。如图7所示,一基板或/及晶片30的表面上设有复数个第一焊垫32以及复数个第二焊垫34。其中,第一焊垫32以阵列排列的方式设于基板或/及晶片30的中心区域,而具有较大直径的第二焊垫34则是设在第一焊垫32所排成阵列的角落区域,例如使第二焊垫34设于第一焊垫32所排成阵列的四个顶点周围位置,而阵列的四个顶点位置上则没有设置任何焊垫。为了确保封装体于焊接过程的可靠性,所有第一焊垫32与第二焊垫34应具有相同或近似高度。
请参考图8,图8为本发明的第四实施例的焊垫结构示意图。如图8所示,一基板或/及晶片30的表面上设有复数个第一焊垫32以及复数个第二焊垫34。其中,第一焊垫32设置于基板或/及晶片30的四个侧边而形成一矩形排列,而具有较大直径的第二焊垫34则是设在第一焊垫32所排成的矩形的四个顶点上。为了确保封装体于焊接过程的可靠性,所有第一焊垫32与第二焊垫34应具有相同或近似高度。
请参考图9,图9为本发明的第五实施例的焊垫结构示意图。如图9所示,一基板或/及晶片30的表面上设有复数个第一焊垫32以及复数个第二焊垫34。其中,第一焊垫32设置于基板或/及晶片30的四个侧边而形成一矩形排列,而第二焊垫34则是设在第一焊垫32所排成的矩形的角落区域,例如使第二焊垫34设于第一焊垫32所排成矩形的四个顶点周围位置,而矩形的四个顶点位置上则没有设置任何焊垫。为了确保封装体于焊接过程的可靠性,所有第一焊垫32与第二焊垫34应具有相同或近似高度。
由于在理想状况下,若以基板或/及晶片中心为圆心,则设于同一同心圆的圆周上的焊垫结构应承受约略相等的热应力,因此本发明亦根据此一应力分布来设置具有不同尺寸的焊垫结构。请参考图10,图10为本发明的第六实施例的焊垫结构示意图。如图10所示,一基板或/及晶片30的表面上设有复数个第一焊垫32以及复数个第二焊垫34。其中,第一焊垫32设于基板或/及晶片30中心区域的复数个同心圆的圆周上,而具有较大直径的第二焊垫34则是设基板或/及晶片32上离基板或/及晶片中心点最远的高应力区域,亦即使第二焊垫34设于基板或/及晶片30上最大圆的圆周上。为了确保封装体于焊接过程的可靠性,所有第一焊垫32与第二焊垫34应具有相同或近似高度。
请参考图11,图11为本发明的第七实施例的焊垫结构示意图。如图11所示,一基板或/及晶片30的表面上设有复数个第一焊垫32以及复数个第二焊垫34。其中,第一焊垫32设于基板或/及晶片30中心区域的复数个同心圆的圆周上,而具有较大直径的第二焊垫34则是设在第一焊垫32所排成同心圆外侧的角落区域。为了确保封装体于焊接过程的可靠性,所有第一焊垫32与第二焊垫34应具有相同或近似高度。
由于本发明焊垫结构不仅适用于覆晶封装结构,更可适用锡球阵列封装(ball grid array,BGA)结构,因此在本发明所有实施例中,基板30可以是一半导体晶片,第一焊垫32与第二焊垫34则为凸块焊垫,用来使半导体晶片连接至其他塑胶或陶瓷基板上。此外,基板30亦可以是一塑胶基板、一陶瓷基板或一印刷电路板,第一焊垫32与第二焊垫34则为锡球焊垫(solder ball pad),用来使上述基板连接至其他晶片或基板上。
请参考图12,图12为本发明一封装体结构示意图。如图12所示,一封装体40由一晶片42、一基板44与一印刷电路板(printed circuit board,PCB)46所构成,且晶片42与基板44之间另设有一底部密封层56,以填满晶片42与基板44之间的空隙。基板44为一塑胶基板或陶瓷基板,其一第一表面上设有复数个凸块焊垫52,且各个凸块焊垫52分别连接至一凸块结构54,以经由凸块结构54连接至晶片42的表面。基板44的第二表面50上设有复数个锡球焊垫58,且各个锡球焊垫58分别连接至一锡球结构60,以经由锡球结构60连接至印刷电路板46的表面。值得注意的是,为了使整个封装体具有较佳的抗热应力与抗疲劳能力,凸块焊垫52或锡球焊垫58应包含至少两种尺寸大小,以利用具有较大尺寸的凸块焊垫52或锡球焊垫58来抑制高应力的影响。至于具有不同尺寸大小的凸块焊垫52或锡球焊垫58在基板44上的排列方式则可参考本发明第一实施例至第七实施例的排列方式。
此外,在图12所示的封装体40中,凸块焊垫52亦可以设在晶片42的表面上,然后利用各个凸块焊垫52分别连接至一凸块结构54,并经由凸块结构54连接至基板44的表面。相同地,锡球焊垫58也可设置在印刷电路板46的表面上,且各个锡球焊垫58分别连接至一锡球结构60,并经由锡球结构60连接至基板44的表面。
相较于习知技术,本发明将基板边缘的预定区域的焊垫尺寸增大,由于大尺寸的焊垫具有较强的机械强度与较佳的抗热应力能力,因此通过增大基板边缘的焊垫尺寸,可以增强封装体对热应力的抵抗能力,以改善封装体的可靠性。此外,本发明利用焊垫制程中光阻图案的开口大小来控制基板上的焊垫尺寸,因此并不需要增加额外的制程或变更原有制程,即可达到改善封装体可靠性的目的。
以上所述仅为本发明的较佳实施例,凡依本发明申请专利范围所做的均等变化与修饰,皆应属本发明专利的涵盖范围。

Claims (34)

1.一种增加封装体可靠性的焊垫结构,该封装体包含有一基板,其特征是:该焊垫结构包含有:
复数个第一焊垫设于该基板表面,且各该第一焊垫具有一第一直径;以及
至少一第二焊垫设于该基板表面的一预定区域,该第二焊垫具有一大于该第一直径的第二直径以在该基板上承受较大的热应力及疲劳强度。
2.如权利要求1所述的焊垫结构,其特征是:该基板为一塑胶基板。
3.如权利要求1所述的焊垫结构,其特征是:该基板为一陶瓷基板。
4.如权利要求1所述的焊垫结构,其特征是:该基板为一印刷电路板。
5.如权利要求1所述的焊垫结构,其特征是:该基板为一晶片。
6.如权利要求1所述的焊垫结构,其特征是:该预定区域为一高应力区域。
7.如权利要求1所述的焊垫结构,其特征是:各该第一焊垫以阵列排列的方式设于该基板的中心区域。
8.如权利要求1所述的焊垫结构,其特征是:该预定区域设于该基板表面的角落区域。
9.如权利要求1所述的焊垫结构,其特征是:该预定区域设于该基板表面的复数个同心圆的各圆周上。
10.如权利要求9所述的焊垫结构,其特征是:各该同心圆上的各该第二焊垫依等间距设于各该相对应的圆周上。
11.如权利要求1所述的焊垫结构,其特征是:该预定区域设于该基板表面的最大圆外部的该基板表面的角落区域。
12.如权利要求1所述的焊垫结构,其特征是:该预定区域设于该基板表面的最大圆的圆周上。
13.如权利要求1所述的焊垫结构,其特征是:该预定区域另包含至少一接地焊垫。
14.如权利要求1所述的焊垫结构,其特征是:各该第一焊垫以及该第二焊垫均为一凸块焊垫,且各该凸块焊垫分别连接至一凸块结构并经由该凸块结构连接至一晶片表面。
15.如权利要求14所述的焊垫结构,其特征是:该晶片与该基板之间另设有一底部密封层,以填满该晶片与该基板之间的空隙。
16.如权利要求1所述的焊垫结构,其特征是:各该第一焊垫以及该第二焊垫均为一锡球焊垫,且各该锡球焊垫分别连接至一锡球结构并经由该锡球结构连接至一印刷电路板表面。
17.一种焊垫结构,其特征是:包含有:
一基板;
复数个第一凸块焊垫设于该基板的一第一表面,且各该第一凸块焊垫均具有一第一直径;
至少一第二凸块焊垫设于该第一表面的一第一预定区域,且该第二凸块焊垫具有一大于该第一直径的第二直径;
复数个第一锡球焊垫设于该基板的一第二表面,且各该锡球焊垫均具有一第三直径;以及
至少一第二锡球焊垫设于该第二表面的一第二预定区域,且该第二锡球焊垫具有一大于该第三直径的第四直径。
18.如权利要求17所述的焊垫结构,其特征是:该基板为一塑胶基板。
19.如权利要求17所述的焊垫结构,其特征是:该基板为一陶瓷基板。
20.如权利要求17所述的焊垫结构,其特征是:该第一预定区域以及该第二预定区域均为一高应力区域。
21.如权利要求17所述的焊垫结构,其特征是:各该第一凸块焊垫以阵列排列的方式设于该基板的中心区域。
22.如权利要求17所述的焊垫结构,其特征是:该第一预定区域设于该第一表面的角落区域。
23.如权利要求17所述的焊垫结构,其特征是:该第一预定区域设于该第一表面的复数个同心圆的各圆周上。
24.如权利要求23所述的焊垫结构,其特征是:各该同心圆上的各该第二凸块焊垫依等间距设于各该相对应的圆周上。
25.如权利要求17所述的焊垫结构,其特征是:该第一预定区域设于该第一表面的最大圆外部的该第一表面的角落区域。
26.如权利要求17所述的焊垫结构,其特征是:该第一预定区域设于该第一表面的最大圆的圆周上。
27.如权利要求17所述的焊垫结构,其特征是:该第一表面为该基板上侧的表面,且各该第一凸块焊垫以及该第二凸块焊垫均分别连接至一凸块结构并经由该凸块结构连接至一晶片表面。
28.如权利要求17所述的焊垫结构,其特征是:各该第一锡球焊垫以阵列排列的方式设于该基板的中心区域。
29.如权利要求17所述的焊垫结构,其特征是:该第二预定区域设于该第二表面的角落区域。
30.如权利要求17所述的焊垫结构,其特征是:该第二预定区域设于该第二表面的复数个同心圆的各圆周上。
31.如权利要求30所述的焊垫结构,其特征是:各该同心圆上的各该第二锡球焊垫依等间距设于各该相对应的圆周上。
32.如权利要求17所述的焊垫结构,其特征是:该第二预定区域设于该第二表面的最大圆外部的该第二表面的角落区域。
33.如权利要求17所述的焊垫结构,其特征是:该第二预定区域设于该第二表面的最大圆的圆周上。
34.如权利要求17所述的焊垫结构,其特征是:该第二表面为该基板下侧的表面,且各该第一锡球焊垫以及该第二锡球焊垫均分别连接至一锡球结构并经由该锡球结构连接至一印刷电路板表面。
CNB031003494A 2002-05-21 2003-01-13 增加封装体可靠性的焊垫结构 Expired - Lifetime CN1242472C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/063,880 2002-05-21
US10/063,880 US6940176B2 (en) 2002-05-21 2002-05-21 Solder pads for improving reliability of a package

Publications (2)

Publication Number Publication Date
CN1459854A true CN1459854A (zh) 2003-12-03
CN1242472C CN1242472C (zh) 2006-02-15

Family

ID=29547827

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB031003494A Expired - Lifetime CN1242472C (zh) 2002-05-21 2003-01-13 增加封装体可靠性的焊垫结构

Country Status (2)

Country Link
US (1) US6940176B2 (zh)
CN (1) CN1242472C (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102208386A (zh) * 2010-03-29 2011-10-05 广达电脑股份有限公司 具有球形焊点的集成电路封装元件
CN104655885A (zh) * 2013-11-15 2015-05-27 本田技研工业株式会社 电流施加装置以及半导体元件的制造方法
CN104681518A (zh) * 2013-12-03 2015-06-03 英飞凌科技股份有限公司 集成ic封装
CN104777335A (zh) * 2014-01-09 2015-07-15 本田技研工业株式会社 电流施加装置以及半导体元件的制造方法
TWI611577B (zh) * 2016-03-04 2018-01-11 矽品精密工業股份有限公司 電子封裝件及半導體基板
CN109952650A (zh) * 2016-11-21 2019-06-28 奥林巴斯株式会社 摄像模块以及内窥镜
CN114664747A (zh) * 2020-12-31 2022-06-24 华为技术有限公司 板级结构及通信设备

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4083638B2 (ja) * 2003-07-30 2008-04-30 東北パイオニア株式会社 フレキシブル配線基板、半導体チップ実装フレキシブル配線基板、表示装置、半導体チップ実装方法
TW200536071A (en) * 2004-04-20 2005-11-01 Advanced Semiconductor Eng Carrier, chip package structure, and circuit board package structure
JP2007059581A (ja) * 2005-08-24 2007-03-08 Konica Minolta Opto Inc 固体撮像装置及びカメラモジュール
WO2007086551A1 (ja) * 2006-01-27 2007-08-02 Ibiden Co., Ltd. プリント配線板及びプリント配線板の製造方法
US20080280393A1 (en) * 2007-05-09 2008-11-13 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for forming package structures
JP2009049499A (ja) * 2007-08-14 2009-03-05 Fujifilm Corp 半導体チップの実装方法及び半導体装置
US8344505B2 (en) * 2007-08-29 2013-01-01 Ati Technologies Ulc Wafer level packaging of semiconductor chips
JP2009182104A (ja) * 2008-01-30 2009-08-13 Toshiba Corp 半導体パッケージ
US8624391B2 (en) * 2009-10-08 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Chip design with robust corner bumps
JP5539077B2 (ja) * 2010-07-09 2014-07-02 ローム株式会社 半導体装置
US8415792B2 (en) 2010-08-04 2013-04-09 International Business Machines Corporation Electrical contact alignment posts
US20120267779A1 (en) 2011-04-25 2012-10-25 Mediatek Inc. Semiconductor package
JP6091053B2 (ja) * 2011-09-14 2017-03-08 キヤノン株式会社 半導体装置、プリント回路板及び電子製品
CN103596352B (zh) * 2012-08-15 2018-02-06 江苏润阳物流器械科技有限公司 软性电路板装置及相机模组
US8970051B2 (en) * 2013-06-28 2015-03-03 Intel Corporation Solution to deal with die warpage during 3D die-to-die stacking
US10510652B2 (en) * 2016-08-15 2019-12-17 Taiwan Semiconductor Manufacturing Company Ltd. Method of manufacturing semiconductor device
US9466578B2 (en) 2013-12-20 2016-10-11 Qualcomm Incorporated Substrate comprising improved via pad placement in bump area
US9576926B2 (en) 2014-01-16 2017-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structure design in fan-out package
KR102154830B1 (ko) 2014-08-05 2020-09-11 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9679830B2 (en) * 2014-10-31 2017-06-13 Mediatek Inc. Semiconductor package
US10497660B2 (en) 2015-02-26 2019-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices
KR102479999B1 (ko) * 2015-09-11 2022-12-22 삼성전자주식회사 패키지 기판
US9972607B2 (en) 2016-08-08 2018-05-15 Semiconductor Components Industries, Llc Semiconductor device and method of integrating power module with interposer and opposing substrates
DE102019111085A1 (de) * 2018-11-27 2020-05-28 Taiwan Semiconductor Manufacturing Co., Ltd. Abschirmstrukturen
JP7056620B2 (ja) * 2019-03-28 2022-04-19 株式会社デンソー 電子装置
US12021048B2 (en) * 2021-08-30 2024-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5153379A (en) * 1990-10-09 1992-10-06 Motorola, Inc. Shielded low-profile electronic component assembly
US5216278A (en) * 1990-12-04 1993-06-01 Motorola, Inc. Semiconductor device having a pad array carrier package
JP3226244B2 (ja) 1993-12-03 2001-11-05 株式会社東芝 樹脂封止型半導体装置
JPH07307410A (ja) * 1994-05-16 1995-11-21 Hitachi Ltd 半導体装置
US5741729A (en) * 1994-07-11 1998-04-21 Sun Microsystems, Inc. Ball grid array package for an integrated circuit
US6121689A (en) * 1997-07-21 2000-09-19 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US6008534A (en) * 1998-01-14 1999-12-28 Lsi Logic Corporation Integrated circuit package having signal traces interposed between power and ground conductors in order to form stripline transmission lines
JP2000100851A (ja) * 1998-09-25 2000-04-07 Sony Corp 半導体部品及びその製造方法、半導体部品の実装構造及びその実装方法
JP3437107B2 (ja) * 1999-01-27 2003-08-18 シャープ株式会社 樹脂封止型半導体装置
US6444563B1 (en) * 1999-02-22 2002-09-03 Motorlla, Inc. Method and apparatus for extending fatigue life of solder joints in a semiconductor device
JP2000260912A (ja) * 1999-03-05 2000-09-22 Fujitsu Ltd 半導体装置の実装構造及び半導体装置の実装方法
US6365978B1 (en) * 1999-04-02 2002-04-02 Texas Instruments Incorporated Electrical redundancy for improved mechanical reliability in ball grid array packages
JP2001257289A (ja) * 2000-03-10 2001-09-21 Mitsubishi Electric Corp 半導体パッケージ、半導体装置並びに半導体装置の製造方法
JP2001319997A (ja) 2000-05-10 2001-11-16 Mitsubishi Electric Corp 半導体パッケージおよび半導体チップ
US6350669B1 (en) * 2000-10-30 2002-02-26 Siliconware Precision Industries Co., Ltd. Method of bonding ball grid array package to circuit board without causing package collapse

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102208386A (zh) * 2010-03-29 2011-10-05 广达电脑股份有限公司 具有球形焊点的集成电路封装元件
CN104655885A (zh) * 2013-11-15 2015-05-27 本田技研工业株式会社 电流施加装置以及半导体元件的制造方法
CN104681518A (zh) * 2013-12-03 2015-06-03 英飞凌科技股份有限公司 集成ic封装
CN104681518B (zh) * 2013-12-03 2018-05-04 英飞凌科技股份有限公司 集成ic封装
CN104777335A (zh) * 2014-01-09 2015-07-15 本田技研工业株式会社 电流施加装置以及半导体元件的制造方法
CN104777335B (zh) * 2014-01-09 2017-10-13 本田技研工业株式会社 电流施加装置以及半导体元件的制造方法
TWI611577B (zh) * 2016-03-04 2018-01-11 矽品精密工業股份有限公司 電子封裝件及半導體基板
CN109952650A (zh) * 2016-11-21 2019-06-28 奥林巴斯株式会社 摄像模块以及内窥镜
CN109952650B (zh) * 2016-11-21 2023-08-08 奥林巴斯株式会社 摄像模块以及内窥镜
CN114664747A (zh) * 2020-12-31 2022-06-24 华为技术有限公司 板级结构及通信设备
CN114664747B (zh) * 2020-12-31 2023-02-03 华为技术有限公司 板级结构及通信设备

Also Published As

Publication number Publication date
CN1242472C (zh) 2006-02-15
US20030218243A1 (en) 2003-11-27
US6940176B2 (en) 2005-09-06

Similar Documents

Publication Publication Date Title
CN1242472C (zh) 增加封装体可靠性的焊垫结构
US5796169A (en) Structurally reinforced ball grid array semiconductor package and systems
TW586199B (en) Flip-chip package
KR100632198B1 (ko) 반도체 디바이스에서 솔더 접합들의 피로 수명을 연장하는방법 및 장치
US6969636B1 (en) Semiconductor package with stress inhibiting intermediate mounting substrate
US7446398B2 (en) Bump pattern design for flip chip semiconductor package
US6475830B1 (en) Flip chip and packaged memory module
US6552267B2 (en) Microelectronic assembly with stiffening member
WO2004034434A2 (en) Components, methods and assemblies for multi-chip packages
KR20020065045A (ko) 확장 패드들을 포함하는 반도체 칩 패키지
US20070165388A1 (en) Interconnection pattern design
TWI544584B (zh) Copper substrate with barrier structure and manufacturing method thereof
CN103871990A (zh) 封装结构及封装方法
US6943060B1 (en) Method for fabricating integrated circuit package with solder bumps
TW201316462A (zh) 封裝件及其製法
CN1168617A (zh) 塑性网格焊球阵列组件
JP2004253544A (ja) 半導体装置の製造方法
US7601612B1 (en) Method for forming solder joints for a flip chip assembly
KR20110124579A (ko) 유. 브이 레이저를 사용한 플립 칩 본딩방법
TWI430421B (zh) 覆晶接合方法
WO2023246418A1 (zh) 电路板组件、电子设备及电路板组件的制作方法
TW540144B (en) Solder pads for improving the reliability of a semiconductor package
TWI735398B (zh) 電子封裝件及其製法
US11031343B2 (en) Fins for enhanced die communication
KR100473015B1 (ko) 전자장치패키지

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20060215