US20030218243A1 - Solder pads for improving reliability of a package - Google Patents

Solder pads for improving reliability of a package Download PDF

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Publication number
US20030218243A1
US20030218243A1 US10/063,880 US6388002A US2003218243A1 US 20030218243 A1 US20030218243 A1 US 20030218243A1 US 6388002 A US6388002 A US 6388002A US 2003218243 A1 US2003218243 A1 US 2003218243A1
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Prior art keywords
solder
pads
substrate
solder pads
predetermined region
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US10/063,880
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US6940176B2 (en
Inventor
Kuo-Ming Chen
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United Microelectronics Corp
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United Microelectronics Corp
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Assigned to UNITED MICROELECTRONICS CORP. reassignment UNITED MICROELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, KUO-MING
Priority to CNB031003494A priority patent/CN1242472C/en
Publication of US20030218243A1 publication Critical patent/US20030218243A1/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch, thickness; Using different connections on the pads
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K2201/09418—Special orientation of pads, lands or terminals of component, e.g. radial or polygonal orientation
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/0465—Shape of solder, e.g. differing from spherical shape, different shapes due to different solder pads
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to solder pads of a package, and more particularly, to solder pads for improving reliability of a package.
  • High performance microelectronic devices often use solder balls or solder bumps for electrically and mechanically interconnection to other microelectronic devices.
  • a very large scale integration (VLSI) chip may be connected to a circuit board or other next level packaging substrate by using solder balls or solder bumps.
  • This connection technology is also referred to as “flip chip” technology.
  • the flip chip technology is an area array connection technology and includes reflowing a body of solder onto a bond pad to form a solder bump, so as to electrically connect an IC die to a packaging board.
  • the flip chip can break through limitations of traditional wire bonding, and the electrical performance is effectively improved due to a shorter connection pass.
  • FIG. 1 is a schematic diagram of a prior art package.
  • a package 10 comprises a chip 12 and a substrate 18 .
  • the chip comprises a plurality of solder bump pads respectively connecting to the corresponding solder bumps 16 .
  • the solder bump pads 14 connect to the substrate 18 by using the solder bumps 16 .
  • an underfill layer 20 is filled in a gap between the chip 12 and the substrate 18 for tightly connecting the chip 12 with the substrate 18 .
  • the substrate 18 comprises a plastic (organic) substrate or a ceramic substrate.
  • a price of the ceramic substrate is high and a source of the ceramic substrate is limited, so that the plastic substrate with a low price and plentiful sources has become a mainstream material used in packages.
  • a problem of non-uniform thermal stress always occurs in a package when using the plastic substrate.
  • a coefficient of thermal expansion of the chip 12 is approximately equal to 2.7 ppm/° C.
  • a coefficient of thermal expansion of the plastic substrate 18 is approximately equal to 17 ppm/° C. Because the chip 12 and the plastic substrate 18 have different coefficients of thermal expansion, a variation of ambient temperature deforms the package, and moreover, the products may fail.
  • FIG. 2(A) and FIG. 2(B) are a schematic diagrams for illustrating deformation of a package due to a variation of ambient temperature.
  • the coefficient of thermal expansion of the plastic substrate 18 is larger than that of the chip 12 .
  • the package 10 is bended upwards due to over expansion of the plastic substrate 18 , as shown in FIG. 2 (A).
  • the package 10 is bended downwards because the plastic substrate 18 shrinks more than the chip 12 does, as shown in FIG. 2(B).
  • a periphery region of the chip 12 is a region with high thermal stress.
  • the deformation of the periphery region is more serious than the deformation of the central region of the chip 12 , which further leads to forming cracks in the package.
  • FIG. 3 and FIG. 4 are schematic diagrams of the solder bump pads located on the surface of the chip. Generally, the solder bump pads are arranged in a matrix on the chip. For explaining the relationship between positions of the solder bump pads and the stress on the chip, FIG. 3 and FIG. 4 only show solder bump pads located on the region of the chip with high stress (i.e. periphery region). As shown in FIG.
  • the solder bump pads 14 are arranged in a matrix on the chip 12 .
  • the largest thermal stress always occurs on a position of the chip 12 with a maximum distance to neutral point (max DNP).
  • max DNP maximum distance to neutral point
  • the solder bump pads 22 located at the four corners of the chip 12 are suffered with higher thermal stress, so that the package forms cracks most easily on the positions of the solder bump pads 22 .
  • the solder bump pads 22 are directly removed to solve the above-mentioned problem according to the prior art method. That is, it is avoided to locate the solder bump pads and the solder bumps at the corners of the chip 12 , which is called a bump corner design rule.
  • the prior art method removes the solder bump pads 14 located at the four corners of the chip 12 .
  • the solder bump pads 14 on other high stress regions of the chip 12 are not removed.
  • the solder bump pads 24 shown in FIG. 4 also suffer from higher stress.
  • the above-mentioned method cannot effectively solve the thermal stress problem, and thus, reliability of the package is reduced.
  • solder pads for improving reliability of a semiconductor package are provided.
  • the package includes a substrate and/or a chip.
  • the solder pad includes a plurality of first solder pads located on a surface of the substrate and/or the chip, and at least a second solder pad located on a predetermined region of the surface of the substrate and/or the chip.
  • Each of the first solder pads has a first diameter.
  • the second solder pad has a second diameter greater than the first diameter so as to sustain a stronger thermal stress on the substrate and/or the chip.
  • solder pads with larger sizes are located on the high stress regions of substrate and/or the chip in the claimed invention.
  • the solder pads with larger sizes can sustain stronger thermal stress and mechanical strength.
  • the claimed invention provides solder pads capable of effectively improving reliability of a package.
  • the claimed invention controls the sizes of the solder pads by adjusting the sizes of the openings of the photoresist layer in the solder pad process.
  • FIG. 1 is a schematic diagram of a prior art package.
  • FIG. 2(A) and FIG. 2(B) are a schematic diagrams for illustrating deformation of a package due to a variation of ambient temperature.
  • FIG. 3 and FIG. 4 are schematic diagrams of the solder bump pads located on the surface of the chip according to the prior art.
  • FIG. 5 to FIG. 11 are schematic diagrams for illustrating the solder pads of the embodiments according to the present invention.
  • FIG. 12 is a schematic diagram of a package according to the present invention.
  • FIG. 5 to FIG. 11 are schematic diagrams for illustrating the solder pads of the embodiments according to the present invention.
  • the solder pads with larger sizes are located on the high stress regions of a substrate and/or a chip in the present invention.
  • the solder pads with larger sizes can sustain stronger thermal stress and mechanical strength.
  • FIG. 5 illustrates the solder pads of the first embodiment.
  • a plurality of first solder pads 32 and a plurality of second solder pads 34 are located on a surface of a substrate and/or a chip 30 .
  • the first solder pads 32 are arranged in a matrix at a center region of the substrate 30 .
  • the second solder pads 34 are arranged at the four vertexes of the matrix formed by the first solder pads 32 .
  • the diameter of the second solder pad 34 is larger than that of the first solder pad 32 .
  • the height of the first solder pad 32 is equal or approximately equal to that of the second solder pad 34 .
  • FIG. 6 illustrates the solder pads of the second embodiment of the present invention.
  • a plurality of first solder pads 32 and a plurality of second solder pads 34 are located on a surface of a substrate and/or a chip 30 .
  • the first solder pads 32 are arranged in a matrix at a center region of the substrate 30 .
  • the second solder pads 34 are located at the corners of the matrix formed by the first solder pads 32 .
  • the corners of the matrix include the four vertexes of the matrix and the positions around the vertexes of the matrix.
  • the diameter of the second solder pad 34 is larger than that of the first solder pad 32 .
  • the height of the first solder pad 32 is equal or approximately equal to that of the second solder pad 34 .
  • FIG. 7 illustrates the solder pads of the third embodiment of the present invention.
  • a plurality of first solder pads 32 and a plurality of second solder pads 34 are located on a surface of a substrate and/or a chip 30 .
  • the first solder pads 32 are arranged in a matrix at a center region of the substrate and/or the chip 30 .
  • the second solder pads 34 are arranged at the regions near the four vertexes of the matrix formed by the first solder pads 32 .
  • the second solder pads 34 are arranged at the positions around the four vertexes of the matrix, and no second solder pads 34 are located at the four vertexes of the matrix.
  • the diameter of the second solder pad 34 is larger than that of the first solder pad 32 .
  • the height of the first solder pad 32 is equal or approximately equal to that of the second solder pad 34 .
  • FIG. 8 illustrates the solder pads of the fourth embodiment of the present invention.
  • a plurality of first solder pads 32 and a plurality of second solder pads 34 are located on a surface of a substrate and/or a chip 30 .
  • the first solder pads 32 are located at the four sides of the substrate and/or the chip 30 and the first solder pads 32 are arranged in a rectangle.
  • the second solder pads 34 are located at the four vertexes of the rectangle formed by the first solder pads 32 .
  • the diameter of the second solder pad 34 is larger than that of the first solder pad 32 .
  • the height of the first solder pad 32 is equal or approximately equal to that of the second solder pad 34 .
  • FIG. 9 illustrates the solder pads of the fifth embodiment of the present invention.
  • a plurality of first solder pads 32 and a plurality of second solder pads 34 are located on a surface of a substrate and/or a chip 30 .
  • the first solder pads 32 are located at the four sides of the substrate and/or the chip 30 and the first solder pads 32 are arranged in a rectangle.
  • the second solder pads 34 are located at the regions near the four vertexes of the rectangle formed by the first solder pads 32 .
  • the second solder pads 34 are arranged at the positions around the four vertexes of the rectangle, and no second solder pads 34 are located at the four vertexes of the rectangle.
  • the diameter of the second solder pad 34 is larger than that of the first solder pad 32 .
  • the height of the first solder pad 32 is equal or approximately equal to that of the second solder pad 34 .
  • FIG. 10 illustrates the solder pads of the sixth embodiment of the present invention. As shown in FIG. 10, a plurality of first solder pads 32 and a plurality of second solder pads 34 are located on a surface of a substrate and/or a chip 30 . The first solder pads 32 are located at circumferences of a plurality of concentric circles.
  • the second solder pads 34 are located at a high stress region, which is farthest from the center of the substrate and/or the chip 30 . That is, the second solder pads 34 are located at the circumference of the maximum circle on the substrate 30 .
  • the diameter of the second solder pad 34 is larger than that of the first solder pad 32 .
  • the height of the first solder pad 32 is equal or approximately equal to that of the second solder pad 34 .
  • FIG. 11 illustrates the solder pads of the seventh embodiment of the present invention.
  • a plurality of first solder pads 32 and a plurality of second solder pads 34 are located on a surface of a substrate 30 .
  • the first solder pads 32 are located at circumferences of a plurality of concentric circles.
  • the second solder pads 34 are located at the corners outside the concentric circles formed by the first solder pads 32 .
  • the diameter of the second solder pad 34 is larger than that of the first solder pad 32 .
  • the height of the first solder pad 32 is equal or approximately equal to that of the second solder pad 34 .
  • the present invention can be applied not only in a flip-chip package, but also in a ball grid array (BGA) package.
  • the substrate 30 can be a semiconductor wafer, and the first solder pads 32 and the second solder pads 34 can be solder bump pads for connecting the semiconductor wafer with the plastic substrate or the ceramic substrate.
  • the substrate 30 comprises a plastic substrate, a ceramic substrate, or a printed circuit board.
  • the first solder pads 32 and the second solder pads 34 are solder ball pads for connecting the above-mentioned substrate with other chips or substrates.
  • FIG. 12 is a schematic diagram of a package according to the present invention.
  • a package 40 comprises a chip 42 , a substrate 44 , and a print circuit board 46 .
  • An underfill layer 56 is filled in a gap between the chip 42 and the substrate 44 .
  • the substrate 44 is a plastic substrate or a ceramic substrate.
  • a plurality of solder bump pads 52 is located on a first surface of the substrate 44 , and each solder bump pad 52 connects to a solder bump 54 .
  • the solder bump pads 52 connect to the chip 42 by use of the solder bumps 54 .
  • a plurality of solder ball pads 58 is located on a second surface of the substrate 44 , and each solder ball pad 58 connects to a solder ball 60 .
  • the solder ball pads 58 connect to the print circuit board 46 by use of the solder balls 60 .
  • the solder bump pads 52 or the solder ball pads 58 should have at least two different kinds of diameters.
  • the solder bump pads 52 or the solder ball pads 58 with larger sizes are used to sustain a stronger thermal stress during a thermal process.
  • the arrangement of the solder bump pads 52 or the solder ball pads 58 can refer to the first embodiment to the seventh embodiment of the present invention.
  • solder bump pads 52 can be located on a surface of the chip 42 in the package 40 shown in FIG. 12. Then, each solder bump pad 52 connects to a solder bump 54 , and uses the solder bump 54 to connect to the substrate 44 . Conversely, the solder ball pads 58 can be located on a surface of the print circuit board 46 . Each solder ball pad 58 connects to a solder ball 60 , and uses the solder ball 60 to connect to the substrate 44 .
  • the solder pads with larger sizes are located on the high stress regions of the substrate in the claimed invention.
  • the solder pads with larger sizes can sustain stronger thermal stress and mechanical strength.
  • the claimed invention provides solder pads capable of effectively improving reliability of a package.
  • the claimed invention controls the sizes of the solder pads by adjusting the sizes of the openings of the photoresist layer in the solder pad process.

Abstract

Solder pads for improving reliability of a semiconductor package are provided. The package includes a substrate and/or a chip. The solder pad includes a plurality of first solder pads located on a surface of the substrate and/or the chip, and at least a second solder pad located on a predetermined region of the surface of the substrate and/or the chip. Each of the first solder pads has a first diameter. The second solder pad has a second diameter greater than the first diameter so as to sustain a stronger thermal stress on the substrate and/or the chip.

Description

    BACKGROUND OF INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to solder pads of a package, and more particularly, to solder pads for improving reliability of a package. [0002]
  • 2. Description of the Prior Art [0003]
  • High performance microelectronic devices often use solder balls or solder bumps for electrically and mechanically interconnection to other microelectronic devices. For instance, a very large scale integration (VLSI) chip may be connected to a circuit board or other next level packaging substrate by using solder balls or solder bumps. This connection technology is also referred to as “flip chip” technology. The flip chip technology is an area array connection technology and includes reflowing a body of solder onto a bond pad to form a solder bump, so as to electrically connect an IC die to a packaging board. The flip chip can break through limitations of traditional wire bonding, and the electrical performance is effectively improved due to a shorter connection pass. [0004]
  • Please refer to FIG. 1. FIG. 1 is a schematic diagram of a prior art package. As shown in FIG. 1, a [0005] package 10 comprises a chip 12 and a substrate 18. The chip comprises a plurality of solder bump pads respectively connecting to the corresponding solder bumps 16. The solder bump pads 14 connect to the substrate 18 by using the solder bumps 16. In addition, an underfill layer 20 is filled in a gap between the chip 12 and the substrate 18 for tightly connecting the chip 12 with the substrate 18.
  • According to the prior art package technology, the [0006] substrate 18 comprises a plastic (organic) substrate or a ceramic substrate. However, a price of the ceramic substrate is high and a source of the ceramic substrate is limited, so that the plastic substrate with a low price and plentiful sources has become a mainstream material used in packages. Nevertheless, a problem of non-uniform thermal stress always occurs in a package when using the plastic substrate. For example, a coefficient of thermal expansion of the chip 12 is approximately equal to 2.7 ppm/° C., and a coefficient of thermal expansion of the plastic substrate 18 is approximately equal to 17 ppm/° C. Because the chip 12 and the plastic substrate 18 have different coefficients of thermal expansion, a variation of ambient temperature deforms the package, and moreover, the products may fail.
  • Please refer to FIG. 2(A) and FIG. 2(B). FIG. 2(A) and FIG. 2(B) are a schematic diagrams for illustrating deformation of a package due to a variation of ambient temperature. As mentioned above, the coefficient of thermal expansion of the [0007] plastic substrate 18 is larger than that of the chip 12. When ambient temperature rises, the package 10 is bended upwards due to over expansion of the plastic substrate 18, as shown in FIG. 2 (A). Conversely, when ambient temperature falls, the package 10 is bended downwards because the plastic substrate 18 shrinks more than the chip 12 does, as shown in FIG. 2(B). Noticeably, a periphery region of the chip 12 is a region with high thermal stress. As a result, the deformation of the periphery region is more serious than the deformation of the central region of the chip 12, which further leads to forming cracks in the package.
  • For preventing deformation of the package due to a thermal stress, arrangement of the [0008] solder bump pads 14 for connecting the chip 12 with the substrate 18 is changed according to the prior art method. That is, positions of the solder bumps 16 are changed to adjust stress distribution on the chip 12 and the substrate 18. Please refer to FIG. 3 and FIG. 4. FIG. 3 and FIG. 4 are schematic diagrams of the solder bump pads located on the surface of the chip. Generally, the solder bump pads are arranged in a matrix on the chip. For explaining the relationship between positions of the solder bump pads and the stress on the chip, FIG. 3 and FIG. 4 only show solder bump pads located on the region of the chip with high stress (i.e. periphery region). As shown in FIG. 3, the solder bump pads 14 are arranged in a matrix on the chip 12. When ambient temperature varies, the largest thermal stress always occurs on a position of the chip 12 with a maximum distance to neutral point (max DNP). For example, the solder bump pads 22 located at the four corners of the chip 12 are suffered with higher thermal stress, so that the package forms cracks most easily on the positions of the solder bump pads 22. As shown in FIG. 4, the solder bump pads 22 are directly removed to solve the above-mentioned problem according to the prior art method. That is, it is avoided to locate the solder bump pads and the solder bumps at the corners of the chip 12, which is called a bump corner design rule.
  • As mentioned above, the prior art method removes the [0009] solder bump pads 14 located at the four corners of the chip 12. However, the solder bump pads 14 on other high stress regions of the chip 12 are not removed. For example, the solder bump pads 24 shown in FIG. 4 also suffer from higher stress. As a result, as the chip 12 becomes larger, the above-mentioned method cannot effectively solve the thermal stress problem, and thus, reliability of the package is reduced.
    • SUMMARY OF INVENTION
  • It is therefore a primary objective of the claimed invention to provide solder pads for improving reliability of a package. [0010]
  • According to the claimed invention, solder pads for improving reliability of a semiconductor package are provided. The package includes a substrate and/or a chip. The solder pad includes a plurality of first solder pads located on a surface of the substrate and/or the chip, and at least a second solder pad located on a predetermined region of the surface of the substrate and/or the chip. Each of the first solder pads has a first diameter. The second solder pad has a second diameter greater than the first diameter so as to sustain a stronger thermal stress on the substrate and/or the chip. [0011]
  • It is an advantage over the prior art that the solder pads with larger sizes are located on the high stress regions of substrate and/or the chip in the claimed invention. The solder pads with larger sizes can sustain stronger thermal stress and mechanical strength. Thus, the claimed invention provides solder pads capable of effectively improving reliability of a package. In addition, the claimed invention controls the sizes of the solder pads by adjusting the sizes of the openings of the photoresist layer in the solder pad process. Thus, it is achievable to improve reliability of the package without adding additional processes and equipment or changing original processes. [0012]
  • These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the multiple figures and drawings.[0013]
    • BRIEF DESCRIPTION OF DRAWINGS
  • FIG. 1 is a schematic diagram of a prior art package. [0014]
  • FIG. 2(A) and FIG. 2(B) are a schematic diagrams for illustrating deformation of a package due to a variation of ambient temperature. [0015]
  • FIG. 3 and FIG. 4 are schematic diagrams of the solder bump pads located on the surface of the chip according to the prior art. [0016]
  • FIG. 5 to FIG. 11 are schematic diagrams for illustrating the solder pads of the embodiments according to the present invention. [0017]
  • FIG. 12 is a schematic diagram of a package according to the present invention.[0018]
    • DETAILED DESCRIPTION
  • Please refer to FIG. 5 to FIG. 11. FIG. 5 to FIG. 11 are schematic diagrams for illustrating the solder pads of the embodiments according to the present invention. The solder pads with larger sizes are located on the high stress regions of a substrate and/or a chip in the present invention. The solder pads with larger sizes can sustain stronger thermal stress and mechanical strength. As shown in FIG. 5, FIG. 5 illustrates the solder pads of the first embodiment. A plurality of [0019] first solder pads 32 and a plurality of second solder pads 34 are located on a surface of a substrate and/or a chip 30. The first solder pads 32 are arranged in a matrix at a center region of the substrate 30. The second solder pads 34 are arranged at the four vertexes of the matrix formed by the first solder pads 32. The diameter of the second solder pad 34 is larger than that of the first solder pad 32. In order to ensure reliability of the package during the welding process, the height of the first solder pad 32 is equal or approximately equal to that of the second solder pad 34.
  • Please refer to FIG. 6. FIG. 6 illustrates the solder pads of the second embodiment of the present invention. As shown in FIG. 6, a plurality of [0020] first solder pads 32 and a plurality of second solder pads 34 are located on a surface of a substrate and/or a chip 30. The first solder pads 32 are arranged in a matrix at a center region of the substrate 30. The second solder pads 34 are located at the corners of the matrix formed by the first solder pads 32. In addition, the corners of the matrix include the four vertexes of the matrix and the positions around the vertexes of the matrix. The diameter of the second solder pad 34 is larger than that of the first solder pad 32. In order to ensure reliability of the package during the welding process, the height of the first solder pad 32 is equal or approximately equal to that of the second solder pad 34.
  • Please refer to FIG. 7. FIG. 7 illustrates the solder pads of the third embodiment of the present invention. As shown in FIG. 7, a plurality of [0021] first solder pads 32 and a plurality of second solder pads 34 are located on a surface of a substrate and/or a chip 30. The first solder pads 32 are arranged in a matrix at a center region of the substrate and/or the chip 30. The second solder pads 34 are arranged at the regions near the four vertexes of the matrix formed by the first solder pads 32. For example, the second solder pads 34 are arranged at the positions around the four vertexes of the matrix, and no second solder pads 34 are located at the four vertexes of the matrix. The diameter of the second solder pad 34 is larger than that of the first solder pad 32. In order to ensure reliability of the package during the welding process, the height of the first solder pad 32 is equal or approximately equal to that of the second solder pad 34.
  • Please refer to FIG. 8. FIG. 8 illustrates the solder pads of the fourth embodiment of the present invention. As shown in FIG. 8, a plurality of [0022] first solder pads 32 and a plurality of second solder pads 34 are located on a surface of a substrate and/or a chip 30. The first solder pads 32 are located at the four sides of the substrate and/or the chip 30 and the first solder pads 32 are arranged in a rectangle. The second solder pads 34 are located at the four vertexes of the rectangle formed by the first solder pads 32. The diameter of the second solder pad 34 is larger than that of the first solder pad 32. In order to ensure reliability of the package during the welding process, the height of the first solder pad 32 is equal or approximately equal to that of the second solder pad 34.
  • Please refer to FIG. 9. FIG. 9 illustrates the solder pads of the fifth embodiment of the present invention. As shown in FIG. 9, a plurality of [0023] first solder pads 32 and a plurality of second solder pads 34 are located on a surface of a substrate and/or a chip 30. The first solder pads 32 are located at the four sides of the substrate and/or the chip 30 and the first solder pads 32 are arranged in a rectangle. The second solder pads 34 are located at the regions near the four vertexes of the rectangle formed by the first solder pads 32. For example, the second solder pads 34 are arranged at the positions around the four vertexes of the rectangle, and no second solder pads 34 are located at the four vertexes of the rectangle. The diameter of the second solder pad 34 is larger than that of the first solder pad 32. In order to ensure reliability of the package during the welding process, the height of the first solder pad 32 is equal or approximately equal to that of the second solder pad 34.
  • Under ideal conditions, taking the center of the substrate and/or the chip as a center of a circle, the solder pads located at the circumference of the same concentric circle are suffered with approximately equal thermal stress. The present invention arranges solder pads with different sizes according to the above-mentioned stress distribution. Please refer to FIG. 10. FIG. 10 illustrates the solder pads of the sixth embodiment of the present invention. As shown in FIG. 10, a plurality of [0024] first solder pads 32 and a plurality of second solder pads 34 are located on a surface of a substrate and/or a chip 30. The first solder pads 32 are located at circumferences of a plurality of concentric circles. The second solder pads 34 are located at a high stress region, which is farthest from the center of the substrate and/or the chip 30. That is, the second solder pads 34 are located at the circumference of the maximum circle on the substrate 30. The diameter of the second solder pad 34 is larger than that of the first solder pad 32. In order to ensure reliability of the package during the welding process, the height of the first solder pad 32 is equal or approximately equal to that of the second solder pad 34.
  • Please refer to FIG. 11. FIG. 11 illustrates the solder pads of the seventh embodiment of the present invention. As shown in FIG. 11, a plurality of [0025] first solder pads 32 and a plurality of second solder pads 34 are located on a surface of a substrate 30. The first solder pads 32 are located at circumferences of a plurality of concentric circles. The second solder pads 34 are located at the corners outside the concentric circles formed by the first solder pads 32. The diameter of the second solder pad 34 is larger than that of the first solder pad 32. In order to ensure reliability of the package during the welding process, the height of the first solder pad 32 is equal or approximately equal to that of the second solder pad 34.
  • The present invention can be applied not only in a flip-chip package, but also in a ball grid array (BGA) package. As a result, in all embodiments of the present invention, the [0026] substrate 30 can be a semiconductor wafer, and the first solder pads 32 and the second solder pads 34 can be solder bump pads for connecting the semiconductor wafer with the plastic substrate or the ceramic substrate. The substrate 30 comprises a plastic substrate, a ceramic substrate, or a printed circuit board. The first solder pads 32 and the second solder pads 34 are solder ball pads for connecting the above-mentioned substrate with other chips or substrates.
  • Please refer to FIG. 12. FIG. 12 is a schematic diagram of a package according to the present invention. As shown in FIG. 12, a [0027] package 40 comprises a chip 42, a substrate 44, and a print circuit board 46. An underfill layer 56 is filled in a gap between the chip 42 and the substrate 44. The substrate 44 is a plastic substrate or a ceramic substrate. A plurality of solder bump pads 52 is located on a first surface of the substrate 44, and each solder bump pad 52 connects to a solder bump 54. The solder bump pads 52 connect to the chip 42 by use of the solder bumps 54. A plurality of solder ball pads 58 is located on a second surface of the substrate 44, and each solder ball pad 58 connects to a solder ball 60. The solder ball pads 58 connect to the print circuit board 46 by use of the solder balls 60. Noticeably, in order to make the package sustain higher thermal stress and higher fatigue strength, the solder bump pads 52 or the solder ball pads 58 should have at least two different kinds of diameters. The solder bump pads 52 or the solder ball pads 58 with larger sizes are used to sustain a stronger thermal stress during a thermal process. The arrangement of the solder bump pads 52 or the solder ball pads 58 can refer to the first embodiment to the seventh embodiment of the present invention.
  • In addition, the [0028] solder bump pads 52 can be located on a surface of the chip 42 in the package 40 shown in FIG. 12. Then, each solder bump pad 52 connects to a solder bump 54, and uses the solder bump 54 to connect to the substrate 44. Conversely, the solder ball pads 58 can be located on a surface of the print circuit board 46. Each solder ball pad 58 connects to a solder ball 60, and uses the solder ball 60 to connect to the substrate 44.
  • In comparison with the prior art, the solder pads with larger sizes are located on the high stress regions of the substrate in the claimed invention. The solder pads with larger sizes can sustain stronger thermal stress and mechanical strength. Thus, the claimed invention provides solder pads capable of effectively improving reliability of a package. In addition, the claimed invention controls the sizes of the solder pads by adjusting the sizes of the openings of the photoresist layer in the solder pad process. Thus, it is achievable to improve reliability of the package without adding additional processes or changing original processes. [0029]
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bound of the appended claims. [0030]

Claims (34)

What is claimed is:
1. Solder pads for improving reliability of a package, the package comprising a substrate, the solder pads comprising:
a plurality of first solder pads positioned on a surface of the substrate, each of the first solder pads having a first diameter; and
at least a second solder pad positioned on a predetermined region of the substrate surface, the second solder pad having a second diameter greater than the first diameter to sustain a stronger thermal stress and a stronger fatigue strength.
2. The solder pads of claim 1 wherein the substrate comprises a plastic substrate.
3. The solder pads of claim 1 wherein the substrate comprises a ceramic substrate.
4. The solder pads of claim 1 wherein the substrate comprises a printed circuit board (PCB).
5. The solder pads of claim 1 wherein the substrate comprises a chip.
6. The solder pads of claim 1 wherein the predetermined region comprises a high stress region.
7. The solder pads of claim 1 wherein the first solder pads are arranged in a matrix at a center region of the substrate.
8. The solder pads of claim 1 wherein the predetermined region comprises the corners of the substrate.
9. The solder pads of claim 1 wherein the predetermined region comprises the circumferences of a plurality of concentric circles on the substrate.
10. The solder pads of claim 9 wherein the second solder pads on each of the concentric circle circumferences are arranged with an equal interval.
11. The solder pads of claim 1 wherein the predetermined region comprises the corners of the substrate on an outside portion of a maximum circle on the substrate.
12. The solder pads of claim 1 wherein the predetermined region comprises the circumference of a maximum circle on the substrate.
13. The solder pads of claim 1 wherein the predetermined region comprises at least a grounded solder pad.
14. The solder pads of claim 1 wherein each of the first solder pads and the second solder pad comprise a solder bump pad, the solder bump pad connecting to a solder bump and using the solder bump to connect to a chip.
15. The solder pads of claim 14 wherein an underfill layer is filled in a gap between the chip and the substrate.
16. The solder pads of claim 1 wherein each of the first solder pads and the second solder pad comprise a solder ball pad, the solder ball pad connecting to a solder ball and using the solder ball to connect to a printed circuit board.
17. Solder pads comprising:
a substrate;
a plurality of first solder bump pads positioned on a first surface of the substrate, each of the first solder bump pads having a first diameter;
at least a second solder bump pad positioned on a first predetermined region of the first surface, the second bump solder pad having a second diameter greater than the first diameter;
a plurality of first solder ball pads positioned on a second surface of the substrate, each of the first solder ball pads having a third diameter; and
at least a second solder ball pad positioned on a second predetermined region of the second surface, the second solder ball pad having a second diameter greater than the third diameter.
18. The solder pads of claim 17 wherein the substrate comprises a plastic substrate.
19. The solder pads of claim 17 wherein the substrate comprises a ceramic substrate.
20. The solder pads of claim 17 wherein the first predetermined region and the second predetermined region comprise a high stress region.
21. The solder pads of claim 17 wherein the first solder bump pads are arranged in a matrix at a center region of the substrate.
22. The solder pads of claim 17 wherein the first predetermined region comprises the corners on the first surface of the substrate.
23. The solder pads of claim 17 wherein the first predetermined region comprises the circumferences of a plurality of concentric circles on the first surface.
24. The solder pads of claim 23 wherein the second solder bump pads on each of the concentric circle circumferences are arranged with an equal interval.
25. The solder pads of claim 17 wherein the first predetermined region comprises the corners of the substrate on an outside portion of a maximum circle on the first surface.
26. The solder pads of claim 17 wherein the first predetermined region comprises the circumference of a maximum circle on the first surface.
27. The solder pads of claim 17 wherein the first surface is an upper surface of the substrate, each of the first solder bump pads and the second solder bump pad connecting to a solder bump and using the solder bump to connect to a chip.
28. The solder pads of claim 17 wherein the first solder ball pads are arranged in a matrix at a center region of the substrate.
29. The solder pads of claim 17 wherein the second predetermined region comprises the corners on the second surface of the substrate.
30. The solder pads of claim 17 wherein the second predetermined region comprises the circumferences of a plurality of concentric circles on the second surface.
31. The solder pads of claim 30 wherein the second solder ball pads on each of the concentric circle circumferences are arranged with an equal interval.
32. The solder pads of claim 17 wherein the second predetermined region comprises the corners of the substrate on an outside portion of a maximum circle on the second surface.
33. The solder pads of claim 17 wherein the second predetermined region comprises the circumference of a maximum circle on the second surface.
34. The solder pads of claim 17 wherein the second surface is a lower surface of the substrate, each of the first solder ball pads and the second solder ball pad connecting to a solder ball and using the solder ball to connect to a printed circuit board.
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Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050230828A1 (en) * 2004-04-20 2005-10-20 Jeng-Da Wu Carrier, chip package structure, and circuit board package structure
US20080280393A1 (en) * 2007-05-09 2008-11-13 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for forming package structures
US20110084390A1 (en) * 2009-10-08 2011-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Chip Design with Robust Corner Bumps
US20110235296A1 (en) * 2010-03-29 2011-09-29 Quanta Computer Inc. Integrated circuit package component with ball conducting joints
US20120031659A1 (en) * 2006-01-27 2012-02-09 Ibiden Co., Ltd Printed Wiring Board And A Method Of Manufacturing A Printed Wiring Board
EP1758373A3 (en) * 2005-08-24 2012-03-21 Konica Minolta Opto, Inc. Solid image pickup unit and camera module
WO2013039258A1 (en) * 2011-09-14 2013-03-21 Canon Kabushiki Kaisha Semiconductor device and printed circuit board
US20130113096A1 (en) * 2010-07-09 2013-05-09 Rohm Co., Ltd. Semiconductor device
US20150200185A1 (en) * 2014-01-16 2015-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structure design in fan-out package
CN105830213A (en) * 2013-12-20 2016-08-03 高通股份有限公司 Substrate Comprising Improved Via Pad Placement In Bump Area
US20170077041A1 (en) * 2015-09-11 2017-03-16 Samsung Electronics Co., Ltd. Package substrates
US20170243814A1 (en) * 2014-10-31 2017-08-24 Mediatek Inc. Semiconductor package
US9972607B2 (en) * 2016-08-08 2018-05-15 Semiconductor Components Industries, Llc Semiconductor device and method of integrating power module with interposer and opposing substrates
US20190175004A1 (en) * 2016-11-21 2019-06-13 Olympus Corporation Imaging module for endoscope, and endoscope
CN114664747A (en) * 2020-12-31 2022-06-24 华为技术有限公司 Board level structure and communication equipment
US20220328440A1 (en) * 2018-11-27 2022-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. Shielding structures
US20230068329A1 (en) * 2021-08-30 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4083638B2 (en) * 2003-07-30 2008-04-30 東北パイオニア株式会社 Flexible wiring board, semiconductor chip mounting flexible wiring board, display device, semiconductor chip mounting method
JP2009049499A (en) * 2007-08-14 2009-03-05 Fujifilm Corp Method for mounting semiconductor chip, and semiconductor device
US8344505B2 (en) 2007-08-29 2013-01-01 Ati Technologies Ulc Wafer level packaging of semiconductor chips
JP2009182104A (en) * 2008-01-30 2009-08-13 Toshiba Corp Semiconductor package
US8415792B2 (en) 2010-08-04 2013-04-09 International Business Machines Corporation Electrical contact alignment posts
US20120267779A1 (en) * 2011-04-25 2012-10-25 Mediatek Inc. Semiconductor package
CN108391366B (en) * 2012-08-15 2022-12-30 南安市威速电子科技有限公司 Imaging device
US8970051B2 (en) * 2013-06-28 2015-03-03 Intel Corporation Solution to deal with die warpage during 3D die-to-die stacking
CN104655885B (en) * 2013-11-15 2018-01-05 本田技研工业株式会社 The manufacture method of electric current bringing device and semiconductor element
US10510652B2 (en) * 2016-08-15 2019-12-17 Taiwan Semiconductor Manufacturing Company Ltd. Method of manufacturing semiconductor device
US9204543B2 (en) * 2013-12-03 2015-12-01 Infineon Technologies Ag Integrated IC package
JP5898243B2 (en) * 2014-01-09 2016-04-06 本田技研工業株式会社 Current application apparatus and semiconductor element manufacturing method
KR102154830B1 (en) 2014-08-05 2020-09-11 삼성전자주식회사 Semiconductor Package and methods for manufacturing the same
US10497660B2 (en) * 2015-02-26 2019-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices
TWI611577B (en) * 2016-03-04 2018-01-11 矽品精密工業股份有限公司 Electronic package and semiconductor substrate
JP7056620B2 (en) * 2019-03-28 2022-04-19 株式会社デンソー Electronic device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5153379A (en) * 1990-10-09 1992-10-06 Motorola, Inc. Shielded low-profile electronic component assembly
US6404062B1 (en) * 1999-03-05 2002-06-11 Fujitsu Limited Semiconductor device and structure and method for mounting the same
US6444563B1 (en) * 1999-02-22 2002-09-03 Motorlla, Inc. Method and apparatus for extending fatigue life of solder joints in a semiconductor device
US6518677B1 (en) * 1997-07-21 2003-02-11 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5216278A (en) * 1990-12-04 1993-06-01 Motorola, Inc. Semiconductor device having a pad array carrier package
JP3226244B2 (en) 1993-12-03 2001-11-05 株式会社東芝 Resin-sealed semiconductor device
JPH07307410A (en) * 1994-05-16 1995-11-21 Hitachi Ltd Semiconductor device
US5741729A (en) * 1994-07-11 1998-04-21 Sun Microsystems, Inc. Ball grid array package for an integrated circuit
US6008534A (en) * 1998-01-14 1999-12-28 Lsi Logic Corporation Integrated circuit package having signal traces interposed between power and ground conductors in order to form stripline transmission lines
JP2000100851A (en) * 1998-09-25 2000-04-07 Sony Corp Semiconductor substrate and manufacture thereof and structure and method for mounting semiconductor parts
JP3437107B2 (en) * 1999-01-27 2003-08-18 シャープ株式会社 Resin-sealed semiconductor device
US6365978B1 (en) * 1999-04-02 2002-04-02 Texas Instruments Incorporated Electrical redundancy for improved mechanical reliability in ball grid array packages
JP2001257289A (en) * 2000-03-10 2001-09-21 Mitsubishi Electric Corp Semiconductor package, semiconductor device and method of manufacturing the same
JP2001319997A (en) 2000-05-10 2001-11-16 Mitsubishi Electric Corp Semiconductor package and semiconductor chip
US6350669B1 (en) * 2000-10-30 2002-02-26 Siliconware Precision Industries Co., Ltd. Method of bonding ball grid array package to circuit board without causing package collapse

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5153379A (en) * 1990-10-09 1992-10-06 Motorola, Inc. Shielded low-profile electronic component assembly
US6518677B1 (en) * 1997-07-21 2003-02-11 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US6444563B1 (en) * 1999-02-22 2002-09-03 Motorlla, Inc. Method and apparatus for extending fatigue life of solder joints in a semiconductor device
US6404062B1 (en) * 1999-03-05 2002-06-11 Fujitsu Limited Semiconductor device and structure and method for mounting the same

Cited By (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050230828A1 (en) * 2004-04-20 2005-10-20 Jeng-Da Wu Carrier, chip package structure, and circuit board package structure
EP1758373A3 (en) * 2005-08-24 2012-03-21 Konica Minolta Opto, Inc. Solid image pickup unit and camera module
US20120031659A1 (en) * 2006-01-27 2012-02-09 Ibiden Co., Ltd Printed Wiring Board And A Method Of Manufacturing A Printed Wiring Board
US9480170B2 (en) * 2006-01-27 2016-10-25 Ibiden Co., Ltd. Printed wiring board and a method of manufacturing a printed wiring board
US20080280393A1 (en) * 2007-05-09 2008-11-13 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for forming package structures
US8624391B2 (en) * 2009-10-08 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Chip design with robust corner bumps
US20110084390A1 (en) * 2009-10-08 2011-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Chip Design with Robust Corner Bumps
US20110235296A1 (en) * 2010-03-29 2011-09-29 Quanta Computer Inc. Integrated circuit package component with ball conducting joints
US9508672B2 (en) * 2010-07-09 2016-11-29 Rohm Co., Ltd. Semiconductor device
US10068823B2 (en) 2010-07-09 2018-09-04 Rohm Co., Ltd. Semiconductor device
US9070673B2 (en) * 2010-07-09 2015-06-30 Rohm Co., Ltd. Semiconductor device
US20150279807A1 (en) * 2010-07-09 2015-10-01 Rohm Co., Ltd. Semiconductor device
US20130113096A1 (en) * 2010-07-09 2013-05-09 Rohm Co., Ltd. Semiconductor device
US20140192499A1 (en) * 2011-09-14 2014-07-10 Canon Kabushiki Kaisha Semiconductor device and printed circuit board
WO2013039258A1 (en) * 2011-09-14 2013-03-21 Canon Kabushiki Kaisha Semiconductor device and printed circuit board
CN105830213A (en) * 2013-12-20 2016-08-03 高通股份有限公司 Substrate Comprising Improved Via Pad Placement In Bump Area
US9466578B2 (en) 2013-12-20 2016-10-11 Qualcomm Incorporated Substrate comprising improved via pad placement in bump area
US10510670B2 (en) 2014-01-16 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structure design in fan-out package
US11424189B2 (en) 2014-01-16 2022-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structure design in fan-out package
US20150200185A1 (en) * 2014-01-16 2015-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structure design in fan-out package
US9576926B2 (en) * 2014-01-16 2017-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structure design in fan-out package
US10109566B2 (en) * 2014-10-31 2018-10-23 Mediatek Inc. Semiconductor package
US20170243814A1 (en) * 2014-10-31 2017-08-24 Mediatek Inc. Semiconductor package
US10032706B2 (en) * 2015-09-11 2018-07-24 Samsung Electronics Co., Ltd. Package substrates
US10256181B2 (en) 2015-09-11 2019-04-09 Samsung Electronics Co., Ltd. Package substrates
US20170077041A1 (en) * 2015-09-11 2017-03-16 Samsung Electronics Co., Ltd. Package substrates
US10438932B2 (en) 2016-08-08 2019-10-08 Semiconductor Components Industries, Llc Semiconductor device and method of integrating power module with interposer and opposing substrates
US9972607B2 (en) * 2016-08-08 2018-05-15 Semiconductor Components Industries, Llc Semiconductor device and method of integrating power module with interposer and opposing substrates
US20190175004A1 (en) * 2016-11-21 2019-06-13 Olympus Corporation Imaging module for endoscope, and endoscope
US20220328440A1 (en) * 2018-11-27 2022-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. Shielding structures
US11855022B2 (en) * 2018-11-27 2023-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Shielding structures
CN114664747A (en) * 2020-12-31 2022-06-24 华为技术有限公司 Board level structure and communication equipment
US20230068329A1 (en) * 2021-08-30 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device

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