TWI544584B - Copper substrate with barrier structure and manufacturing method thereof - Google Patents

Copper substrate with barrier structure and manufacturing method thereof Download PDF

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Publication number
TWI544584B
TWI544584B TW103101847A TW103101847A TWI544584B TW I544584 B TWI544584 B TW I544584B TW 103101847 A TW103101847 A TW 103101847A TW 103101847 A TW103101847 A TW 103101847A TW I544584 B TWI544584 B TW I544584B
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Taiwan
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substrate
copper
barrier
wafer
clad
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TW103101847A
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TW201530706A (zh
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zi-zhi Lin
jian-ke Liao
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Priority to TW103101847A priority Critical patent/TWI544584B/zh
Priority to US14/262,199 priority patent/US20150206852A1/en
Priority to US14/720,496 priority patent/US20150255423A1/en
Publication of TW201530706A publication Critical patent/TW201530706A/zh
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Publication of TWI544584B publication Critical patent/TWI544584B/zh

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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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Description

具阻隔結構之敷銅基板及其製造方法
本發明係關於一種基板及其製造方法，特別是指一種具阻隔結構之敷銅基板及其製造方法。
於半導體技術領域中，半導體晶片以覆晶形式(Flip-Chip)藉由多數以矩陣型態排列之導電金屬銲塊，如錫球或錫片電性連接到基板或印刷電路板上。當晶片以覆晶方式焊接到基板上時，基板表層係佈設有一阻焊層(Solder Mask)，該阻焊層下埋設多條導電線路，各導電線路終端對應於晶片錫塊焊接之位置上形成有一外露出該阻焊層之銲墊(Solder Pads)，因此，該錫塊與基板上各銲墊對應焊結後，晶片訊號可透過該錫塊以及散佈於基板表層並藉由貫孔貫穿基板中心樹脂層之導電線路傳送至基板底部，再與外部裝置電性連接。一般銲墊形式的基板1為如第1圖所示，係為阻焊層定義(Solder Mask Defined,SMD)，該阻焊層2的開口3之尺寸小於形成在基板1之樹脂層4上的銲墊5之尺寸，以令該銲墊5之周緣為該阻焊層2所覆蓋。而覆晶封裝技術(Flip-chip Technology)係預先在晶片6之作用表面的晶片銲墊7上形成複數個錫球8，再以作用表面朝下的方式將該晶片6迴焊至基板1，而形成包含晶片銲墊7、錫球8及基板銲墊5之焊結接 合，之後再以底部填膠或模壓製程充佈一絕緣膠材至晶片6之底部間隙，以強化錫球8之焊接力；然而，當以前述之封裝技術應用於高功率模組上，由於高電壓電流之工作狀態使其產生相當大之熱能，此時晶片的散熱性及穩定性即成為必須克服之重點。
如第2圖所示，業界為克服此問題，一種利用錫片9搭配迴焊(Reflow)製程之技術方案則被廣為使用，但因為錫片9在迴焊爐的過程中會由固態轉換成液態，此時液態錫則可能會經由基板1表面而流向相鄰的導電線路，以致引發相鄰導電線路間的橋接短路，進而使晶片6損毀或功能失效，抑或者需花費更多的人力物力成本來進行修復。
綜上所陳，習知的基板1結構及封裝技術仍具上述之缺失而有待改進。
本發明之主要目的在於提供一種具阻隔結構之敷銅基板，其可避免錫片在迴焊爐中形成液態錫後，因接觸其他訊號線而造成短路之問題。
為了達成上述目的，本發明所提供一種具阻隔結構之敷銅基板，其包含有一承載區以及一阻隔區，該承載區可供一晶片電性連接之用，該阻隔區形成於該承載區之周圍，以阻隔該晶片及該承載區。
其更包含有至少一導電片，該至少一導電片係設 於該晶片與該基板之承載區之間，以供該晶片電性連接於該基板。
為了達成上述目的，本發明所提供另一種具阻隔結構之敷銅基板，其包含有複數個承載區以及複數個阻隔區，各該承載區可供各該晶片電性連接之用，各該阻隔區形成於各該承載區之周圍，以阻隔各該晶片及各該承載區。
其更包含有複數個導電片，各該導電片係固設於各該晶片與各該基板之承載區之間，以供各該晶片電性連接於該基板。
其中該基板之阻隔區係為一凹槽。
其中該基板之阻隔區係為一擋牆。
其中該基板係為一陶瓷層以及形成於該陶瓷層上下表面之覆銅層所構成。
為了達成上述目的，本發明所提供一種具阻隔結構之敷銅基板的製造方法，其包含有下列步驟：提供一基板且分別定義出至少一承載區以及至少一形成於該至少一承載區周圍之阻隔區；提供至少一晶片於該至少一承載區；以及提供一連接手段於該至少一晶片與該至少一承載區之間，以供電性連接之用。
其中定義該至少一阻隔區係包括有提供一光罩(Mask)並經由一曝光顯影製程後，蝕刻(Etching)形成至少一凹槽之步驟。
其中定義該至少一阻隔區係包括有提供一光罩(Mask)並以沉積(Deposition)或濺鍍(Sputter)製程形成至少一擋 牆之步驟。
其中該基板包括於一陶瓷層之上下表面分別形成一覆銅層之步驟。
其中該連接手段係先提供至少一導電片於該至少一晶片與該至少一承載區之間，並經過一迴焊(Reflow)製程將該至少一晶片電性連接於該至少一承載區。
藉此，本發明之敷銅基板可供該晶片平坦設置，且利於導熱，以提升該晶片之工作效能，更可透過該阻隔區之技術特徵來避免該錫片在迴焊爐中形成液態錫後，因接觸其他訊號線而造成短路之問題。
為使 貴審查委員能進一步了解本發明之構成、特徵及其目的，以下乃舉本發明之若干實施例，並配合圖式詳細說明如後，同時讓熟悉該技術領域者能夠具體實施，惟以下所述者，僅係為了說明本發明之技術內容及特徵而提供之一實施方式，凡為本發明領域中具有一般通常知識者，於了解本發明之技術內容及特徵之後，以不違背本發明之精神下，所為之種種簡單之修飾、替換或構件之減省，皆應屬於本發明意圖保護之範疇。
1‧‧‧基板
2‧‧‧阻焊層
3‧‧‧開口
4‧‧‧樹脂層
5‧‧‧銲墊
6‧‧‧晶片
7‧‧‧晶片銲墊
8‧‧‧錫球
9‧‧‧錫片
10‧‧‧敷銅基板
10'‧‧‧敷銅基板
11‧‧‧承載區
13‧‧‧阻隔區
131‧‧‧凹槽
133‧‧‧擋牆
15‧‧‧陶瓷層
17‧‧‧覆銅層
20‧‧‧晶片
30‧‧‧導通片(錫片)
以下將藉由所列舉之實施例，配合隨附之圖式，詳細說明本發明之技術內容及特徵，其中：
第1圖為習用之基板及封裝結構的剖面圖。
第2圖為另一習用之基板及封裝結構的剖面圖。
第3圖為本發明第一較佳實施例所提供之具阻隔結構之敷 銅基板的剖面圖，主要顯示阻隔區為凹槽之結構。
第4圖為本發明該第一較佳實施例所提供之具阻隔結構之敷銅基板的剖面圖，主要顯示阻隔區為擋牆之結構。
第5圖為本發明第二較佳實施例所提供之具阻隔結構之敷銅基板的俯視圖，主要顯示各晶片及各阻隔區分佈之位置。
第6圖為本發明該第二較佳實施例所提供之具阻隔結構之敷銅基板的剖面圖，主要顯示凹槽位於各晶片之間的態樣。
第7圖為本發明該第二較佳實施例所提供之具阻隔結構之敷銅基板的剖面圖，主要顯示擋牆位於各晶片之間的態樣。
第8圖A-D為本發明該第一、第二較佳實施例所提供之具阻隔結構之敷銅基板製造方法的流程圖，主要顯示凹槽係以曝光顯影製程後蝕刻所形成。
第9圖A-D為本發明該第一、第二較佳實施例所提供之具阻隔結構之敷銅基板製造方法的流程圖，主要顯示擋牆係以沉積或濺鍍製程形成。
為了詳細說明本發明之結構、特徵及功效所在，茲列舉一第一較佳實施例並配合下列圖式說明如後，其中：請參閱第3圖及第4圖所示，為本發明該第一較佳實施例所提供之一種具阻隔結構之敷銅基板10，其包含有一承載區11以及一阻隔區13，該承載區11可供一晶片20設 置且電性連接之用，該阻隔區13形成於該承載區11之周圍，用以將該晶片20及該承載區11與其外圍作阻隔。在本發明該第一較佳實施例中，該晶片20與該敷銅基板10之承載區11之間係以至少一導電片30來做為其電性連接，該至少一導電片30在實際實施中以錫片較佳，而該阻隔區13則可依不同的製程需求而形成為一凹槽131結構或者為一擋牆133結構，藉此，該至少一錫片30不僅可供該晶片20平坦地設置於該敷銅基板10上，更可透過該阻隔區13為凹槽131或擋牆133之結構而防止該至少一錫片30在液態後，而流經或接觸其他訊號線而造成短路之問題。
請再參閱第5圖至第7圖所示，係為本發明一第二較佳實施例之具阻隔結構的敷銅基板10'，其包含有複數個相互鄰近的該承載區11以及複數個形成於各該承載區11周圍之該阻隔區13，各該承載區11與各該晶片20之間係以複數個錫片30來作為固接以及電性連接之用，各該阻隔區13之結構與該第一較佳實施例相同，係可依不同的製程需求而為該凹槽131或者該擋牆133，用以阻隔彼此相鄰的各該晶片20或彼此相鄰的各該承載區11，以避免該錫片30在迴焊爐中形成液態錫後，因接觸其他訊號線而造成短路之問題。
值得一提的是，如第8圖及第9圖所示，該第一、第二較佳實施之具阻隔結構的敷銅基板10、10'係為一陶瓷層15以及形成於該陶瓷層15上下表面之覆銅層17所構成，其 具有良好的導熱性能以及導電性，藉以克服電路布線寬度細密化、單位面積上功率消耗越來越大所造成高熱能的問題，更因此有效地提供各該晶片20散熱之用，以避免零組件形成失效。
再請參閱第8圖A-D所示，係為本發明提供的一種具阻隔結構之敷銅基板10、10'的製造方法，其包含有下列步驟：
步驟A：在該陶瓷層15之上下表面分別形成該覆銅層17，以形成該敷銅基板10、10'。
步驟B：利用光罩(Mask)來定義出該敷銅基板10、10'之承載區11以及阻隔區13，接著經由曝光顯影製程後，以蝕刻(Etching)形成圍繞於該承載區11周圍之凹槽131。
步驟C：提供該錫片30於該晶片20與該承載區11之間，以供電性連接之用。
步驟D：提供該晶片20設於該錫片30且位於該承載區11上方，且利用一連接手段將該晶片20、該錫片30及該敷銅基板10、10'之承載區11作電性連接，其中該連接手段係將設於該晶片20與該承載區11之間的該錫片30，經過一迴焊(Reflow)製程而使該晶片20可與該敷銅基板10、10'之該承載區11作電性連接。
再請參閱第9圖A-D所示，係為本發明提供的另一種具阻隔結構之敷銅基板10、10'的製造方法，其包含有下 列步驟：
步驟A：在該陶瓷層15之上下表面分別形成該覆銅層17，以形成該敷銅基板10、10'。
步驟B：利用光罩(Mask)來定義出該敷銅基板10、10'之承載區11以及阻隔區13，接著經由沉積(Deposition)或濺鍍(Sputter)製程形成圍繞於該承載區11周圍之擋牆133。
步驟C：提供該錫片30於該晶片20與該承載區11之間，以供電性連接之用。
步驟D：提供該晶片20設於該錫片30且位於該承載區11上方，且利用一連接手段將該晶片20、該錫片30及該敷銅基板10、10'之承載區11作電性連接，其中該連接手段係將設於該晶片20與該承載區11之間的該錫片30，經過一迴焊(Reflow)製程而使該晶片20可與該敷銅基板10、10'之該承載區11作電性連接。
藉此，無論是本發明的第一較佳實施例或是第二較佳實施例之敷銅基板10、10'，其皆可提供該晶片20平坦設置，且透過該陶瓷層15及該覆銅層17的結構而較佳的導熱與散熱效果，以提升該晶片20之工作效能，更可利用該阻隔區13為該凹槽131或該擋牆133之技術特徵來避免該錫片30在迴焊爐中形成液態錫後，因接觸其他訊號線而造成短路之問題。
本發明於前揭露實施例中所揭露的構成元件，僅 為舉例說明，並非用來限制本案之範圍，其他等效元件的替代或變化，亦應為本案之申請專利範圍所涵蓋。
10'‧‧‧敷銅基板
11‧‧‧承載區
131‧‧‧凹槽
20‧‧‧晶片
30‧‧‧導通片

Claims (10)

  1. 一種具阻隔結構之敷銅基板，係為一陶瓷層以及形成於該陶瓷層上下表面之覆銅層所構成，該基板包含有一承載區以及一阻隔區，該承載區可供一晶片電性連接之用，該阻隔區形成於該承載區之周圍。
  2. 根據申請專利範圍第1項之具阻隔結構之敷銅基板，其更包含有至少一導電片，該至少一導電片係設於該晶片與該基板之承載區之間，以供該晶片電性連接於該基板。
  3. 一種具阻隔結構之敷銅基板，係為一陶瓷層以及形成於該陶瓷層上下表面之覆銅層所構成，該基板包含有複數個承載區以及複數個阻隔區，各該承載區可分別供複數個晶片電性連接之用，各該阻隔區形成於各該承載區之周圍，以阻隔各該承載區。
  4. 根據申請專利範圍第3項之具阻隔結構之敷銅基板，其更包含有複數個導電片，各該導電片係固設於各該晶片與各該基板之承載區之間，以供各該晶片電性連接於該基板。
  5. 根據申請專利範圍第1項及第3項其中之一之具阻隔結構之敷銅基板，其中該基板之阻隔區係為一凹槽。
  6. 根據申請專利範圍第1項及第3項其中之一之具阻隔結構之敷銅基板，其中該基板之阻隔區係為一擋牆。
  7. 一種具阻隔結構之敷銅基板的製造方法，其包含有下列步驟：於一陶瓷層之上下表面分別形成一覆銅層，以製成一基板； 於該基板分別定義出至少一承載區以及至少一形成於該至少一承載區周圍之阻隔區；提供至少一晶片於該至少一承載區；以及提供一連接手段於該至少一晶片與該至少一承載區之間，以供電性連接之用。
  8. 根據申請專利範圍第7項之具阻隔結構之敷銅基板的製造方法，其中定義該至少一阻隔區係包括有提供一光罩(Mask)並經由一曝光顯影製程後，蝕刻(Etching)形成至少一凹槽之步驟。
  9. 根據申請專利範圍第7項之具阻隔結構之敷銅基板的製造方法，其中定義該至少一阻隔區係包括有提供一光罩(Mask)並以沉積(Deposition)或濺鍍(Sputter)製程形成至少一擋牆之步驟。
  10. 根據申請專利範圍第7項之具阻隔結構之敷銅基板的製造方法，其中該連接手段係先提供至少一導電片於該至少一晶片與該至少一承載區之間，並經過一迴焊(Reflow)製程將該至少一晶片電性連接於該至少一承載區。
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