WO2017036344A1 - 影像传感器封装结构及其封装方法 - Google Patents

影像传感器封装结构及其封装方法 Download PDF

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Publication number
WO2017036344A1
WO2017036344A1 PCT/CN2016/096737 CN2016096737W WO2017036344A1 WO 2017036344 A1 WO2017036344 A1 WO 2017036344A1 CN 2016096737 W CN2016096737 W CN 2016096737W WO 2017036344 A1 WO2017036344 A1 WO 2017036344A1
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WIPO (PCT)
Prior art keywords
pad
substrate
chip
packaged
package structure
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PCT/CN2016/096737
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English (en)
French (fr)
Inventor
王之奇
沈志杰
陈佳炜
Original Assignee
苏州晶方半导体科技股份有限公司
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Priority claimed from CN201520662836.8U external-priority patent/CN204905258U/zh
Priority claimed from CN201510540994.0A external-priority patent/CN105097862A/zh
Application filed by 苏州晶方半导体科技股份有限公司 filed Critical 苏州晶方半导体科技股份有限公司
Priority to US15/753,968 priority Critical patent/US20180247962A1/en
Publication of WO2017036344A1 publication Critical patent/WO2017036344A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H01L27/14627—Microlenses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Definitions

  • the present invention relates to the field of semiconductor chip packaging, and in particular, to a package structure of an image sensor and a packaging method thereof.
  • the existing wafer level package structure is shown in Figure 1. It includes a chip 200 to be packaged and a cover layer 300.
  • the microlens 211 is formed on the first surface 200a of the chip 200 to be packaged, and the pad 212 is formed inside the chip 200 to be packaged near the first surface 200a.
  • a support structure 320 is disposed between the first surface 200a of the chip 200 to be packaged and the first surface 300a of the cover layer 300. The surface of the support structure 320 is coated with an adhesive for bonding the cover layer 300 and the chip 200 to be packaged. After the chip to be packaged 200 is bonded to the cover layer 300, a cavity 310 is formed between the microlens 211 and the cover layer 300.
  • a plurality of etching grooves 215 are formed on the second surface 200b of the chip 200 to be packaged, and the bottom of the etching groove 215 is electrically connected to the pad 212.
  • An insulating layer 213 and a conductive layer 214 are formed on the surface of the etched trench 215, and solder joints 216 are formed on the conductive layer 214, and the solder joints 216 are electrically connected to the solder joints on the external circuit board, so that the solder to be packaged
  • the chip 200 is electrically connected to an external circuit board.
  • the existing wafer level package structure needs to be etched on the chip to be packaged, increasing The damage rate of the chip to be packaged, and the etching process and the film deposition process are required for the package structure, the process is cumbersome and the package cost is high.
  • the first aspect of the present invention provides an image sensor package structure to reduce the damage rate of a chip to be packaged.
  • a second aspect of the present invention provides a packaging method of an image sensor package structure to simplify a packaging process and reduce packaging cost.
  • An image sensor package structure comprising:
  • the chip to be packaged includes a first surface and a second surface respectively located on two sides of the chip to be packaged, and a photosensitive region and a first pad located around the photosensitive region are disposed on the first surface;
  • a substrate disposed on a first surface side of the chip to be packaged the substrate includes a third surface and a fourth surface respectively disposed on two sides of the substrate, wherein the third surface is provided with a second pad and a third pad; The second pad is located at a side of the third pad away from the photosensitive region; wherein a first surface of the chip to be packaged is opposite to a third surface of the substrate; the first pad and The third pad is connected.
  • a conductive layer is disposed on the substrate, the conductive layer is electrically connected to the second pad and the third pad, and the conductive layer is formed by a metal wire, and a line width of the metal wire The line spacing is between 20-50 microns.
  • the metal wiring has a line width and a line spacing of 30 micrometers.
  • solder bumps are further formed on the surface of the first pad and/or the third pad.
  • the material of the substrate is a transparent material.
  • the substrate is made of an opaque material, and the substrate is provided with an opening penetrating the substrate, and the opening exposes a photosensitive area of the chip to be packaged.
  • a protective layer is disposed on the fourth surface of the substrate, and the protective layer covers the open area.
  • a lens module assembly is disposed on the fourth surface of the substrate corresponding to the position of the photosensitive region.
  • the lens assembly includes a lens and a lens holder for supporting the lens.
  • the height of the second pad is greater than a sum of heights of the chip to be packaged, the first pad, and the third pad.
  • a packaging method for an image sensor package structure comprising:
  • the chip to be packaged includes a first surface and a second surface respectively located on two sides of the chip to be packaged, and the first surface is provided with a photosensitive region and a first portion around the photosensitive region a solder pad;
  • the substrate includes a third surface and a fourth surface respectively disposed on two sides of the substrate, the third surface is provided with a second pad and a third pad, and the second pad is located at the third a pad away from a side of the photosensitive region;
  • the first pad and the third pad are soldered together to package the chip to be packaged and the substrate together.
  • a conductive layer is disposed on the substrate, the conductive layer is electrically connected to the second pad and the third pad, and the conductive layer is formed by a metal wire, and a line width of the metal wire The line spacing is between 20-50 microns.
  • the metal wiring has a line width and a line spacing of 30 micrometers.
  • the material of the substrate is a transparent material.
  • the substrate is made of an opaque material, and the substrate is provided with an opening penetrating the substrate, and the opening exposes a photosensitive area of the chip to be packaged.
  • the method further includes: forming a protective layer on the fourth surface of the substrate, the protective layer covering the open area.
  • the method further includes forming a lens module assembly on a fourth surface of the substrate corresponding to the position of the photosensitive region.
  • the present invention has the following beneficial effects:
  • the signal on the chip to be packaged can be transmitted through the first pad, the third pad and the second pad, and the second pad disposed on the third surface of the substrate can
  • the solder joints on the external circuit board are electrically connected, so that the signals can be transmitted between the chip to be packaged and the external circuit board through the first pad, the third pad, and the second pad.
  • the signal transmission method does not need to etch the back surface of the packaged chip, and forms an internal extension of the chip to be packaged from the back side of the chip to be packaged.
  • the etched trench is stretched. Therefore, the wafer level image sensor package structure provided by the present invention reduces the damage rate of the chip to be packaged.
  • the packaging method provided by the present invention only needs to form a solder pad on the chip to be packaged and the substrate, and does not require an etching process and a thin film deposition process. Therefore, the packaging method provided by the present invention simplifies the packaging process and is advantageous for reducing the packaging cost.
  • FIG. 1 is a schematic diagram of a package structure of a wafer level image sensor in the prior art
  • FIG. 2 is a schematic diagram of a first image sensor package structure according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a second image sensor package structure according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a third image sensor package structure according to an embodiment of the present invention.
  • FIG. 5 is a schematic flow chart of a packaging method of an image sensor package structure according to an embodiment of the present invention.
  • the damage rate of the chip to be packaged is high.
  • the present invention provides a package structure of an image sensor, including: a chip to be packaged, the chip to be packaged includes an opposite first surface and a second surface, and the first surface is provided with a photosensitive region and a first pad located around the photosensitive region;
  • a substrate disposed on a first surface side of the chip to be packaged the substrate includes a third surface and a fourth surface respectively disposed on two sides of the substrate, wherein the third surface is provided with a second pad and a third pad; The second pad is located at a side of the third pad away from the photosensitive region; wherein a first surface of the chip to be packaged is opposite to a third surface of the substrate; the first pad and The third pad is connected.
  • the signal on the chip to be packaged can pass the a solder pad, a third pad and a second pad are transported out, and the second pad disposed on the third surface of the substrate can be electrically connected to the solder joint on the external circuit board, thereby, the chip to be packaged and the external circuit board Signal transmission can be achieved between the first pad, the third pad, and the second pad.
  • the signal transmission method does not need to etch the back surface of the packaged chip, and forms an etching groove extending from the back surface of the chip to be packaged to the inside of the chip to be packaged. Therefore, the wafer level image sensor package structure provided by the invention reduces the package to be packaged. The damage rate of the chip.
  • FIG. 2 is a cross-sectional structural diagram of an image sensor package structure according to an embodiment of the present invention. As shown in FIG. 2, the image sensor package structure includes:
  • the chip to be packaged 21 includes a first surface 21a and a second surface 21b respectively located on both sides of the chip to be packaged, and a photosensitive region 211 is disposed on the first surface 21a and is formed in the photosensitive region. a first pad 212 around 211;
  • the substrate 22 disposed on a side of the first surface 21a of the chip 21 to be packaged, the substrate 22 includes a third surface 22a and a fourth surface 22b respectively located on two sides of the substrate, and the second surface 22a is provided with a second solder a pad 221 and a third pad 222, and the second pad 221 is located on a side of the third pad 222 away from the photosensitive region 211; wherein the first surface 21a of the chip 21 to be packaged The third surface 22a of the substrate 22 is opposite; the third pad 222 is connected to the first pad 212.
  • the second pad 221 disposed on the substrate 22 is electrically connected to the circuit board 30 outside the package structure.
  • the circuit board 30 is provided with solder joints, and the second solder pads 221 can be connected to the solder joints on the circuit board 30 to realize electrical signal transmission between the chip 21 to be packaged and the external circuit board 30.
  • the circuit board 30 does not belong to the components of the image sensor package structure provided by the present invention.
  • the chip 21 to be packaged is an image sensor chip, and the image sensor may be a complementary metal oxide (CMOS) image sensor and an electronic coupling device.
  • CMOS complementary metal oxide
  • One of the (CCD) image sensors is an image sensor chip, and the image sensor may be a complementary metal oxide (CMOS) image sensor and an electronic coupling device.
  • CMOS complementary metal oxide
  • CCD complementary metal oxide
  • the photosensitive region 211 may be disposed at any position of the first surface 21a of the chip 21 to be packaged. In general, the photosensitive region 211 is disposed at a central region of the first surface 21a of the chip 21 to be packaged.
  • An image sensor unit (not shown in FIG. 2) may be formed in the photosensitive region 211 of the packaged chip 21, and a surface of the image sensor unit is formed with a microlens 213.
  • the microlens 213 is used to collect incident light that is incident on the surface of the photosensitive region 211 and is transmitted into the image sensor unit.
  • a first pad 212 is disposed around the photosensitive region 211.
  • the material of the first pad 212 is a conductive material, which may be a metal material such as Al, Au, and Cu.
  • the first pad 212 may be plural, and it may be located on at least one side of the photosensitive region 211.
  • the first pads 212 may be located on four sides of the photosensitive region 211, and the first pads 212 are distributed in a rectangular shape on the chip 21 to be packaged, and a plurality of first pads are disposed on each side.
  • Pad 212 It should be noted that the number of the first pads 212 depends on the type of chips to be packaged. In other examples, the first pad 212 is located on opposite sides of the photosensitive region 211. It should be noted that since the first pads 212 can form different distribution shapes according to different kinds of chips, the distribution position of the first pads 212 does not limit the protection range of the present invention.
  • the chip 21 to be packaged is provided with the photosensitive region 211 and the first pad 212 located around the photosensitive region 211. It is also possible to have a driving unit (not shown in FIG. 2) for driving the chip, a reading unit (not shown in FIG. 2) for acquiring the photosensitive region current, and a processing unit for processing the photosensitive region current (in FIG. 2). Not shown).
  • a driving unit not shown in FIG. 2 for driving the chip
  • a reading unit not shown in FIG. 2
  • a processing unit for processing the photosensitive region current (in FIG. 2).
  • other components may be included on the chip to be packaged 21, and since these components are not closely related to the inventive point of the present invention, they will not be described in detail herein.
  • the material of the substrate 22 may be a transparent material or an opaque material.
  • the material of the substrate 22 can be the same as the material of the circuit board 30.
  • the substrate 22 may be made of plastic material or metal copper.
  • the substrate 22 may be made of glass.
  • the substrate 22 is provided with an opening 223 penetrating both surfaces of the substrate 22.
  • the opening 223 is capable of exposing the photosensitive region 211 of the chip 21 to be packaged.
  • the position of the opening 223 may correspond to the position of the photosensitive region 211.
  • the size of the opening 223 may be greater than or equal to the size of the photosensitive region 211. With the opening 223, light can be directly incident on the photosensitive region 211 surface.
  • the third pad 222 may be located around the opening 223, and the second pad 221 is located on a side of the third pad 222 away from the photosensitive region 211.
  • a conductive layer (not shown in FIG. 2) is disposed on the substrate 22, and the conductive layer may be composed of a metal wiring.
  • the line width and the line pitch of the metal wiring on the substrate 22 are small, for example, may be between 20-50 microns, more specifically, on the substrate 22.
  • the metal wiring has a line width and a line spacing of 30 microns. Compared with the line width and line spacing of about 100 micrometers used in the prior art, the size of the image sensor package structure provided by the present invention is about 2/3 smaller than that of the prior art package structure. Therefore, the image sensor package structure provided by the present invention makes the fabricated device more compact.
  • the size of the substrate 22 is generally larger than the size of the chip 21 to be packaged, and in the image sensor package structure provided by the embodiment of the present invention, the second pad 221 is further outward relative to the chip 21 to be packaged.
  • the second pad 221 is connected to the circuit board 30, the chip 21 to be packaged is wrapped between the circuit board 30 and the substrate 22, so that the chip to be packaged is wrapped around the substrate 22 and the circuit board 30. Therefore, the substrate 22 and the circuit board 30 can form a protection for the chip to be packaged, so that the breakage of the chip 21 to be packaged can be avoided.
  • the second pad 221 may be a metal solder ball.
  • the material of the second pad 221 may be a metal solder material commonly used in the art, such as metal tin. It should be noted that there may be a plurality of second pads 221 which may be distributed in a rectangular shape on the substrate 22 or in a straight line parallel to each other.
  • the third pad 222 may be a metal bump.
  • the metal material may be Al, Au or Cu.
  • the position of the third pad 222 on the substrate corresponds to the position of the first pad 212 on the chip to be packaged.
  • the third pads 222 are also distributed in a rectangular shape on the substrate 22.
  • the number of the third pads 222 is the same as the number of the first pads 212.
  • solder bumps 224 may be formed on the surface of the third pad 222.
  • the solder bumps 224 are used for bonding with the first pads 212 to solder the first pads 212 and the second pads 222 together, thereby encapsulating the substrate 22 and the chip 21 to be packaged together.
  • the material for forming the solder bumps 224 is related to the material of the first pad 212 and the bonding process of the two.
  • the material of the first pad 212 is Al
  • the material of the solder bump 224 is Au
  • the bonding process is ultrasonic hot pressing
  • the material of the first pad 212 is Au
  • the material of 224 is Sn
  • the joining process is a eutectic bonding method.
  • solder bumps may also be formed on the surface of the first pad 212. At this time, the solder bumps may not be formed on the surface of the third pad 222. Solder bumps on the surface of the pad 212 solder the first pad 212 and the third pad 222 together. The solder bumps formed on the surface of the first pad 212 are related to the material and the material of the third pad 222 and the bonding process of the two.
  • the connection process is ultrasonic hot pressing mode; when the material of the third pad 222 is Au, the solder bump The material of 224 is Sn, and the joining process is a eutectic bonding method.
  • the circuit board 30 may be a rigid printed circuit board PCB board or a flexible circuit board FPC. It should be noted that a plurality of solder joints are disposed on the circuit board 30, and the second solder pads 221 disposed on the substrate 22 are connected to the solder joints on the circuit board 30, so that the packaged chips 21 and 22 to be packaged are to be packaged. It is connected to the circuit board 30.
  • the chip 21 to be packaged and the circuit board 30 are transferred between the first pad 212, the solder bump 224, the third pad 222, the conductive layer, and the second pad 221. electric signal.
  • the signal transmission method does not need to etch the back surface of the packaged chip, and forms an etching groove extending from the back surface of the chip to be packaged to the inside of the chip to be packaged. Therefore, the wafer level image sensor package structure provided by the invention reduces the package to be packaged. The damage rate of the chip.
  • the first pad 212 disposed on the chip 21 to be packaged is generally a pad protruding from the first surface 21a, and the third pad 222 disposed on the substrate 22 is formed by the third surface 22a. Protruding pads.
  • the distance between the circuit board 30 and the substrate 22 should be not less than the first pad 212, the third pad 222, the chip to be packaged 21, and the circuit board 30. The sum of the heights of the solder joints on the top.
  • the sum of the height of the second pad 221 and the height of the solder joint on the circuit board 30 is not less than the chip to be packaged 21, the first pad 212, and the third pad 222.
  • the difference between the height of the second pad 221 and the heights of the chip to be packaged 21, the first pad 212, and the third pad 222 is not less than 100 micrometers.
  • a protective layer 23 for protecting the photosensitive region 211 is further provided on the fourth surface of the substrate 22.
  • the protective layer 23 can be a plastic film or a glass layer. It should be noted that when the substrate 22 is provided with the opening 223, the protective layer 23 also covers the surface area of the opening 223.
  • the lens module assembly may be assembled directly on the protective layer 23, or the protective layer 23 may be removed on the fourth surface of the substrate 22. Assemble the lens module assembly.
  • the protective layer 23 is an opaque material layer, the opaque material layer needs to be removed before the lens module assembly is assembled, and the lens module assembly is assembled on the fourth surface of the substrate 22 corresponding to the photosensitive region.
  • the substrate 22 is an opaque substrate.
  • the substrate 22 may also be a transparent substrate such as a glass substrate.
  • the substrate 22 is a transparent substrate, since light energy passes through the transparent substrate and reaches the photosensitive region 211, at this time, an opening may not be provided on the substrate.
  • the schematic diagram of the image sensor package structure is shown in FIG.
  • the image sensor package structure shown in FIG. 3 is substantially the same as the image sensor package structure shown in FIG. 2, except that the substrate 22' shown in FIG. 3 is a transparent substrate, and the photosensitive region 211 is not disposed thereon.
  • 22'a and 22'b denote the third surface and the fourth surface of the substrate 22', respectively.
  • 221' denotes a second pad disposed on the third surface of the substrate 22'
  • 222' denotes a third pad disposed on the third surface of the substrate 22'
  • 224' denotes the third pad Solder bumps on pad 222'.
  • an opening may be provided on the transparent substrate, and the image sensor package structure is the same as that shown in FIG. 2 .
  • the lens module assembly is not disposed on the fourth surface of the substrate 22.
  • a lens module assembly is disposed on a fourth surface of the substrate corresponding to the position of the photosensitive region, so that Eliminate the process of assembling the lens module assembly. See Figure 4 for details.
  • FIG. 4 is an improvement based on the image sensor package structure shown in FIG. 2.
  • the image sensor package structure shown in FIG. 4 has many similarities with the image sensor package structure shown in FIG. For the sake of brevity, only the differences are described here, and the similarities are shown in the related description of FIG. 2.
  • the image sensor package structure shown in FIG. 4 includes, in addition to the components shown in FIG. 2, the following:
  • the position of the lens 41 corresponds to the position of the opening 223, and the size of the lens 41 is greater than or equal to the size of the opening 223, so that external light can be transmitted through the lens to the surface of the photosensitive area 211 of the image sensor. If the substrate 22 is a transparent substrate and no opening is provided thereon, the size of the lens 41 at this time is greater than or equal to the size of the photosensitive region 211.
  • the protective layer 23 shown in FIG. 2 is not included in the image sensor package structure shown in FIG. 4.
  • the lens module assembly 40 may also be formed directly above the protective layer, which will not be described in detail herein.
  • other devices such as resistors, inductors, capacitors, integrated circuit blocks, or optical components may be present on the fourth surface of the substrate 22.
  • the specific device type may be selected according to the substrate and the type of chip to be packaged.
  • the lens holder 42 and the opening edge have a certain lateral distance
  • the substrate 22 has a certain longitudinal distance from the lens 41. Therefore, the lens holder 42 and the substrate 22 are Other devices may be formed on the fourth surface of the substrate 22 between the other, which are capable of forming a high-density stacked structure between the lens holder 42 and the substrate 22, thereby facilitating miniaturization of the device.
  • an optical component such as a polarizer, an infrared filter, or the like may be formed between the lens 41 and the opening 223 for improving the image quality of the image sensor.
  • the embodiment of the present invention further provides a package method of the image sensor package structure. See Figure 5 for details.
  • FIG. 5 is a schematic flow chart of a packaging method of an image sensor package structure according to an embodiment of the present invention. As shown in FIG. 5, the encapsulation method includes the following steps:
  • the chip to be packaged includes a first surface and a second surface respectively located on two sides of the chip to be packaged, and the photosensitive surface is disposed on the first surface and is located around the photosensitive region a first pad;
  • the substrate includes a third surface and a fourth surface respectively disposed on two sides of the substrate, the third surface is provided with a second pad and a third pad, and the second pad is located at the The third pad is away from a side of the photosensitive region;
  • the chip to be packaged 21 includes an opposite first surface 21a and a second surface 21b, on the first surface is provided with a photosensitive region 211 and a first pad 212 around the photosensitive region 211;
  • An image sensor unit (not shown in FIG. 2) is disposed in the photosensitive region 211, and a surface of the image sensor unit is formed with a microlens 213.
  • the microlens 213 is used to collect incident light that is incident on the surface of the photosensitive region 110 and is transmitted into the image sensor unit.
  • the substrate 22 includes a third surface 22a and a fourth surface 22b respectively located on both sides of the substrate, and a second pad 221 and a third pad 223 are formed on the third surface 22a.
  • the material of the substrate 22 may be a transparent material or an opaque material.
  • the substrate 22 is further provided with an opening 223 penetrating the two surfaces, the opening 223 being capable of exposing the photosensitive region of the packaged chip to be packaged.
  • a conductive layer is disposed on the substrate, and the conductive layer is composed of a metal wiring having a line width and a line pitch of 20-50 micrometers. between. Further, the metal wiring has a line width and a line pitch of 30 ⁇ m.
  • the first pad 212 and the third pad 222 are also automatically aligned.
  • the soldering is to solder the first pad 212 and the third pad 222 together by solder bumps 224 formed on the surface of the first pad 212 or the third pad 222.
  • the welding method includes eutectic bonding, ultrasonic hot pressing, hot press welding, and ultrasonic pressure welding.
  • the image sensor package structure according to the embodiment of the present invention can be formed. Since the packaging method provided by the present invention only needs to form a solder pad on the chip to be packaged and the substrate, and does not require an etching process and a thin film deposition process, the packaging method provided by the present invention simplifies the packaging process and is advantageous for reducing the packaging cost.
  • a second pad on the packaged substrate may be soldered to the circuit board.
  • the circuit board according to the embodiment of the present invention may be a circuit board conventionally used in the art, and the circuit board may be a rigid printed circuit board or a flexible circuit board.
  • the foregoing packaging method may further include the following steps:
  • a protective layer 23 is formed on the fourth surface 22b of the substrate 22, and when an opening is provided on the substrate, the protective layer covers the open area.
  • the protective layer 23 may be a plastic film or a glass layer.
  • step S504 is not limited. It may be performed before or after encapsulation of the package chip 21 and the substrate 22. As an example, the embodiment of the present invention performs step S504 after the package 21 and the substrate 22 are packaged.
  • the packaging method described above may further include the following steps, so that the formed package structure has a lens module assembly.
  • a lens module assembly 40 is formed on a fourth surface 22b of the substrate 22 corresponding to the position of the photosensitive region, the lens module assembly 40 including a lens 41 and a lens holder 42 for supporting the lens 41.
  • the position of the lens 41 corresponds to the position of the opening 223, and the size of the lens 41 is greater than or equal to the size of the opening 223, so that external light can be transmitted through the lens to the surface of the photosensitive area 211 of the image sensor. If the substrate 22 is a transparent substrate and no opening is provided thereon, the size of the lens 41 at this time is greater than or equal to the size of the photosensitive region 211.

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Abstract

一种影像传感器封装结构及其封装方法，封装结构包括：待封装芯片（21），待封装芯片（21）包括分别位于待封装芯片（21）两侧的第一表面（21a）和第二表面（21b），在第一表面（21a）上设置有感光区（211）以及位于感光区（211）周围的第一焊垫（212）；设置于待封装芯片（21）第一表面侧（21a）的基板（22），基板（22）包括分别位于基板（22）两侧的第三表面（22a）和第四表面（22b），第三表面（22a）上设置有第二焊垫（221）和第三焊垫（222）；第二焊垫（221）位于第三焊垫（222）远离所述感光区（211）的一侧；待封装芯片（21）的第一表面（21a）和基板的第三表面（22a）相对；第一焊垫（212）和第三焊垫（222）连接在一起。该影像传感器封装结构形成了对待封装芯片很好的保护，能够防止待封装芯片的断裂。

Description

影像传感器封装结构及其封装方法
本申请要求于2015年8月28日提交中国专利局,申请号为201510540994.0,发明名称为“影像传感器封装结构及其封装方法”的中国专利申请的优先权，要求于2015年8月28日提交中国专利局，申请号为201520662836.8,发明名称为“影像传感器封装结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体芯片封装领域，尤其涉及一种影像传感器的封装结构及其封装方法。
背景技术
传统的影像传感器封装结构通常采用引线键合(Wire Bonding)进行封装，但随着集成电路的飞速发展，较长的引线使得产品尺寸无法达到理想要求。随着技术的发展，晶圆级封装逐渐取代引线键合封装，且晶圆级封装是目前较为常用的封装方法。
现有的晶圆级封装结构如图1所示。其包括待封装芯片200和覆盖层300。其中，在待封装芯片200的第一表面200a上形成有微透镜211，并且在待封装芯片200靠近第一表面200a的内部形成有焊垫212。在待封装芯片200的第一表面200a以及覆盖层300的第一表面300a之间设置有支撑结构320。支撑结构320的表面涂布有粘合胶，用于粘接覆盖层300和待封装芯片200。在待封装芯片200与覆盖层300粘接后，在微透镜211上方与覆盖层300之间形成空腔310。
为了能够将待封装芯片200与外部的电路板实现电连接，在待封装芯片200的第二表面200b形成有多个刻蚀槽215，该刻蚀槽215的底部与焊垫212导通。在刻蚀槽215表面上形成有绝缘层213以及导电层214，并且在导电层214上形成焊点216，焊点216与外部电路板上的焊点实现电连接，如此，就能够将待封装芯片200与外部电路板实现电连接。
然而，现有的晶圆级封装结构需要在待封装芯片上进行刻蚀工艺，增加 了待封装芯片的损坏率，而且，由于该封装结构需要刻蚀工艺和薄膜淀积工艺，其工序较为繁琐并且封装成本较高。
发明内容
有鉴于此，本发明的第一方面提供了一种影像传感器封装结构，以降低待封装芯片的损坏率。
本发明的第二方面提供了一种影像传感器封装结构的封装方法，以简化封装工序，降低封装成本。
为了达到上述发明目的，本发明采用了如下技术方案：
一种影像传感器封装结构，包括：
待封装芯片，所述待封装芯片包括分别位于待封装芯片两侧的第一表面和第二表面，在所述第一表面上设置有感光区以及位于所述感光区周围的第一焊垫；
设置于所述待封装芯片第一表面侧的基板，所述基板包括分别位于基板两侧的第三表面和第四表面，所述第三表面上设置有第二焊垫和第三焊垫；所述第二焊垫位于所述第三焊垫远离所述感光区的一侧；其中，所述待封装芯片的第一表面和所述基板的第三表面相对；所述第一焊垫和所述第三焊垫连接。
可选的，所述基板上设置有导电层，所述导电层与所述第二焊垫和所述第三焊垫电连接，所述导电层由金属布线构成，所述金属布线的线宽和线间距在20-50微米之间。
可选的，所述金属布线的线宽和线间距为30微米。
可选的，所述第一焊垫和/或所述第三焊垫的表面上还形成有焊接凸点。
可选的，所述基板的材质为透明材质。
可选的，所述基板的材质为不透光材质，所述基板上设置有贯穿所述基板的开口，所述开口暴露出所述待封装芯片的感光区。
可选的，所述基板的第四表面上设置有保护层，所述保护层覆盖开口区域。
可选的，所述基板的第四表面上对应所述感光区的位置设置有镜头模组组件。
可选的，所述镜头组件包括透镜和用于支撑所述透镜的透镜支架。
可选的，所述第二焊垫的高度大于所述待封装芯片、所述第一焊垫以及所述第三焊垫的高度之和。
一种影像传感器封装结构的封装方法，包括：
提供待封装芯片和基板；所述待封装芯片包括分别位于待封装芯片两侧的第一表面和第二表面，在所述第一表面上设置有感光区以及位于所述感光区周围的第一焊垫；所述基板包括分别位于基板两侧的第三表面和第四表面，所述第三表面上设置有第二焊垫和第三焊垫，所述第二焊垫位于所述第三焊垫远离所述感光区的一侧；
按照所述第一表面和第三表面相对的方式放置所述待封装芯片和所述基板，且使所述第一焊垫和所述第三焊垫对准；
将所述第一焊垫和所述第三焊垫焊接在一起，从而将所述待封装芯片和所述基板封装在一起。
可选的，所述基板上设置有导电层，所述导电层与所述第二焊垫和所述第三焊垫电连接，所述导电层由金属布线构成，所述金属布线的线宽和线间距在20-50微米之间。
可选的，所述金属布线的线宽和线间距为30微米。
可选的，所述基板的材质为透明材质。
可选的，所述基板的材质为不透光材质，所述基板上设置有贯穿所述基板的开口，所述开口暴露出所述待封装芯片的感光区。
可选的，还包括：在所述基板的第四表面上形成保护层，所述保护层覆盖开口区域。
可选的，还包括：在所述基板的第四表面上对应所述感光区的位置形成镜头模组组件。
相较于现有技术，本发明具有以下有益效果：
本发明提供的影像传感器封装结构中，待封装芯片上的信号能够通过第一焊垫、第三焊垫以及第二焊垫传输出去，并且设置在基板第三表面上的第二焊垫能够与外部电路板上的焊点电连接，因而，待封装芯片与外部电路板之间可以通过第一焊垫、第三焊垫和第二焊垫实现信号的传输。这种信号传输方式无需对待封装芯片的背面进行刻蚀，形成自待封装芯片背面向待封装芯片内部延 伸的刻蚀槽，所以，本发明提供的晶圆级影像传感器封装结构，降低了待封装芯片的损坏率。
此外，本发明提供的封装方法只需在待封装芯片和基板上形成焊垫，无需刻蚀工艺和薄膜淀积工艺，所以，本发明提供的封装方法简化了封装工序，有利于降低封装成本。
附图说明
为了清楚地理解本发明和现有技术的方案，下面将描述本发明和现有技术的技术方案所用到的附图做一简要说明。显而易见地，这些附图仅是本发明的部分实施例，本领域技术人员在未付出创造性劳动的前提下，还可以获得其它附图。
图1是现有技术中晶圆级影像传感器封装结构示意图；
图2是本发明实施例提供的第一种影像传感器封装结构示意图；
图3是本发明实施例提供的第二种影像传感器封装结构示意图；
图4是本发明实施例提供的第三种影像传感器封装结构示意图；
图5是本发明实施例提供的影像传感器封装结构的封装方法流程示意图。
具体实施方式
下面结合附图对本发明的具体实施方式进行详细描述。
正如背景技术部分所述，现有技术中的晶圆级影像传感器的封装结构中，其待封装芯片的损坏率较高。
本发明为了解决上述技术问题，提供了一种影像传感器的封装结构，其包括：待封装芯片，所述待封装芯片包括相对的第一表面和第二表面，在所述第一表面上设置有感光区以及位于所述感光区周围的第一焊垫；
设置于所述待封装芯片第一表面侧的基板，所述基板包括分别位于基板两侧的第三表面和第四表面，所述第三表面上设置有第二焊垫和第三焊垫；所述第二焊垫位于所述第三焊垫远离所述感光区的一侧；其中，所述待封装芯片的第一表面和所述基板的第三表面相对；所述第一焊垫和所述第三焊垫连接。
在本发明提供的影像传感器封装结构中，待封装芯片上的信号能够通过第 一焊垫、第三焊垫以及第二焊垫传输出去，并且设置在基板第三表面上的第二焊垫能够与外部电路板上的焊点电连接，因而，待封装芯片与外部电路板之间可以通过第一焊垫、第三焊垫和第二焊垫实现信号的传输。这种信号传输方式无需对待封装芯片的背面进行刻蚀，形成自待封装芯片背面向待封装芯片内部延伸的刻蚀槽，所以，本发明提供的晶圆级影像传感器封装结构，降低了待封装芯片的损坏率。
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。在详述本发明实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明的保护范围。此外，在实际制作中应包含长度、宽度及深度的三围空间尺寸。
请参考图2。图2是本发明实施例提供的一种影像传感器封装结构的剖面结构示意图。如图2所示，该影像传感器封装结构包括：
待封装芯片21，所述待封装芯片21包括分别位于待封装芯片两侧的第一表面21a和第二表面21b，在所述第一表面21a上设置有感光区211以及形成于所述感光区211周围的第一焊垫212；
设置于所述待封装芯片21第一表面21a侧的基板22，所述基板22包括分别位于基板两侧的第三表面22a和第四表面22b，所述第三表面22a上设置有第二焊垫221和第三焊垫222，且所述第二焊垫221位于所述第三焊垫222远离所述感光区211的一侧；其中，所述待封装芯片21的第一表面21a和所述基板22的第三表面22a相对；所述第三焊垫222与所述第一焊垫212连接在一起。
需要说明的是，设置在基板22上的第二焊垫221用于与封装结构外部的电路板30电连接。具体地，电路板30上设置有焊点，第二焊垫221可以与电路板30上的焊点连接，从而实现待封装芯片21与外部电路板30之间的电信号传输。需要进一步说明的是，电路板30不属于本发明提供的影像传感器封装结构的部件。
待封装芯片在本发明实施例中，待封装芯片21为影像传感器芯片，所述影像传感器可以为互补金属氧化物(CMOS)影像传感器和电子耦合器件 (CCD)影像传感器其中的一种。
感光区211可以设置在待封装芯片21第一表面21a的任一位置，通常情况下，感光区211设置在待封装芯片21第一表面21a的中心区域。
待封装芯片21的感光区211内还可以形成有影像传感器单元(图2中未示出)，该影像传感器单元的表面形成有微透镜213。所述微透镜213用于汇集照射到感光区211表面的入射光并传递到图像传感器单元内。
所述感光区211的周围设置有第一焊垫212。所述第一焊垫212的材料为导电材料，其可以为金属材料，如Al、Au和Cu。具体地说，第一焊垫212可以为多个，其可以位于感光区211的至少一个侧边上。作为其中一个示例，第一焊垫212可以位于感光区211的四个侧边上，并且第一焊垫212在待封装芯片21上呈矩形分布，每一侧边上设置有若干个第一焊垫212。需要说明的是，第一焊垫212的数量多少取决于待封装芯片的类型。在其它示例中，第一焊垫212位于感光区211相对的两条侧边上。需要说明的是，由于第一焊垫212可以根据不同种类的芯片形成不同的分布形状，所以，第一焊垫212的分布位置不限制本发明的保护范围。
需要说明的是，作为一个完整的待封装芯片，在本发明实施例中，待封装芯片21上除了设置有上述所述的感光区211和位于感光区211周围的第一焊垫212之外，还可以在其上设置有用于驱动芯片的驱动单元(图2中未示出)、获取感光区电流的读取单元(图2中未示出)、处理感光区电流的处理单元(图2中未示出)。此外，待封装芯片21上还可以包括其它部件，由于这些部件与本发明的发明点关系不密切，所以，在此不作详细描述。
在本发明实施例中，基板22的材质可以为透明材质，也可以为不透光材质。具体到基板22的材质，其可以与电路板30材质相同。例如基板22可以为塑胶材质或金属铜材质。此外，基板22也可以为玻璃材质。为了使得光能够达到待封装芯片的感光区211，当基板22的材质为不透光材质时，如图2所示，基板22上设置有贯穿所述基板22两表面的开口223。该开口223能够暴露出所述待封装芯片21的感光区211。作为本发明的一个具体实施例，开口223的位置可以与所述感光区211的位置相对应。而且，开口223的尺寸可以大于或等于感光区211的尺寸。利用该开口223，光可以直接入射到感光区 211表面。在该实施例中，第三焊垫222可以位于开口223的周围，第二焊垫221位于第三焊垫222远离感光区211的一侧。
为了能够将待封装芯片21上的电路与外围电路实现电连接，基板22上设置有导电层(图2中未示出)，该导电层可以由金属布线构成。为了减小影像传感器封装结构的尺寸，在本发明实施例中，基板22上的金属布线的线宽和线间距较小，例如可以在20-50微米之间，更具体地说，基板22上的金属布线的线宽和线间距为30微米。相较于现有技术中采用的100微米左右的线宽和线间距，本发明提供的影像传感器封装结构的尺寸比现有技术中的封装结构缩小2/3左右。因此，本发明提供的影像传感器封装结构使得制成的器件更加小型化。
需要说明的是，基板22的尺寸通常大于待封装芯片21的尺寸，并且在本发明实施例提供的影像传感器封装结构中，第二焊垫221相对于所述待封装芯片21更靠外。如此，当第二焊垫221与电路板30连接在一起后，就将待封装芯片21包裹在电路板30和基板22之间，如此，待封装芯片就被包裹在基板22和电路板30之间，因此，基板22和电路板30能够形成对待封装芯片的保护，如此可以避免待封装芯片21的断裂。
作为示例，第二焊垫221可以为金属焊球。该第二焊垫221的材料可以采用本领域惯用的金属焊接材料，如金属锡。需要说明的是，可以存在多个第二焊垫221，其在基板22上可以呈矩形分布，也可以呈两条相互平行的直线形分布。
在本发明实施例中，第三焊垫222可以为金属凸块。其金属材料可以为Al、Au或Cu。需要说明的是，第三焊垫222在基板上的位置与所述第一焊垫212在待封装芯片上的位置相对应。当第一焊垫212在待封装芯片21上呈矩形分布时，第三焊垫222在基板22上也呈矩形分布。并且，第三焊垫222的数量与第一焊垫212的数量相同。
需要说明的是，为了实现与待封装芯片21上的第一焊垫212的焊接，该第三焊垫222的表面上可以形成有焊接凸点224。该焊接凸点224用于与第一焊垫212的结合，从而将第一焊垫212和第二焊垫222焊接在一起，进而将基板22和待封装芯片21的封装在一起。
在本发明实施例中，用于形成焊接凸点224的材料与第一焊垫212的材料和两者的连接工艺相关。当第一焊垫212的材料为Al时，所述焊接凸点224的材料为Au，连接工艺为超声热压方式；当所述第一焊垫212的材料为Au时，所述焊接凸点224的材料为Sn，连接工艺为共晶键合方式。
作为本发明实施例的变型，焊接凸点也可以形成在第一焊垫212的表面上，此时，第三焊垫222表面上可以不形成有焊接凸点，此时，通过形成在第一焊垫212表面上的焊接凸点将第一焊垫212和第三焊垫222焊接在一起。形成于第一焊垫212表面上的焊接凸点与材料与第三焊垫222的材料和两者的连接工艺相关。当第三焊垫222的材料为Al时，所述焊接凸点224的材料为Au，连接工艺为超声热压方式；当所述第三焊垫222的材料为Au时，所述焊接凸点224的材料为Sn，连接工艺为共晶键合方式。
在本发明实施例中，电路板30可以为硬性印刷电路板PCB板也可以为柔性电路板FPC。需要说明的是，电路板30上设置有很多焊点，设置在所述基板22上的第二焊垫221与电路板30上的焊点连接，从而将封装后的待封装芯片21和基板22与电路板30连接在一起。
需要说明的是，在该影像传感器封装结构中，待封装芯片21与电路板30之间通过第一焊垫212、焊接凸点224、第三焊垫222、导电层以及第二焊垫221传送电信号。这种信号传输方式无需对待封装芯片的背面进行刻蚀，形成自待封装芯片背面向待封装芯片内部延伸的刻蚀槽，所以，本发明提供的晶圆级影像传感器封装结构，降低了待封装芯片的损坏率。
在本发明实施例中，设置于待封装芯片21上的第一焊垫212通常为由第一表面21a凸出的焊垫，设置于基板22上的第三焊垫222为由第三表面22a凸出的焊垫。另外，为了使得电路板30能够保护封装新片21的第二表面，电路板30与基板22之间的距离应不小于第一焊垫212、第三焊垫222、待封装芯片21以及电路板30上的焊点的高度之和。如此，在本发明实施例中，第二焊垫221的高度和电路板30上的焊点的高度之和不小于待封装芯片21、所述第一焊垫212以及所述第三焊垫222的高度之和。而且，第二焊垫221的高度与所述待封装芯片21、所述第一焊垫212以及所述第三焊垫222的高度之和相比，其差值不小于100微米。
作为本发明的可选实施例，为了防止感光区被外界污染，如图2所示，在基板22的第四表面上还设置有用于保护感光区211的保护层23。该保护层23可以为塑料薄膜或玻璃层。需要说明的是，当基板22上设置有开口223时，该保护层23还覆盖该开口223表面区域。
需要说明的是，当保护层23为透明材料层时，在后续组装镜头模组组件时，可以直接在该保护层23上组装，也可以将该保护层23去除，在基板22的第四表面上组装镜头模组组件。但是，当保护层23为不透明材料层时，在后续组装镜头模组组件之前，需要先去除该不透明材料层，在基板22的第四表面上对应感光区的位置组装镜头模组组件。
此外，需要说明的是，当开口223上方不覆盖有保护层23时，形成的图像传感器不会出现色差或鬼影等光学现象，所以，在后续组装镜头模组组件时，最好去除掉保护层或玻璃层，这样有利于提高影像传感器的影像质量。
需要说明的是，图2所示的影像传感器封装结构中，其基板22为不透明基板。作为本发明的另一实施例，基板22也可以采用透明基板，如采用玻璃基板。当基板22为透明基板时，由于光能透过透明基板到达感光区211，所以，此时，在基板上可以不设置有开口。该影像传感器封装结构示意图如图3所示。
图3所示的影像传感器封装结构与图2所示的影像传感器封装结构基本相同，其不同之处仅在于图3所示的基板22’为透明基板，其上未设置有与感光区211对应的开口。在图3中，22’a和22’b分别表示基板22’的第三表面和第四表面。221’表示设置在所述基板22’第三表面上的第二焊垫,222’表示设置在所述基板22’第三表面上的第三焊垫，224’表示设置在所述第三焊垫222’上的焊接凸点。
需要说明的是，作为本发明实施例的扩展，也可以在透明基板上设置有开口，此时影像传感器封装结构与图2所示的结构相同。
需要说明的是，图2和图3所示的影像传感器封装结构，在基板22的第四表面上不设置有镜头模组组件。为了制作成影像器件，需要在制作影像器件时将镜头模组组件安装在基板22的第四表面上对应所述感光区的位置。
作为本发明的另一实施例，还可以在图2和图3所示的影像传感器封装结构中，在其基板的第四表面上对应所述感光区的位置设置有镜头模组组件，如此可以免去后续组装镜头模组组件的过程。具体参见图4。
需要说明的是，图4是在图2所示的影像传感器封装结构的基础上进行的改进，图4所示的影像传感器封装结构与图2所示的影像传感器封装结构有诸多相似之处，为了简要起见，在此仅着重描述其不同之处，其相似之处请参见图2的相关描述。
如图4所示的影像传感器封装结构，除了具有图2所示的各个部件以外，还包括：
设置在所述基板22第四表面上对应所述感光区的位置的镜头模组组件40，所述镜头模组组件40包括透镜41和用于支撑透镜41的透镜支架42。其中，透镜41的位置与所述开口223的位置相对应，且透镜41的尺寸大于或等于开口223的尺寸，使得外界光能透过透镜照射到影像传感器的感光区211表面。若基板22为透明基板且其上不设置有开口时，此时透镜41的尺寸大于或等于感光区211的尺寸。
需要说明的是，图4所示的影像传感器封装结构中不包括图2所示的保护层23。作为本发明实施例的扩展，当设置在基板第四表面上方的保护层为透明材料层时，也可以直接在该保护层的上方形成镜头模组组件40，在此不再详细描述。
在其它实施例中，在基板22的第四表面上还可以具有其它器件，如电阻、电感、电容、集成电路块或光学组件等，具体器件类型可根据基板和待封装芯片的类型进行选择。
另外，当透镜41的尺寸大于开口的尺寸时，透镜支架42和开口边缘有一定的横向距离，且所述基板22与透镜41之间有一定的纵向距离，因此，在透镜支架42和基板22之间的基板22第四表面上可以形成其它器件，该其它器件能够在透镜支架42和基板22之间形成高密度堆叠结构，从而有利于器件的小型化。此外，在透镜41和开口223之间还可以形成光学组件，例如偏振镜、红外线滤镜等，用于提高图像传感器的成像质量。
以上为本发明实施例提供的影像传感器封装结构的具体实施方式。
基于上述实施例提供的影像传感器封装结构，相应地，本发明实施例还提供了影像传感器封装结构的封装方法。具体参见图5。
图5是本发明实施例提供的影像传感器封装结构的封装方法流程示意图。如图5所示，该封装方法包括以下步骤：
S501、提供待封装芯片和基板，所述待封装芯片包括分别位于待封装芯片两侧的第一表面和第二表面，在所述第一表面上设置有感光区以及位于所述感光区周围的第一焊垫；所述基板包括分别位于基板两侧的第三表面和第四表面，所述第三表面上设置有第二焊垫和第三焊垫，所述第二焊垫位于所述第三焊垫远离所述感光区的一侧；
如图2所示，待封装芯片21包括相对的第一表面21a和第二表面21b，在所述第一表面上设置有感光区211以及位于所述感光区211周围的第一焊垫212；在感光区211内设置有影像传感器单元(图2中未示出)，该影像传感器单元的表面形成有微透镜213。所述微透镜213用于汇集照射到感光区110表面的入射光并传递到图像传感器单元内。
继续如图2所示，基板22包括分别位于基板两侧的第三表面22a和第四表面22b，在第三表面22a上形成有第二焊垫221和第三焊垫223。所述基板22的材质可以为透明材质，也可以为不透明材质。当基板22为不透明材质时，为了使光能够入射到待封装芯片的感光区，基板22上还设置有贯穿两表面的开口223，该开口223能够暴露出封装后的待封装芯片的感光区。
为了实现第二焊垫221与第三焊垫230的电连接，所述基板上设置有导电层，所述导电层由金属布线构成，所述金属布线的线宽和线间距在20-50微米之间。更进一步地，所述金属布线的线宽和线间距为30微米。
S502、按照所述第一表面和第三表面相对的方式放置所述待封装芯片和所述基板，且使所述第一焊垫和所述第三焊垫对准；
需要说明的是，为了使得第一焊垫和第三焊垫较为容易地实现对准，在基板22上可以设置有对准标记。具体地说，该对准标记可以为形成于第三表面22a上的待封装芯片位置标记。并且该待封装芯片位置标记的形状与待封装芯片的形状相似，其尺寸等于或略大于待封装芯片的尺寸。例如，当待封装芯片的形状为正方形时，则对应的形成于基板22上的待封装芯片位置标记也为正 方形。
当将待封装芯片21放置在基板22上的待封装芯片位置标记上后，第一焊垫212和第三焊垫222也就自动对准。
作为本发明实施例的扩展，也可以在待封装芯片和基板上形成相互配合的对准标记，当待封装芯片上的对准标记与基板上的对准标记配合对准后，也就实现了第一焊垫212和第三焊垫222的对准。
S503、将所述第一焊垫和所述第三焊垫焊接在一起，从而将所述待封装芯片和所述基板封装在一起；
所述焊接是通过形成于第一焊垫212或第三焊垫222表面上的焊接凸点224将第一焊垫212和第三焊垫222焊接在一起。所述焊接方式包括共晶键合、超声热压、热压焊接和超声波压焊等。
通过以上步骤即可形成本发明实施例所述的影像传感器封装结构。由于本发明提供的封装方法只需在待封装芯片和基板上形成焊垫，无需刻蚀工艺和薄膜淀积工艺，所以，本发明提供的封装方法简化了封装工序，有利于降低封装成本。
另外，为了实现封装结构与电路板的电连接，还可以将封装后的基板上的第二焊垫焊接在所述电路板上。需要说明的是，本发明实施例所述的电路板可以为本领域惯用的电路板，并且该电路板可以为硬性的印刷电路板，也可以为柔性电路板。
为了防止上述形成的影像传感器封装结构的感光区被外界污染，作为本发明的可选实施例，上述封装方法还可以包括以下步骤：
S504、在所述基板的第四表面上形成保护层，当所述基板上设置有开口时，所述保护层覆盖开口区域：
具体地，继续如图2所示，在基板22的第四表面22b上形成保护层23，并且当所述基板上设置有开口时，该保护层覆盖开口区域。需要说明的是，该保护层23可以为塑料薄膜或玻璃层。
需要说明的是，在本发明实施例中，对步骤S504的执行顺序不做限定。其可以在封装芯片21和基板22封装之前执行，也可以在其之后执行。作为示例，本发明实施例在待封装芯片21和基板22封装之后执行步骤S504。
此外，作为本发明的另一实施例，上述所述的封装方法还可以包括以下步骤，以使形成的封装结构具有镜头模组组件。
S505、在所述基板的第四表面上对应所述感光区的位置形成镜头模组组件：
如图4所示，在基板22的第四表面22b上对应所述感光区的位置形成镜头模组组件40，所述镜头模组组件40包括透镜41和用于支撑透镜41的透镜支架42。其中，透镜41的位置与所述开口223的位置相对应，且透镜41的尺寸大于或等于开口223的尺寸，使得外界光能透过透镜照射到影像传感器的感光区211表面。若基板22为透明基板且其上不设置有开口时，此时透镜41的尺寸大于或等于感光区211的尺寸。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (17)

  1. 一种影像传感器封装结构，其特征在于，包括：
    待封装芯片，所述待封装芯片包括分别位于待封装芯片两侧的第一表面和第二表面，在所述第一表面上设置有感光区以及位于所述感光区周围的第一焊垫；以及
    设置于所述待封装芯片第一表面侧的基板，所述基板包括分别位于基板两侧的第三表面和第四表面，所述第三表面上设置有第二焊垫和第三焊垫；所述第二焊垫位于所述第三焊垫远离所述感光区的一侧；其中，所述待封装芯片的第一表面和所述基板的第三表面相对；所述第一焊垫和所述第三焊垫连接。
  2. 根据权利要求1所述的封装结构，其特征在于，所述基板上设置有导电层，所述导电层与所述第二焊垫和所述第三焊垫电连接，所述导电层由金属布线构成，所述金属布线的线宽和线间距在20-50微米之间。
  3. 根据权利要求2所述的封装结构，其特征在于，所述金属布线的线宽和线间距为30微米。
  4. 根据权利要求1所述的封装结构，其特征在于，所述第一焊垫和/或所述第三焊垫的表面上还形成有焊接凸点。
  5. 根据权利要求1所述的封装结构，其特征在于，所述基板的材质为透明材质。
  6. 根据权利要求1所述的封装结构，其特征在于，所述基板的材质为不透光材质，所述基板上设置有贯穿所述基板的开口，所述开口暴露出所述待封装芯片的感光区。
  7. 根据权利要求6所述的封装结构，其特征在于，所述基板的第四表面上设置有保护层，所述保护层覆盖开口区域。
  8. 根据权利要求1-7任一项所述的封装结构，其特征在于，所述基板的第四表面上对应所述感光区的位置设置有镜头模组组件。
  9. 根据权利要求8所述的封装结构，其特征在于，所述镜头组件包括透镜和用于支撑所述透镜的透镜支架。
  10. 根据权利要求1-7任一项所述的封装结构，其特征在于，所述第二焊 垫的高度大于所述待封装芯片、所述第一焊垫以及所述第三焊垫的高度之和。
  11. 一种影像传感器封装结构的封装方法，其特征在于，包括：
    提供待封装芯片和基板；所述待封装芯片包括分别位于待封装芯片两侧的第一表面和第二表面，在所述第一表面上设置有感光区以及位于所述感光区周围的第一焊垫；所述基板包括分别位于基板两侧的第三表面和第四表面，所述第三表面上设置有第二焊垫和第三焊垫，所述第二焊垫位于所述第三焊垫远离所述感光区的一侧；
    按照所述第一表面和第三表面相对的方式放置所述待封装芯片和所述基板，且使所述第一焊垫和所述第三焊垫对准；以及
    将所述第一焊垫和所述第三焊垫焊接在一起，从而将所述待封装芯片和所述基板封装在一起。
  12. 根据权利要求11所述的方法，其特征在于，所述基板上设置有导电层，所述导电层与所述第二焊垫和所述第三焊垫电连接，所述导电层由金属布线构成，所述金属布线的线宽和线间距在20-50微米之间。
  13. 根据权利要求12所述的方法，其特征在于，所述金属布线的线宽和线间距为30微米。
  14. 根据权利要求11所述的方法，其特征在于，所述基板的材质为透明材质。
  15. 根据权利要求11所述的方法，其特征在于，所述基板的材质为不透光材质，所述基板上设置有贯穿所述基板的开口，所述开口暴露出所述待封装芯片的感光区。
  16. 根据权利要求15所述的方法，其特征在于，还包括：
    在所述基板的第四表面上形成保护层，所述保护层覆盖开口区域。
  17. 根据权利要求11-16任一项所述的方法，其特征在于，还包括：
    在所述基板的第四表面上对应所述感光区的位置形成镜头模组组件。
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