JP2018157150A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2018157150A JP2018157150A JP2017054722A JP2017054722A JP2018157150A JP 2018157150 A JP2018157150 A JP 2018157150A JP 2017054722 A JP2017054722 A JP 2017054722A JP 2017054722 A JP2017054722 A JP 2017054722A JP 2018157150 A JP2018157150 A JP 2018157150A
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Abstract
【課題】微細化に優れ、無線通信機能を有する半導体装置を提供する。
【解決手段】本実施形態による半導体装置は、第1半導体チップおよび第2半導体チップを備える。第1半導体チップは、第1半導体基板の第1面または該第1面とは反対側にある第2面上に設けられる第1インダクタ部分を有する。第1金属電極は、第1面と第2面との間に設けられ第1半導体基板を貫通し第1インダクタ部分に接続される。第2半導体チップは、第2半導体基板の第3面または該第3面とは反対側にある第4面上に設けられる第2インダクタ部分を有する。第2金属電極は、第3面と第4面との間に設けられ第2半導体基板を貫通し第2インダクタ部分に接続される。第1および第2半導体チップは積層される。第1および第2インダクタ部分は、1つのインダクタ素子として第1または第2金属電極を介して電気的に接続されている。
【選択図】図1
Description
図1は、本実施形態による半導体装置1の構成の一例を示す断面図である。半導体装置1は、例えば、NAND型EEPROM(Electrically Erasable and Programmable Read-Only Memory)等を有し、かつ、通信機能を有する半導体装置である。半導体装置1は、例えば、IoT技術等において、他の物体に取り付けられたセンサ等からの情報を取得し、その情報を内部のNAND型EEPROMに保存し、並びに、その情報を無線通信により外部のサーバ等へ送信可能とする。また、半導体装置1は、無線通信により外部のサーバ等から情報を取得し、その情報を内部のNAND型EEPROMに保存可能としてもよい。
図5は、第1実施形態の変形例による半導体装置1の構成の一例を示す断面図である。第1実施形態による半導体装置1との違いは、インダクタ部分330の構成である。従って、他の構成については、その詳細な説明を省略する。
図6(A)は、第1半導体チップ30aの第1面F1(または第2半導体チップ30bの第3面F3)側にある構成を示す。図6(B)は、第1半導体チップ30aの第2面F2(または第2半導体チップ30bの第4面F4)側にある構成を第1面F1側から見た図を示す。即ち、図6(A)および図6(B)は、ともに第1面F1または第3面F3から見た図であり、図6(B)のインダクタ部分330a_2,330b_2は透視図として破線で示されている。図6(B)のインダクタ部分330a_2,330b_2は、図示されている第1面F1または第3面F3から見ると、それぞれ図6(A)のインダクタ部分330a_1,330b_1とほぼ同じ位置(ほぼ重複する位置)に設けられている。また、図6(A)および図6(B)に示すインダクタ部分330a_1,330a_2,330b_1,330b_2は、設けられている面や位置が異なるが、図3に示すインダクタ部分330とほぼ同一の構成でよい。従って、インダクタ部分330a_1,330a_2,330b_1,330b_2は、第1および第2半導体チップ30a,30bの両面に設けられており、半導体チップ30の積層方向から見たときに互いにほぼ重複するように設けられている。
図7A〜図7Cは、第2実施形態による半導体装置1の構成の一例を示す断面図である。図8(A)および図8(B)は、それぞれ第1半導体チップ30aおよび第2半導体チップ30bの構成の一例を示す平面図である。図7Aは、図8(A)および図8(B)における7a−7a線に沿った断面に対応する。図7Bは、図8(A)および図8(B)における7b−7b線に沿った断面に対応する。図7Cは、図8(A)および図8(B)における7c−7c線に沿った断面図に対応する。
図10A〜図10Cは、第2実施形態の変形例による半導体装置1の構成の一例を示す断面図である。第2実施形態による半導体装置1との違いは、インダクタ部分330の構成である。従って、他の構成については、その詳細な説明を省略する。
図12Aおよび図12Bは、第3実施形態による半導体装置1の構成の一例を示す断面図である。図13(A)および図13(B)は、それぞれ第1および第2半導体チップ30a,30bの構成の一例を示す平面図である。図12Aは、図13(A)および図13(B)における12a−12a線に沿った断面に対応する。図12Bは、図13(A)および図13(B)における12b−12b線に沿った断面に対応する。
変形例は、第3実施形態による半導体装置1に、第2実施形態の変形例を適用したものである。
Claims (6)
- 第1半導体基板の第1面上に設けられた第1半導体素子と、前記第1半導体基板の前記第1面または該第1面とは反対側にある第2面の上方に設けられた第1インダクタ部分と、前記第1面と前記第2面との間に設けられ前記第1半導体基板を貫通し前記第1インダクタ部分に接続された第1金属電極と、を有する第1半導体チップ、および、
第2半導体基板の第3面上に設けられた第2半導体素子と、前記第2半導体基板の前記第3面または該第3面とは反対側にある第4面の上方に設けられた第2インダクタ部分と、前記第3面と前記第4面との間に設けられ前記第2半導体基板を貫通し前記第2インダクタ部分に接続された第2金属電極と、を有する第2半導体チップ、を備え、
前記第1および第2半導体チップは積層され、
前記第1および第2インダクタ部分は、1つのインダクタ素子として前記第1または第2金属電極を介して電気的に接続されている、半導体装置。 - 前記第1および第2インダクタ部分は、それぞれ略環形状を有する、請求項1に記載の半導体装置。
- 前記第1および第2半導体チップの積層方向から見たときに、前記第1インダクタ部分と前記第2インダクタ部分とは重複し、かつ、前記第1金属電極と前記第2金属電極とが重複する、請求項1または請求項2に記載の半導体装置。
- 前記第1および第2半導体チップは、ほぼ同一構成の半導体チップである、請求項1から請求項3のいずれか一項に記載の半導体装置。
- 前記第1インダクタ部分は、第1端部および第2端部を備える配線であり、
前記第2インダクタ部分は、第3端部および第4端部を備える配線であり、
前記第2および第3端部は前記第1金属電極を介して接続され、前記第4端部は前記第2金属電極と接続され、
前記第1および第2半導体チップの積層方向から見たときに、前記第1端部および前記第4端部は重複し、かつ、前記第1または第2金属電極により接続された前記第1および第2インダクタ部分の配線は略環形状を有する、請求項1に記載の半導体装置。 - 前記第1インダクタ部分は、第1端部および第2端部を備える配線であり、
前記第2インダクタ部分は、第3端部および第4端部を備える配線であり、
前記第1および第2インダクタ部分の配線は、それぞれ略渦巻き形状を有し、
前記第2および第3端部は前記第1金属電極を介して接続され、前記第4端部は前記第2金属電極と接続され、
前記第1および第2半導体チップの積層方向から見たときに、前記第1端部および前記第4端部は重複する、請求項1に記載の半導体装置。
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006042097A (ja) * | 2004-07-29 | 2006-02-09 | Kyocera Corp | アンテナ配線基板 |
JP2006114954A (ja) * | 2004-09-14 | 2006-04-27 | Seiko Epson Corp | 電気光学装置及び電子機器 |
KR100714310B1 (ko) * | 2006-02-23 | 2007-05-02 | 삼성전자주식회사 | 변압기 또는 안테나를 구비하는 반도체 패키지들 |
JP2007306536A (ja) * | 2006-04-13 | 2007-11-22 | Sohdai Antenna Corp | アンテナ |
JP2008004852A (ja) * | 2006-06-23 | 2008-01-10 | Tokyo Electron Ltd | 石英製品及び熱処理装置 |
JP2011238895A (ja) * | 2010-04-13 | 2011-11-24 | Denso Corp | 半導体装置およびその製造方法 |
US20150311159A1 (en) * | 2013-12-13 | 2015-10-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Electromagnetic bandgap structure for three dimensional ics |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7531417B2 (en) | 1998-12-21 | 2009-05-12 | Megica Corporation | High performance system-on-chip passive device using post passivation process |
JP2003124429A (ja) * | 2001-10-15 | 2003-04-25 | Matsushita Electric Ind Co Ltd | モジュール部品 |
US7239013B2 (en) | 2002-07-18 | 2007-07-03 | Hitachi Chemical Co., Ltd. | Multilayer wiring board, method for producing the same, semiconductor device and radio electronic device |
TWI312181B (en) * | 2003-05-27 | 2009-07-11 | Megica Corporatio | High performance system-on-chip passive device using post passivation process |
US20100127937A1 (en) | 2008-11-25 | 2010-05-27 | Qualcomm Incorporated | Antenna Integrated in a Semiconductor Chip |
US8618629B2 (en) * | 2009-10-08 | 2013-12-31 | Qualcomm Incorporated | Apparatus and method for through silicon via impedance matching |
JP2011146616A (ja) | 2010-01-18 | 2011-07-28 | Sumitomo Bakelite Co Ltd | 電子回路装置、その電子回路基板 |
JP2013005252A (ja) | 2011-06-17 | 2013-01-07 | Elpida Memory Inc | 通信装置 |
JP2016164962A (ja) * | 2015-02-26 | 2016-09-08 | ルネサスエレクトロニクス株式会社 | 半導体チップおよび半導体装置並びに電池パック |
US9653421B2 (en) * | 2015-04-07 | 2017-05-16 | Noda Screen Co., Ltd. | Semiconductor device |
TWI563615B (en) * | 2015-05-05 | 2016-12-21 | Siliconware Precision Industries Co Ltd | Electronic package structure and the manufacture thereof |
WO2017036344A1 (zh) * | 2015-08-28 | 2017-03-09 | 苏州晶方半导体科技股份有限公司 | 影像传感器封装结构及其封装方法 |
US10134671B1 (en) * | 2017-05-02 | 2018-11-20 | Micron Technology, Inc. | 3D interconnect multi-die inductors with through-substrate via cores |
US10121739B1 (en) * | 2017-05-02 | 2018-11-06 | Micron Technology, Inc. | Multi-die inductors with coupled through-substrate via cores |
-
2017
- 2017-03-21 JP JP2017054722A patent/JP2018157150A/ja active Pending
- 2017-07-05 TW TW106122479A patent/TWI691042B/zh active
- 2017-08-02 CN CN201710650748.XA patent/CN108630666A/zh not_active Withdrawn
- 2017-09-12 US US15/702,156 patent/US10566311B2/en active Active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006042097A (ja) * | 2004-07-29 | 2006-02-09 | Kyocera Corp | アンテナ配線基板 |
JP2006114954A (ja) * | 2004-09-14 | 2006-04-27 | Seiko Epson Corp | 電気光学装置及び電子機器 |
KR100714310B1 (ko) * | 2006-02-23 | 2007-05-02 | 삼성전자주식회사 | 변압기 또는 안테나를 구비하는 반도체 패키지들 |
US20070194427A1 (en) * | 2006-02-23 | 2007-08-23 | Choi Yun-Seok | Semiconductor package including transformer or antenna |
CN101026145A (zh) * | 2006-02-23 | 2007-08-29 | 三星电子株式会社 | 包括变压器或天线的半导体封装 |
JP2007227897A (ja) * | 2006-02-23 | 2007-09-06 | Samsung Electronics Co Ltd | 変圧器またはアンテナを有する半導体パッケージ |
JP2007306536A (ja) * | 2006-04-13 | 2007-11-22 | Sohdai Antenna Corp | アンテナ |
JP2008004852A (ja) * | 2006-06-23 | 2008-01-10 | Tokyo Electron Ltd | 石英製品及び熱処理装置 |
JP2011238895A (ja) * | 2010-04-13 | 2011-11-24 | Denso Corp | 半導体装置およびその製造方法 |
US20150311159A1 (en) * | 2013-12-13 | 2015-10-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Electromagnetic bandgap structure for three dimensional ics |
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