TWI728143B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TWI728143B
TWI728143B TW106122516A TW106122516A TWI728143B TW I728143 B TWI728143 B TW I728143B TW 106122516 A TW106122516 A TW 106122516A TW 106122516 A TW106122516 A TW 106122516A TW I728143 B TWI728143 B TW I728143B
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Taiwan
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conductive pattern
pad
pattern
width
length
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TW106122516A
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English (en)
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TW201814863A (zh
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朴秀貞
白寶娜
金庸鎬
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南韓商三星電子股份有限公司
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Abstract

一種半導體裝置包括半導體晶片、設置在所述半導體晶片上的接墊以及設置在半導體晶片上的絕緣圖案。所述絕緣圖案具有暴露出所述接墊的開口，且在所述開口中設置有導電圖案，所述導電圖案耦合到所述接墊。當在平面圖中觀察時，所述接墊的兩個相對的端部與所述導電圖案間隔開，且所述導電圖案的兩個相對的端部與所述接墊間隔開。另外，當在平面圖中觀察時，所述導電圖案包括第一導電圖案及第二導電圖案，所述第一導電圖案的長度平行於第一方向，所述第二導電圖案的長度平行於第二方向。所述第一方向與所述第二方向相對於彼此斜交。

Description

半導體裝置
本發明涉及一種半導體裝置，且具體來說，涉及一種半導體裝置的凸塊堆疊。
對具有許多引腳及小的節距的半導體裝置的需求正在增大。因此，已進行了許多研究來使半導體裝置按比例縮小。半導體裝置具有電連接結構（例如，焊料球或焊料凸塊）以電性連接到另一電子裝置或印刷電路板。需要開發一種旨在提高半導體裝置的電連接結構的可靠性及穩定性的技術。
本發明的一些實施例提供一種可靠性高的半導體裝置及包括所述半導體裝置的半導體封裝。
本發明的一些實施例提供一種高縮比（highly-scaled）的半導體裝置。
根據本發明的一些實施例，一種半導體裝置可包括：半導體晶片；接墊，設置在所述半導體晶片上；絕緣圖案，設置在所述半導體晶片上且具有開口，所述開口暴露出所述接墊；以及導電圖案，設置在所述絕緣圖案上。當在平面圖中觀察時，所述接墊可具有與所述導電圖案間隔開的兩個相對的端部，且所述導電圖案可具有與所述接墊間隔開的兩個相對的端部。所述導電圖案在所述導電圖案的長度的方向上的圖案尺寸可為所述導電圖案在所述導電圖案的寬度的方向上的圖案尺寸的1.7倍至3倍。
根據本發明的一些實施例，一種半導體裝置可包括：基底；第一凸塊堆疊，設置在所述基底的表面上且包括第一接墊及位於所述第一接墊上的第一導電圖案；以及第二凸塊堆疊，設置在所述基底的所述表面上且包括第二接墊及位於所述第二接墊上的第二導電圖案。所述第一接墊的寬度可大於所述第一導電圖案的寬度，所述第一導電圖案的長度可大於所述第一接墊的長度，且所述第二導電圖案的寬度可大於所述第二接墊的寬度。所述第一導電圖案的寬度方向及所述第二導電圖案的寬度方向可平行於第一方向。
根據本發明的一些實施例，一種半導體裝置可包括：半導體晶片；接墊，設置在所述半導體晶片上；絕緣圖案，設置在所述半導體晶片上且具有開口，所述開口暴露出所述接墊；以及導電圖案，設置在所述開口中且耦合到所述接墊。當在平面圖中觀察時，所述接墊的兩個相對的端部可與所述導電圖案間隔開，且所述導電圖案的兩個相對的端部可與所述接墊間隔開。另外，當在平面圖中觀察時，所述導電圖案可包括第一導電圖案及第二導電圖案，所述第一導電圖案的長軸平行於第一方向，所述第二導電圖案的長軸平行於第二方向，且所述第一方向與所述第二方向可相對於彼此斜交（oblique to each other）。
根據本發明的一些實施例，一種半導體裝置包括半導體晶片。在所述半導體晶片上設置有接墊以在半導體晶片的第一電元件與位於半導體晶片外部的第二電元件之間傳送電訊號。在所述半導體晶片上設置有絕緣圖案，所述絕緣圖案具有開口，所述開口暴露出所述接墊的中心部分。在所述絕緣圖案上設置有導電圖案，且所述導電圖案被形成為使得導電圖案的長軸垂直於所述接墊的長軸，且所述導電圖案沿所述導電圖案的長軸的長度是所述導電圖案的平行於所述接墊的長軸的寬度的約1.7倍至3倍。且所述導電圖案與所述接墊的暴露出的中心部分完全重疊。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
以下將闡述根據本發明一些實施例的半導體裝置及其半導體封裝。
圖1A是說明根據本發明一些實施例的半導體裝置的平面圖。圖1B是沿圖1A所示線I-I'截取的剖視圖。
參照圖1A及圖1B，半導體裝置10可包括半導體基底100以及凸塊堆疊201及202。半導體裝置10可為記憶體晶片、邏輯晶片或包括記憶體元件及邏輯元件二者的半導體晶片。半導體基底100可由矽、鍺或矽鍺形成或者可包含矽、鍺或矽鍺。半導體基底100可具有彼此面對的第一表面100a與第二表面100b。半導體基底100可包括電路層110。
凸塊堆疊201及202可設置在半導體基底100的第一表面100a上。凸塊堆疊201及202可電性連接到設置在電路層110中的整合元件（圖中未示出）。在本說明書中，表達方式“電性連接或電性耦合”可意指多個元件直接連接/直接耦合到彼此或者通過另一導電元件間接連接或間接耦合到彼此。另外，表達方式“元件電性連接或電性耦合到電路層110”可意指所述元件電性連接或電性耦合到設置在電路層110中的整合元件。凸塊堆疊201及202可用作用於從半導體裝置10接收電訊號或將電訊號發送到半導體裝置10的路徑。凸塊堆疊201及202可包括彼此間隔開的第一凸塊堆疊201及第二凸塊堆疊202。第一凸塊堆疊201可包括第一接墊211及第一導電圖案221，且第二凸塊堆疊202可包括第二接墊212及第二導電圖案222。接墊211及212可設置在半導體基底100的第一表面100a上。接墊211及212可包含導電材料（例如，鋁或銅）。當在平面圖中觀察時，第一接墊211的中心部分可與第一導電圖案221的中心部分重疊，而第一接墊211的兩個相對的端部可不與第一導電圖案221重疊。第一接墊211的中心部分可設置在第一接墊211的兩個相對的端部之間。第一方向x及第二方向y可平行於半導體基底100的第一表面100a。第一方向x與第二方向y可相對於彼此斜交。協力廠商向z可實質上垂直於半導體基底100的第一表面100a。當在平面圖中觀察時，第一導電圖案221的長軸可平行於第一方向x且第一導電圖案221的短軸可平行於第二方向y。
如上所述，第二凸塊堆疊202可包括第二接墊212及第二導電圖案222。當將第二凸塊堆疊202旋轉90度時，第二凸塊堆疊202可具有與第一凸塊堆疊201實質上相同的平面形狀。第二導電圖案222的長軸可平行於第二方向y。第二導電圖案222的兩個相對的端部可不與第二接墊212重疊。第二接墊212的兩個相對的端部可不與第二導電圖案222重疊。
如圖1B所示，導電圖案221及222可包括凸塊下圖案231及232以及柱狀圖案241及242。儘管圖中未示出，然而凸塊下圖案231及232中的每一個可包括障壁圖案及晶種圖案。障壁圖案可由鈦、鎢、鉻或其合金形成或者可包含鈦、鎢、鉻或其合金。晶種圖案可由銅、鎳或其合金形成或者可包含銅、鎳或其合金。柱狀圖案241及242可設置在凸塊下圖案231及232上。柱狀圖案241及242可由含銅材料形成。在第一導電圖案221及第二導電圖案222的底表面上可分別設置有第一焊料圖案251及第二焊料圖案252。
圖2是說明根據本發明一些實施例的半導體封裝的剖視圖。為使說明簡潔起見，可由相似的或相同的參考編號來標識前面闡述的元件，而不再對其重複的說明予以贅述。
參照圖2，除了半導體裝置10之外，半導體封裝1還可包括封裝基底1000。舉例來說，封裝基底1000可包括印刷電路板。在封裝基底1000的頂表面上可設置有導電接墊1100。在封裝基底1000的底表面上可設置有外部端子1900。導電接墊1100可通過封裝基底1000電性連接到外部端子1900，如由虛線所示。半導體裝置10可被配置成具有與參照圖1A及圖1B闡述的半導體裝置10實質上相同的特徵。半導體裝置10可安裝在封裝基底1000上。半導體裝置10可被設置成使得第一表面100a面對封裝基底1000的頂表面。凸塊堆疊201及202可通過回焊製程連接到導電接墊1100，且因此，半導體裝置10可電性連接到封裝基底1000。凸塊堆疊201及202可夾置在封裝基底1000與半導體裝置10之間。在封裝基底1000的頂表面上可設置有模塑圖案2000以覆蓋半導體裝置10。模塑圖案2000可延伸至填充封裝基底1000與半導體裝置10之間的間隙，從而密封地包封凸塊堆疊201及202。在下文中，將更詳細地闡述凸塊堆疊201及202。
圖3A是說明根據本發明一些實施例的凸塊堆疊的平面圖。舉例來說，圖3A可為圖1A所示區II的平面圖。圖3B是沿圖3A所示線IV-IV'截取的剖視圖且示出圖1B所示區III的放大截面。圖3C是沿圖3A所示線V-V'截取的剖視圖。圖3D是沿圖3A所示線VI-VI'截取的剖視圖。為使說明簡潔起見，可由相似的或相同的參考編號來標識前面闡述的元件，而不再對其重複的說明予以贅述。
參照圖3A及圖3B，半導體裝置10可包括半導體基底100、絕緣圖案120以及凸塊堆疊201及202。半導體基底100可包括電路層110。電路層110可包括絕緣層111、整合元件115及內部線113，且此處，整合元件115及內部線113可設置在絕緣層111中。整合元件115可包括例如電晶體。第一凸塊堆疊201可包括第一接墊211、第一導電圖案221及第一焊料圖案251。第二凸塊堆疊202可包括第二接墊212、第二導電圖案222及第二焊料圖案252。第一接墊211及第二接墊212可設置在電路層110的底表面上。接墊211及212可由導電材料（例如，鋁）形成或者包含導電材料。接墊211及212可通過內部線113電性連接到整合元件115。
絕緣圖案120可設置在半導體基底100、第一接墊211及第二接墊212上。絕緣圖案120可覆蓋第一接墊211的兩個相對的端部及第二接墊212的兩個相對的端部。絕緣圖案120可有助於減小施加到第一接墊211及第二接墊212中的每一個的兩個相對的端部的應力。絕緣圖案120可包括第一絕緣圖案121及第二絕緣圖案122。第一絕緣圖案121可由氧化矽、氮化矽或氮氧化矽形成或者可包含氧化矽、氮化矽或氮氧化矽。第二絕緣圖案122可設置在第一絕緣圖案121上。第二絕緣圖案122可由聚合物（例如，聚醯亞胺）形成或者可包含聚合物。絕緣圖案120可被設置成具有第一開口131及第二開口132。第一開口131及第二開口132可被設置成分別暴露出第一接墊211及第二接墊212。舉例來說，第一絕緣圖案121中的開口131及132以及第二絕緣圖案122中的開口131及132可通過單個程序（例如，通過單個蝕刻製程）形成。第一絕緣圖案121中的開口131的內側表面及開口132的內側表面可分別從第二絕緣圖案122中的開口131的內側表面及開口132的內側表面延伸。
第一導電圖案221可包括第一凸塊下圖案231及第一柱狀圖案241。第一凸塊下圖案231可設置在絕緣圖案120的底表面上及第一開口131中。第一凸塊下圖案231可耦合到第一接墊211。第一柱狀圖案241可設置在第一凸塊下圖案231上。當在平面圖中觀察時，第一柱狀圖案241可與第一凸塊下圖案231重疊。第一柱狀圖案241可在協力廠商向z上與第一凸塊下圖案231對齊。
如圖3A及圖3B所示，第一接墊211的寬度W2可大於第一導電圖案221的寬度W1。在本說明書中，元件的寬度可為元件在第一方向x上的圖案尺寸（pattern size），且元件的長度可為元件在第二方向y上的圖案尺寸。元件的圖案尺寸可為元件在所選擇方向上的最大圖案尺寸。第一導電圖案221的寬度W1可實質上等於第一凸塊下圖案231的寬度及第一柱狀圖案241的寬度。在其中第一接墊211的寬度W2小於第一導電圖案221的寬度W1的110%、且在形成第一開口131的過程中存在製程失效（例如，罩幕圖案未對齊）的情形中，第一接墊211可能不被第一開口131暴露出。另外，在製造或操作半導體裝置10的過程期間，電路層110可能被機械應力損壞。舉例來說，在電路層110中可形成裂紋，從而造成內部線113或整合元件115的損壞。在其中第一接墊211的寬度W2大於第一導電圖案221的寬度W1的150%的情形中，半導體裝置10的佔用面積可能增大。在一些實施例中，第一接墊211的寬度W2可為第一導電圖案221的寬度W1的約110%至150%。由於第一接墊211會吸收機械應力，因此可使得防止或抑制電路層110被機械應力損壞成為可能。此外，可防止製程失效或第一開口131的未對齊且因此第一導電圖案221可良好地連接到第一接墊211。因此，半導體裝置10可按比例縮小（scaled down）。在第一方向x上，第一開口131的圖案尺寸D1可小於第一接墊211的寬度W2及第一導電圖案221的寬度W1。即使存在製程失效，第一開口131仍可被形成為暴露出第一接墊211。
結合圖2參照圖3A及圖3C，第一導電圖案221的長度L1可大於第一接墊211的長度L2。第一導電圖案221的長度L1可實質上等於第一凸塊下圖案231的長度及第一柱狀圖案241的長度。在其中第一導電圖案221的長度L1小於第一接墊211的長度L2的110%的情形中，在第一凸塊堆疊201與圖2所示封裝基底1000的導電接墊1100中的對應的一個導電接墊1100之間的電性連接中可能出現故障。作為實例，在回焊製程期間，在第一凸塊堆疊201與導電接墊1100中的一個導電接墊1100之間可能出現非潤濕問題（non-wetting issue）。作為另一實例，在半導體封裝1的操作期間，電路層110可被機械應力損壞。在其中第一導電圖案221的長度L1大於第一接墊211的長度L2的150%的情形中，半導體裝置10的佔用面積可能增大。在一些實施例中，第一導電圖案221的長度L1可為第一接墊211的長度L2的約110%至150%。第一凸塊堆疊201可牢固地連接到圖2所示封裝基底1000的導電接墊1100中的一個導電接墊1100。半導體裝置10可按比例縮小。
當在第二方向y上測量時，第一開口131的圖案尺寸D2可小於第一接墊211的長度L2及第一導電圖案221的長度L1。絕緣圖案120可被設置成覆蓋第一接墊211的兩個相對的端部並保護第一接墊211。第一接墊211的長度L2被示出為大於第一接墊211的寬度W2，但在某些實施例中，第一接墊211的長度L2可實質上等於第一接墊211的寬度W2。
第二導電圖案222可包括第二凸塊下圖案232及第二柱狀圖案242。第二導電圖案222可與第一導電圖案221相似。舉例來說，第二凸塊下圖案232及第二柱狀圖案242可由與第一凸塊下圖案231及第一柱狀圖案241相同的材料形成或者可包含與第一凸塊下圖案231及第一柱狀圖案241相同的材料。第二凸塊下圖案232可設置在絕緣圖案120上及第二開口132中。第二凸塊下圖案232可耦合到第二接墊212。第二柱狀圖案242可設置在第二凸塊下圖案232上且可在協力廠商向z上與第二凸塊下圖案232對齊。
當將第二導電圖案222旋轉90度時，第二導電圖案222可具有與第一導電圖案221實質上相同的平面形狀。舉例來說，第二導電圖案222的寬度W3可實質上等於第一導電圖案221的長度L1，且第二導電圖案222的長度L3可實質上等於第一導電圖案221的寬度W1。第二接墊212的寬度W4可實質上等於第一接墊211的長度L2，且第二接墊212的長度L4可實質上等於第一接墊211的寬度W2。在本說明書中，長度與寬度相等是指兩個長度或寬度之間的差處於製造過程的製程容差（process tolerance）內，且這種差並不是人們所期望的。
如圖3A及圖3B所示，第二導電圖案222的寬度W3可大於第二接墊212的寬度W4。第二導電圖案222的寬度W3可實質上等於第二凸塊下圖案232的寬度及第二柱狀圖案242的寬度。舉例來說，第二導電圖案222的寬度W3可為第二接墊212的寬度W4的約110%至150%。由於第二接墊212會吸收機械應力，因此可使得防止或抑制電路層110被損壞成為可能。半導體裝置10可按比例縮小。在第一方向x上，第二開口132的圖案尺寸D3可小於第二導電圖案222的寬度W3及第二接墊212的寬度W4。即使在形成第二開口132的過程中存在製程失效，第二開口132仍可被形成為暴露出第二接墊212。因此，第二導電圖案222可良好地連接到第二接墊212。
如圖3A及圖3D所示，第二導電圖案222的長度L3可實質上等於第二凸塊下圖案232的長度及第二柱狀圖案242的長度。第二接墊212的長度L4可大於第二導電圖案222的長度L3。舉例來說，第二接墊212的長度L4可為第二導電圖案222的長度L3的約110%至150%。因此，半導體基底100可通過第二凸塊堆疊202穩定地連接到圖2所示封裝基底1000，且半導體基底100可按比例縮小。在第二方向y上，第二開口132的圖案尺寸D4可小於第二導電圖案222的長度L3及第二接墊212的長度L4。
導電圖案221及222中的每一個在各自的長軸方向上的圖案尺寸可為在各自的短軸方向上的圖案尺寸的1.7倍至3倍（例如，2倍）。舉例來說，第一導電圖案221的長度L1可為第一導電圖案221的寬度W1的1.7倍至3倍。第二導電圖案222的寬度W3可為第二導電圖案222的長度L3的1.7倍至3倍。在一些實施例中，導電圖案221及222中的每一個在各自的長軸方向上的圖案尺寸可為在各自的短軸方向上的圖案尺寸的約2倍。在其中導電圖案221及222中的每一個在各自的長軸方向上的圖案尺寸比在各自的短軸方向上的圖案尺寸的1.7倍小的情形中，在將凸塊堆疊201及凸塊堆疊202連接到封裝基底1000的導電接墊1100時可能出現故障。另外，在製造或操作半導體裝置10的過程期間，電路層110可被機械應力損壞。相比之下，在其中導電圖案221及222中的每一個在各自的長軸方向上的圖案尺寸比在各自的短軸方向上的圖案尺寸的3倍大的情形中，在導電圖案221及222之間可能形成短路，或者半導體裝置10的佔用面積可能增大。在一些實施例中，導電圖案221及222中的每一個可被配置成使各自的長圖案尺寸與短圖案尺寸之間的比率能夠處於可允許的範圍內，且這可使得防止或抑制電路層110被損壞成為可能。結果，凸塊堆疊201及202可良好地連接到封裝基底1000。
在第一柱狀圖案241的底表面及第二柱狀圖案242的底表面上可分別設置有第一焊料圖案251及第二焊料圖案252。第一焊料圖案251及第二焊料圖案252可延伸至至少部分地覆蓋柱狀圖案241的側表面及242的側表面。第一焊料圖案251及第二焊料圖案252可由與第一導電圖案221及第二導電圖案222的材料不同的材料形成或者可包含與第一導電圖案221及第二導電圖案222的材料不同的材料。舉例來說，焊料圖案251及252可由錫、鉛、銀或其合金形成或者可包含錫、鉛、銀或其合金。
將參照圖1A闡述凸塊堆疊201及202的平面排列。當在平面圖中觀察時，半導體基底可具有第一側101、第二側102、第三側103及第四側104。半導體基底100的第一側101與第三側103可彼此相對且與第二側102及第四側104相鄰。半導體基底100的第一側101及第三側103可平行於第一方向x。半導體基底100的第二側102及第四側104可平行於第二方向y。
在一些實施例中，多個第一凸塊堆疊201可設置在半導體基底100上。第一凸塊堆疊201可設置在半導體基底100的第一表面100a上且與第一側101及第三側103相鄰。另外，多個第二凸塊堆疊202可設置在半導體基底100上。第二凸塊堆疊202可設置在半導體基底100的第一表面100a上且與第二側102及第四側104相鄰。導電圖案221及222的排列可根據凸塊堆疊201及202的排列而改變。通過控制凸塊堆疊201及202的排列，可使減小導電圖案221及222的節距（pitch）成為可能。這使得將半導體封裝1按比例縮小成為可能。
第一接墊211的長軸可平行於第一方向x，且第二接墊212的長軸可平行於第二方向y。彼此相鄰的第一接墊211與第二接墊212之間的空間可不同於第一接墊211之間的空間以及可不同於第二接墊212之間的空間。接墊211與212之間的空間可根據凸塊堆疊201及202的排列而定。第一接墊211及第二接墊212可電性連接到圖3B所示內部線113。通過控制凸塊堆疊201及202的排列，可使得在放置電路層110的內部線113時的自由度增大成為可能。凸塊堆疊201及202的平面排列可並不僅限於圖式中所示的實例。
圖4A至圖4G是說明根據本發明一些實施例的半導體封裝的放大剖視圖。為使說明簡潔起見，可由相似的或相同的參考編號來標識前面闡述的元件，而不再對其重複的說明予以贅述。在圖4A至圖4G的以下說明中，將闡述單個凸塊堆疊、單個導電接墊及單個互連圖案。
參照圖2及圖4A，第一接墊211及第一導電圖案221中的每一個可具有八邊形截面。絕緣圖案120的第一開口131中的每一個可具有八邊形截面。在其中半導體裝置10安裝在封裝基底1000上的情形中，第一凸塊堆疊201可耦合到封裝基底1000。當在平面圖中觀察時，封裝基底1000可包括設置在第一導電圖案221附近的互連圖案1200。在其中第一導電圖案221具有八邊形截面的情形中，可使得防止或抑制在第一凸塊堆疊201與互連圖案1200之間形成短路成為可能。因此，可使得在放置互連圖案1200時的自由度提高或半導體封裝1的可靠性提高成為可能。儘管圖中未示出，然而第一接墊211及第一開口131中的至少一個可不具有八邊形截面。具有來說，第一接墊211可具有四角形截面，且絕緣圖案120的第一開口131可具有圓形截面或橢圓形截面。
結合圖2參照圖4B，第一導電圖案221可具有六邊形截面。因此，可使得防止或抑制在第一凸塊堆疊201與封裝基底1000的互連圖案1200之間形成短路成為可能。
結合圖2參照圖4C及圖4D，第一導電圖案221可具有兩個相對的側221c及221d，所述兩個相對的側221c及221d與互連圖案1200相距不同的距離定位。當在平面圖中觀察時，互連圖案1200可比靠近第一導電圖案221的一側221d來說更靠近第一導電圖案221的另一側221c，且另一側221c可具有比側221d的長度L1小的長度L5或L5'。第一導電圖案221的另一側221d可為與參照圖3A至圖3C闡述的導電圖案221的長度L1實質上相同的長度。因此，可使得防止或抑制在互連圖案1200與第一凸塊堆疊201之間形成短路成為可能。
結合圖2參照圖4E及圖4F，當在平面圖中觀察時，第一導電圖案221可被設置成具有凹陷區215。當在平面圖中觀察時，凹陷區215可與導電接墊1100重疊。第一焊料圖案251可具有與第一導電圖案221對應的形狀。第一導電圖案221可通過第一焊料圖案251耦合到封裝基底1000的導電接墊1100。第一導電圖案221可具有凹陷區215，且第一凸塊堆疊201（例如，第一焊料圖案251）可牢固地連接到互連圖案1200。
參照圖4G，第一導電圖案221可具有多邊形形狀。第一開口131可具有三角形形狀。
第一接墊211、第一開口131及第一導電圖案221的平面形狀可並非僅限於圖4A至圖4G所示實例，而是可作出各種改變。第二接墊212、第二導電圖案222及第二開口132可具有與參照圖4A至圖4G闡述的第一接墊211、第一導電圖案221及第一開口131的平面形狀相似的平面形狀。當將第二接墊212、第二導電圖案222及第二開口132旋轉90度時，第二接墊212、第二導電圖案222及第二開口132可被設置成具有與第一接墊211、第一導電圖案221及第一開口131對應的形狀。為簡潔起見，未在圖4A至圖4D及圖4G中示出封裝基底1000的導電接墊1100，但封裝基底1000的導電接墊1100可被設置成與第一導電圖案221重疊。另外，為簡潔起見，未在圖4E至圖4G中示出封裝基底1000的互連圖案1200。
圖5A是說明根據本發明一些實施例的半導體裝置的平面圖。舉例來說，圖5A可為圖1A所示區II的平面圖。圖5B是沿圖5A所示線VII-VII'截取的剖視圖。圖5C是沿圖5A所示線V-V'截取的剖視圖。為使說明簡潔起見，可由相似的或相同的參考編號來標識前面闡述的元件，而不再對其重複的說明予以贅述。
參照圖5A至圖5C，半導體裝置10可包括半導體基底100、第一凸塊堆疊201及第二凸塊堆疊202。第一導電圖案221及第二導電圖案222可被配置成具有與圖1A至3D的第一導電圖案221及第二導電圖案222實質上相同的特徵。舉例來說，導電圖案221及222中的每一個在各自的長軸方向上的圖案尺寸可為導電圖案221及222中的每一個在各自的短軸方向上的圖案尺寸的1.7倍至3倍。
在半導體基底100的第一表面100a上可設置有絕緣圖案120。絕緣圖案120可具有第一開口131及第二開口132。第一開口131及第二開口132可具有與接墊211及212間隔開的側表面。第一接墊211的寬度W2可小於第一開口131在第一方向x上的圖案尺寸D1。第一導電圖案221的寬度W1可小於第一接墊211的寬度W2。第一接墊211的長度L2可小於第一開口131在第二方向y上的圖案尺寸D2。第一導電圖案221的長度L1可小於第一接墊211的長度L2。
第二接墊212的寬度W4可小於第二開口132在第一方向x上的圖案尺寸D3。第二導電圖案222的寬度W3可小於第二接墊212的寬度W4。第二接墊212的長度L4可小於第二開口132在第二方向y上的圖案尺寸D4。第二導電圖案222的長度L3可小於第二接墊212的長度L4。
根據本發明的一些實施例，可對導電圖案的寬度/長度比率進行控制，且這可使得改善將凸塊堆疊連接到半導體基底或封裝基底的連接結構的電特性成為可能。接墊的兩個相對的端部可不與導電圖案重疊，且接墊可具有增大的佔用面積。導電圖案的兩個相對的側可不與接墊重疊，且導電圖案可具有增大的佔用面積。這可使得在半導體裝置與封裝基底之間實現良好的電連接結構成為可能。在一些實施例中，半導體裝置可按比例縮小。
按照所述領域中的傳統，可採用用於執行所闡述的一個或多個功能的區塊來闡述及說明各實施例。這些區塊（在本文中可將其稱作單元或模組等）是由例如邏輯閘、積體電路、微處理器、微控制器、記憶體電路、被動電子元件、主動電子元件、光學元件、硬接線式電路（hardwired circuit）等類比及/或數位電路以實體方式進行實作，且可視需要通過韌體及/或軟體來驅動。所述電路可例如被實施於一個或多個半導體晶片中或例如印刷電路板等基底支撐件（substrate support）上。構成區塊的電路可由專用硬體、或由處理器（例如，一個或多個經過程式設計的微處理器及相關聯的電路系統）或者由用於執行所述區塊的某些功能的專用硬體與用於執行所述區塊的其他功能的處理器的組合來實作。所述實施例中的每一區塊可在不背離本發明的範圍的條件下在實體上分成兩個或更多個交互作用且分立的區塊。相同地，所述實施例的區塊可在不背離本發明的範圍的條件下在實體上組合成多個複雜區塊。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
1‧‧‧半導體封裝10‧‧‧半導體裝置100‧‧‧半導體基底100a‧‧‧第一表面100b‧‧‧第二表面101‧‧‧第一側102‧‧‧第二側103‧‧‧第三側104‧‧‧第四側110‧‧‧電路層111‧‧‧絕緣層113‧‧‧內部線115‧‧‧整合元件120‧‧‧絕緣圖案121‧‧‧第一絕緣圖案122‧‧‧第二絕緣圖案131‧‧‧第一開口132‧‧‧第二開口201‧‧‧第一凸塊堆疊202‧‧‧第二凸塊堆疊211‧‧‧第一接墊212‧‧‧第二接墊215‧‧‧凹陷區221‧‧‧第一導電圖案221c、221d‧‧‧側222‧‧‧第二導電圖案231‧‧‧第一凸塊下圖案232‧‧‧第二凸塊下圖案241‧‧‧第一柱狀圖案242‧‧‧第二柱狀圖案251‧‧‧第一焊料圖案252‧‧‧第二焊料圖案1000‧‧‧封裝基底1100‧‧‧導電接墊1200‧‧‧互連圖案1900‧‧‧外部端子2000‧‧‧模塑圖案D1、D2、D3、D4‧‧‧圖案尺寸I-I'、IV-IV'、V-V'、VI-VI'、VII-VII'‧‧‧線II、III‧‧‧區L1、L2、L3、L4、L5、L5'‧‧‧長度x‧‧‧第一方向y‧‧‧第二方向z‧‧‧第三方向W1、W2、W3、W4‧‧‧寬度
結合附圖閱讀以下簡要說明將會更清楚地理解各示例性實施例。所述附圖代表本文中所闡述的非限制性示例性實施例。 圖1A是說明根據本發明一些實施例的半導體裝置的平面圖。 圖1B是沿圖1A所示線I-I'截取的剖視圖。 圖2是說明根據本發明一些實施例的半導體封裝的剖視圖。 圖3A是說明根據本發明一些實施例的凸塊堆疊的平面圖。 圖3B是沿圖3A所示線IV-IV'截取的剖視圖。 圖3C是沿圖3A所示線V-V'截取的剖視圖。 圖3D是沿圖3A所示線VI-VI'截取的剖視圖。 圖4A至圖4G是說明根據本發明一些實施例的半導體封裝的放大剖視圖。 圖5A是說明根據本發明一些實施例的半導體裝置的平面圖。 圖5B是沿圖5A所示線VII-VII'截取的剖視圖。 圖5C是沿圖5A所示線V-V'截取的剖視圖。 應注意，這些圖旨在說明某些示例性實施例中所使用的方法、結構及/或材料的一般特性且旨在對下文提供的書面說明進行補充。然而，這些圖式並未按比例繪製且可能並不精確地反映任意給定實施例的精確結構或性能特性，且不應被解釋為界定或限制示例性實施例所涵蓋的值或特性的範圍。舉例來說，為清楚起見，可減小或誇大分子、層、區及/或結構性元件的相對厚度及定位。在各圖式中所使用的相似或相同的參考編號旨在表示存在相似或相同的元件或特徵。
1‧‧‧半導體封裝
10‧‧‧半導體裝置
100‧‧‧半導體基底
100a‧‧‧第一表面
110‧‧‧電路層
120‧‧‧絕緣圖案
201‧‧‧第一凸塊堆疊
202‧‧‧第二凸塊堆疊
211‧‧‧第一接墊
212‧‧‧第二接墊
221‧‧‧第一導電圖案
222‧‧‧第二導電圖案
231‧‧‧第一凸塊下圖案
232‧‧‧第二凸塊下圖案
241‧‧‧第一柱狀圖案
242‧‧‧第二柱狀圖案
251‧‧‧第一焊料圖案
252‧‧‧第二焊料圖案
1000‧‧‧封裝基底
1100‧‧‧導電接墊
1200‧‧‧互連圖案
1900‧‧‧外部端子
2000‧‧‧模塑圖案
x‧‧‧第一方向
z‧‧‧第三方向

Claims (16)

  1. 一種半導體裝置，包括：半導體晶片；接墊，設置在所述半導體晶片上；絕緣圖案，設置在所述半導體晶片上，所述絕緣圖案具有開口，所述開口暴露出所述接墊；以及導電圖案，設置在所述絕緣圖案上，其中：當在平面圖中觀察時，所述接墊具有與所述導電圖案間隔開的兩個相對的端部，所述導電圖案具有與所述接墊間隔開的兩個相對的端部，且所述導電圖案在所述導電圖案的長度的方向上的圖案尺寸是所述導電圖案在所述導電圖案的寬度的方向上的圖案尺寸的1.7倍至3倍，其中所述開口在寬度方向上的圖案尺寸小於所述接墊的寬度，且所述開口在長度方向上的圖案尺寸小於所述接墊的長度。
  2. 如申請專利範圍第1項所述的半導體裝置，其中所述導電圖案的所述長度是所述接墊的所述長度的110%至150%，且所述接墊的所述寬度是所述導電圖案的所述寬度的110%至150%。
  3. 如申請專利範圍第1項所述的半導體裝置，更包括：多對所述接墊與所述導電圖案，其中：所述導電圖案中的一個的長度平行於第一方向，所述導電圖案中的另一個的長度平行於第二方向，且所述第一方向與所述第二方向相對於彼此斜交。
  4. 如申請專利範圍第1項所述的半導體裝置，其中所述導電圖案具有八邊形平面形狀，且所述開口具有八邊形平面形狀。
  5. 如申請專利範圍第1項所述的半導體裝置，更包括所述導電圖案的焊料圖案，其中所述焊料圖案含有與所述導電圖案的材料不同的材料。
  6. 一種半導體裝置，包括：基底；第一凸塊堆疊，設置在所述基底的表面上，所述第一凸塊堆疊包括第一接墊及位於所述第一接墊上的第一導電圖案；第二凸塊堆疊，設置在所述基底的所述表面上，所述第二凸塊堆疊包括第二接墊及位於所述第二接墊上的第二導電圖案；以及絕緣圖案，設置在所述基底的所述表面上且具有第一開口及第二開口，其中：所述第一接墊的寬度大於所述第一導電圖案的寬度，所述第一導電圖案的長度大於所述第一接墊的長度，所述第二導電圖案的寬度大於所述第二接墊的寬度，所述第一導電圖案的寬度方向及所述第二導電圖案的寬度方向平行於第一方向，當在平面圖中觀察時，所述第一接墊具有與所述第一導電圖案間隔開的相對兩端，所述第一開口被設置成暴露出所述第一接墊，所述第二開口被設置成暴露出所述第二接墊，所述第一開口的寬度小於所述第一接墊的所述寬度及所述第一導電圖案的所述寬度，且 所述第一開口的長度小於所述第一接墊的所述長度及所述第一導電圖案的所述長度。
  7. 如申請專利範圍第6項所述的半導體裝置，其中所述第二接墊的長度大於所述第二導電圖案的長度。
  8. 如申請專利範圍第7項所述的半導體裝置，其中所述第一接墊的所述寬度是所述第一導電圖案的所述寬度的110%至150%，所述第一導電圖案的所述長度是所述第一接墊的所述長度的110%至150%，所述第二導電圖案的所述寬度是所述第二接墊的所述寬度的110%至150%，且所述第二接墊的所述長度是所述第二導電圖案的所述長度的110%至150%。
  9. 如申請專利範圍第6項所述的半導體裝置，其中所述第一導電圖案的所述長度是所述第一導電圖案的所述寬度的1.7倍至3倍。
  10. 如申請專利範圍第6項所述的半導體裝置，其中所述第二導電圖案的所述寬度實質上等於所述第一導電圖案的所述長度。
  11. 如申請專利範圍第6項所述的半導體裝置，其中當在平面圖中觀察時，所述第一導電圖案及所述第二導電圖案被設置成分別與所述基底的第一側及第二側相鄰，且所述基底的所述第一側及所述第二側彼此相鄰。
  12. 如申請專利範圍第6項所述的半導體裝置，其中所述基底包括電路層，且所述第一接墊與所述第二接墊電性連接到所述電路層。
  13. 一種半導體裝置，包括： 半導體晶片；接墊，設置在所述半導體晶片上；絕緣圖案，設置在所述半導體晶片上，所述絕緣圖案具有開口，所述開口暴露出所述接墊；以及導電圖案，設置在所述開口中且耦合到所述接墊，其中：當在平面圖中觀察時，所述接墊的兩個相對的端部與所述導電圖案間隔開，所述導電圖案的兩個相對的端部與所述接墊間隔開，當在所述平面圖中觀察時，所述導電圖案包括第一導電圖案及第二導電圖案，所述第一導電圖案的長軸平行於第一方向，所述第二導電圖案的長軸平行於第二方向，且所述第一方向與所述第二方向相對於彼此斜交，其中所述開口的寬度小於所述接墊的寬度及所述導電圖案的寬度，且所述開口的長度小於所述接墊的長度及所述導電圖案的長度。
  14. 如申請專利範圍第13項所述的半導體裝置，其中所述導電圖案在所述導電圖案的長軸方向上的圖案尺寸是所述導電圖案在所述導電圖案的短軸方向上的圖案尺寸的1.7倍至3倍。
  15. 如申請專利範圍第13項所述的半導體裝置，其中所述導電圖案包括：凸塊下圖案，耦合到所述接墊；以及柱狀圖案，設置在所述凸塊下圖案上。
  16. 如申請專利範圍第13項所述的半導體裝置，更包括： 封裝基底，其中：所述導電圖案設置在所述半導體晶片與所述封裝基底之間，且所述半導體晶片通過所述導電圖案電性連接到所述封裝基底。
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