CN107958889B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN107958889B
CN107958889B CN201710953285.4A CN201710953285A CN107958889B CN 107958889 B CN107958889 B CN 107958889B CN 201710953285 A CN201710953285 A CN 201710953285A CN 107958889 B CN107958889 B CN 107958889B
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pattern
pad
conductive pattern
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CN107958889A (zh
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朴秀贞
白宝娜
金庸镐
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

一种半导体装置包括半导体芯片、设置在所述半导体芯片上的接垫以及设置在半导体芯片上的绝缘图案。所述绝缘图案具有暴露出所述接垫的开口，且在所述开口中设置有导电图案，所述导电图案耦合到所述接垫。当在平面图中观察时，所述接垫的两个相对的端部与所述导电图案间隔开，且所述导电图案的两个相对的端部与所述接垫间隔开。另外，当在平面图中观察时，所述导电图案包括第一导电图案及第二导电图案，所述第一导电图案的长度平行于第一方向，所述第二导电图案的长度平行于第二方向。所述第一方向与所述第二方向相对于彼此斜交。

Description

半导体装置
[相关申请的交叉参考]
本专利申请主张在2016年10月14日在韩国知识产权局提出申请的韩国专利申请第10-2016-0133793号的优先权，所述韩国专利申请的全部内容并入本文供参考。
技术领域
本发明涉及一种半导体装置，且具体来说，涉及一种半导体装置的凸块堆叠。
背景技术
对具有许多引脚及小的节距的半导体装置的需求正在增大。因此，已进行了许多研究来使半导体装置按比例缩小。半导体装置具有电连接结构(例如，焊料球或焊料凸块)以电连接到另一电子装置或印刷电路板。需要开发一种旨在提高半导体装置的电连接结构的可靠性及稳定性的技术。
发明内容
本发明的一些实施例提供一种可靠性高的半导体装置及包括所述半导体装置的半导体封装。
本发明的一些实施例提供一种高缩比(highly-scaled)的半导体装置。
根据本发明的一些实施例，一种半导体装置可包括：半导体芯片；接垫，设置在所述半导体芯片上；绝缘图案，设置在所述半导体芯片上且具有开口，所述开口暴露出所述接垫；以及导电图案，设置在所述绝缘图案上。当在平面图中观察时，所述接垫可具有与所述导电图案间隔开的两个相对的端部，且所述导电图案可具有与所述接垫间隔开的两个相对的端部。所述导电图案在所述导电图案的长度的方向上的图案尺寸可为所述导电图案在所述导电图案的宽度的方向上的图案尺寸的1.7倍至3倍。
根据本发明的一些实施例，一种半导体装置可包括：衬底；第一凸块堆叠，设置在所述衬底的表面上且包括第一接垫及位于所述第一接垫上的第一导电图案；以及第二凸块堆叠，设置在所述衬底的所述表面上且包括第二接垫及位于所述第二接垫上的第二导电图案。所述第一接垫的宽度可大于所述第一导电图案的宽度，所述第一导电图案的长度可大于所述第一接垫的长度，且所述第二导电图案的宽度可大于所述第二接垫的宽度。所述第一导电图案的宽度方向及所述第二导电图案的宽度方向可平行于第一方向。
根据本发明的一些实施例，一种半导体装置可包括：半导体芯片；接垫，设置在所述半导体芯片上；绝缘图案，设置在所述半导体芯片上且具有开口，所述开口暴露出所述接垫；以及导电图案，设置在所述开口中且耦合到所述接垫。当在平面图中观察时，所述接垫的两个相对的端部可与所述导电图案间隔开，且所述导电图案的两个相对的端部可与所述接垫间隔开。另外，当在平面图中观察时，所述导电图案可包括第一导电图案及第二导电图案，所述第一导电图案的长轴平行于第一方向，所述第二导电图案的长轴平行于第二方向，且所述第一方向与所述第二方向可相对于彼此斜交(oblique to each other)。
根据本发明的一些实施例，一种半导体装置包括半导体芯片。在所述半导体芯片上设置有接垫以在半导体芯片的第一电组件与位于半导体芯片外部的第二电组件之间传送电信号。在所述半导体芯片上设置有绝缘图案，所述绝缘图案具有开口，所述开口暴露出所述接垫的中心部分。在所述绝缘图案上设置有导电图案，且所述导电图案被形成为使得导电图案的长轴垂直于所述接垫的长轴，且所述导电图案沿所述导电图案的长轴的长度是所述导电图案的平行于所述接垫的长轴的宽度的约1.7倍至3倍。且所述导电图案与所述接垫的暴露出的中心部分完全重叠。
附图说明
结合附图阅读以下简要说明将会更清楚地理解各示例性实施例。所述附图代表本文中所阐述的非限制性示例性实施例。
图1A是说明根据本发明一些实施例的半导体装置的平面图。
图1B是沿图1A所示线I-I'截取的剖视图。
图2是说明根据本发明一些实施例的半导体封装的剖视图。
图3A是说明根据本发明一些实施例的凸块堆叠的平面图。
图3B是沿图3A所示线IV-IV'截取的剖视图。
图3C是沿图3A所示线V-V'截取的剖视图。
图3D是沿图3A所示线VI-VI'截取的剖视图。
图4A至图4G是说明根据本发明一些实施例的半导体封装的放大剖视图。
图5A是说明根据本发明一些实施例的半导体装置的平面图。
图5B是沿图5A所示线VII-VII'截取的剖视图。
图5C是沿图5A所示线V-V'截取的剖视图。
应注意，这些图旨在说明某些示例性实施例中所使用的方法、结构及/或材料的一般特性且旨在对下文提供的书面说明进行补充。然而，这些图式并未按比例绘制且可能并不精确地反映任意给定实施例的精确结构或性能特性，且不应被解释为界定或限制示例性实施例所涵盖的值或特性的范围。举例来说，为清楚起见，可减小或夸大分子、层、区及/或结构性元件的相对厚度及定位。在各图式中所使用的相似或相同的参考编号旨在表示存在相似或相同的元件或特征。
具体实施方式
以下将阐述根据本发明一些实施例的半导体装置及其半导体封装。
图1A是说明根据本发明一些实施例的半导体装置的平面图。图1B是沿图1A所示线I-I'截取的剖视图。
参照图1A及图1B，半导体装置10可包括半导体衬底100以及凸块堆叠201及202。半导体装置10可为存储器芯片、逻辑芯片或包括存储器元件及逻辑元件二者的半导体芯片。半导体衬底100可由硅、锗或硅锗形成或者可包含硅、锗或硅锗。半导体衬底100可具有彼此面对的第一表面100a与第二表面100b。半导体衬底100可包括电路层110。
凸块堆叠201及202可设置在半导体衬底100的第一表面100a上。凸块堆叠201及202可电连接到设置在电路层110中的集成装置(图中未示出)。在本说明书中，表达方式“电连接或电耦合”可意指多个元件直接连接/直接耦合到彼此或者通过另一导电元件间接连接或间接耦合到彼此。另外，表达方式“元件电连接或电耦合到电路层110”可意指所述元件电连接或电耦合到设置在电路层110中的集成装置。凸块堆叠201及202可用作用于从半导体装置10接收电信号或将电信号发送到半导体装置10的路径。凸块堆叠201及202可包括彼此间隔开的第一凸块堆叠201及第二凸块堆叠202。第一凸块堆叠201可包括第一接垫211及第一导电图案221，且第二凸块堆叠202可包括第二接垫212及第二导电图案222。接垫211及212可设置在半导体衬底100的第一表面100a上。接垫211及212可包含导电材料(例如，铝或铜)。当在平面图中观察时，第一接垫211的中心部分可与第一导电图案221的中心部分重叠，而第一接垫211的两个相对的端部可不与第一导电图案221重叠。第一接垫211的中心部分可设置在第一接垫211的两个相对的端部之间。第一方向x及第二方向y可平行于半导体衬底100的第一表面100a。第一方向x与第二方向y可相对于彼此斜交。第三方向z可实质上垂直于半导体衬底100的第一表面100a。当在平面图中观察时，第一导电图案221的长轴可平行于第一方向x且第一导电图案221的短轴可平行于第二方向y。
如上所述，第二凸块堆叠202可包括第二接垫212及第二导电图案222。当将第二凸块堆叠202旋转90度时，第二凸块堆叠202可具有与第一凸块堆叠201实质上相同的平面形状。第二导电图案222的长轴可平行于第二方向y。第二导电图案222的两个相对的端部可不与第二接垫212重叠。第二接垫212的两个相对的端部可不与第二导电图案222重叠。
如图1B所示，导电图案221及222可包括凸块下图案231及232以及柱状图案241及242。尽管图中未示出，然而凸块下图案231及232中的每一个可包括障壁图案及晶种图案。障壁图案可由钛、钨、铬或其合金形成或者可包含钛、钨、铬或其合金。晶种图案可由铜、镍或其合金形成或者可包含铜、镍或其合金。柱状图案241及242可设置在凸块下图案231及232上。柱状图案241及242可由含铜材料形成。在第一导电图案221及第二导电图案222的底表面上可分别设置有第一焊料图案251及第二焊料图案252。
图2是说明根据本发明一些实施例的半导体封装的剖视图。为使说明简洁起见，可由相似的或相同的参考编号来标识前面阐述的元件，而不再对其重复的说明予以赘述。
参照图2，除了半导体装置10之外，半导体封装1还可包括封装衬底1000。举例来说，封装衬底1000可包括印刷电路板。在封装衬底1000的顶表面上可设置有导电接垫1100。在封装衬底1000的底表面上可设置有外部端子1900。导电接垫1100可通过封装衬底1000电连接到外部端子1900，如由虚线所示。半导体装置10可被配置成具有与参照图1A及图1B阐述的半导体装置10实质上相同的特征。半导体装置10可安装在封装衬底1000上。半导体装置10可被设置成使得第一表面100a面对封装衬底1000的顶表面。凸块堆叠201及202可通过回焊工艺连接到导电接垫1100，且因此，半导体装置10可电连接到封装衬底1000。凸块堆叠201及202可夹置在封装衬底1000与半导体装置10之间。在封装衬底1000的顶表面上可设置有模制图案2000以覆盖半导体装置10。模制图案2000可延伸至填充封装衬底1000与半导体装置10之间的间隙，从而密封地包封凸块堆叠201及202。在下文中，将更详细地阐述凸块堆叠201及202。
图3A是说明根据本发明一些实施例的凸块堆叠的平面图。举例来说，图3A可为图1A所示区II的平面图。图3B是沿图3A所示线IV-IV'截取的剖视图且示出图1B所示区III的放大截面。图3C是沿图3A所示线V-V'截取的剖视图。图3D是沿图3A所示线VI-VI'截取的剖视图。为使说明简洁起见，可由相似的或相同的参考编号来标识前面阐述的元件，而不再对其重复的说明予以赘述。
参照图3A及图3B，半导体装置10可包括半导体衬底100、绝缘图案120以及凸块堆叠201及202。半导体衬底100可包括电路层110。电路层110可包括绝缘层111、集成装置115及内部线113，且此处，集成装置115及内部线113可设置在绝缘层111中。集成装置115可包括例如晶体管。第一凸块堆叠201可包括第一接垫211、第一导电图案221及第一焊料图案251。第二凸块堆叠202可包括第二接垫212、第二导电图案222及第二焊料图案252。第一接垫211及第二接垫212可设置在电路层110的底表面上。接垫211及212可由导电材料(例如，铝)形成或者包含导电材料。接垫211及212可通过内部线113电连接到集成装置115。
绝缘图案120可设置在半导体衬底100、第一接垫211及第二接垫212上。绝缘图案120可覆盖第一接垫211的两个相对的端部及第二接垫212的两个相对的端部。绝缘图案120可有助于减小施加到第一接垫211及第二接垫212中的每一个的两个相对的端部的应力。绝缘图案120可包括第一绝缘图案121及第二绝缘图案122。第一绝缘图案121可由氧化硅、氮化硅或氮氧化硅形成或者可包含氧化硅、氮化硅或氮氧化硅。第二绝缘图案122可设置在第一绝缘图案121上。第二绝缘图案122可由聚合物(例如，聚酰亚胺)形成或者可包含聚合物。绝缘图案120可被设置成具有第一开口131及第二开口132。第一开口131及第二开口132可被设置成分别暴露出第一接垫211及第二接垫212。举例来说，第一绝缘图案121中的开口131及132以及第二绝缘图案122中的开口131及132可通过单个工艺(例如，通过单个蚀刻工艺)形成。第一绝缘图案121中的开口131的内侧表面及开口132的内侧表面可分别从第二绝缘图案122中的开口131的内侧表面及开口132的内侧表面延伸。
第一导电图案221可包括第一凸块下图案231及第一柱状图案241。第一凸块下图案231可设置在绝缘图案120的底表面上及第一开口131中。第一凸块下图案231可耦合到第一接垫211。第一柱状图案241可设置在第一凸块下图案231上。当在平面图中观察时，第一柱状图案241可与第一凸块下图案231重叠。第一柱状图案241可在第三方向z上与第一凸块下图案231对齐。
如图3A及图3B所示，第一接垫211的宽度W2可大于第一导电图案221的宽度W1。在本说明书中，元件的宽度可为元件在第一方向x上的图案尺寸(pattern size)，且元件的长度可为元件在第二方向y上的图案尺寸。元件的图案尺寸可为元件在所选择方向上的最大图案尺寸。第一导电图案221的宽度W1可实质上等于第一凸块下图案231的宽度及第一柱状图案241的宽度。在其中第一接垫211的宽度W2小于第一导电图案221的宽度W1的110％、且在形成第一开口131的过程中存在工艺故障(例如，掩模图案未对齐)的情形中，第一接垫211可能不被第一开口131暴露出。另外，在制造或操作半导体装置10的过程期间，电路层110可能被机械应力损坏。举例来说，在电路层110中可形成裂纹，从而造成内部线113或集成装置115的损坏。在其中第一接垫211的宽度W2大于第一导电图案221的宽度W1的150％的情形中，半导体装置10的占用面积可能增大。在一些实施例中，第一接垫211的宽度W2可为第一导电图案221的宽度W1的约110％至150％。由于第一接垫211会吸收机械应力，因此可使得防止或抑制电路层110被机械应力损坏成为可能。此外，可防止工艺故障或第一开口131的未对齐且因此第一导电图案221可良好地连接到第一接垫211。因此，半导体装置10可按比例缩小(scaled down)。在第一方向x上，第一开口131的图案尺寸D1可小于第一接垫211的宽度W2及第一导电图案221的宽度W1。即使存在工艺故障，第一开口131仍可被形成为暴露出第一接垫211。
结合图2参照图3A及图3C，第一导电图案221的长度L1可大于第一接垫211的长度L2。第一导电图案221的长度L1可实质上等于第一凸块下图案231的长度及第一柱状图案241的长度。在其中第一导电图案221的长度L1小于第一接垫211的长度L2的110％的情形中，在第一凸块堆叠201与图2所示封装衬底1000的导电接垫1100中的对应的一个导电接垫1100之间的电连接中可能出现故障。作为实例，在回焊工艺期间，在第一凸块堆叠201与导电接垫1100中的一个导电接垫1100之间可能出现非润湿问题(non-wetting issue)。作为另一实例，在半导体封装1的操作期间，电路层110可被机械应力损坏。在其中第一导电图案221的长度L1大于第一接垫211的长度L2的150％的情形中，半导体装置10的占用面积可能增大。在一些实施例中，第一导电图案221的长度L1可为第一接垫211的长度L2的约110％至150％。第一凸块堆叠201可牢固地连接到图2所示封装衬底1000的导电接垫1100中的一个导电接垫1100。半导体装置10可按比例缩小。
当在第二方向y上测量时，第一开口131的图案尺寸D2可小于第一接垫211的长度L2及第一导电图案221的长度L1。绝缘图案120可被设置成覆盖第一接垫211的两个相对的端部并保护第一接垫211。第一接垫211的长度L2被示出为大于第一接垫211的宽度W2，但在某些实施例中，第一接垫211的长度L2可实质上等于第一接垫211的宽度W2。
第二导电图案222可包括第二凸块下图案232及第二柱状图案242。第二导电图案222可与第一导电图案221相似。举例来说，第二凸块下图案232及第二柱状图案242可由与第一凸块下图案231及第一柱状图案241相同的材料形成或者可包含与第一凸块下图案231及第一柱状图案241相同的材料。第二凸块下图案232可设置在绝缘图案120上及第二开口132中。第二凸块下图案232可耦合到第二接垫212。第二柱状图案242可设置在第二凸块下图案232上且可在第三方向z上与第二凸块下图案232对齐。
当将第二导电图案222旋转90度时，第二导电图案222可具有与第一导电图案221实质上相同的平面形状。举例来说，第二导电图案222的宽度W3可实质上等于第一导电图案221的长度L1，且第二导电图案222的长度L3可实质上等于第一导电图案221的宽度W1。第二接垫212的宽度W4可实质上等于第一接垫211的长度L2，且第二接垫212的长度L4可实质上等于第一接垫211的宽度W2。在本说明书中，长度与宽度相等是指两个长度或宽度之间的差处于制造工艺的工艺容差(process tolerance)内，且这种差并不是人们所期望的。
如图3A及图3B所示，第二导电图案222的宽度W3可大于第二接垫212的宽度W4。第二导电图案222的宽度W3可实质上等于第二凸块下图案232的宽度及第二柱状图案242的宽度。举例来说，第二导电图案222的宽度W3可为第二接垫212的宽度W4的约110％至150％。由于第二接垫212会吸收机械应力，因此可使得防止或抑制电路层110被损坏成为可能。半导体装置10可按比例缩小。在第一方向x上，第二开口132的图案尺寸D3可小于第二导电图案222的宽度W3及第二接垫212的宽度W4。即使在形成第二开口132的过程中存在工艺故障，第二开口132仍可被形成为暴露出第二接垫212。因此，第二导电图案222可良好地连接到第二接垫212。
如图3A及图3D所示，第二导电图案222的长度L3可实质上等于第二凸块下图案232的长度及第二柱状图案242的长度。第二接垫212的长度L4可大于第二导电图案222的长度L3。举例来说，第二接垫212的长度L4可为第二导电图案222的长度L3的约110％至150％。因此，半导体衬底100可通过第二凸块堆叠202稳定地连接到图2所示封装衬底1000，且半导体衬底100可按比例缩小。在第二方向y上，第二开口132的图案尺寸D4可小于第二导电图案222的长度L3及第二接垫212的长度L4。
导电图案221及222中的每一个在各自的长轴方向上的图案尺寸可为在各自的短轴方向上的图案尺寸的1.7倍至3倍(例如，2倍)。举例来说，第一导电图案221的长度L1可为第一导电图案221的宽度W1的1.7倍至3倍。第二导电图案222的宽度W3可为第二导电图案222的长度L3的1.7倍至3倍。在一些实施例中，导电图案221及222中的每一个在各自的长轴方向上的图案尺寸可为在各自的短轴方向上的图案尺寸的约2倍。在其中导电图案221及222中的每一个在各自的长轴方向上的图案尺寸比在各自的短轴方向上的图案尺寸的1.7倍小的情形中，在将凸块堆叠201及凸块堆叠202连接到封装衬底1000的导电接垫1100时可能出现故障。另外，在制造或操作半导体装置10的过程期间，电路层110可被机械应力损坏。相比之下，在其中导电图案221及222中的每一个在各自的长轴方向上的图案尺寸比在各自的短轴方向上的图案尺寸的3倍大的情形中，在导电图案221及222之间可能形成短路，或者半导体装置10的占用面积可能增大。在一些实施例中，导电图案221及222中的每一个可被配置成使各自的长图案尺寸与短图案尺寸之间的比率能够处于可允许的范围内，且这可使得防止或抑制电路层110被损坏成为可能。结果，凸块堆叠201及202可良好地连接到封装衬底1000。
在第一柱状图案241的底表面及第二柱状图案242的底表面上可分别设置有第一焊料图案251及第二焊料图案252。第一焊料图案251及第二焊料图案252可延伸至至少部分地覆盖柱状图案241的侧表面及242的侧表面。第一焊料图案251及第二焊料图案252可由与第一导电图案221及第二导电图案222的材料不同的材料形成或者可包含与第一导电图案221及第二导电图案222的材料不同的材料。举例来说，焊料图案251及252可由锡、铅、银或其合金形成或者可包含锡、铅、银或其合金。
将参照图1A阐述凸块堆叠201及202的平面排列。当在平面图中观察时，半导体衬底可具有第一侧101、第二侧102、第三侧103及第四侧104。半导体衬底100的第一侧101与第三侧103可彼此相对且与第二侧102及第四侧104相邻。半导体衬底100的第一侧101及第三侧103可平行于第一方向x。半导体衬底100的第二侧102及第四侧104可平行于第二方向y。
在一些实施例中，多个第一凸块堆叠201可设置在半导体衬底100上。第一凸块堆叠201可设置在半导体衬底100的第一表面100a上且与第一侧101及第三侧103相邻。另外，多个第二凸块堆叠202可设置在半导体衬底100上。第二凸块堆叠202可设置在半导体衬底100的第一表面100a上且与第二侧102及第四侧104相邻。导电图案221及222的排列可根据凸块堆叠201及202的排列而改变。通过控制凸块堆叠201及202的排列，可使减小导电图案221及222的节距(pitch)成为可能。这使得将半导体封装1按比例缩小成为可能。
第一接垫211的长轴可平行于第一方向x，且第二接垫212的长轴可平行于第二方向y。彼此相邻的第一接垫211与第二接垫212之间的空间可不同于第一接垫211之间的空间以及可不同于第二接垫212之间的空间。接垫211与212之间的空间可根据凸块堆叠201及202的排列而定。第一接垫211及第二接垫212可电连接到图3B所示内部线113。通过控制凸块堆叠201及202的排列，可使得在放置电路层110的内部线113时的自由度增大成为可能。凸块堆叠201及202的平面排列可并不仅限于图式中所示的实例。
图4A至图4G是说明根据本发明一些实施例的半导体封装的放大剖视图。为使说明简洁起见，可由相似的或相同的参考编号来标识前面阐述的元件，而不再对其重复的说明予以赘述。在图4A至图4G的以下说明中，将阐述单个凸块堆叠、单个导电接垫及单个互连图案。
参照图2及图4A，第一接垫211及第一导电图案221中的每一个可具有八边形截面。绝缘图案120的第一开口131中的每一个可具有八边形截面。在其中半导体装置10安装在封装衬底1000上的情形中，第一凸块堆叠201可耦合到封装衬底1000。当在平面图中观察时，封装衬底1000可包括设置在第一导电图案221附近的互连图案1200。在其中第一导电图案221具有八边形截面的情形中，可使得防止或抑制在第一凸块堆叠201与互连图案1200之间形成短路成为可能。因此，可使得在放置互连图案1200时的自由度提高或半导体封装1的可靠性提高成为可能。尽管图中未示出，然而第一接垫211及第一开口131中的至少一个可不具有八边形截面。具有来说，第一接垫211可具有四角形截面，且绝缘图案120的第一开口131可具有圆形截面或椭圆形截面。
结合图2参照图4B，第一导电图案221可具有六边形截面。因此，可使得防止或抑制在第一凸块堆叠201与封装衬底1000的互连图案1200之间形成短路成为可能。
结合图2参照图4C及图4D，第一导电图案221可具有两个相对的侧221c及221d，所述两个相对的侧221c及221d与互连图案1200相距不同的距离定位。当在平面图中观察时，互连图案1200可比靠近第一导电图案221的一侧221d来说更靠近第一导电图案221的另一侧221c，且另一侧221c可具有比侧221d的长度L1小的长度L5或L5'。第一导电图案221的另一侧221d可为与参照图3A至图3C阐述的导电图案221的长度L1实质上相同的长度。因此，可使得防止或抑制在互连图案1200与第一凸块堆叠201之间形成短路成为可能。
结合图2参照图4E及图4F，当在平面图中观察时，第一导电图案221可被设置成具有凹陷区215。当在平面图中观察时，凹陷区215可与导电接垫1100重叠。第一焊料图案251可具有与第一导电图案221对应的形状。第一导电图案221可通过第一焊料图案251耦合到封装衬底1000的导电接垫1100。第一导电图案221可具有凹陷区215，且第一凸块堆叠201(例如，第一焊料图案251)可牢固地连接到互连图案1200。
参照图4G，第一导电图案221可具有多边形形状。第一开口131可具有三角形形状。
第一接垫211、第一开口131及第一导电图案221的平面形状可并非仅限于图4A至图4G所示实例，而是可作出各种改变。第二接垫212、第二导电图案222及第二开口132可具有与参照图4A至图4G阐述的第一接垫211、第一导电图案221及第一开口131的平面形状相似的平面形状。当将第二接垫212、第二导电图案222及第二开口132旋转90度时，第二接垫212、第二导电图案222及第二开口132可被设置成具有与第一接垫211、第一导电图案221及第一开口131对应的形状。为简洁起见，未在图4A至图4D及图4G中示出封装衬底1000的导电接垫1100，但封装衬底1000的导电接垫1100可被设置成与第一导电图案221重叠。另外，为简洁起见，未在图4E至图4G中示出封装衬底1000的互连图案1200。
图5A是说明根据本发明一些实施例的半导体装置的平面图。举例来说，图5A可为图1A所示区II的平面图。图5B是沿图5A所示线VII-VII'截取的剖视图。图5C是沿图5A所示线V-V'截取的剖视图。为使说明简洁起见，可由相似的或相同的参考编号来标识前面阐述的元件，而不再对其重复的说明予以赘述。
参照图5A至图5C，半导体装置10可包括半导体衬底100、第一凸块堆叠201及第二凸块堆叠202。第一导电图案221及第二导电图案222可被配置成具有与图1A至3D的第一导电图案221及第二导电图案222实质上相同的特征。举例来说，导电图案221及222中的每一个在各自的长轴方向上的图案尺寸可为导电图案221及222中的每一个在各自的短轴方向上的图案尺寸的1.7倍至3倍。
在半导体衬底100的第一表面100a上可设置有绝缘图案120。绝缘图案120可具有第一开口131及第二开口132。第一开口131及第二开口132可具有与接垫211及212间隔开的侧表面。第一接垫211的宽度W2可小于第一开口131在第一方向x上的图案尺寸D1。第一导电图案221的宽度W1可小于第一接垫211的宽度W2。第一接垫211的长度L2可小于第一开口131在第二方向y上的图案尺寸D2。第一导电图案221的长度L1可小于第一接垫211的长度L2。
第二接垫212的宽度W4可小于第二开口132在第一方向x上的图案尺寸D3。第二导电图案222的宽度W3可小于第二接垫212的宽度W4。第二接垫212的长度L4可小于第二开口132在第二方向y上的图案尺寸D4。第二导电图案222的长度L3可小于第二接垫212的长度L4。
根据本发明的一些实施例，可对导电图案的宽度/长度比率进行控制，且这可使得改善将凸块堆叠连接到半导体衬底或封装衬底的连接结构的电特性成为可能。接垫的两个相对的端部可不与导电图案重叠，且接垫可具有增大的占用面积。导电图案的两个相对的侧可不与接垫重叠，且导电图案可具有增大的占用面积。这可使得在半导体装置与封装衬底之间实现良好的电连接结构成为可能。在一些实施例中，半导体装置可按比例缩小。
按照所述领域中的传统，可采用用于执行所阐述的一个或多个功能的区块来阐述及说明各实施例。这些区块(在本文中可将其称作单元或模块等)是由例如逻辑门、集成电路、微处理器、微控制器、存储器电路、无源电子组件、有源电子组件、光学组件、硬接线式电路(hardwired circuit)等模拟及/或数字电路以实体方式进行实作，且可视需要通过固件及/或软件来驱动。所述电路可例如被实施于一个或多个半导体芯片中或例如印刷电路板等衬底支撑件(substrate support)上。构成区块的电路可由专用硬件、或由处理器(例如，一个或多个经过编程的微处理器及相关联的电路系统)或者由用于执行所述区块的某些功能的专用硬件与用于执行所述区块的其他功能的处理器的组合来实作。所述实施例中的每一区块可在不背离本发明的范围的条件下在实体上分成两个或更多个交互作用且分立的区块。相同地，所述实施例的区块可在不背离本发明的范围的条件下在实体上组合成多个复杂区块。
尽管已具体示出并阐述了本发明的示例性实施例，但所属领域中的普通技术人员将理解，可在不背离随附权利要求书的精神及范围的条件下，对所述示例性实施例作出形式及细节上的改变。

Claims (16)

1.一种半导体装置，其特征在于，包括：
半导体芯片；
接垫，设置在所述半导体芯片上；
绝缘图案，设置在所述半导体芯片上，所述绝缘图案具有开口，所述开口暴露出所述接垫；以及
导电图案，设置在所述绝缘图案上，其中：
当在平面图中观察时，所述接垫具有与所述导电图案间隔开的两个相对的端部，
当在平面图中观察时，所述导电图案具有与所述接垫间隔开的两个相对的端部，且
所述导电图案在所述导电图案的长度的方向上的图案尺寸是所述导电图案在所述导电图案的宽度的方向上的图案尺寸的1.7倍至3倍，且
所述开口在宽度方向上的图案尺寸小于所述接垫的宽度，且所述开口在长度方向上的图案尺寸小于所述接垫的长度。
2.根据权利要求1所述的半导体装置，其特征在于，
所述导电图案的所述长度是所述接垫的所述长度的110％至150％，且
所述接垫的所述宽度是所述导电图案的所述宽度的110％至150％。
3.根据权利要求1所述的半导体装置，其特征在于，进一步包括：
多对所述接垫与所述导电图案，其中：
所述导电图案中的一个导电图案的长度平行于第一方向，
所述导电图案中的另一个导电图案的长度平行于第二方向，且
所述第一方向与所述第二方向相对于彼此斜交。
4.根据权利要求1所述的半导体装置，其特征在于，
所述导电图案具有八边形平面形状，且
所述开口具有八边形平面形状。
5.根据权利要求1所述的半导体装置，其特征在于，进一步包括所述导电图案的焊料图案，其中所述焊料图案含有与所述导电图案的材料不同的材料。
6.一种半导体装置，其特征在于，包括：
衬底；
第一凸块堆叠，设置在所述衬底的表面上，所述第一凸块堆叠包括第一接垫及位于所述第一接垫上的第一柱状图案；
第二凸块堆叠，设置在所述衬底的所述表面上，所述第二凸块堆叠包括第二接垫及位于所述第二接垫上的第二柱状图案；以及
绝缘图案，设置在所述衬底的所述表面上且具有第一开口及第二开口，其中：
所述第一接垫的宽度大于所述第一柱状图案的宽度，
所述第一柱状图案的长度大于所述第一接垫的长度，
所述第二柱状图案的宽度大于所述第二接垫的宽度，且
所述第一柱状图案的宽度方向及所述第二柱状图案的宽度方向平行于第一方向，
当在平面图中观察时，所述第一接垫具有与所述第一柱状图案间隔开的两个相对的端部，
所述第一开口被设置成暴露出所述第一接垫，
所述第二开口被设置成暴露出所述第二接垫，
所述第一开口的宽度小于所述第一接垫的宽度及所述第一柱状图案的宽度，且
所述第一开口的长度小于所述第一接垫的长度及所述第一柱状图案的长度。
7.根据权利要求6所述的半导体装置，其特征在于，所述第二接垫的长度大于所述第二柱状图案的长度。
8.根据权利要求7所述的半导体装置，其特征在于，
所述第一接垫的所述宽度是所述第一柱状图案的所述宽度的110％至150％，
所述第一柱状图案的所述长度是所述第一接垫的所述长度的110％至150％，
所述第二柱状图案的所述宽度是所述第二接垫的所述宽度的110％至150％，且
所述第二接垫的所述长度是所述第二柱状图案的所述长度的110％至150％。
9.根据权利要求6所述的半导体装置，其特征在于，所述第一柱状图案的所述长度是所述第一柱状图案的所述宽度的1.7倍至3倍。
10.根据权利要求6所述的半导体装置，其特征在于，所述第二柱状图案的所述宽度等于所述第一柱状图案的所述长度。
11.根据权利要求6所述的半导体装置，其特征在于，当在平面图中观察时，所述第一柱状图案及所述第二柱状图案被设置成分别与所述衬底的第一侧及第二侧相邻，且所述衬底的所述第一侧及所述第二侧彼此相邻。
12.根据权利要求6所述的半导体装置，其特征在于，所述衬底包括电路层，且
所述第一接垫与所述第二接垫电连接到所述电路层。
13.一种半导体装置，其特征在于，包括：
半导体芯片；
接垫，设置在所述半导体芯片上；
绝缘图案，设置在所述半导体芯片上，所述绝缘图案具有开口，所述开口暴露出所述接垫；以及
导电图案，设置在所述开口中且耦合到所述接垫，其中：
当在平面图中观察时，所述接垫的两个相对的端部与所述导电图案间隔开，
所述导电图案的两个相对的端部与所述接垫间隔开，
当在所述平面图中观察时，所述导电图案包括第一导电图案及第二导电图案，所述第一导电图案的长轴平行于第一方向，所述第二导电图案的长轴平行于第二方向，
所述第一方向与所述第二方向相对于彼此斜交，
所述开口的宽度小于所述接垫的宽度及所述导电图案的宽度，且
所述开口的长度小于所述接垫的长度及所述导电图案的长度。
14.根据权利要求13所述的半导体装置，其特征在于，所述导电图案在所述导电图案的长轴方向上的图案尺寸是所述导电图案在所述导电图案的短轴方向上的图案尺寸的1.7倍至3倍。
15.根据权利要求13所述的半导体装置，其特征在于，所述导电图案包括：
凸块下图案，耦合到所述接垫；以及
柱状图案，设置在所述凸块下图案上。
16.根据权利要求13所述的半导体装置，其特征在于，进一步包括：
封装衬底，其中：
所述导电图案设置在所述半导体芯片与所述封装衬底之间，且所述半导体芯片通过所述导电图案电连接到所述封装衬底。
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