TWI529908B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI529908B
TWI529908B TW104106919A TW104106919A TWI529908B TW I529908 B TWI529908 B TW I529908B TW 104106919 A TW104106919 A TW 104106919A TW 104106919 A TW104106919 A TW 104106919A TW I529908 B TWI529908 B TW I529908B
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TW
Taiwan
Prior art keywords
wiring substrate
conductive pad
conductive
wiring
conductive pads
Prior art date
Application number
TW104106919A
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English (en)
Other versions
TW201523836A (zh
Inventor
Toshikazu Ishikawa
Mikako Okada
Original Assignee
Renesas Electronics Corp
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Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of TW201523836A publication Critical patent/TW201523836A/zh
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Publication of TWI529908B publication Critical patent/TWI529908B/zh

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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Description

半導體裝置
本發明係關於半導體裝置，尤其係關於適用於具有將複數之半導體封裝多段疊層之疊層封裝(Package On Package：POP)構造之半導體裝置的有效技術。
作為半導體封裝之一形態，已知的有系統級封裝(System In Package：SIP)，其係於一個配線基板上安裝不同種類之複數的半導體晶片(例如微控制器晶片及記憶體晶片)而構成系統。
作為該種SIP之一例，有日本特開平10-12809號公報(專利文獻1)中記載之多晶片模組(Multi Chip Module：MCM)。該MCM具有由絕緣層與配線層構成之多層配線基板，該多層配線基板之表面以倒裝晶片方式安裝有複數之晶片。
多層配線基板之內面，形成有排列於格子上之複數的外部輸出入信號用導電墊，該等墊上連接有由焊球等構成之外部輸出入信號端子。又，多層配線基板之表面及內層形成有連接複數之晶片之端子與外部輸出入信號端子的信號配線、及連接複數之晶片之端子間的信號配線。
再者，排列於多層配線基板之內面之外部輸出入信號用導電墊的內側，形成有複數之檢查用導電端子，該等係連接複數之晶片的端子間，且不與外部連接，藉由檢查探針接觸該檢查用導電端子，便可對晶片之所有端子的連接狀態及各晶片之動作進行檢查。
另一方面，作為不同於上述SIP之形態之半導體封裝，有日本特開2007-123454號公報(專利文獻2)中記載之疊層封裝(Package On Package：POP)。該POP不同於將複數之晶片搭載於一個配線基板上之SIP，其係製備由搭載微控制器晶片之配線基板構成之封裝及搭載由記憶體晶片之配線基板構成之封裝，藉由使該兩者重合將晶片相互連接而構成系統的疊層封裝。
POP具備複數個配線基板，故具有以下優點：即使在隨系統之多機能化使微控制器晶片之輸出入端子數增加之情形時，與相同安裝面積之SIP相比亦可增加信號配線之數量。又，由於POP係於各配線基板安裝晶片後將晶片相互連接，故可於連接晶片之步驟前判定晶片與配線基板的連接狀態，能有效提升封裝之裝配良率。再，與SIP相比，亦可靈活對應系統之少量化、多品種化。
[專利文獻1]日本特開平10-12809號公報
[專利文獻2]日本特開2007-123454號公報
作為行動電話等小型資訊通信終端機器用系統，本發明者研討導入可根據用途更改搭載之半導體晶片的POP，取代先前之SIP。
該POP係於具有多層配線層的第1配線基板的表面安裝微控制器晶片，於第2配線基板之表面安裝記憶體晶片。微控制器晶片經由沿其主面之4邊形成之複數的焊球，於第1配線基板之表面(信號用墊)以倒裝晶片方式連接(面朝下安裝)。且，記憶體晶片面朝上安裝於第2配線基板之表面，經由複數之Au線連接於第2配線基板之表面的信號用墊。
微控制器晶片之接合墊(外部連接端子)之數量極多於記憶體晶片，故，接合墊(及於其表面所形成之焊球)沿微控制器晶片之主面的 4邊配置為2行，且內側行之接合墊與外側行之接合墊以交錯配置。因此，於第1配線基板之表面所形成之導電墊亦配置為2行，且內側行之導電墊與外側行之導電墊以交錯配置。
安裝有微控制器晶片之第1配線基板與安裝有記憶體晶片之第2配線基板，經由形成於第2配線基板之內面的複數之焊球而電性連接。由於第1配線基板之表面的中央部安裝有微控制器晶片，故該等焊球沿第2配線基板之內面的外周部而配置。第1配線基板之表面的外周部(微控制器晶片之外側)形成有連接該等焊球的導電墊。
於第1配線基板之內面，與上述專利文獻1之SIP相同，形成有排列於格子上之複數的外部輸出入信號用導電墊，且該等導電墊上連接有焊球。第1配線基板之表面的信號用墊與內面之外部輸出入信號用墊，經由連接基板表面之信號配線、內層之信號配線及該二者之通孔而電性連接。
如上述而構成之POP，將第1配線基板與第2配線基板連接後，有必要進行確認微控制器晶片與記憶體晶片之導通狀態的測試步驟。該測試係將連接於微控制器晶片與記憶體晶片之測試用導電墊形成於第1配線基板的內面，藉由使探針接觸於該測試用導電墊檢查晶片間的導通狀態而進行。
上述測試用導電墊，考慮與安裝有先前之SIP之主機板的互換性，或第1配線基板之配線層數的增加，較好的是，與上述專利文獻1之SIP相同，配置於外部輸出入信號用導電墊的內側。
然而，POP之情形，由於安裝有微控制器晶片之第1配線基板與安裝有記憶體晶片之第2配線基板，係經由配置於第2配線基板之外周部之焊球而電性連接，故，若將測試用導電墊配置於外部輸出入信號用導電墊的內側，當連接上述焊球與測試用導電墊時，第1配線基板內之配線量將增多。因此，會因作為配線基板材料之配線與絕緣層的 熱膨脹係數差，導致第1配線基板易產生翹曲。作為克服該翹曲之對策，若加厚絕緣層，使配線基板具有剛性，將使POP之薄型化更困難，且配線基板之製造價格成本亦將上升。
又，隨POP之小型化、高機能化的進展，為增加微控制器晶片之外部連接端子數，且進一步促使第1配線基板之表面形成之配線或導電墊之小間距化，如上述，若以2行配置第1配線基板之表面的導電墊，且以交錯配置內側行的導電墊與外側行的導電墊，則要將連接外側行之導電墊與測試用導電墊之配線繞接穿過內側行之導電墊間將變得困難。
本發明之一目的在於提供一種推進POP之小型化、高機能化的技術。
本發明之另一目的在於提供一種提高POP之可靠性的技術。
本發明之又一目的在於提供一種降低POP之製造成本的技術。
本發明之上述及其他之目的與新穎之特徵，將藉由本說明書之記述及附加圖式詳細闡明。
本申請專利案所揭示之發明中具代表性者之概要，簡單說明如下。
本申請專利案之發明，係將安裝有具備微控制器電路之第1半導體晶片之第1配線基板、與安裝有具備記憶體電路之第2半導體晶片之第2配線基板疊層之POP構造的半導體裝置，且，上述第1配線基板係以使安裝有上述第1半導體晶片之第1面與上述第2配線基板之一面相對向而配置，且於上述第1面內，經由形成於較安裝有上述第1半導體晶片之區域更為外側之複數的第1導電墊，與上述第2配線基板電性連接；於不同於上述第1配線基板之上述第1面的第2面，形成有複數之測試用導電墊，及用以判定構成外部輸出入用端子之複數的第2導電 墊、上述第1半導體晶片及上述第2半導體晶片之導通狀態良否；上述測試用導電墊係於上述第2面內，配置於較上述第2導電墊更為外側。
1A‧‧‧POP
2‧‧‧微控制器晶片(第1半導體晶片)
3‧‧‧基底基板(第1配線基板)
4‧‧‧記憶體晶片(第2半導體晶片)
5‧‧‧記憶體基板(第2配線基板)
6p、7p‧‧‧導電墊(第3導電墊)
8p‧‧‧導電墊(第1導電墊)
9p‧‧‧外部輸出入用導電墊(第2導電墊)
10p‧‧‧測試用導電墊
11、12、13‧‧‧焊球
14‧‧‧膜下樹脂
15‧‧‧虛設晶片
16‧‧‧Au線
17、18、19‧‧‧導電墊
20‧‧‧模製塑料
21‧‧‧墊
22‧‧‧通孔
23‧‧‧內面配線
24‧‧‧通孔
25‧‧‧表面配線
26‧‧‧GND平坦層
27‧‧‧電源平坦層
30‧‧‧第2層配線
31‧‧‧第3層配線
32‧‧‧第4層配線
33‧‧‧第5層配線
35‧‧‧通孔
圖1係本發明之一實施形態之POP的概略構成的剖面圖。
圖2係構成POP之一部分之基底基板之內面的平面圖。
圖3係圖2之一部分的擴大平面圖。
圖4係於構成POP之一部分之基底基板之表面形成的導電墊的配置的平面圖。
圖5係將微控制器晶片安裝於構成POP之一部分之基底基板之表面的狀態的平面圖。
圖6係圖4之一部分的擴大平面圖。
圖7係於構成POP之一部分之基底基板之內層形成之GND平坦層的平面圖。
圖8係於構成POP之一部分之基底基板之內層形成之電源平坦層的平面圖。
圖9係將安裝於POP之微控制器晶片及記憶體晶片連接於測試用導電墊之配線路徑的一例的要部剖面圖。
圖10係安裝於POP之微控制器晶片之主面的平面圖。
圖11係將安裝於POP之微控制器晶片及記憶體晶片連接於測試用導電墊之配線路徑的另一例的要部剖面圖。
圖12係將安裝於POP之微控制器晶片及記憶體晶片連接於測試用導電墊之配線路徑的又一例的要部剖面圖。
圖13係於構成POP之一部分之基底基板的表面安裝微控制器之狀態的平面圖。
圖14係於構成POP之一部分之基底基板的表面安裝微控制器之狀態的平面圖。
[發明之效果]
藉由本申請專利案所揭示之發明中具代表性者所獲得之效果，簡單說明如下。
可推進POP的小型化、高機能化。且，可提高POP的可靠性。
以下根據圖示詳細說明本發明之實施形態。另，說明實施形態之全圖中，對於同一部件原則上附註相同符號，省略其重複說明。
(實施形態1)
本實施形態之半導體裝置係搭載於行動電話等小型資訊通信終端機器的疊層封裝(Package On Package：POP)。
首先，用圖1(剖面圖)說明本實施形態之POP的概略構成。POP 1A係2層構造的疊層型封裝，其係於安裝有第1半導體晶片2之基底基板(第1配線基板)3的上部，使安裝有第2半導體晶片4之記憶體基板(第2配線基板)5重合而成。此處，第1半導體晶片2係將可程式化邏輯電路與微控制器電路集積於1個晶片而成者，在以下說明中稱之為微控制器晶片。又，第2半導體晶片4係形成有具備512百萬位元、或1千兆位元之記憶容量的DRAM(Dynamic Random Access Memory)電路者，在以下說明中稱之為記憶體晶片。
另，圖1所示之POP 1A係於記憶體基板5之表面(上表面)疊層2個記憶體晶片4而實現1.5千兆位元之記憶容量，而亦可適當更改安裝於記憶體基板5之記憶體晶片4的記憶容量或個數。即，藉由更改安裝於記憶體基板5之記憶體晶片4的記憶容量或個數，POP 1A幾乎無需更改安裝有微控制器2之基底基板3側的規格，便可製造多品種的半導體裝置。
基底基板3係具有用增層法製造之6層之配線(表面配線、內面配線及4層之內層配線)的多層配線基板，將配線層相互電性絕緣之絕緣 層係由使玻璃纖維或碳纖維浸漬於樹脂之預成形體構成。又，6層之配線係由以銅(Cu)為主體之導電膜構成。圖1中，該等配線之圖示被省略，僅表示有形成於基底基板3之表面(上表面)的導電墊6p、7p、8p、形成於基底基板3之內面的外部輸出入用導電墊9p及測試用導電墊10p。
微控制器2經由其主面(下表面)上形成之複數的焊球11，以倒裝晶片方式連接(面朝下連接)於基底基板3之表面的導電墊(第3導電墊)6p、7p。微控制器晶片2之主面藉由膜下樹脂14密封。省略其圖示者中，微控制器2由於接合墊(輸出入端子)之數量極多，故接合墊(及其表面連接之焊球11)沿微控制器晶片2之主面的4邊被配置為2行，且，內側行的接合墊與外側行的接合墊以交錯配置。
基底基板3之內面形成有複數之外部輸出入用導電墊(第2導電墊)9p，該等表面電性連接有焊球13。POP 1A經由該等焊球13而安裝於資訊通信終端機器之主機板。省略其圖示者中，基底基板3之表面之配線與內面之外部輸出入用導電墊9p，經由內層配線及連接該等配線之通孔而電性連接。
上述外部輸出入用導電墊9p的外側形成有複數之測試用導電墊10p。該等測試用導電墊10p係於POP 1A之裝配完成後，用以判定微控制器晶片2與記憶體晶片4之導通狀態良否的端子。即，POP 1A之製造者於將裝配完成之POP 1A出貨給用戶(資訊通信終端機器製造者等)之前，將探針接觸於測試用導電墊10p來確認微控制器晶片2與記憶體晶片4的導通狀態。因此，當用戶於資訊通信終端機器之主機板上安裝POP 1A時，無需將測試用導電墊10p連接於主機板，故不於測試用導電墊10p上連接焊球13。
另一方面，安裝有2個記憶體晶片4之記憶體基板5係由以玻璃環氧樹脂等作為絕緣層之樹脂基板構成。該2個記憶體晶片4，其一個以 面朝上安裝於記憶體基板5之表面，另一個經由虛設晶片15疊層於上述記憶體晶片4之上。2個記憶體晶片4分別經由Au線16而電性連接於記憶體晶片4之表面的導電墊17。2個記憶體晶片4、虛設晶片15、Au線16及導電墊17藉由模製樹脂20予以密封。記憶體基板5之內面形成有導電墊18，該導電墊18經由無圖示之通孔而電性連接於上述導電墊17，且該導電墊18之表面電性連接有焊球12。導電墊17、18分別沿記憶體基板5之外周部被配置為2行。
連接於記憶體基板5之導電墊18的焊球12，亦電性連接於基底基板3之表面之外周部形成的導電墊(第1導電墊)8p，藉此，使安裝有微控制器晶片2之基底基板3、與安裝有記憶體晶片4之記憶體基板5電性連接。為不使安裝於基底基板3之微控制器晶片2之上表面與記憶體基板5之下表面接觸，使焊球12之直徑大於微控制器晶片2之主面形成之焊球11之直徑與微控制器晶片2之厚度的合計厚度。
如上述，基底基板3之內面形成有外部輸出入用導電墊9p及測試用導電墊10p。圖2係基底基板3之內面的平面圖，圖3係圖2之一部分(四角框包圍之區域)的擴大平面圖。另，圖2及圖3省略連接於外部輸出入用導電墊9p之焊球13的圖示。
如圖2所示，外部輸出入用導電墊9p以格子狀配置於基底基板3的內面。且，外部輸出入用導電墊9p之外側配置有測試用導電墊10p(用影線表示)。如圖3所示，各個外部輸出入用導電墊9p之附近形成有通孔22，外部輸出入用導電墊9p與其附近之通孔22藉由內面配線(第6層配線)23而電性連接。外部輸出入用導電墊9p經由通孔22及內面配線23而電性連接於內層配線(無圖示)。又，各個測試用導電墊10p之附近亦形成有通孔22，測試用導電墊10p與其附近之通孔22藉由內面配線23而電性連接。測試用導電墊10p經由通孔22及內面配線23而電性連接於後述之內層配線。
圖4係基底基板3之表面形成之導電墊6p、7p、8p的布局的平面圖，圖5係將微控制器晶片2安裝於基底基板3之表面之狀態的平面圖，圖6係圖4之一部分(四角框包圍之區域)的擴大平面圖。
如上述，微控制器晶片2之接合墊沿微控制器晶片2之主面的4邊被配置為2行，且內側行的接合墊與外側行的接合墊以交錯配置。因此，如圖4及圖6所示，載置有連接於微控制器晶片2之接合墊之焊球11的基底基板3的導電墊6p、7p，亦沿與基底基板3之4邊平行的方向被配置為2行，且內側行的導電墊6p與外側行的導電墊7p以交錯配置。又，如圖6所示，導電墊6p、7p、8p分別經由表面配線(第1層配線)25及通孔24被連接於內層配線(無圖示)。另，圖4及圖5為避免圖示繁瑣，省略了表面配線25與通孔24的圖式。
圖7係於基底基板3之內層(第3層之配線層)形成之GND平坦層26的平面圖，圖8係於第4層配線層形成之電源平坦層27的平面圖。
為促進供給於POP 1A之電源的安定化，除連接上下層之配線之通孔(無圖示)所形成的區域以外，GND平坦層26係以覆蓋第3層配線層之大致全面而形成。基於同樣的理由，除連接上下層之配線之通孔(無圖示)所形成的區域以外，電源平坦層27亦以覆蓋第4層配線層之大致全面而形成。
圖9係將微控制器晶片2及記憶體晶片4連接於測試用導電墊10p之配線之路徑的一例的要部剖面圖。如圖9所示，經由形成於基底基板3之配線層，將微控制器晶片2及記憶體晶片4連接於測試用導電墊10p之情形時，原則上，微控制器晶片2與記憶體晶片4經由外側行的導電墊7p而電性連接。其理由為，如上述，在POP構造之情形時，用以促使連接於記憶體基板5之導電墊18的焊球12與基底基板3導通的導電墊(第1導電墊)8p，係位於較用以與微控制器2電性連接的導電墊6p、7p之更外(基底基板之周緣部)側。又因為，隨半導體裝置之小型化使導 電墊6p、7p之間距變小，故於該導電墊間繞接配線變得困難。
因此，如圖10所示，與微控制器晶片2相同，於微控制器晶片2之主面形成之複數的導電墊(電極)19中，原則上，於外側(微控制器晶片2之周緣部)行配置有電性連接於測試用導電墊10p之導電墊19。圖9所示之例中，微控制器晶片2與記憶體晶片4，經由與外側行之導電墊7p一體形成之表面配線25而電性連接。又，該表面配線25，經由基底基板3之外周附近形成之第2層配線30、第3層配線31、第4層配線32、第5層配線33及將該等電性連接之通孔22、24、35，而電性連接於測試用導電墊10p。
又，如圖11所示之例中，微控制器晶片2與記憶體晶片4，經由與外側行之導電墊7p一體形成之表面配線25、通孔24及第2層配線30而電性連接。又，該第2層配線30，經由基底基板3之外周附近形成之第3層配線31、第4層配線32、第5層配線33及將該等電性連接之通孔22、24、35，而電性連接於測試用導電墊10p。
另，因配線設計規則之限制，當產生不能經由外側行之導電墊7p將微控制器晶片2與記憶體晶片4電性連接之處時，或因微控制器2之設計規則的限制，不能於外側行之墊(電極)7p配置與測試用導電墊10p電性連接之墊(第1墊)時，則經由內側行之導電墊6p將微控制器晶片2與記憶體晶片4電性連接。例如圖12所示之例，微控制器晶片2與記憶體晶片4係經由內側行之導電墊6p、通孔24、及延伸於比外側行之導電墊7p更內側之第2層配線30而電性連接。又，該第2層配線30，經由基底基板3之外周附近形成之第3層配線31、第4層配線32、第5層配線33及將該等電性連接之通孔22、24、35，而電性連接於測試用導電墊10p。
如此，本實施形態之POP 1A將用以判定微控制器晶片2與記憶體晶片4之導通狀態良否的測試用導電墊10p配置於外部輸出入用導電墊 9p的外側。而將微控制器晶片2及記憶體晶片4電性連接於測試用導電墊10p時，原則上使用外側行的導電墊7p，唯有因配線設計規則之限制而不能使用外側行之導電墊7p時，才使用內側行的導電墊6p。
藉此，比較將測試用導電墊10p配置於外部輸出入用導電墊9p之內側之情形，可縮短焊球12至測試用導電墊10p之配線路徑。因此，形成於基底基板3之配線量減少，故可抑制配線與絕緣層(預成形體)之熱膨脹係數差所引起之基底基板3的翹曲。基底基板3形成之配線量，即配線長度縮短，故又可期待雜訊之降低等電性特性之提高。
又，藉由上述方法，將連接微控制器晶片2及記憶體晶片4與測試用導電墊10p之通孔35，配置於基底基板3之外周附近。另一方面，將測試用導電墊10p配置於外部輸出入用導電墊9p之內側時，則將連接微控制器晶片2及記憶體晶片4與測試用導電墊10p之通孔配置於基底基板3之內側。然而，當該通孔被配置於基底基板3之內側時，形成於基底基板3之內層之GND平坦層26及電源平坦層27容易因通孔而受到區隔，故其面積減小。相對於此，將連接微控制器晶片2及記憶體晶片4與測試用導電墊10p之通孔35配置於基底基板3之外周附近之本實施形態的POP LA，由於GND平坦層26及電源平坦層27較難因通孔35而受到區隔，故GND平坦層26及電源平坦層27之面積增加，可謀求供給於POP 1A之電源的安定化。
又，藉由使用外側行之導電墊7p將微控制器晶片2及記憶體晶片4連接於測試用導電墊10p，可將連接於導電墊7p之表面配線25引出到導電墊7p之外側，將連接於內側行之導電墊6p的表面配線25引出到導電墊6p之內側。藉此，便不需要穿過相鄰的內側之導電墊6p、6p之間、或相鄰的外側之導電墊7p、7p之間的表面配線25，使得更容易實現導電墊6p、7p之小間距化。
又，由於導電墊6p、7p之小間距化變得容易，可降低基底基板3 之製造成本。即，製作於小間距之導電墊6p、7p之間配置配線之配線基板時，需有如ABF薄膜等之高價的配線基板材料。然而，不於導電墊6p、7p之間配置配線之情形時，可以比於導電墊6p、7p之間配置配線之情形較寬鬆之配線設計規則使導電墊6p、7p小間距化，故可使用比ABF薄膜加工精度低、但製造價格成本便宜之預成形體等的配線基板材料。
將外側行之導電墊7p連接於測試用導電墊10p時，只要使用沿基底基板3之4邊配置之導電墊7p中，形成於基底基板3之角隅部與其附近之區域(例如上述圖4之四角框包圍之區域)的導電墊7p即可。
(實施形態2)
上述實施形態1中，將微控制器晶片2安裝於基底基板3之表面的中央，但如圖13或圖14所示，亦可將微控制器晶片2安裝於偏離基底基板3之表面之中央的位置。該情形下，亦可於連接於測試用導電墊10p之外側之導電墊7p的附近配置導電墊8p，且，藉由將測試用導電墊10p配置於外側之導電墊7p的外側，亦可減少形成於基底基板3之配線量。
以上，根據實施形態具體說明了本發明者所為之發明，然而本發明並非限定於上述實施形態，當然亦可於不脫離其要旨之範圍內進行各種更改。
例如，亦可於基底基板(第1配線基板)上疊層複數之記憶體基板(第2配線基板)。又，安裝於記憶體基板(第2配線基板)之記憶體晶片(第2半導體晶片)，亦可為具有DRAM以外之記憶體電路，例如快閃記憶體電路之記憶體晶片。
[產業上之可利用性]
本發明可有效適用於具有將複數之半導體封裝以多段疊層之疊層封裝(POP)構造的半導體裝置。
1A‧‧‧POP
2‧‧‧微控制器晶片(第1半導體晶片)
3‧‧‧基底基板(第1配線基板)
4‧‧‧記憶體晶片(第2半導體晶片)
5‧‧‧記憶體基板(第2配線基板)
6p、7p‧‧‧導電墊(第3導電墊)
8p‧‧‧導電墊(第1導電墊)
9p‧‧‧外部輸出入用導電墊(第2導電墊)
10p‧‧‧測試用導電墊
11、12、13‧‧‧焊球
14‧‧‧膜下樹脂
15‧‧‧虛設晶片
16‧‧‧Au線
17、18‧‧‧導電墊
20‧‧‧模製塑料
22‧‧‧通孔
24‧‧‧通孔
25‧‧‧表面配線
26‧‧‧GND平坦層
27‧‧‧電源平坦層
30‧‧‧第2層配線
31‧‧‧第3層配線
32‧‧‧第4層配線
33‧‧‧第5層配線
35‧‧‧通孔

Claims (23)

  1. 一種半導體裝置，其包含：第1配線基板，其包含第1表面、形成於上述第1表面之複數的第1導電墊、形成於上述第1表面的複數之第2導電墊、與上述第1表面為相反側之第2表面、形成於上述第2表面的複數之外部輸出入用導電墊、及形成於上述第2表面的複數之測試用導電墊，上述第1配線基板之上述第2導電墊係分別電性連接於上述第1配線基板之上述第1導電墊，且上述第1配線基板之上述測試用導電墊係分別電性連接於上述第1配線基板之上述第1導電墊及上述第1配線基板之上述第2導電墊之兩者；第1半導體晶片，其係搭載於上述第1配線基板之上述第1表面，該第1半導體晶片係電性連接於上述第1配線基板之上述第1導電墊；第2配線基板，其係包含第3表面、形成於上述第3表面的複數之第3導電墊、與上述第3表面相反側之第4表面、及形成於上述第4表面的複數之第4導電墊，上述第2配線基板之上述第4導電墊係分別電性連接於上述第2配線基板之上述第3導電墊，且上述第2配線基板係以使上述第2配線基板之上述第4表面與上述第1配線基板之上述第1表面相對向之方式疊層於上述第1配線基板上；第2半導體晶片，其係搭載於上述第2配線基板之上述第3表面，該第2半導體晶片係電性連接於上述第2配線基板之上述第3導電墊；及複數之第1焊球，其係分別形成於上述第1配線基板之上述外部輸出入用導電墊且並未分別形成於上述第1配線基板之上述測試用導電墊；且 上述第2配線基板之上述第4導電墊係分別電性連接於上述第1配線基板之上述第2導電墊；上述第1配線基板之上述第2導電墊於俯視時係配置於上述第1半導體晶片之周圍，且於俯視時係配置於較上述第1配線基板之上述第1導電墊更靠上述第1配線基板之上述第1表面之外周部；上述第1配線基板之上述第2導電墊及上述第2配線基板之上述第4導電墊係分別形成於上述上述第1及第2配線基板之外部區域，該外部區域係位於上述第1及第2半導體晶片之外；上述第1配線基板之上述測試用導電墊於俯視時係配置於上述外部輸出入用導電墊之周圍，且於俯視時係配置於較上述第1配線基板之上述外部輸出入用導電墊更靠上述第1配線基板之上述第2表面之外周部。
  2. 如請求項1之半導體裝置，其中上述第2半導體晶片係經由複數之配線而電性連接於上述第2配線基板之上述第3導電墊；且上述第1配線基板之上述第2導電墊、上述第2配線基板之上述第4導電墊及上述第2配線基板之上述第3導電墊係分別形成於上述第1及第2配線基板之外部區域，該外部區域係位於上述第1及第2半導體晶片之外。
  3. 如請求項1之半導體裝置，其中上述第2配線基板之上述第4導電墊係分別經由複數之第2焊球而電性連接於上述第1配線基板之上述第2導電墊；且上述第1配線基板之上述第2導電墊、上述第2配線基板之上述第4導電墊及上述第2焊球係分別配置於上述第1及第2配線基板之外部區域，該外部區域係位於上述第1及第2半導體晶片之外。
  4. 如請求項1之半導體裝置，其中 上述外部輸出入用導電墊與上述測試用導電墊於俯視時係沿上述第1配線基板之上述第2表面之外周部配置，且配置成複數行；且上述測試用導電墊係配置於複數之第5導電墊之最外側之行，該複數之第5導電墊係包含上述外部輸出入用導電墊及上述測試用導電墊之兩者。
  5. 如請求項1之半導體裝置，其中上述第1配線基板係多層配線基板，其包含形成於上述第1配線基板之上述第1表面的複數之第1層配線、及形成於上述第1配線基板之上述第1表面與上述第1配線基板之上述第2表面之間的複數之第2層配線；上述第1配線基板之上述第2導電墊係分別經由上述第1層配線而電性連接於上述第1配線基板之上述第1導電墊；上述第1配線基板之上述測試用導電墊係分別經由上述第1層配線及上述第2層配線之兩者而電性連接於上述第1配線基板之上述第1導電墊及上述第1配線基板之上述第2導電墊之兩者。
  6. 如請求項1之半導體裝置，其中上述第1配線基板之絕緣層係包含在纖維中浸漬有樹脂之預成形體。
  7. 如請求項1之半導體裝置，其中於俯視時上述第1配線基板之形狀係包含矩形；上述第1半導體晶片係以倒裝晶片方式安裝於上述第1配線基板之上述第1表面上；上述第1導電墊係沿與上述第1配線基板之側平行之方向配置成2行；且內側行之上述第1導電墊與於外側行之上述第1導電墊係以交錯 方式配置。
  8. 如請求項7之半導體裝置，其中形成於上述第1配線基板之上述第2表面的上述測試用導電墊係電性連接於配置在外側行的上述第1導電墊。
  9. 如請求項8之半導體裝置，其中配置於外側行之上述第1導電墊係配置於上述第1配線基板之上述第1表面之角隅部及其附近。
  10. 一種半導體裝置，其包含：第1配線基板，其包含第1表面、形成於上述第1表面的複數之第1導電墊、形成於上述第1表面的複數之第2導電墊、與上述第1表面為相反側之第2表面、形成於上述第2表面的複數之外部輸出入用導電墊、及形成於上述第2表面的複數之測試用導電墊，上述第1配線基板之上述第2導電墊係分別電性連接於上述第1配線基板之上述第1導電墊，且上述第1配線基板之上述測試用導電墊係分別電性連接於上述第1配線基板之上述第1導電墊及上述第1配線基板之上述第2導電墊之兩者；第1半導體晶片，其係搭載於上述第1配線基板之上述第1表面，該第1半導體晶片係電性連接於上述第1配線基板之上述第1導電墊；第2配線基板，其係包含第3表面、形成於上述第3表面的複數之第3導電墊、與上述第3表面為相反側之第4表面、及形成於上述第4表面的複數之第4導電墊，上述第2配線基板之上述第4導電墊係分別電性連接於上述第2配線基板之上述第3導電墊，且上述第2配線基板係以使上述第2配線基板之上述第4表面與上述第1配線基板之上述第1表面相對向之方式疊層於上述第1配線基板上；第2半導體晶片，其係搭載於上述第2配線基板之上述第3表 面，該第2半導體晶片係電性連接於上述第2配線基板之上述第3導電墊；及複數之第1焊球，其係分別形成於上述第1配線基板之上述外部輸出入用導電墊，且並未分別形成於上述第1配線基板之上述測試用導電墊；其中上述第2配線基板之上述第4導電墊係分別電性連接於上述第1配線基板之上述第2導電墊；上述第1配線基板之上述第2導電墊係配置於較上述第1配線基板之上述第1導電墊更靠上述第1配線基板之上述第1表面之外周部；於剖視時上述第1配線基板之上述第2導電墊及上述第2配線基板之上述第4導電墊係未與上述第2半導體晶片重疊；且上述第1配線基板之上述測試用導電墊係配置於較上述第1配線基板之上述外部輸出入用導電墊更靠上述第1配線基板之上述第2表面之外周部。
  11. 如請求項10之半導體裝置，其中上述第2配線基板之上述第4導電墊係分別經由複數之第2焊球而電性連接於上述第1配線基板之上述第2導電墊；且於剖視時上述第1配線基板之上述第2導電墊、上述第2配線基板之上述第4導電墊及上述焊球並未與上述第2半導體晶片重疊。
  12. 如請求項10之半導體裝置，其中複數之第5導電墊係包含上述外部輸出入用導電墊與上述測試用導電墊之兩者，於俯視時係沿上述第1配線基板之上述第2表面之外周部配置，且配置成複數行；且上述測試用導電墊係配置於上述複數之第5導電墊之最外側行。
  13. 如請求項10之半導體裝置，其中上述第1配線基板係多層配線基板，其包含形成於上述第1配線基板之上述第1表面的複數之第1層配線、及形成於上述第1配線基板之上述第1表面與上述第1配線基板之上述第2表面之間的複數之第2層配線；上述第1配線基板之上述第2導電墊係分別經由上述第1層配線而電性連接於上述第1配線基板之上述第1導電墊；上述第1配線基板之上述測試用導電墊係分別經由上述第1層配線及上述第2層配線之兩者而電性連接於上述第1配線基板之第1導電墊及上述第1配線基板之上述第2導電墊之兩者。
  14. 如請求項10之半導體裝置，其中上述第1配線基板之絕緣層係包含在纖維中浸漬有樹脂之預成形體。
  15. 如請求項10之半導體裝置，其中於俯視時上述第1配線基板之形狀係包含矩形；上述第1半導體晶片係以倒裝晶片方式安裝於上述第1配線基板之上述第1表面；上述第1導電墊係沿與上述第1配線基板之側平行之方向配置成2行；且於內側行的上述第1導電墊與於外側行的上述第1導電墊係以交錯方式配置。
  16. 如請求項15之半導體裝置，其中形成於上述第1配線基板之上述第2表面的上述測試用導電墊係電性連接於配置在外側行的上述第1導電墊。
  17. 如請求項16之半導體裝置，其中配置於外側行的上述第1導電墊係配置於上述第1配線基板之上 述第1表面之角隅部及其附近。
  18. 一種半導體裝置，其包含：配線基板，其包含上表面、形成於上述上表面的上導電墊、與上述上表面為相反側之下表面、形成於上述下表面的下導電墊、及形成於上述下表面的測試用導電墊，上述上導電墊係電性連接於另一半導體晶片之導電墊；搭載於上述配線基板之上述上表面的半導體晶片；及焊球，其係與上述下導電墊連接；其中上述測試用導電墊係電性連接於上述上導電墊；上述上導電墊係配置於較上述半導體晶片更靠上述配線基板之周緣部；上述測試用導電墊係配置於較上述下導電墊更靠上述配線基板之上述周緣部；且上述測試用導電墊係暴露成能被探針接觸。
  19. 如請求項18之半導體裝置，其中上述測試用導電墊係配置於最外側行。
  20. 如請求項18之半導體裝置，其中上述測試用導電墊係電性連接於上述上導電墊及上述半導體晶片之兩者。
  21. 如請求項18之半導體裝置，其中上述半導體晶片係包含主表面及形成於上述主表面之外部連接端子；且上述半導體晶片係以使上述半導體晶片與上述配線基板之上述上表面相對向之方式搭載於上述配線基板之上表面。
  22. 如請求項18之半導體裝置，其中上述配線基板係包含複數之配線層；且 上述下導電墊係經由上述配線層而電性連接於上述半導體晶片。
  23. 如請求項18之半導體裝置，其中上述配線基板係包含複數之配線層；且上述測試用導電墊係經由上述配線層而電性連接於上述上導電墊。
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