CN101026145A - 包括变压器或天线的半导体封装 - Google Patents

包括变压器或天线的半导体封装 Download PDF

Info

Publication number
CN101026145A
CN101026145A CNA2006101494998A CN200610149499A CN101026145A CN 101026145 A CN101026145 A CN 101026145A CN A2006101494998 A CNA2006101494998 A CN A2006101494998A CN 200610149499 A CN200610149499 A CN 200610149499A CN 101026145 A CN101026145 A CN 101026145A
Authority
CN
China
Prior art keywords
semiconductor
open loop
loop shape
chip
chips wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2006101494998A
Other languages
English (en)
Other versions
CN100487892C (zh
Inventor
崔允硕
李稀裼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN101026145A publication Critical patent/CN101026145A/zh
Application granted granted Critical
Publication of CN100487892C publication Critical patent/CN100487892C/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
    • H01Q9/04—Resonant antennas
    • H01Q9/16—Resonant antennas with feed intermediate between the extremities of the antenna, e.g. centre-fed dipole
    • H01Q9/26—Resonant antennas with feed intermediate between the extremities of the antenna, e.g. centre-fed dipole with folded element or elements, the folded parts being spaced apart a small fraction of operating wavelength
    • H01Q9/27—Spiral antennas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/1423—Monolithic Microwave Integrated Circuit [MMIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

本发明提供了一种半导体封装，该半导体封装包括封装板和顺序堆叠在封装板上的多个半导体芯片。各半导体芯片均包括半导体基底和形成在该半导体基底上的开环形芯片线。开环形芯片线具有第一端部和第二端部。开环形芯片线的第一端部和第二端部通过连接件互相电连接，所述连接件和所述开环形芯片线构成螺旋形天线。

Description

包括变压器或天线的半导体封装
本申请要求于2006年2月23日提交的第2006-17903号韩国专利申请的优先权，其全部内容通过引用包含于此。
技术领域
本发明的实施例总体上涉及半导体封装。更具体地讲，本发明的实施例涉及包括变压器或天线的半导体封装。
背景技术
随着便携式电子设备的尺寸继续减小，安装在便携式电子设备中的半导体封装的尺寸也必须相应地按比例减小。此外，为了提高半导体封装内部的电路的计算和/或存储容量，已经开发了封装技术用来在单个半导体封装中安装多个半导体芯片。例如，这些封装技术包括多芯片封装(MCP)技术、多堆叠封装(MSP)技术和系统级封装(SIP)技术。
一些半导体封装内部的电路包括天线，用于与其它电路例如相邻的半导体封装内部的电路的无线通信。这种天线的性能易于随着天线的长度和结构而改变。例如，用来接收低频信号的天线的性能随着天线的长度增加而趋于提高。即，增加天线的长度趋于增强天线的低频特性。
半导体封装经常安装在集成电路(IC)卡中。安装在IC卡中的半导体封装包括变压器，变压器包括基于由外部系统提供的外部功率产生内部功率的电磁铁线圈。换言之，当IC卡接触外部系统的终端设备时，IC卡中的半导体封装经常通过在内部安装的变压器产生适当的内部功率。
例如，在第6,686,649号由Mathews等申请的题目为“具有内屏蔽物和天线的多芯片半导体封装(Multi chip Semiconductor Package with IntegralShield and Antenna)”的美国专利，和在第5,023,624号由Heckaman等申请的题目为“具有盖安装的天线元件的微波芯片载体封装(Microwave Chip CarrierPackage Having Cover-mounted Antenna Element)”的美国专利中揭示了包括天线的半导体封装。在这些半导体封装中，接地屏蔽物形成在安装在封装基底上的半导体芯片的周围，天线形成在接地屏蔽物的上方。将接地屏蔽物设计成防止通过天线发送或接收的信号和通过半导体芯片的操作产生的电信号之间的电磁干扰。然而，不幸的是，天线和接地屏蔽物通常形成在围绕半导体芯片的半导体封装的外部。因此，这些天线是减小包括天线和接地屏蔽物的半导体封装的整体尺寸的障碍。
发明内容
根据本发明的一个实施例，一种半导体封装包括封装板和顺序堆叠在封装板上的多个半导体芯片。各半导体芯片均包括半导体基底和形成在该半导体基底上的开环形芯片线，各开环形芯片线均具有第一端部和第二端部。半导体封装还包括连接件，所述连接件电连接在不同半导体基底上形成的开环形芯片线的第一端部和第二端部，以形成螺旋形天线。
根据本发明的另一实施例，一种半导体封装包括：封装板，具有表面和大块区域；开环形板线，形成在该封装板的大块区域中或表面上，该开环形板线具有第一端部和第二端部；多个半导体芯片，顺序地堆叠在该封装板上。各半导体芯片均包括半导体基底和形成在该半导体基底上的开环形芯片线。各开环形芯片线均具有第一端部和第二端部。半导体封装还包括连接件，所述连接件将在不同半导体基底上形成的开环形芯片线的第一端部和第二端部以及所述开环形板线的第一端部和第二端部电连接，以形成螺旋形天线。
根据本发明的又一实施例，一种半导体封装包括：封装板，具有前表面和后表面；多个上半导体芯片，顺序地堆叠在该封装板的前表面上。各半导体芯片均包括半导体基底和形成在该半导体基底上的开环形芯片线，各开环形芯片线均具有第一端部和第二端部。半导体封装还包括：连接件，电连接在不同半导体基底上形成的开环形芯片线的第一端部和第二端部，以形成螺旋形天线；下半导体芯片，安装在封装板的后表面上。
根据本发明的再一实施例，一种多堆叠封装包括多个顺序堆叠的封装板和多个分别安装在所述封装板上的半导体芯片。各半导体芯片均包括半导体基底和形成在该半导体基底上的开环形芯片线，各开环形芯片线均具有第一端部和第二端部。半导体封装还包括连接件，所述连接件电连接在不同半导体基底上形成的开环形芯片线的第一端部和第二端部，以与开环形芯片线一起构成螺旋形天线。
根据本发明的再一实施例，一种半导体封装包括封装板和顺序堆叠在该封装板上的多个半导体芯片。各半导体芯片均包括半导体基底和形成在该半导体基底上的开环形芯片线，各开环形芯片线均具有第一端部和第二端部。半导体封装还包括第一组连接件，第一组连接件电连接开环形芯片线中最上面的开环形芯片线的第一端部、开环形芯片线中最下面的开环形芯片线的第二端部以及在最上面的开环形芯片线和最下面的开环形芯片线之间的中间开环形芯片线的第一端部和第二端部，从而与开环形芯片线一起构成螺旋形线圈。半导体封装还包括第二组连接件，第二组连接件电连接到最上面的开环形芯片线的第二端部，以与螺旋形线圈一起形成变压器的感应线圈。
附图说明
下面将参照附图中示出的几个实施例来描述本发明。在所有的附图中，相同的标号表示相同的示例性元件、组件或步骤。此外，为了举例说明的清晰起见，会夸大一些区域、元件和层的厚度和大小。在图中：
图1是根据本发明一个实施例的多芯片封装的剖视图；
图2是示出了在图1中示出的多芯片封装中的螺旋天线和接地屏蔽物的透视图；
图3是根据本发明另一实施例的多芯片封装的剖视图；
图4是示出了在图3中示出的多芯片封装中的螺旋天线的透视图；
图5是示出了根据本发明又一实施例的多芯片封装的剖视图；
图6是示出了根据本发明实施例的多堆叠封装的分解透视图；
图7是根据本发明再一实施例的多芯片封装的剖视图；
图8至图12是示出了在根据发明各种实施例的半导体封装中采用的半导体芯片的制造方法的剖视图。
具体实施方式
下面，参照相应的附图来描述本发明的示例性实施例。提出这些实施例作为教导示例。通过权利要求限定本发明的实际范围。
图1是根据本发明一个实施例的多芯片封装的剖视图，图2是示出了在图1中示出的多芯片封装的螺旋天线和接地屏蔽物的透视图。
参照图1和图2，包括第一半导体芯片C1、第二半导体芯片C2和第三半导体芯片C3的多个半导体芯片顺序地堆叠在封装板PB1上。封装板PB1包括本体1，本体1具有前表面1FS和后表面1BS。封装板PB1还包括形成在前表面1FS上的第一上板线3a、第二上板线3b和第三上板线3c以及形成在后表面1BS上的第一下板线5a、第二下板线5b和第三下板线5c。第一上板线3a通过穿过本体1的第一板塞(未示出)连接到第一下板线5a，第二上板线3b通过穿过本体1的第二板塞(未示出)连接到第二下板线5b，第三上板线3c通过穿过本体1的第三板塞(未示出)连接到第三下板线5c。第一下板线5a、第二下板线5b和第三下板线5c分别与多个球53接触。
第一半导体芯片C1、第二半导体芯片C2和第三半导体芯片C3顺序地堆叠在封装板PB1的前表面1FS上。第一半导体芯片C1包括：第一半导体基底61；中间绝缘层63，形成在第一半导体基底61上；多个下芯片焊盘，形成在中间绝缘层63上。下芯片焊盘包括第一下芯片焊盘65a和第二下芯片焊盘65b。此外，第一半导体芯片C1包括：下绝缘层67，在第一下芯片焊盘65a和第二下芯片焊盘65b的上方形成在中间绝缘层63上；多个上芯片焊盘，形成在下绝缘层67上；上绝缘层71，在上芯片焊盘的上方形成在下绝缘层67上。上芯片焊盘包括第一上芯片焊盘69a和第二上芯片焊盘69b。第一上芯片焊盘69a和第二上芯片焊盘69b分别通过穿过下绝缘层67的通孔电连接到第一下芯片焊盘65a和第二下芯片焊盘65b。此外，第一半导体芯片C1包括形成在上绝缘层71上的第一开环形芯片线73LP。第一开环形芯片线73LP具有第一端部73c和第二端部73d。第一开环形芯片线73LP通常包括重新分布的金属线。
第一下芯片焊盘65a可电连接到第一芯片环形芯片线73LP的第一端部73c，以用作收发信号焊盘。此外，键合焊盘73b通常形成在上绝缘层71上。键合焊盘73b通过穿过上绝缘层71的通孔电连接到第二上芯片焊盘69b。
在第一半导体芯片C1为引线键合芯片的情况下，键合焊盘73b通常通过第一键合引线49a电连接到第一上板线3a。在没有设置键合焊盘73b的情况下，第一键合引线49a通常直接连接到第二上芯片焊盘69b。第一半导体芯片C1通常通过第一粘结剂8接触封装板PB1的前表面1FS。
第二半导体芯片C2通过第二粘结剂21接触第一半导体芯片C1。第二半导体芯片C2包括：第二半导体基底23；中间绝缘层25，形成在第二半导体基底23上；第一芯片焊盘27a和第二芯片焊盘27b，形成在中间绝缘层25上。第二半导体芯片C2还包括：绝缘层29，在芯片焊盘27a和27b的上方形成在中间绝缘层25上；第二开环形芯片线33LP，形成在绝缘层29上。
第二开环形芯片线33LP具有第一端部33c和第二端部33d，通常包括重新分布的金属线。此外，第二半导体芯片C2通常包括形成在绝缘层29上的第一键合焊盘33a和第二键合焊盘33b。第一键合焊盘33a和第二键合焊盘33b通过穿过绝缘层29的通孔分别电连接到第一芯片焊盘27a和第二芯片焊盘27b。
第二开环形芯片线33LP的第一端部33c通过第一连接件31电连接到第一开环形芯片线73LP的第二端部73d。第一连接件31通常包括穿过第二半导体基底23的第一金属塞，如图1中所示。
第一键合焊盘33a和第二键合焊盘33b通过第二键合引线49b电连接到第二上板线33b。在没有设置第一键合焊盘33a和第二键合焊盘33b的情况下，第二键合引线49b与第一芯片焊盘27a和第二芯片焊盘27b直接接触。
第三半导体芯片C3通过第三粘结剂35接触第二半导体芯片C2。第三半导体芯片C3通常具有与第二半导体芯片C2的结构相同的结构。例如，在图1中，第三半导体芯片C3包括：第三半导体基底37；中间绝缘层39，形成在第三半导体基底37上；第一芯片焊盘41a和第二芯片焊盘41b，形成在中间绝缘层39上。此外，第三半导体芯片C3包括：绝缘层43，在第一芯片焊盘41a和第二芯片焊盘41b的上方形成在中间绝缘层39上；第三开环形芯片线47LP，形成在绝缘层43上。第三开环形芯片线47LP具有第一端部47c和第二端部47d。第三开环形芯片线47LP还可以是重新分布的金属线。此外，第三半导体芯片C3包括形成在绝缘层43上的第一键合焊盘47a和第二键合焊盘47b。第一键合焊盘47a和第二键合焊盘47b通过穿过绝缘层43的通孔分别电连接到第一芯片焊盘41a和第二芯片焊盘41b。
第三开环形芯片线47LP的第一端部47c通过第二连接件45电连接到第二开环形芯片线33LP的第二端部33d。第二连接件45包括穿过第三半导体基底37的第二金属塞，如图1中所示。
第一键合焊盘47a和第二键合焊盘47b通过第三键合引线49c电连接到第三上板线3c。在没有设置第一键合焊盘47a和第二键合焊盘47b的情况下，第三键合引线49c通常与第一芯片焊盘41a和第二芯片焊盘41b直接接触。用环氧塑封料(epoxy molding compound)51密封第一半导体芯片C1、第二半导体芯片C2和第三半导体芯片C3以及第一键合引线49a、第二键合引线49b和第三键合引线49c。
在图1和图2中示出的器件中，第一开环形芯片线73LP、第二开环形芯片线33LP、第三开环形芯片线47LP、第一连接件31和第二连接件45构成连接到收发信号焊盘65a的螺旋形天线，即，螺旋天线。
第一半导体芯片C1通常包括具有形成在第一半导体基底61上的单片微波集成电路(MMIC)的芯片。在MMIC被包括在第一半导体基底61上的情况下，由MMIC芯片产生的电磁波信号会劣化由天线执行的收发功能。因此，为了防止天线的性能由于第一半导体芯片C1产生的电磁波信号而被劣化，第一半导体芯片C1通常还包括置于第一半导体基底61和第一开环形芯片线73LP之间的平面型接地屏蔽物69g。作为示例，平面型接地屏蔽物69g通常形成在下绝缘层67和上绝缘层71之间。平面型接地屏蔽物69g相当于以较大面积与第一半导体基底61叠置的接地板，如图1和图2中所示。接地屏蔽物69g电连接到形成在中间绝缘层63上的接地芯片焊盘65g。
图3是根据本发明另一示例性实施例的多芯片封装的剖视图，图4是示出了在图3中示出的多芯片封装的螺旋天线的透视图。
参照图3和图4，包括第一半导体芯片C1′、第二半导体芯片C2′和第三半导体芯片C3′的多个半导体芯片顺序地堆叠在封装板PB2上。第二半导体芯片C2′和第三半导体芯片C3′分别具有与图1中示出的第二半导体芯片C2和第三半导体芯片C3的组件和结构基本相同的组件和结构。因此，为避免冗余，将省略对第二半导体芯片C2′和第三半导体芯片C3′的详细描述。
封装板PB2具有与图1中示出的封装板PB1的结构相似的结构。例如，封装板PB2包括具有前表面1FS和后表面1BS的本体1、第一上板线3a、第二上板线3b和第三上板线3c、第一下板线5a、第二下板线5b和第三下板线5c以及球53。此外，封装板PB2还包括形成在前表面1FS上的第一板焊盘3d和第二板焊盘3e以及形成在本体1内的开环形板线7LP。开环形板线7LP也具有第一端部7a和第二端部7b。
在其它实施例中，开环形板线7LP形成在本体1的前表面1FS或后表面1BS上。在开环形板线7LP形成在本体1的前表面1FS上的情况下，开环形板线7LP的第一端部7a和第二端部7b分别代替第一板焊盘3d和第二板焊盘3e。
可选择地，在开环形板线7LP形成在本体1的大块区域上或本体1的后表面1BS上的情况下，开环形板线7LP的第一端部7a和第二端部7b分别电连接到第一板焊盘3d和第二板焊盘3e。
第一半导体芯片C1′堆叠在封装板PB2的前表面1FS上。第一半导体芯片C1′包括：第一半导体基底9；中间绝缘层11，形成在第一半导体基底9上；多个芯片焊盘，形成在中间绝缘层11上。芯片焊盘包括第一芯片焊盘13a和第二芯片焊盘13b。此外，第一半导体芯片C1′包括：绝缘层15，在第一芯片焊盘13a和第二芯片焊盘13b的上方形成在中间绝缘层11上；第一开环形芯片线19LP，形成在绝缘层15上。第一开环形芯片线19LP具有第一端部19c和第二端部19d，并且通常包括重新分布的金属线。第一半导体芯片C1′还包括形成在绝缘层15上的键合焊盘19b。键合焊盘19b通过穿过绝缘层15的通孔电连接到第二芯片焊盘13b。
在第一芯片焊盘13a包括收发信号焊盘的情况下，第一芯片焊盘13a通过信号焊盘连接件17a和局部线19a电连接到开环形板线7LP的第一端部7a，第一开环形芯片线19LP的第一端部19c通过第一连接件17b电连接到开环形板线7LP的第二端部7b。局部线19a形成绝缘层15上的金属线，信号焊盘连接件17a和第一连接件17b形成穿过第一半导体基底9的金属塞。
在第一半导体芯片C1′为引线键合焊盘的情况下，键合焊盘19b通过图1中示出的示例性实施例的第一键合引线49a电连接到第一上板线3a。在没有设置键合焊盘19b的情况下，第一键合引线49a直接连接到第二芯片焊盘13b。
第二半导体芯片C2′堆叠在第一半导体芯片C1′上。第二半导体芯片C2′具有与图1的第二半导体芯片C2的结构基本相同的结构。因此，第二开环形芯片线33LP的第一端部33c通过第二连接件31′电连接到第一开环形芯片线19LP的第二端部19d。第二连接件31′通常包括如上面对于图1所描述的穿过第二半导体基底23的金属塞。
第三半导体芯片C3′堆叠在第二半导体芯片C2′上。第三半导体芯片C3′具有与图1的第三半导体芯片C3的结构基本相同的结构。因此，第三开环形芯片线47LP的第一端部47c通过第三连接件45′电连接到第二开环形芯片线33LP的第二端部33d。第三连接件45′形成如上面对于图1所描述的穿过第三半导体基底37的金属塞。
结果，开环形板线7LP、第一开环形芯片线19LP、第二开环形芯片线33LP和第三开环形芯片线47LP以及连接件17a、17b、31′和45′构成连接到收发信号焊盘13a的螺旋形天线，即螺旋天线，如图4中所示。
电连接到收发信号焊盘13a的开环形板线设置在封装板PB2中或设置在封装板PB2上。结果，相对于图1和图2中示出的天线，该多芯片封装的天线的长度增加。因此，可通过图3和图4中示出的天线收发低频信号。
图5是根据本发明又一实施例的多芯片封装的剖视图。
参照图5，包括第一上半导体芯片FC1、第二上半导体芯片C2″和第三上半导体芯片C3″的多个上半导体芯片顺序地堆叠在封装板PB3上。如图5中所示，第二上半导体芯片C2″和第三上半导体芯片C3″分别具有与图1中示出的第二半导体芯片C2和第三半导体芯片C3的结构和组件基本相同的结构和组件。因此，为避免冗余，将省略对第二上半导体芯片C2″和第三上半导体芯片C3″的详细描述。
封装板PB3包括具有前表面101FS和后表面101BS的本体101。封装板PB3还包括形成在前表面101FS上的第一上板线103a、第二上板线103b和第三上板线103c以及形成在后表面101BS上的第一下板线105s和第二下板线105g。封装板PB3还包括形成在前表面101FS上的上收发板线103s。第一下板线105s通过穿过本体101的板塞104s电连接到上收发板线103s。即，第一下板线105s相当于下收发板线。第二下板线105g相当于接地板线。
下半导体芯片FC2形成在封装板PB3的后表面101BS上。在图5中示出的实施例中，第一上半导体芯片FC1和下半导体芯片FC2分别构成第一倒装片(flip chip)和第二倒装芯片。然而，可选择地，第一上半导体芯片FC1和下半导体芯片FC2中的一个或多个可包括具有与第二上半导体芯片C2″和第三上半导体芯片C3″的构造相同的构造的引线键合芯片。
第一倒装芯片FC1包括：第一半导体基底125；中间绝缘层127，形成在第一半导体基底125的前表面上；芯片焊盘129，形成在中间绝缘层127上；下绝缘层131，在芯片焊盘129的上方形成中间绝缘层127上；第一开环形芯片线135LP，形成在下绝缘层131上。第一倒装芯片FC1还包括形成在下绝缘层131上的键合焊盘135a。键合焊盘135a通过穿过下绝缘层131的通孔电连接到芯片焊盘129。此外，第一倒装芯片FC1包括上绝缘层137，上绝缘层137在键合焊盘135a和第一开环形芯片线135LP的上方形成在下绝缘层131上。
第一倒装芯片FC1还包括穿过上绝缘层137并从上绝缘层137的表面突起的多个金属凸起。凸起包括收发信号凸起139s和多个芯片凸起139a。收发信号凸起139s电连接到第一开环形芯片线135LP的第一端部135b，芯片凸起139a电连接到形成在第一半导体基底125中的内部电路的电源焊盘、接地焊盘和信号焊盘。收发信号凸起139a与上收发板线103s接触，芯片凸起139a与对应的第一上板线103a接触。第一粘结剂141形成在第一倒装芯片FC1和封装板PB3之间。
第二倒装芯片FC2包括：半导体基底109；中间绝缘层111，形成在半导体基底109的前表面上；芯片焊盘，形成在中间绝缘层111上。芯片焊盘包括收发信号焊盘113s，收发信号焊盘113s电连接到形成在半导体基底109中的内部电路的收发端。芯片焊盘还包括第一接地焊盘113g′、第二接地焊盘113g″、电源焊盘(未示出)和信号焊盘(未示出)。
第二倒装芯片FC2还包括：下绝缘层115，在芯片焊盘113s、113g′和113g″的上方形成在中间绝缘层111上；多个键合焊盘，形成在下绝缘层115上；上绝缘层119，在键合焊盘的上方形成在下绝缘层115上；多个芯片凸起，穿过上绝缘层119并接触键合焊盘。键合焊盘包括：收发信号键合焊盘117s，电连接到收发信号焊盘113s；接地键合焊盘117d，电连接到第二接地焊盘113g″，芯片凸起包括接触收发信号焊盘113s的收发信号凸起121s和接触接地键合焊盘117d的接地凸起121g。
收发信号凸起121s接触下收发板线105s，接地凸起121g接触接地板线105g。结果，第二倒装芯片FC2的收发信号焊盘113s通过板塞104s电连接到第一开环形芯片线135LP的第一端部135b。粘结剂123形成在第二倒装芯片FC2和封装板PB3之间。第二倒装芯片FC2和粘结剂123的侧壁覆盖有环氧树脂125。在这种情况下，暴露了第二倒装芯片FC2的后表面，即半导体基底109的后表面。
第二上半导体芯片C2″和第三上半导体芯片C3″顺序地堆叠在第一倒装芯片FC1的后表面上。第二开环形芯片线33LP的第一端部33c通过第一连接件133和第二连接件31″电连接到第一开环形芯片线135LP的第二端部135c。如图5中所示，第一连接件133包括穿过第一半导体基底125的第一金属塞，第二连接件31″包括穿过第二半导体基底23的第二金属塞。第三开环形芯片线47LP的第一端部47c通过第三连接件45″电连接到第二开环形芯片线33LP的第二端部33d。第三连接件45″形成穿过第三半导体基底37的第三金属塞。结果，第一开环形芯片线135LP、第二开环形芯片线33LP、第三开环形芯片线47LP、第一连接件133、第二连接件31″和第三连接件45″构成电连接到第二倒装芯片FC2的收发信号焊盘113s的螺旋形天线，即螺旋天线。
在第二倒装芯片FC2包括具有形成在半导体基底109内的单片微波集成电路(MMIC)的半导体芯片的情况下，在MMIC芯片的操作期间，会从MMIC芯片产生电磁波信号。因此，为了防止天线的性能由于从第二倒装芯片FC2产生的电磁波信号而被劣化，第二倒装芯片FC2还包括形成在半导体基底109上的平面型接地屏蔽物117g。平面型接地屏蔽物117g可形成在下绝缘层115和上绝缘层119之间。平面型接地屏蔽物117g可相当于以较大面积与半导体基底109叠置的接地板，如图5中所示。接地屏蔽物117g电连接到第一接地焊盘113g′。
在另一实施例中，用形成在本体101中或封装板PB3的表面上的平面型接地屏蔽物107g代替第二倒装芯片FC2的接地屏蔽物117g。接地屏蔽物107g通过第二下板线105g和接地凸起121g电连接到第二倒装芯片FC2的第二接地焊盘113g″。
图6是示出了根据本发明实施例的多堆叠封装的分解透视图。
参照图6，多堆叠封装包括多个封装板，所述多个封装板包括第一封装板PB11、第二封装板PB22和第三封装板PB33。第一封装板PB11、第二封装板PB22和第三封装板PB33顺序地堆叠。第一封装板PB11包括：第一本体151，具有前表面和后表面；第一板线153a，形成在第一本体151的前表面上。第二封装板PB22包括：第二本体161，具有前表面和后表面；第二板线163a和163b，形成在第二本体161的前表面上。类似地，第三封装板PB33包括：第三本体171，具有前表面和后表面；第三板线173a，形成在第三本体171的前表面上。
第一半导体芯片C11安装在第一封装板PB11的前表面上，第二半导体芯片C22安装在第二封装板PB22的前表面上。类似地，第三半导体芯片C33安装在第三封装板PB33的前表面上。结果，第一半导体芯片C11设置在第一封装板PB11和第二封装板PB22之间，第二半导体芯片C22设置在第二封装板PB22和第三封装板PB33之间。
第一半导体芯片C11包括第一半导体基底155和形成在第一半导体基底155上的第一开环形芯片线157。第二半导体芯片C22包括第二半导体基底165和形成在第二半导体基底165上的第二开环形芯片线167。类似地，第三半导体芯片C33包括第三半导体基底175和形成在第三半导体基底175上的第三开环形芯片线177。第一开环形芯片线157、第二开环形芯片线167和第三开环形芯片线177通常包括重新分布的金属线。
第一封装板PB11和第一半导体芯片C11构成第一半导体封装PKG1，第二封装板PB22和第二半导体芯片C22构成第二半导体封装PKG2。另外，第三封装板PB33和第三半导体芯片C33构成第三半导体封装PKG3。结果，半导体封装为多堆叠封装。
第一开环形芯片线157的第一端部电连接到形成在第一半导体基底155中的内部电路的收发信号焊盘(未示出)，第一开环形芯片线157的第二端部通过第一键合引线159电连接到第一板线153a。第二开环形芯片线167的第一端部通过第二键合引线169a电连接到第二板线的第一线163a，第二开环形芯片线167的第二端部通过第二键合引线169b电连接到第二板线的第二线163b。此外，第三开环形芯片线177的第一端部通过第三键合引线179电连接到第三板线173a。
通过形成在第二封装板PB22的后表面上的第一连接件160例如焊球(solder ball)将第一板线153a电连接到第二板线的第一线163a，通过形成在第三封装板PB33的后表面上的第二连接件170例如焊球将第二板线的第二线163b电连接到第三板线173a。结果，第一开环形芯片线157、第二开环形芯片线167和第三开环形芯片线177、键合引线159、169a、169b和179、板线153a、163a、163b和173a以及连接件160和170构成螺旋形天线，即，螺旋天线。
在第一半导体芯片C11为具有形成在第一半导体基底155中的单片微波集成电路(MMIC)的半导体芯片时，在MMIC芯片的操作期间，会从MMIC芯片产生电磁波信号。因此，为了防止天线的性能由于从第一半导体芯片C11产生的电磁波信号而被劣化，第一半导体芯片C11还可包括形成在第一半导体基底155上的平面型接地屏蔽物(未示出)。平面型接地屏蔽物通常形成在第一开环形芯片线157和第一半导体基底155之间。如参照图1、图2和图5所描述的，接地屏蔽物相当于以较大面积与第一半导体基底155叠置的接地板。
图7是根据本发明再一实施例的多芯片封装的剖视图。该实施例示出了具有变压器的感应线圈的多芯片封装。
参照图7，多芯片封装与图3中示出的多芯片封装相似，所述多芯片封装还包括：连接件31p和45p，分别穿过第二半导体基底23和第三半导体基底37；第三芯片焊盘13c，形成在第一半导体基底9上。第三芯片焊盘13c通过连接件31p和45p电连接到第三开环形芯片线47LP的第二端部47d。结果，第一开环形芯片线19LP、第二开环形芯片线33LP、第三开环形芯片线47LP、开环形板线7LP以及连接件17a、17b、31′、45′、31p和45p构成连接到第一芯片焊盘13a和第三芯片焊盘13c的变压器的感应线圈。感应线圈相当于电磁铁线圈。
在没有设置开环形芯片线7LP的情况下，第一开环形芯片线19LP的第一端部19c电连接到第一芯片焊盘13a。在这种情况下，感应线圈仅由第一开环形芯片线19LP、第二开环形芯片线33LP、第三开环形芯片线47LP以及连接件31′、45′、31p和45p组成。
图7中示出的多芯片封装一般用在例如集成电路卡(IC卡)的设备中。在多芯片封装用于IC卡的情况下，如果IC卡接触提供外来磁场(MF)的系统终端，则感应线圈会产生操作IC卡中的内部电路的电源电压。因此，可在连接到系统终端的主系统和IC卡之间执行期望的通信。
图8至图12是示出了制造图3中示出的第一半导体芯片C1′的方法的剖视图。虽然描述的方法是关于第一半导体芯片C1′，但是该方法可易于适用于形成其它半导体芯片，例如图3中示出的第二半导体芯片C2′和第三半导体芯片C3′。
参照图8，在具有第一厚度T1的半导体基底9′上形成中间绝缘层11。在中间绝缘层11上形成包括第一芯片焊盘13a和第二芯片焊盘13b的多个芯片焊盘。
参照图9，在芯片焊盘13a和13b的上方在半导体基底9′上形成下绝缘层15。然后，将下绝缘层15、中间绝缘层11和半导体基底9′图案化，以形成穿过下绝缘层15、中间绝缘层11和初始半导体基底9′的第一孔和第二孔。通常利用干蚀刻工艺来执行蚀刻工艺。分别在第一孔和第二孔中形成第一连接件17a和第二连接件17b。通常利用电镀技术形成连接件17a和17b，以构成金属塞。
参照图10，将下绝缘层15图案化，以形成分别暴露第一芯片焊盘13a和第二芯片焊盘13b的通孔15a和15b。
参照图11，在第一通孔15a和第二通孔15b的上方在下绝缘层15上形成重新分布的金属层。然后将重新分布的金属层图案化，以形成开环形芯片线19LP、局部线19a和键合焊盘19b。开环形芯片线19LP具有第一端部19c和第二端部19d。
形成开环形芯片线19LP，使得第一端部19c覆盖第二连接件17b，键合焊盘19b覆盖暴露第二芯片焊盘13b的第二通孔15b。另外，当第一芯片焊盘13a为收发信号焊盘13a时，局部线19a形成在暴露收发信号焊盘13a的第一通孔15a和第一连接件17a的顶表面的上方。在这些条件下，第一连接件17a形成信号焊盘连接件。因此，第一芯片焊盘13a通过局部线19a电连接到第一连接件17a。
接着，在开环形芯片线19LP的上方在半导体基底9′上形成上绝缘层20。将上绝缘层20图案化，以形成暴露开环形芯片线19LP的第二端部19d的第一开口20a和暴露键合焊盘19b的第二开口20b。
参照图12，选择性地抛光初始半导体基底9′的后表面，以形成具有小于第一厚度T1的第二厚度T2的半导体基底9。结果，第一连接件17a和第二连接件17b从半导体基底9的后表面突起。换言之，第一连接件17a和第二连接件17b具有突起“P”。
根据上述实施例，开环形芯片线形成在半导体封装中的半导体芯片上，还设置了连接件以使开环形芯片线的端部互相连接。因此，利用开环形芯片线和连接件形成连接到半导体芯片中的一个半导体芯片的收发信号焊盘的螺旋形天线。此外，可设置电连接到螺旋形天线的端部的其它连接件，另外的连接件可电连接到半导体芯片的一个芯片焊盘。在这种情况下，利用螺旋形天线和另外的连接件可实现变压器的感应线圈。结果，本发明无需增加半导体封装的尺寸就可提供高性能的天线和/或高性能的变压器。
前述示例性实施例是教导示例。本领域的普通技术人员应该明白，在不脱离由权利要求限定的本发明的范围的情况下，可以对示例性实施例进行形式和细节上的各种改变。

Claims (31)

1、一种半导体封装，包括：
封装板；
多个半导体芯片，顺序堆叠在所述封装板上，各半导体芯片均包括半导体基底和形成在该半导体基底上的开环形芯片线，各开环形芯片线均具有第一端部和第二端部；
连接件，电连接在不同半导体基底上形成的所述开环形芯片线的所述第一端部和所述第二端部，以形成螺旋形天线。
2、如权利要求1所述的半导体封装，其中，所述半导体芯片中最下面的芯片包括置于所述最下面的芯片的半导体基底和所述最下面的芯片的开环形芯片线之间的平面型接地屏蔽物；
其中，所述接地屏蔽物电连接到所述最下面的芯片的接地焊盘。
3、如权利要求1所述的半导体封装，其中，所述连接件包括穿过半导体基底的金属塞。
4、如权利要求1所述的半导体封装，其中，所述半导体芯片中最下面的芯片包括形成在所述最下面的芯片的半导体基底上的收发信号焊盘；
其中，所述收发信号焊盘电连接到所述最下面的芯片的开环形芯片线的第一端部和第二端部中的任一端部。
5、如权利要求1所述的半导体封装，其中，所述开环形芯片线包括重新分布的金属线。
6、如权利要求1所述的半导体封装，其中，所述多个半导体芯片包括顺序堆叠的第一半导体芯片、第二半导体芯片和第三半导体芯片；
其中，所述第一半导体芯片、所述第二半导体芯片和所述第三半导体芯片的所述开环形芯片线分别包括第一开环形芯片线、第二开环形芯片线和第三开环形芯片线；
其中，所述第一半导体芯片、所述第二半导体芯片和所述第三半导体芯片的所述半导体基底分别包括第一半导体基底、第二半导体基底和第三半导体基底。
7、如权利要求6所述的半导体封装，其中，所述第一半导体芯片还包括形成在所述第一半导体基底上的收发信号焊盘；
其中，所述收发信号焊盘电连接到所述第一开环形芯片线的第一端部。
8、如权利要求7所述的半导体封装，其中，所述第一半导体芯片还包括置于所述第一开环形芯片线和所述第一半导体基底之间的平面型接地屏蔽物；
其中，所述平面型接地屏蔽物电连接到所述第一半导体芯片的接地焊盘。
9、如权利要求7所述的半导体封装，其中，所述连接件包括：
第一连接件，将所述第一开环形芯片线的第二端部电连接到所述第二开环形芯片线的第一端部；
第二连接件，将所述第二开环形芯片线的第二端部电连接到所述第三开环形芯片线的第一端部。
10、如权利要求9所述的半导体封装，其中，所述第一连接件包括穿过所述第二半导体基底的第一金属塞，所述第二连接件包括穿过所述第三半导体基底的第二金属塞。
11、一种半导体封装，包括：
封装板，具有表面和大块区域；
开环形板线，形成在所述封装板的所述大块区域中或所述表面上，所述开环形板线具有第一端部和第二端部；
多个半导体芯片，顺序地堆叠在所述封装板上，各半导体芯片均包括半导体基底和形成在该半导体基底上的开环形芯片线，各开环形芯片线均具有第一端部和第二端部；
连接件，将在不同半导体基底上形成的所述开环形芯片线的第一端部和第二端部以及所述开环形板线的所述第一端部和所述第二端部电连接，以形成螺旋形天线。
12、如权利要求11所述的半导体封装，其中，所述连接件包括穿过所述半导体基底的金属塞。
13、如权利要求11所述的半导体封装，其中，所述半导体芯片中最下面的芯片还包括形成在所述最下面的芯片的半导体基底上的收发信号焊盘；
其中，所述收发信号焊盘通过所述连接件中的任意一个电连接到所述开环形芯片线的第一端部和第二端部的任意一个。
14、如权利要求11所述的半导体封装，其中，所述开环形芯片线包括重新分布的金属线。
15、如权利要求11所述的半导体封装，其中，所述多个半导体芯片包括顺序堆叠的第一半导体芯片、第二半导体芯片和第三半导体芯片；
其中，所述第一半导体芯片、所述第二半导体芯片和所述第三半导体芯片的所述开环形芯片线分别包括第一开环形芯片线、第二开环形芯片线和第三开环形芯片线；
其中，所述第一半导体芯片、所述第二半导体芯片和所述第三半导体芯片的所述半导体基底分别包括第一半导体基底、第二半导体基底和第三半导体基底。
16、如权利要求15所述的半导体封装，其中，所述第一半导体芯片还包括形成在所述第一半导体基底上的收发信号焊盘；
其中，所述收发信号焊盘电连接到所述开环形板线的第一端部。
17、如权利要求16所述的半导体封装，其中，所述连接件包括：
信号焊盘连接件，将所述收发信号焊盘电连接到所述开环形板线的所述第一端部；
第一连接件，将所述开环形板线的所述第二端部电连接到所述第一开环形芯片线的第一端部；
第二连接件，将所述第一开环形芯片线的第二端部电连接到所述第二开环形芯片线的第一端部；
第三连接件，将所述第二开环形芯片线的第二端部电连接到所述第三开环形芯片线的第一端部。
18、如权利要求17所述的半导体封装，其中，所述信号焊盘连接件包括穿过所述第一半导体基底的信号焊盘金属塞；
其中，所述第一连接件包括穿过所述第一半导体基底的第一金属塞，所述第二连接件包括穿过所述第二半导体基底的第二金属塞，所述第三连接件包括穿过所述第三半导体基底的第三金属塞。
19、一种半导体封装，包括：
封装板，具有前表面和后表面；
多个上半导体芯片，顺序地堆叠在所述封装板的所述前表面上，各半导体芯片均包括半导体基底和形成在该半导体基底上的开环形芯片线，各开环形芯片线均具有第一端部和第二端部；
连接件，电连接在不同半导体基底上形成的开环形芯片线的第一端部和第二端部，以形成螺旋形天线；
下半导体芯片，安装在所述封装板的所述后表面上。
20、如权利要求19所述的半导体封装，其中，所述下半导体芯片包括半导体基底和形成在该半导体基底上的收发信号焊盘；
其中，所述收发信号焊盘通过穿过所述封装板的板塞电连接到所述上半导体芯片中最下面的芯片的开环形芯片线的第一端部。
21、如权利要求20所述的半导体封装，其中，所述封装板还包括平面型接地屏蔽物，所述接地屏蔽物形成在所述封装板的大块区域中，或者形成在所述封装板的所述前表面或所述后表面上；
其中，所述接地屏蔽物与所述上半导体芯片中最下面的芯片和所述下半导体芯片叠置。
22、如权利要求20所述的半导体封装，其中，所述下半导体芯片包括倒装芯片。
23、如权利要求22所述的半导体封装，其中，所述倒装芯片还包括形成在所述半导体基底上的接地屏蔽物；
其中，所述接地屏蔽物形成在所述半导体基底和所述封装板之间。
24、如权利要求19所述的半导体封装，其中，所述上半导体芯片中最下面的芯片包括倒装芯片。
25、一种多堆叠封装，包括：
多个顺序堆叠的封装板；
多个半导体芯片，分别安装在所述封装板上，各半导体芯片均包括半导体基底和形成在该半导体基底上的开环形芯片线，各开环形芯片线均具有第一端部和第二端部；
连接件，电连接在不同半导体基底上形成的开环形芯片线的第一端部和第二端部，以与所述开环形芯片线一起构成螺旋形天线。
26、如权利要求25所述的多堆叠封装，其中，安装在所述封装板的最下面的板上的最下面的半导体芯片还包括收发信号焊盘；
其中，所述收发信号焊盘电连接到所述最下面的半导体芯片的开环形芯片线的第一端部和第二端部中的任意一端部。
27、如权利要求26所述的多堆叠封装，其中，所述最下面的半导体芯片还包括平面型接地屏蔽物，所述平面型接地屏蔽物置于所述最下面的半导体芯片的半导体基底和所述最下面的芯片的开环形芯片线之间。
28、一种半导体封装，包括：
封装板：
多个半导体芯片，顺序堆叠在所述封装板上，各半导体芯片均包括半导体基底和形成在该半导体基底上的开环形芯片线，各开环形芯片线均具有第一端部和第二端部：
第一组连接件，电连接所述开环形芯片线中最上面的开环形芯片线的第一端部、所述开环形芯片线中最下面的开环形芯片线的第二端部以及在所述最上面的开环形芯片线和所述最下面的开环形芯片线之间的中间开环形芯片线的第一端部和第二端部，从而与所述开环形芯片线一起构成螺旋形线圈；
第二组连接件，电连接到所述最上面的开环形芯片线的第二端部，以与所述螺旋形线圈一起形成变压器的感应线圈。
29、如权利要求28所述的半导体封装，其中，所述第一组连接件和所述第二组连接件包括穿过所述半导体基底和所述半导体芯片的金属塞。
30、如权利要求28所述半导体封装，其中，所述最下面的开环形芯片线的第一端部电连接到所述半导体芯片中最下面的芯片的第一焊盘；
其中，所述最上面的开环形芯片线的所述第二端部通过所述第二组连接件电连接到所述最下面的芯片的第二焊盘。
31、如权利要求28所述的半导体封装，其中，所述封装板还包括开环形板线，所述开环形板线设置在所述封装板的大块区域中或所述封装板的表面上，并具有第一端部和第二端部；
其中，所述开环形板线的所述第一端部电连接到所述半导体芯片中最下面的芯片的第一焊盘；
其中，所述开环形板线的所述第二端部电连接到所述最下面的开环形芯片线的第一端部；
其中，所述最上面的开环形芯片线的所述第二端部通过所述第二组连接件电连接到所述最下面的芯片的第二焊盘。
CNB2006101494998A 2006-02-23 2006-11-21 包括变压器或天线的半导体封装 Active CN100487892C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020060017903 2006-02-23
KR20060017903A KR100714310B1 (ko) 2006-02-23 2006-02-23 변압기 또는 안테나를 구비하는 반도체 패키지들

Publications (2)

Publication Number Publication Date
CN101026145A true CN101026145A (zh) 2007-08-29
CN100487892C CN100487892C (zh) 2009-05-13

Family

ID=38269642

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2006101494998A Active CN100487892C (zh) 2006-02-23 2006-11-21 包括变压器或天线的半导体封装

Country Status (4)

Country Link
US (1) US7868462B2 (zh)
JP (1) JP2007227897A (zh)
KR (1) KR100714310B1 (zh)
CN (1) CN100487892C (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102487059A (zh) * 2010-12-02 2012-06-06 三星电子株式会社 堆叠式封装结构
CN102224590B (zh) * 2008-11-25 2014-06-04 高通股份有限公司 集成于半导体芯片中的天线
CN104078458A (zh) * 2013-03-29 2014-10-01 日月光半导体制造股份有限公司 堆叠式半导体结构及其制造方法
CN104167406A (zh) * 2013-05-16 2014-11-26 三星电子株式会社 半导体封装件
CN105304617A (zh) * 2014-05-30 2016-02-03 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN105304287A (zh) * 2014-06-16 2016-02-03 意法半导体股份有限公司 集成变压器
JP2018157150A (ja) * 2017-03-21 2018-10-04 東芝メモリ株式会社 半導体装置

Families Citing this family (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8633577B2 (en) * 2006-01-24 2014-01-21 Renesas Electronics Corporation Integrated circuit device
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US7791199B2 (en) 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
KR100836536B1 (ko) 2006-12-21 2008-06-10 한국과학기술원 컨덕터의 안테나에 대한 영향이 감소된 에스아이피 및 그설계 방법
JP5584474B2 (ja) 2007-03-05 2014-09-03 インヴェンサス・コーポレイション 貫通ビアによって前面接点に接続された後面接点を有するチップ
SG148901A1 (en) 2007-07-09 2009-01-29 Micron Technology Inc Packaged semiconductor assemblies and methods for manufacturing such assemblies
KR100906065B1 (ko) * 2007-07-12 2009-07-03 주식회사 동부하이텍 반도체칩, 이의 제조 방법 및 이를 가지는 적층 패키지
JP2009021499A (ja) * 2007-07-13 2009-01-29 Toshiba Corp 積層型半導体装置
CN103178032B (zh) 2007-07-31 2017-06-20 英闻萨斯有限公司 使用穿透硅通道的半导体封装方法
US8445996B2 (en) 2007-10-11 2013-05-21 Samsung Electronics Co., Ltd. Semiconductor package
KR101481576B1 (ko) * 2008-10-06 2015-01-14 삼성전자주식회사 반도체 패키지
JP4833192B2 (ja) * 2007-12-27 2011-12-07 新光電気工業株式会社 電子装置
US8253241B2 (en) * 2008-05-20 2012-08-28 Infineon Technologies Ag Electronic module
US8129266B2 (en) * 2008-07-09 2012-03-06 Semiconductor Componenets Industries, LLC Method of forming a shielded semiconductor device and structure therefor
US8183673B2 (en) * 2008-10-21 2012-05-22 Samsung Electronics Co., Ltd. Through-silicon via structures providing reduced solder spreading and methods of fabricating the same
US8049319B2 (en) * 2008-10-24 2011-11-01 Electronics And Telecommunications Research Institute Ultra wideband system-on-package
KR20100048610A (ko) 2008-10-31 2010-05-11 삼성전자주식회사 반도체 패키지 및 그 형성 방법
US8278749B2 (en) 2009-01-30 2012-10-02 Infineon Technologies Ag Integrated antennas in wafer level package
JP2011082450A (ja) 2009-10-09 2011-04-21 Elpida Memory Inc 半導体装置及びこれを備える情報処理システム
US8035218B2 (en) * 2009-11-03 2011-10-11 Intel Corporation Microelectronic package and method of manufacturing same
KR20110050964A (ko) * 2009-11-09 2011-05-17 주식회사 하이닉스반도체 반도체 패키지 및 이의 제조 방법
US9999129B2 (en) * 2009-11-12 2018-06-12 Intel Corporation Microelectronic device and method of manufacturing same
US8304917B2 (en) * 2009-12-03 2012-11-06 Powertech Technology Inc. Multi-chip stacked package and its mother chip to save interposer
KR20110078189A (ko) * 2009-12-30 2011-07-07 삼성전자주식회사 적층 구조의 반도체 칩들을 구비하는 메모리 카드 및 메모리 시스템
US8970000B2 (en) 2010-01-18 2015-03-03 Infineon Technologies Austria Ag Signal transmission arrangement
US8199518B1 (en) 2010-02-18 2012-06-12 Amkor Technology, Inc. Top feature package and method
US8946886B1 (en) 2010-05-13 2015-02-03 Amkor Technology, Inc. Shielded electronic component package and method
KR20110133945A (ko) * 2010-06-08 2011-12-14 삼성전자주식회사 스택 패키지 및 그의 제조 방법
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US9007273B2 (en) 2010-09-09 2015-04-14 Advances Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
JP5172925B2 (ja) * 2010-09-24 2013-03-27 株式会社東芝 無線装置
US8451618B2 (en) 2010-10-28 2013-05-28 Infineon Technologies Ag Integrated antennas in wafer level package
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
KR101099587B1 (ko) 2011-04-20 2011-12-28 앰코 테크놀로지 코리아 주식회사 Ｔｓｖ를 이용한 적층 칩 반도체 패키지
JP5417389B2 (ja) 2011-07-13 2014-02-12 株式会社東芝 無線装置
JP5414749B2 (ja) 2011-07-13 2014-02-12 株式会社東芝 無線装置
US8659126B2 (en) * 2011-12-07 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit ground shielding structure
US8610247B2 (en) 2011-12-30 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for a transformer with magnetic features
US20130113089A1 (en) * 2011-11-09 2013-05-09 Azurewave Technologies, Inc. Module ic package structure having a metal shielding function for preventing electrical malfunction induced by short-circuit
US8786060B2 (en) * 2012-05-04 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US9136213B2 (en) 2012-08-02 2015-09-15 Infineon Technologies Ag Integrated system and method of making the integrated system
CN103811444B (zh) * 2012-11-07 2016-11-23 环旭电子股份有限公司 电子装置、系统级封装模块及系统级封装模块的制造方法
JP6121705B2 (ja) 2012-12-12 2017-04-26 株式会社東芝 無線装置
JP6027905B2 (ja) * 2013-01-31 2016-11-16 新光電気工業株式会社 半導体装置
US9978688B2 (en) 2013-02-28 2018-05-22 Advanced Semiconductor Engineering, Inc. Semiconductor package having a waveguide antenna and manufacturing method thereof
US20150179555A1 (en) * 2013-12-20 2015-06-25 Sung Soo Kim Integrated circuit packaging system with vialess substrate and method of manufacture thereof
KR20150088453A (ko) * 2014-01-24 2015-08-03 한국전자통신연구원 다중 대역 플라즈마 루프 안테나
US9190345B1 (en) * 2014-03-28 2015-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
EP3410127A4 (en) * 2016-01-25 2019-08-28 Kyocera Corporation MEASUREMENT SENSOR HOUSING, AND MEASUREMENT SENSOR
US10243272B2 (en) * 2016-04-27 2019-03-26 Getac Technology Corporation Antenna device and antenna module having the antenna device
US10079222B2 (en) * 2016-11-16 2018-09-18 Powertech Technology Inc. Package-on-package structure and manufacturing method thereof
US10177095B2 (en) 2017-03-24 2019-01-08 Amkor Technology, Inc. Semiconductor device and method of manufacturing thereof
US11164826B2 (en) 2019-08-30 2021-11-02 Nxp Usa, Inc. Packaged integrated circuit having stacked die and method for making
SE2030349A1 (en) * 2020-11-30 2021-12-21 Gapwaves Ab Improved ultra-wideband circular-polarized radiation element with integrated feeding

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5023624A (en) * 1988-10-26 1991-06-11 Harris Corporation Microwave chip carrier package having cover-mounted antenna element
WO1999032304A1 (en) * 1997-12-22 1999-07-01 Hitachi, Ltd. Semiconductor device
CN1243294A (zh) 1998-07-28 2000-02-02 东芝株式会社 集成电路卡和数据读写装置和无线标记及它们的制造方法
US6351033B1 (en) * 1999-10-06 2002-02-26 Agere Systems Guardian Corp. Multifunction lead frame and integrated circuit package incorporating the same
KR100663177B1 (ko) * 1999-12-16 2007-01-02 고등기술연구원연구조합 안테나가 내장된 금속상 저온 동시 소성 세라믹 기판의제작방법
EP1126522A1 (en) * 2000-02-18 2001-08-22 Alcatel Packaged integrated circuit with radio frequency antenna
US6304232B1 (en) * 2000-02-24 2001-10-16 The Goodyear Tire & Rubber Company Circuit module
JP3939504B2 (ja) * 2001-04-17 2007-07-04 カシオ計算機株式会社 半導体装置並びにその製造方法および実装構造
US6686649B1 (en) * 2001-05-14 2004-02-03 Amkor Technology, Inc. Multi-chip semiconductor package with integral shield and antenna
EP1378961A3 (en) 2002-07-04 2005-07-13 Antenna Tech, Inc. Multi-band helical antenna on multilayer substrate
US6933603B2 (en) * 2002-07-11 2005-08-23 Teledyne Technologies Incorporated Multi-substrate layer semiconductor packages and method for making same
US20040061213A1 (en) * 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
US7049691B2 (en) * 2002-10-08 2006-05-23 Chippac, Inc. Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package
JP2004342948A (ja) 2003-05-19 2004-12-02 Tdk Corp 電子部品モジュール
JP4381113B2 (ja) 2003-11-27 2009-12-09 三洋電機株式会社 アンテナ共用器
CN2676405Y (zh) 2003-12-10 2005-02-02 立卫科技股份有限公司 芯片黏着胶材
KR100585226B1 (ko) 2004-03-10 2006-06-01 삼성전자주식회사 방열판을 갖는 반도체 패키지 및 그를 이용한 적층 패키지
US20060214271A1 (en) * 2005-03-23 2006-09-28 Jeremy Loraine Device and applications for passive RF components in leadframes
US7763963B2 (en) * 2005-05-04 2010-07-27 Stats Chippac Ltd. Stacked package semiconductor module having packages stacked in a cavity in the module substrate
US7312519B2 (en) * 2006-01-12 2007-12-25 Stats Chippac Ltd. Stacked integrated circuit package-in-package system

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102224590B (zh) * 2008-11-25 2014-06-04 高通股份有限公司 集成于半导体芯片中的天线
CN102487059A (zh) * 2010-12-02 2012-06-06 三星电子株式会社 堆叠式封装结构
CN104078458A (zh) * 2013-03-29 2014-10-01 日月光半导体制造股份有限公司 堆叠式半导体结构及其制造方法
CN104078458B (zh) * 2013-03-29 2017-07-25 日月光半导体制造股份有限公司 堆叠式半导体结构及其制造方法
CN104167406A (zh) * 2013-05-16 2014-11-26 三星电子株式会社 半导体封装件
CN104167406B (zh) * 2013-05-16 2018-08-28 三星电子株式会社 半导体封装件
CN105304617A (zh) * 2014-05-30 2016-02-03 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN105304617B (zh) * 2014-05-30 2018-08-07 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN105304287A (zh) * 2014-06-16 2016-02-03 意法半导体股份有限公司 集成变压器
CN105304287B (zh) * 2014-06-16 2018-01-16 意法半导体股份有限公司 集成变压器
JP2018157150A (ja) * 2017-03-21 2018-10-04 東芝メモリ株式会社 半導体装置
CN108630666A (zh) * 2017-03-21 2018-10-09 东芝存储器株式会社 半导体装置

Also Published As

Publication number Publication date
US20070194427A1 (en) 2007-08-23
CN100487892C (zh) 2009-05-13
US7868462B2 (en) 2011-01-11
KR100714310B1 (ko) 2007-05-02
JP2007227897A (ja) 2007-09-06

Similar Documents

Publication Publication Date Title
CN100487892C (zh) 包括变压器或天线的半导体封装
US8587096B2 (en) Semiconductor device including shielding layer and fabrication method thereof
US9496226B2 (en) Semiconductor device, semiconductor package, and electronic device
CN101432926B (zh) 内置天线电路模块及其制造方法
CN102196663B (zh) 印刷电路板和半导体封装及其制造方法及电气和电子设备
US20120306095A1 (en) Semiconductor package and fabrication method of the same
US20140124907A1 (en) Semiconductor packages
US7616167B2 (en) Semiconductor device and method of producing the same
US8922012B2 (en) Integrated circuit chip and flip chip package having the integrated circuit chip
US7436683B2 (en) Wafer level packaging structure with inductors and manufacture method thereof
KR20110102384A (ko) 반도체 장치, 그 제조 방법, 밀리파 유전체 내 전송 장치, 그 제조 방법, 및 밀리파 유전체 내 전송 시스템
US20120235880A1 (en) Ultrahigh-frequency package module
KR101717982B1 (ko) 커플링 도전 패턴을 포함하는 반도체 장치
US20140138819A1 (en) Semiconductor device including tsv and semiconductor package including the same
US8207606B2 (en) Semiconductor device
US8310062B2 (en) Stacked semiconductor package
WO1999003062A1 (en) Noncontact ic card
US20230170310A1 (en) Semiconductor package
TWI659518B (zh) 電子封裝件及其製法
US8383463B2 (en) Semiconductor package having an antenna with reduced area and method for fabricating the same
US8304876B2 (en) Semiconductor package and method for manufacturing the same
US8424771B2 (en) RFID tag
US11916042B2 (en) Semiconductor package having chip stack
US20060076658A1 (en) Semiconductor package structure with microstrip antennan
US8692133B2 (en) Semiconductor package

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant