WO2019007412A1 - 一种影像传感芯片的封装结构及其封装方法 - Google Patents

一种影像传感芯片的封装结构及其封装方法 Download PDF

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Publication number
WO2019007412A1
WO2019007412A1 PCT/CN2018/094766 CN2018094766W WO2019007412A1 WO 2019007412 A1 WO2019007412 A1 WO 2019007412A1 CN 2018094766 W CN2018094766 W CN 2018094766W WO 2019007412 A1 WO2019007412 A1 WO 2019007412A1
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Prior art keywords
image sensing
area
substrate
package
sensing chip
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PCT/CN2018/094766
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English (en)
French (fr)
Inventor
王之奇
耿志明
Original Assignee
苏州晶方半导体科技股份有限公司
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Priority claimed from CN201720812265.0U external-priority patent/CN207381401U/zh
Priority claimed from CN201710547345.2A external-priority patent/CN107170769B/zh
Application filed by 苏州晶方半导体科技股份有限公司 filed Critical 苏州晶方半导体科技股份有限公司
Priority to US16/612,606 priority Critical patent/US11049899B2/en
Publication of WO2019007412A1 publication Critical patent/WO2019007412A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/041—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L31/00
    • H01L25/042—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L31/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H01L27/14607—Geometry of the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14623—Optical shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1876—Particular processes or apparatus for batch treatment of the devices

Definitions

  • the present invention relates to the field of image acquisition devices, and more particularly to a package structure of an image sensor chip and a package method thereof.
  • An image sensor chip is an electronic device that senses external light and converts it into an electrical signal.
  • Image sensing chips are typically fabricated using semiconductor fabrication processes. After the image sensing chip is fabricated, a series of packaging processes are performed on the image sensing chip to form a packaged package structure for use in various electronic devices such as digital cameras, digital video cameras, and the like.
  • the solder pads on the surface of the image sensing chip and the solder pads of the substrate are soldered to each other, and the image sensing chip and the substrate are sealed and fixed by the adhesive. .
  • the present invention provides a package structure of an image sensor chip and a package method thereof.
  • the process is simple and the manufacturing cost is reduced.
  • the present invention provides the following technical solutions:
  • a package structure of an image sensing chip comprising:
  • An image sensing chip includes an opposite first surface and a second surface, the first surface having a plurality of pixel points for acquiring image information and a plurality of first pixels connected to the pixel points Solder pad
  • the substrate covering the first surface of the image sensor chip, wherein the substrate is provided with a wiring line and a contact end connected to the wiring line; the wiring line is used for electrical connection with an external circuit;
  • the periphery of the image sensor chip is bonded to the substrate by an anisotropic conductive paste, and the first pad is electrically connected to the contact end through the anisotropic conductive paste, perpendicular to the In the direction of the substrate, the anisotropic conductive paste surrounds all of the pixel points and does not overlap the pixel points.
  • the substrate includes a first region and a second region surrounding the first region; the first region is a light transmissive region;
  • the first surface of the image sensing chip includes: an acquisition area and a non-collection area surrounding the collection area; the collection area is opposite to the first area; the first pad is located in the non-collection area ;
  • anisotropic conductive paste is located between the non-acquisition area and the second area.
  • the substrate is a transparent material.
  • the wiring line is located at a surface of the second region facing the image sensor chip, and a light shielding layer is disposed between the wiring line and the substrate.
  • the substrate is a non-transparent material; the first region is provided with a window penetrating the substrate, and the window is for exposing all the pixels.
  • a transparent cover plate fixed on the substrate is further included, and the transparent cover covers the window.
  • the substrate is further provided with an external terminal electrically connected to the wiring line toward a side surface of the image sensing chip, and the external terminal is used for electrically connecting with the external circuit. .
  • the external circuit has a jack
  • the external terminal is a mating pin that matches the jack, and the wiring line is electrically connected to the external circuit by being plugged into the jack through the plug pin.
  • the method further includes:
  • a light source compensation device disposed on a side of the substrate facing away from the image sensing chip.
  • the first bonding pads are evenly distributed on the periphery of the image sensing chip.
  • the first surface of the image sensing chip is further provided with a plurality of auxiliary spacers, and the shape of the auxiliary spacer is the same as the shape of the first bonding pad, and the auxiliary pad The sheet and the first pad are evenly distributed on a periphery of the image sensing chip.
  • the auxiliary pad and the first pad are located at the same rectangular periphery, and the plurality of first pads are symmetrically distributed on two opposite sides of the rectangle;
  • a plurality of the auxiliary spacers are symmetrically distributed on the other two sides of the rectangle.
  • the auxiliary pad and the first pad are located at the same rectangular periphery, and the first pad and the auxiliary pad are alternately arranged at the periphery of the rectangle. .
  • the present invention also provides a method for packaging an image sensing chip, which is used to fabricate the package structure according to any of the above, the packaging method comprising:
  • Providing a plate comprising a plurality of arrayed package regions, a cutting channel between adjacent package regions; the package region being provided with a wiring line and a contact end electrically connected to the wiring line; the wiring The line is used to electrically connect to an external circuit;
  • An image sensing chip is bonded and fixed in the package area by an anisotropic conductive paste, the image sensing chip includes an opposite first surface and a second surface, and the first surface has a plurality of a pixel of the image information and a plurality of first pads connected to the pixel;
  • the periphery of the image sensing chip is bonded and fixed to the package region through the anisotropic conductive adhesive, and the first bonding pad is electrically connected to the contact end through the anisotropic conductive adhesive;
  • the anisotropic conductive paste surrounds all of the pixel points in a direction perpendicular to the package region and does not overlap the pixel dots.
  • the package area includes a first area and a second area surrounding the first area; the first area is a light transmissive area; and the first surface of the image sensor chip includes An acquisition area and a non-collection area surrounding the collection area; the collection area is opposite to the first area; the first pad is located in the non-collection area;
  • the image sensor chip is bonded and fixed in the package area by the anisotropic conductive paste, including:
  • An anisotropic conductive paste is coated on a periphery of each of the package regions, and one of the image sensing chips is bonded to the anisotropic conductive paste to thermally cure the anisotropic conductive paste.
  • the image sensing chip is fixed to the substrate by the anisotropic conductive paste, and is electrically connected to the first pad;
  • anisotropic conductive paste is located between the non-acquisition area and the second area.
  • the substrate is a transparent material
  • the providing a board comprises:
  • a light shielding layer of a predetermined pattern structure on the surface of the plate, the light shielding layer of the predetermined pattern structure having an opening corresponding to the first area, the opening for exposing the corresponding first area;
  • the wiring line and the contact end are formed on a side surface of the predetermined pattern structure with a light shielding layer facing away from the board.
  • the substrate is a non-transparent material
  • the providing a board comprises:
  • a window penetrating the package area is formed in a first region of each of the package regions, the window for exposing all of the pixel points.
  • the method further includes:
  • a transparent cover is attached to each of the windows.
  • the method before performing the cutting, the method further includes:
  • a light source compensation device is disposed on a surface of each of the package regions facing away from the image sensing chip.
  • the method before performing the cutting, the method further includes:
  • the external terminal and the image sensing chip are located on the same side of the plate.
  • the first pad of the image sensor chip is directly connected to the contact end on the substrate through the anisotropic conductive adhesive.
  • the substrate and the image sensor chip can be bonded and fixed by the anisotropic conductive adhesive.
  • FIG. 1 is a schematic diagram of a package structure of an image sensing chip according to an embodiment of the present invention
  • FIG. 2 is a plan view of the package structure of FIG. 1 in a direction opposite to the first direction Z;
  • FIG. 3 is a top plan view of the package structure of FIG. 1 in a first direction Z;
  • FIG. 4 is a schematic diagram of a package structure of another image sensing chip according to an embodiment of the present invention.
  • FIG. 5 is a top view of an image sensing chip according to an embodiment of the present invention.
  • FIG. 6 is a top view of another image sensing chip according to an embodiment of the present invention.
  • FIG. 7 is a top view of still another image sensing chip according to an embodiment of the present invention.
  • FIGS. 8-11 are schematic flowcharts of a packaging method according to an embodiment of the present invention.
  • FIG. 12 is a schematic flowchart diagram of another encapsulation method according to an embodiment of the present invention.
  • FIG. 1 is a schematic diagram of a package structure of an image sensing chip according to an embodiment of the present invention
  • FIG. 2 is a top view of the package structure shown in FIG. 1 in a reverse direction of the first direction Z
  • the package structure includes: an image sensing chip 11 including an opposite first surface and a second surface, the first surface having a plurality of pixel points 12 for acquiring image information and a plurality of a first pad 13 connected to the pixel 12; a substrate 14 covering the first surface of the image sensing chip 11, wherein the substrate 14 is provided with a wiring line and a contact end connected to the wiring line;
  • the wiring lines are used to electrically connect to external circuits.
  • the wiring line includes a first interconnecting line for electrically connecting the pixel point 12 to an external circuit.
  • the external circuit performs image processing based on the image information acquired at the pixel point 12.
  • the periphery of the image sensing chip 11 is bonded to the substrate 14 via an anisotropic conductive adhesive 15 , and the first bonding pad 13 is electrically connected to the contact end through the anisotropic conductive adhesive 15 .
  • the anisotropic conductive paste 15 surrounds all of the pixel dots 12 in a direction perpendicular to the substrate 14 and does not overlap the pixel dots 12.
  • the wiring line and the contact end are not shown in FIG. 1 and FIG.
  • the direction perpendicular to the substrate 14 is defined as a first direction Z, and the first direction Z is directed by the image sensing chip 11 to the substrate 14.
  • the second direction X and the third direction Y are defined to be perpendicular to the first direction Z, respectively, and the second direction X is perpendicular to the third direction Y.
  • the second direction X and the third direction Y are both parallel to the substrate 14.
  • the substrate 14 includes a first area A and a second area B surrounding the first area A; the first area A is a light-transmitting area; the first surface of the image sensing chip 11 includes: an acquisition area C And a non-collection area D surrounding the collection area C; the collection area C is disposed opposite to the first area A; the first pad 13 is located in the non-acquisition area D.
  • the anisotropic conductive paste 15 is located between the non-acquisition area D and the second area B.
  • the first area A completely exposes the collection area C.
  • the first area A may be set to be the same as the collection area C.
  • the substrate 14 is a transparent material. Therefore, light can be incident on the collection area C of the image sensing chip 11 directly through the first region A.
  • the substrate 14 may be a glass substrate or a transparent plastic substrate.
  • the wiring line is located on the surface of the second region B facing the image sensor chip 11, and a light shielding layer is disposed between the wiring line and the substrate 14.
  • the contact end is located on a side surface of the light shielding layer facing away from the substrate 14.
  • the light shielding layer is disposed on the side of the substrate 14 facing the image sensing chip 11 to prevent friction from damaging the light shielding layer.
  • the wiring line and the contact end are shielded by the light shielding layer, and the appearance of the package structure is ensured not to show the wiring line and the contact end.
  • the light shielding layer is not shown in FIGS. 1-3.
  • the light shielding layer is a black ink layer.
  • the substrate 14 is further disposed on a side surface of the image sensing chip 11 with an external terminal 16 electrically connected to the wiring line, and the external terminal 16 is electrically connected to the external circuit to make an external circuit It is electrically connected to the pixel point 12 in the image sensor chip 11.
  • the external terminal 16 is located at a position corresponding to the second region B of the substrate 14 and does not overlap the image sensing chip 11.
  • the external terminal 16 is a solder ball. In other embodiments, the external terminal 16 can also be a pad. When the external terminal is a solder ball or a pad, the external terminal 16 can be soldered to a pad in an external circuit to electrically connect the external circuit to the wiring line.
  • the external circuit has a jack
  • the external terminal 16 may also be a mating pin that matches the jack.
  • the wiring line passes through the plug pin and the The plugging of the jacks enables electrical connection to the external circuitry.
  • the package structure of the embodiment of the present invention further includes: a light source compensation device disposed on a surface of the substrate 14 facing away from the side of the image sensing chip 11 in order to ensure the image quality of the package structure in a weak light environment. 17.
  • the light source compensation device 17 is located at a position of the substrate 14 corresponding to the second region B.
  • the light source compensation device 17 is an LED device.
  • the operation of the light source compensation device can be controlled by an external circuit.
  • the wiring line further includes a second interconnecting line for electrically connecting the light source compensating device to the external circuit.
  • the second interconnecting line is insulated from the first interconnecting line.
  • the light source compensating device 17 can be connected to the external end circuit through the through hole of the substrate 14 and the contact end of the substrate 14 toward the surface of the image sensing chip 11, or the light source compensating device 17 can be in contact with the other side of the substrate 14 through the FPC. End connection.
  • the substrate 14 is a transparent material. Therefore, the first region A is transparent, and the substrate 14 is packaged with the image sensing chip 11 and electrically connected to the external circuit, and the image sensing chip 11 can be multiplexed. Cover.
  • FIG. 4 is a schematic diagram of a package structure of another image sensing chip according to an embodiment of the present invention. Transparent material.
  • the first area A is provided with a window K penetrating the substrate 14, and the window K is for exposing all of the pixel points 12. Since the substrate 14 is a non-transparent material at this time, it is not necessary to provide a light shielding layer at this time.
  • the substrate 14 When the substrate 14 is a non-transparent material, the substrate 14 may be a PCB substrate, or an opaque plastic substrate, or a semiconductor substrate. At this time, the package structure further includes: a transparent cover 18 fixed on the substrate 14, the transparent cover 18 covering the window K. The transparent cover 18 may be tempered glass.
  • the substrate 14 may be a single layer or a multi-layer stacked structure, and the corresponding first interconnecting lines and/or second interconnecting lines may also be a single layer or a multi-layer stacked structure.
  • the substrate 14 is a PCB substrate or an opaque plastic substrate
  • the first interconnection line and the second interconnection line are a multi-layer stacked structure
  • the first interconnection line and/or the second interconnection line A metal plug or via connection structure interconnecting a plurality of metal circuit layers and interconnecting metal circuit layers of adjacent layers may be included.
  • the first interconnect line and/or the second interconnect line may include a via interconnect structure penetrating the semiconductor substrate and being located on the first surface and/or the second surface of the semiconductor substrate A rewiring metal wiring layer electrically connected to the via interconnect structure.
  • the number of the first interconnection lines is plural ( ⁇ 2)
  • the number of the second interconnection lines is plural ( ⁇ 2)
  • different first interconnection lines and/or second interconnections The lines are isolated from each other and insulated from each other.
  • the number of the first interconnection lines and the second interconnection lines and the manner of routing are set according to electronic components that are required to be connected to an external circuit.
  • FIG. 5 is a top view of an image sensing chip according to an embodiment of the present invention.
  • the first pad 13 of the image sensing chip 11 is uniformly distributed in the image sensing.
  • the first pad 13 is located in the non-collection area D of the image sensor chip 11. All of the first pads 13 surround the collection area C.
  • the first bonding pads 13 are evenly distributed at the peripheral position of the image sensing chip 11, when the anisotropic conductive adhesive 15 is used to bond the fixed substrate 14 and the image sensing chip 11, the image sensing can be performed.
  • the pressure of the anisotropic conductive adhesive 15 is relatively uniform around the chip 11, and the adhesion between the substrate 14 and the image sensing chip 11 is ensured, thereby avoiding the uneven pressure of the anisotropic conductive adhesive 15 by the image sensing chip 11. Problems such as excessive partial pressure of the overflow or poor adhesion due to insufficient pressure.
  • FIG. 6 is a top view of another image sensing chip according to an embodiment of the present invention.
  • the first surface of the image sensing chip 11 is further provided with a plurality of auxiliary spacers. 19.
  • the auxiliary pad 19 has the same shape as the first pad 13, and the auxiliary pad 19 and the first pad 13 are evenly distributed on the periphery of the image sensor chip.
  • the auxiliary pad 19 and the first pad 13 are evenly distributed on the periphery of the image sensor chip 11.
  • the auxiliary spacer 19 makes the pressure of the anisotropic conductive adhesive 15 around the image sensing chip 11 relatively uniform, and ensures the substrate 14 and The image sensing chip 11 has a bonding effect, which avoids problems such as excessive partial pressure due to uneven pressure of the anisotropic conductive adhesive 15 by the image sensing chip 11 or poor adhesion due to insufficient pressure. .
  • the auxiliary spacer 19 and the first pad 13 are located at the same rectangular periphery, and the plurality of first pads 13 are symmetrically distributed on opposite sides of the rectangle.
  • a plurality of the auxiliary spacers 19 are symmetrically distributed on the other two sides of the rectangle.
  • FIG. 7 is a top view of still another image sensing chip according to an embodiment of the present invention.
  • the auxiliary pad 19 and the first pad 13 are in the same rectangular shape.
  • FIG. 7 differs from FIG. 6 in that the first pad 13 and the auxiliary pad 19 are alternately arranged around the rectangle. The distance between the first pad 13 and the auxiliary pad 19 is the same.
  • the chip when the chip is packaged, in order to obtain a thin chip package structure, the chip needs to be thinned. Specifically, the chip may be thinned by mechanical polishing or chemical etching. However, the mechanical strength of the chip after the thinning treatment is weak.
  • a surface of the image sensing chip 11 facing away from the substrate 14 is subjected to a thinning process, and after the thinning process, a surface of the image sensing chip 11 facing away from the substrate 14 is provided with a reinforcing layer.
  • the mechanical strength of the reinforcing layer is greater than the mechanical strength of the image sensor chip 11. In this way, the image sensing chip 11 can be further thinned in the prior art, and the mechanical strength is increased by the reinforcing layer, and the thickness of the image sensing chip 11 is greatly reduced while ensuring the chip package.
  • the structure has good mechanical strength.
  • the package structure of the embodiment of the present invention can further increase the thickness of the image sensor chip 11 by reducing the thickness of the image sensor chip 11 relative to the package structure of the prior art, so that the thickness of the image sensor chip 11 is thinner.
  • the reinforcing layer with better strength compensates for the mechanical strength after the thinning treatment, and the thinness of the chip package structure can be achieved.
  • the reinforcing layer may be a molding material.
  • the image sensing chip 11 and the substrate 14 when the image sensing chip 11 and the substrate 14 are packaged, the image sensing chip 11 is directly bonded and fixed by the anisotropic conductive adhesive 15 without a soldering process.
  • the substrate 14 electrically connects the first pad 13 and the wiring line on the substrate 14 while the image sensor chip 11 and the substrate 14 are bonded and fixed, and the process is simple and the manufacturing cost is low.
  • the distribution of the first pad 13 or the auxiliary pad 19 may be arranged, so that the pressure of the anisotropic conductive adhesive 15 around the image sensing chip 11 is relatively uniform, and the substrate 14 and the image sensing chip 11 are bonded and fixed. The effect is to avoid problems such as overflowing glue or poor adhesion.
  • FIG. 8 is a schematic flowchart of a packaging method according to an embodiment of the present invention.
  • the packaging method includes:
  • Step S11 As shown in FIG. 8 and FIG. 9, a plate 21 is provided.
  • the plate 21 includes a plurality of package regions 22 arranged in an array with a cutting channel 20 between adjacent package regions 22.
  • Fig. 8 is a plan view of the sheet material 21, and Fig. 9 is a cross-sectional view of Fig. 8 in the PP' direction.
  • the encapsulation area 22 includes a first area A and a second area B surrounding the first area A; the first area AA is a light transmissive area.
  • the sheet 21 is divided into a plurality of substrates 14.
  • the package area 22 is provided with a wiring line and a contact end electrically connected to the wiring line; the wiring line is for electrical connection with an external circuit.
  • the wiring line and the contact end are not shown in FIG.
  • the sheet material 21 is a transparent material as an example.
  • the providing a plate material comprises: a light shielding layer having a predetermined pattern structure formed on a surface of the plate material 21, wherein the light shielding layer of the predetermined pattern structure has a first area A a corresponding opening for exposing the corresponding first region A; the wiring line and the contact end are formed on a side surface of the predetermined pattern structure with a light shielding layer facing away from the plate.
  • the mask layer of the predetermined pattern structure may be used to form the light shielding layer of the predetermined pattern structure by an evaporation process; or the predetermined pattern is formed by a photolithography process.
  • a light shielding layer of the structure; or a light shielding layer of the predetermined pattern structure is formed by a screen printing process.
  • the wiring line can be formed by a screen printing process.
  • Step S12 As shown in FIG. 10, an image sensing chip 11 is bonded and fixed to the package region 22 through the anisotropic conductive paste 17.
  • the image sensing chip 11 includes an opposite first surface and a second surface, the first surface having a plurality of pixel points 12 for acquiring image information and a plurality of first pads connected to the pixel points 12 13.
  • the first surface of the image sensing chip 11 includes: an acquisition area and a non-collection area surrounding the collection area; the collection area is opposite to the first area A; the first pad 13 is located at the Non-acquisition area.
  • the image sensing chip 11 can refer to the foregoing package structure embodiment, and details are not described herein again.
  • the method for bonding and fixing the image sensing chip 11 in the package region 22 includes: coating an anisotropic conductive paste 15 on a periphery of each of the package regions 22, and the anisotropic conductive adhesive Bonding one of the image sensing chips 11 to the anisotropic conductive paste 15 for heat curing, so that the image sensing chip 11 is fixed to the substrate 14 by the anisotropic conductive adhesive 15 And electrically connected to the first pad 13.
  • the anisotropic conductive paste 15 is located between the non-inductive region and the second region B.
  • the anisotropic conductive paste 15 has electrical conductivity in a direction perpendicular to the substrate 14, and electrical insulation in a direction parallel to the substrate 14.
  • Step S13 cutting and separating the plate material 21 along the cutting channel 20 to form a package structure of the plurality of image sensing chips.
  • the method before performing the cutting, the method further includes: forming an external terminal 16 electrically connected to the wiring line on each of the packaging regions 22, the external terminal 16 being electrically connected to the external circuit .
  • the external terminal 16 and the image sensing chip 11 are located on the same side of the plate 21 .
  • the method further includes: providing a light source compensation device 17 on a side of each package area 22 facing away from the image sensor chip 11, and the light source compensation device 17 is located in the second area.
  • the method further comprises: thinning one side surface of the back surface plate 21 of the image sensing chip 11, and after thinning A reinforcing layer is formed on one surface of the back surface plate 21 of the image sensor chip 11.
  • the sheet 21 is divided into a plurality of substrates 14, each of which includes one of the package regions 22.
  • the periphery of the image sensing chip 11 is bonded and fixed to the package region 22 through the anisotropic conductive adhesive 15, and the first bonding pad 13 passes through the anisotropic conductive adhesive 15 and the The contact terminals 13 are electrically connected; for each of the package regions 22, the anisotropic conductive paste 15 surrounds all of the pixel points 12 in a direction perpendicular to the package regions, and is not associated with the pixel dots 12 overlap.
  • the package structure is shown in Figure 1.
  • the plate material 21 is taken as a transparent material as an example, that is, the substrate 14 is a dog material. After cutting, each substrate 14 corresponds to the position of the image sensing chip 11 in the collection area. Light.
  • the board 21 is a non-transparent material, that is, when the substrate 14 is a non-transparent material, a window is formed at a position corresponding to the collection area of each of the image sensing chips 11 at the time of the board 21, and then the image sensing is fixed on the package area 22. After the chip 11, it is necessary to fix the transparent cover on the window.
  • FIG. 12 is a schematic flowchart of another encapsulation method according to an embodiment of the present invention.
  • the encapsulation method includes:
  • Step S21 As shown in Fig. 12, the sheet material 12 is provided, at which time the sheet material 12 is a non-transparent material.
  • the sheet 21 also includes a plurality of package regions 22 with a dicing trench 20 between the package regions 22 and a package region 22 having a first region A and a second region B.
  • a window K penetrating the package region 22 in the first direction Z is formed in the first region A of each of the package regions 22, and the window K is used to expose all the pixel points of the image sensor chip. .
  • Step S22 As shown in FIG. 13, an image sensing chip 11 is bonded and fixed to the package region 22 by an anisotropic conductive paste.
  • Step S23 As shown in FIG. 14, the transparent cover 18 is fixed to each of the windows K.
  • Step S24 As shown in FIG. 15, an external terminal 16 electrically connected to the wiring line is formed on each of the package regions 22, and a light source compensation is disposed on a surface of each of the package regions 22 facing away from the image sensing chip 11.
  • Step S25 cutting and separating the plate material 21 along the cutting channel 20 to form a package structure of the plurality of image sensing chips. After cutting, the package structure is shown in Figure 4.
  • the image sensing chip 11 can be packaged to form the package structure, and the image sensing chip 11 and the board 21 are packaged without a soldering process, and the manufacturing process is simple and the cost is low. .

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Abstract

本发明公开了一种影像传感芯片的封装结构及其封装方法，该封装结构包括：影像传感芯片，所述影像传感芯片包括相对的第一表面以及第二表面，所述第一表面具有多个用于采集图像信息的像素点以及多个与所述像素点连接的第一焊垫；覆盖所述影像传感芯片的第一表面的基板，所述基板具有布线线路以及与所述布线线路连接的接触端；所述布线线路用于与外部电路电连接；所述影像传感芯片的周缘通过各向异性导电胶与所述基板粘结固定，所述第一焊垫通过所述各向异性导电胶与所述接触端电连接，在垂直于所述基板的方向上，所述各向异性导电胶包围所有所述像素点，与所述像素点不交叠。本发明技术方案在对影像传感芯片进行封装时，工艺简单，降低了制作成本。

Description

一种影像传感芯片的封装结构及其封装方法
本申请要求于2017年07月6日提交中国专利局、申请号为201710547345.2、发明名称为“一种影像传感芯片的封装结构及其封装方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
本申请要求于2017年07月6日提交中国专利局、申请号为201720812265.0、发明名称为“一种影像传感芯片的封装结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及图像采集装置技术领域，更具体的说，涉及一种影像传感芯片的封装结构及其封装方法。
背景技术
影像传感芯片是一种能够感受外部光线并将其转换成电信号的电子器件。影像传感芯片通常采用半导体制造工艺进行芯片制作。在影像传感芯片制作完成后，再通过对影像传感芯片进行一系列封装工艺从而形成封装好的封装结构，以用于诸如数码相机、数码摄像机等等的各种电子设备。
现有技术中，影像传感芯片进行封装时，以便是将影像传感芯片表面的焊垫与一基板的焊垫相互焊接，并通过黏胶将影像传感芯片与所述基板四周进行密封固定。
通过上述描述可知，现有技术对影像传感芯片进行封装时，需要焊接后再通过黏胶粘结固定，工艺复杂，成本高。
发明内容
为了解决上述问题，本发明提供了一种影像传感芯片的封装结构及其封装方法，在对影像传感芯片进行封装时，工艺简单，且降低了制作成本。
为了实现上述目的，本发明提供如下技术方案：
一种影像传感芯片的封装结构，所述封装结构包括：
影像传感芯片，所述影像传感芯片包括相对的第一表面以及第二表面，所述第一表面具有多个用于采集图像信息的像素点以及多个与所述像素点连接的第一焊垫；
覆盖所述影像传感芯片的第一表面的基板，所述基板上设置有布线线路以及与所述布线线路连接的接触端；所述布线线路用于与外部电路电连接；
所述影像传感芯片的周缘通过各向异性导电胶与所述基板粘结固定，且所述第一焊垫通过所述各向异性导电胶与所述接触端电连接，在垂直于所述基板的方向上，所述各向异性导电胶包围所有所述像素点，且与所述像素点不交叠。
优选的，在上述封装结构中，所述基板包括第一区域以及包围所述第一区域的第二区域；所述第一区域为透光区域；
所述影像传感芯片的第一表面包括：采集区域以及包围所述采集区域的非采集区域；所述采集区域与所述第一区域相对设置；所述第一焊垫位于所述非采集区域；
其中，所述各向异性导电胶位于所述非采集区域与所述第二区域之间。
优选的，在上述封装结构中，所述基板为透明材料。
优选的，在上述封装结构中，所述布线线路位于所述第二区域朝向所述影像传感芯片的表面，且所述布线线路与所述基板之间具有遮光层。
优选的，在上述封装结构中，所述基板为非透明材料；所述第一区域设置有贯穿所述基板的窗口，所述窗口用于露出所有所述像素点。
优选的，在上述封装结构中，还包括固定在所述基板上的透明盖板，所述透明盖板覆盖所述窗口。
优选的，在上述封装结构中，所述基板朝向所述影像传感芯片的一侧表面还设置有与所述布线线路电连接的外接端子，所述外接端子用于与所述外部电路电连接。
优选的，在上述封装结构中，所述外部电路具有插孔；
所述外接端子为与所述插孔相匹配的插接引脚，所述布线线路通过所述插接引脚与所述插孔插接实现与所述外部电路的电连接。
优选的，在上述封装结构中，还包括：
设置在所述基板背离所述影像传感芯片一侧表面的光源补偿装置。
优选的，在上述封装结构中，所述第一焊垫均匀的分布在所述影像传感芯片的周缘。
优选的，在上述封装结构中，所述影像传感芯片的第一表面还设置有多个辅助垫片，所述辅助垫片的形状与所述第一焊垫的形状相同，所述辅助垫片与所述第一焊垫均匀的分布在所述影像传感芯片的周缘。
优选的，在上述封装结构中，所述辅助垫片与所述第一焊垫位于同一矩形的周边，多个所述第一焊垫对称的分布在所述矩形相对的两条边上；
多个所述辅助垫片对称的分布在所述矩形相对的另外两条边上。
优选的，在上述封装结构中，所述辅助垫片与所述第一焊垫位于同一矩形的周边，在所述矩形的周边，所述第一焊垫与所述辅助垫片交替排布设置。
本发明还提供了一种影像传感芯片的封装方法，用于制作上述任一项所述的封装结构，所述封装方法包括：
提供一板材，所板材包括多个阵列排布的封装区，相邻封装区之间具有切割沟道；所述封装区设置有布线线路以及与所述布线线路电连接的接触端；所述布线线路用于与外部电路电连接；
通过各向异性导电胶，在所述封装区均粘结固定一个影像传感芯片，所述影像传感芯片包括相对的第一表面以及第二表面，所述第一表面具有多个用于采集图像信息的像素点以及多个与所述像素点连接的第一焊垫；
沿着所述切割沟道对所述板材进行切割分离，形成多个所述影像传感芯片的封装结构；切割后，所述板材分割为多个基板，每一个所述基板包括一个所述封装区；
其中，所述影像传感芯片的周缘通过所述各向异性导电胶与所述封装区粘结固定，且所述第一焊垫通过所述各向异性导电胶与所述接触端电连接；对于每一个所述封装区，在垂直于所述封装区的方向上，所述各向异性导电胶包围所有所述像素点，且与所述像素点不交叠。
优选的，在上述封装方法中，所述封装区包括第一区域以及包围所述第一区域的第二区域；所述第一区域为透光区域；所述影像传感芯片的第一表面包括：采集区域以及包围所述采集区域的非采集区域；所述采集区域与所述第一区域相对设置；所述第一焊垫位于所述非采集区域；
所述通过各向异性导电胶，在所述封装区均粘结固定一个影像传感芯片包括：
在每个所述封装区的周缘涂覆各向异性导电胶，并在所述各向异性导电胶上粘合一个所述影像传感芯片，对所述各向异性导电胶进行热压固化，使得所述影像传感芯片通过所述各向异性导电胶与所述基板固定，且与所述第一焊垫电连接；
其中，所述各向异性导电胶位于所述非采集区域与所述第二区域之间。
优选的，在上述封装方法中，所述基板为透明材料；
所述提供一板材包括：
在所述板材表面形成预设图案结构的遮光层，所述预设图案结构的遮光层具有与所述第一区域一一对应的开口，所述开口用于露出对应的所述第一区域；
在所述预设图案结构的遮光层背离所述板材的一侧表面形成所述布线线路以及所述接触端。
优选的，在上述封装方法中，所述基板为非透明材料；
所述提供一板材包括：
在每个所述封装区的第一区域形成贯穿所述封装区的窗口，所述窗口用于露出所有所述像素点。
优选的，在上述封装方法中，还包括：
在每个所述窗口上固定透明盖板。
优选的，在上述封装方法中，在进行切割之前，还包括：
在每个所述封装区背离所述影像传感芯片一侧的表面设置光源补偿装置。
优选的，在上述封装方法中，在进行切割之前，还包括：
在每个所述封装区上形成与所述布线线路电连接的外接端子，所述外接端子用于与所述外部电路电连接；
其中，所述外接端子与所述影像传感芯片位于所述板材的同一侧。
通过上述描述可知，本发明实施例提供的影像传感芯片的封装结构及其封装方法中，影像传感芯片的第一焊垫直接通过各向异性导电胶与所述基板上的接触端电连接，同时通过所述各向异性导电胶可以实现所述基板与所述影像传 感芯片的粘结固定，相对于需要焊接以及黏胶的现有技术，本发明技术方案在对影像传感芯片进行封装时，工艺简单，且降低了制作成本。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为本发明实施例提供的一种影像传感芯片的封装结构的示意图；
图2为图1所示封装结构在第一方向Z的反方向上的俯视图；
图3为图1所述封装结构在第一方向Z上的俯视图；
图4为本发明实施例提供的另一种影像传感芯片的封装结构的示意图；
图5为本发明实施例提供的一种影像传感芯片的俯视图；
图6为本发明实施例提供的另一种影像传感芯片的俯视图；
图7为本发明实施例提供的又一种影像传感芯片的俯视图；
图8-图11为本发明实施例提供的一种封装方法的流程示意图；
图12-图15为本发明实施例提供的另一种封装方法的流程示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本发明作进一步详细的说明。
参考图1-图3，图1为本发明实施例提供的一种影像传感芯片的封装结构的示意图，图2为图1所示封装结构在第一方向Z的反方向上的俯视图，图3为图1所述封装结构在第一方向Z上的俯视图。
该封装结构包括：影像传感芯片11，所述影像传感芯片11包括相对的第一表面以及第二表面，所述第一表面具有多个用于采集图像信息的像素点12以及多个与所述像素点12连接的第一焊垫13；覆盖所述影像传感芯片11的第一表面 的基板14，所述基板14上设置有布线线路以及与所述布线线路连接的接触端；所述布线线路用于与外部电路电连接。所述布线线路包括用于将所述像素点12与外部电路电连接的第一互联线路。外部电路根据像素点12采集的图像信息进行图像处理。
所述影像传感芯片11的周缘通过各向异性导电胶15与所述基板14粘结固定，且所述第一焊垫13通过所述各向异性导电胶15与所述接触端电连接，在垂直于所述基板14的方向上，所述各向异性导电胶15包围所有所述像素点12，且与所述像素点12不交叠。图1图3中未示出所述布线线路以及所述接触端。
本发明实施例中，定义垂直于所述基板14的方向为第一方向Z，第一方向Z由所述影像传感芯片11指向所述基板14。定义第二方向X与第三方向Y分别与第一方向Z垂直，且第二方向X与第三方向Y垂直。第二方向X与第三方向Y均与所述基板14平行。
所述基板14包括第一区域A以及包围所述第一区域A的第二区域B；所述第一区域A为透光区域；所述影像传感芯片11的第一表面包括：采集区域C以及包围所述采集区域C的非采集区域D；所述采集区域C与所述第一区域A相对设置；所述第一焊垫13位于所述非采集区域D。其中，所述各向异性导电胶15位于所述非采集区域D与所述第二区域B之间。
在所述第一方向Z上，所述第一区域A完全露出所述采集区域C。可选的，可以设置所述第一区域A与所述采集区域C相同。
在图1-图3所示实施方式中，基板14为透明材料。因此，光线可以直接通过第一区域A入射影像传感芯片11的采集区域C。当基板14为透明材料时，所述基板14可以为玻璃基板或是透明塑料基板。
所述布线线路位于所述第二区域B朝向所述影像传感芯片11的表面，且所述布线线路与所述基板14之间具有遮光层。
所述接触端位于所述遮光层的背离基板14的一侧表面。将遮光层设置在基板14朝向影像传感芯片11的一侧，避免摩擦损坏遮光层。通过遮光层遮挡布线线路以及所述接触端，保证封装结构的外观不显示布线线路以及所述接触端。图1-图3中未示出所述遮光层。可选的，所述遮光层为黑色油墨层。
所述基板14朝向所述影像传感芯片11的一侧表面还设置有与所述布线线路电连接的外接端子16，所述外接端子16用于与所述外部电路电连接，以使得外部电路与影像传感芯片11中的像素点12电连接。在所述第一方向Z上，所述外接端子16位于基板14对应所述第二区域B的位置，且与所述影像传感芯片11不交叠。
在图1所示实施方式中，所述外接端子16为锡球。其他实施方式中，外接端子16还可以为焊盘。当外接端子为锡球或是焊盘时，外接端子16可以与外部电路中的焊垫焊接，以使得外部电路与布线线路电连接。
其他实施方式中，所述外部电路具有插孔，所述外接端子16还可以为与所述插孔相匹配的插接引脚，此时，所述布线线路通过所述插接引脚与所述插孔的插接实现与所述外部电路的电连接。
为了保证该封装结构在光线较弱的环境下的成像质量，本发明实施例所述封装结构中，还包括：设置在所述基板14背离所述影像传感芯片11一侧表面的光源补偿装置17。在所述第一方向Z上，所述光源补偿装置17位于基板14对应所述第二区域B的位置。可选的，所述光源补偿装置17为LED器件。可以通过外部电路控制光源补偿装置的工作。所述布线线路还包括用于将所述光源补偿装置与所述外部电路电连接的第二互联线路。所述第二互联线路与所述第一互联线路绝缘。
光源补偿装置17可以通过贯穿基板14的过孔与基板14朝向影像传感芯片11表面的接触端连接，进而与外部电路连接，或是光源补偿装置17通过FPC与位于基板14另一侧的接触端连接。
在上述实施方式中，基板14为透明材料，因此，第一区域A透光，基板14在实现对影像传感芯片11封装，与外部电路电连接的同时，还可以复用影像传感芯片11的盖板。
本发明实施例所述封装结构还可以如图4所示，图4为本发明实施例提供的另一种影像传感芯片的封装结构的示意图，图4所示封装结构中，基板14为非透明材料。此时，所述第一区域A设置有贯穿所述基板14的窗口K，所述窗口K用于露出所有所述像素点12。由于此时基板14为非透明材料，故此时无需设置遮光层。
当所述基板14为非透明材料时，所述基板14可以为PCB基板、或是不透明塑料基板、或是半导体基板。此时，该封装结构还包括：固定在所述基板14上的透明盖板18，所述透明盖板18覆盖所述窗口K。所述透明盖板18可以为钢化玻璃。所述基板14可以为单层或多层堆叠结构，相应的所述第一互连线路和/或第二互连线路也可以为单层或多层堆叠结构。
当所述基板14为PCB基板或是不透明塑料基板时，所述第一互连线路和第二互连线路为多层堆叠结构时，所述第一互连线路和/或第二互连线路可以包括多层金属线路层和将相邻层的金属线路层互连的金属插塞或过孔连接结构。
当所述基板14为半导体基板时，所述第一互连线路和/或第二互连线路可以包括贯穿半导体基板的通孔互连结构以及位于半导体基板的第一表面和/或第二表面上的与通孔互连结构电连接的再布线金属线路层。
所述第一互连线路的数量为多个(≥2个)，所述第二互连线路的数量为多个(≥2个)，不同的第一互连线路和/或第二互连线路之间是相互隔离的，且相互绝缘的。根据需要与外部电路连接的电子元件设置所述第一互连线路和第二互连线路的数量以及走线方式。
参考图5，图5为本发明实施例提供的一种影像传感芯片的俯视图，图5所示实施方式中，影像传感芯片11的第一焊垫13均匀的分布在所述影像传感芯片11的周缘。第一焊垫13位于影像传感芯片11的非采集区域D。所有第一焊垫13包围采集区域C。该实施方式中，由于第一焊垫13均匀的分布在影像传感芯片11的周缘位置，当采用各向异性导电胶15粘结固定基板14与影像传感芯片11时，可以使得影像传感芯片11四周对各向异性导电胶15的压力较为均匀，保证基板14与影像传感芯片11粘合固定效果，避免了由于影像传感芯片11对各向异性导电胶15的压力不均匀导致的局部压力过大的溢胶或是压力不足导致的粘合效果差等问题。
参考图6，图6为本发明实施例提供的另一种影像传感芯片的俯视图，图6所示实施方式中，所述影像传感芯片11的第一表面还设置有多个辅助垫片19，所述辅助垫片19的形状与所述第一焊垫13的形状相同，所述辅助垫片19与所述第一焊垫13均匀的分布在所述影像传感芯片的周缘。
所述辅助垫片19与所述第一焊垫13均匀的分布在影像传感芯片11的周缘。在采用各向异性导电胶15粘结固定基板14与影像传感芯片11时，所述辅助垫片19使得影像传感芯片11四周对各向异性导电胶15的压力较为均匀，保证基板14与影像传感芯片11粘合固定效果，避免了由于影像传感芯片11对各向异性导电胶15的压力不均匀导致的局部压力过大的溢胶或是压力不足导致的粘合效果差等问题。所述第一焊垫13与所述辅助垫片19的间距、所述第一焊垫13与所述第一焊垫13的间距、所述辅助垫片19与所述辅助垫片19的间距均相同。
在图6所示实施方式中，所述辅助垫片19与所述第一焊垫13位于同一矩形的周边，多个所述第一焊垫13对称的分布在所述矩形相对的两条边上；多个所述辅助垫片19对称的分布在所述矩形相对的另外两条边上。
参考图7，图7为本发明实施例提供的又一种影像传感芯片的俯视图，图7所示实施方式中，同样所述辅助垫片19与所述第一焊垫13位于同一矩形的周边，图7与图6不同在于，在所述矩形的周边，所述第一焊垫13与所述辅助垫片19交替排布设置。所述第一焊垫13与所述辅助垫片19的间距均相同。
现有技术对芯片进行封装时，为了得到较薄厚度的芯片封装结构，需要对芯片进行减薄处理，具体的，可以通过机械研磨或是化学刻蚀等方式对芯片进行减薄处理。但是，经过减薄处理后的芯片的机械强度较弱。
本发明实施例所述封装结构中，影像传感芯片11背离基板14的一侧表面经过减薄处理，且减薄处理后，影像传感芯片11背离基板14的一侧表面设置有加强层。所述加强层的机械强度大于所述影像传感芯片11的机械强度。这样，可以在现有技术上对所述影像传感芯片11进行更大幅度的减薄处理，并通过加强层增加机械强度，在大幅度降低所述影像传感芯片11厚度的同时保证芯片封装结构具有较好的机械强度。也就是说，本发明实施例所述封装结构，相对于现有技术中的封装结构，可以进一步增加减薄处理降低影像传感芯片11厚度，使得影像传感芯片11的厚度更薄，通过机械强度更好的加强层补偿减薄处理后的机械强度，可以实现芯片封装结构的轻薄化。可选的，所述加强层可以为塑封材料。
通过上述描述可知，本发明实施例提供的封装结构中，影像传感芯片11 与基板14之间进行封装时，无需焊接工艺，直接通过各向异性导电胶15粘结固定影像传感芯片11与基板14，在粘结固定影像传感芯片11与基板14的同时使得第一焊垫13与基板14上的布线线路电连接，工艺简单，制作成本低。且还可以布局第一焊垫13的分布或是增加辅助垫片19，使得影像传感芯片11四周对各向异性导电胶15的压力较为均匀，保证基板14与影像传感芯片11粘合固定效果，避免溢胶或是粘合效果差等问题。
基于上述封装结构实施例，本发明另一实施例还提供了一种封装方法，用于对影像传感芯片进行封装，以形成上述实施例中的封装结构。该封装方法如图8-图11所示，图8-图11为本发明实施例提供的一种封装方法的流程示意图。该封装方法包括：
步骤S11：如图8和图9所示，提供一板材21，所板材21包括多个阵列排布的封装区22，相邻封装区22之间具有切割沟道20。
图8为板材21的俯视图，图9为图8在PP’方向的切面图。所述封装区22包括第一区域A以及包围所述第一区域A的第二区域B；所述第一区域AA为透光区域。后续步骤中，切割后，所述板材21分割为多个基板14。
所述封装区22设置有布线线路以及与所述布线线路电连接的接触端；所述布线线路用于与外部电路电连接。图8中未示出所述布线线路以及接触端。
图8-图11所示实施方式中，以板材21是透明材料为例进行说明。当所述板材21为透明材料时，所述提供一板材包括：在所述板材21表面形成预设图案结构的遮光层，所述预设图案结构的遮光层具有与所述第一区域A一一对应的开口，所述开口用于露出对应的所述第一区域A；在所述预设图案结构的遮光层背离所述板材的一侧表面形成所述布线线路以及所述接触端。
形成所述预设图案结构的遮光层时，可以采用预设图案结构的掩膜板，通过蒸镀工艺形成所述预设图案结构的遮光层；或，通过光刻工艺形成所述预设图案结构的遮光层；或，通过丝网印刷工艺形成所述预设图案结构的遮光层。形成所述布线线路时，可以通过丝网印刷工艺形成所述布线线路。
步骤S12：如图10所示，通过各向异性导电胶17，在所述封装区22均粘结固定一个影像传感芯片11。
所述影像传感芯片11包括相对的第一表面以及第二表面，所述第一表面具有多个用于采集图像信息的像素点12以及多个与所述像素点12连接的第一焊垫13。
所述影像传感芯片11的第一表面包括：采集区以及包围所述采集区域的非采集区域；所述采集区域与所述第一区域A相对设置；所述第一焊垫13位于所述非采集区域。所述影像传感芯片11可以参考上述封装结构实施例，在此不再赘述。
具体的，在所述封装区22均粘结固定影像传感芯片11的方法包括：在每个所述封装区22的周缘涂覆各向异性导电胶15，并在所述各向异性导电胶15上粘合一个所述影像传感芯片11，对所述各向异性导电胶15进行热压固化，使得所述影像传感芯片11通过所述各向异性导电胶15与所述基板14固定，且与所述第一焊垫13电连接。其中，所述各向异性导电胶15位于所述非感应区域与所述第二区域B之间。各向异性导电胶15在垂直于基板14的方向上具有导电性，平行于基板14的方向上具有电绝缘性。
步骤S13：沿着所述切割沟道20对所述板材21进行切割分离，形成多个所述影像传感芯片的封装结构。
如图11所示，在进行切割之前，还包括：在每个所述封装区22上形成与所述布线线路电连接的外接端子16，所述外接端子16用于与所述外部电路电连接。其中，所述外接端子16与所述影像传感芯片11位于所述板材21的同一侧。在封装区22固定影像传感芯片11后，在进行切割之前，还包括：在每个封装区22背离影像传感芯片11的一侧表面设置光源补偿装置17，光源补偿装置17位于第二区域B。
当在所述封装区22均粘结固定一个影像传感芯片11后，在切割之前，还包括：对影像传感芯片11背面板材21的一侧表面进行减薄处理，并在减薄处理后，在影像传感芯片11背面板材21的一侧表面形成加强层。
切割后，所述板材21分割为多个基板14，每一个所述基板14包括一个所述封装区22。其中，所述影像传感芯片11的周缘通过所述各向异性导电胶15与所述封装区22粘结固定，且所述第一焊垫13通过所述各向异性导电胶15与所述接触端13电连接；对于每一个所述封装区22，在垂直于所述封装区 的方向上，所述各向异性导电胶15包围所有所述像素点12，且与所述像素点12不交叠。切割后，封装结构如图1所示。
在图8-图11所示封装方法中，以板材21为透明材料为例进行说明，即基板14为狗命材料，切割后，每个基板14均对应影像传感芯片11采集区域的位置透光。
当板材21为非透明材料时，即基板14为非透明材料时，此时需要在板材21对应各个影像传感芯片11的采集区域位置形成窗口，后续在封装区22上粘结固定影像传感芯片11后，需要在窗口上固定透明盖板。
当基板14为非透明材料时，封装方法可以如图12-图15所示，图12-图15为本发明实施例提供的另一种封装方法的流程示意图，该封装方法包括：
步骤S21：如图12所示，提供以板材12，此时板材12为非透明材料。
板材21同样包括多个封装区22，封装区22之间具有切割沟道20，封装区22具有第一区域A以及第二区域B。
此时需要在每个所述封装区22的第一区域A形成在第一方向Z上贯穿所述封装区22的窗口K，所述窗口K用于露出影像传感芯片的所有所述像素点。
步骤S22：如图13所示，通过各向异性导电胶，在所述封装区22均粘结固定一个影像传感芯片11。
步骤S23：如图14所示，在每个所述窗口K上固定透明盖板18。
步骤S24：如图15所示，在每个所述封装区22上形成与所述布线线路电连接的外接端子16，在每个封装区22背离影像传感芯片11的一侧表面设置光源补偿装置17。
步骤S25：沿着所述切割沟道20对所述板材21进行切割分离，形成多个所述影像传感芯片的封装结构。切割后，封装结构如图4所示。
本发明实施例所述封装方法中，可以用于对影像传感芯片11进行封装，形成上述封装结构，将影像传感芯片11与板材21进行封装时，无需焊接工艺，制作工艺简单，成本低。
需要说明的是，本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相 参见即可。对于实施例公开的封装方法而言，由于其与实施例公开的封装结构相对应，所以描述的比较简单，相关之处参见封装结构相应部分说明即可。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (20)

  1. 一种影像传感芯片的封装结构，其特征在于，包括：
    影像传感芯片，所述影像传感芯片包括相对的第一表面以及第二表面，所述第一表面具有多个用于采集图像信息的像素点以及多个与所述像素点连接的第一焊垫；
    覆盖所述影像传感芯片的第一表面的基板，所述基板上设置有布线线路以及与所述布线线路连接的接触端；所述布线线路用于与外部电路电连接；
    所述影像传感芯片的周缘通过各向异性导电胶与所述基板粘结固定，且所述第一焊垫通过所述各向异性导电胶与所述接触端电连接，在垂直于所述基板的方向上，所述各向异性导电胶包围所有所述像素点，且与所述像素点不交叠。
  2. 根据权利要求1所述的封装结构，其特征在于，所述基板包括第一区域以及包围所述第一区域的第二区域；所述第一区域为透光区域；
    所述影像传感芯片的第一表面包括：采集区域以及包围所述采集区域的非采集区域；所述采集区域与所述第一区域相对设置；所述第一焊垫位于所述非采集区域；
    其中，所述各向异性导电胶位于所述非采集区域与所述第二区域之间。
  3. 根据权利要求2所述的封装结构，其特征在于，所述基板为透明材料。
  4. 根据权利要求3所述的封装结构，其特征在于，所述布线线路位于所述第二区域朝向所述影像传感芯片的表面，且所述布线线路与所述基板之间具有遮光层。
  5. 根据权利要求2所述的封装结构，其特征在于，所述基板为非透明材料；所述第一区域设置有贯穿所述基板的窗口，所述窗口用于露出所有所述像素点。
  6. 根据权利要求5所述的封装结构，其特征在于，还包括固定在所述基板上的透明盖板，所述透明盖板覆盖所述窗口。
  7. 根据权利要求1所述的封装结构，其特征在于，所述基板朝向所述影像传感芯片的一侧表面还设置有与所述布线线路电连接的外接端子，所述外接端子用于与所述外部电路电连接。
  8. 根据权利要求7所述的封装结构，其特征在于，所述外部电路具有插孔；
    所述外接端子为与所述插孔相匹配的插接引脚，所述布线线路通过所述插接引脚与所述插孔插接实现与所述外部电路的电连接。
  9. 根据权利要求1所述的封装结构，其特征在于，还包括：
    设置在所述基板背离所述影像传感芯片一侧表面的光源补偿装置。
  10. 根据权利要求1所述的封装结构，其特征在于，所述第一焊垫均匀的分布在所述影像传感芯片的周缘。
  11. 根据权利要求1所述的封装结构，其特征在于，所述影像传感芯片的第一表面还设置有多个辅助垫片，所述辅助垫片的形状与所述第一焊垫的形状相同，所述辅助垫片与所述第一焊垫均匀的分布在所述影像传感芯片的周缘。
  12. 根据权利要求11所述的封装结构，其特征在于，所述辅助垫片与所述第一焊垫位于同一矩形的周边，多个所述第一焊垫对称的分布在所述矩形相对的两条边上；
    多个所述辅助垫片对称的分布在所述矩形相对的另外两条边上。
  13. 根据权利要求11所述的封装结构，其特征在于，所述辅助垫片与所述第一焊垫位于同一矩形的周边，在所述矩形的周边，所述第一焊垫与所述辅助垫片交替排布设置。
  14. 一种影像传感芯片的封装方法，用于制作如权利要求1-13任一项所述的封装结构，其特征在于，所述封装方法包括：
    提供一板材，所板材包括多个阵列排布的封装区，相邻封装区之间具有切割沟道；所述封装区设置有布线线路以及与所述布线线路电连接的接触端；所述布线线路用于与外部电路电连接；
    通过各向异性导电胶，在所述封装区均粘结固定一个影像传感芯片，所述影像传感芯片包括相对的第一表面以及第二表面，所述第一表面具有多个用于采集图像信息的像素点以及多个与所述像素点连接的第一焊垫；
    沿着所述切割沟道对所述板材进行切割分离，形成多个所述影像传感芯片的封装结构；切割后，所述板材分割为多个基板，每一个所述基板包括一个所述封装区；
    其中，所述影像传感芯片的周缘通过所述各向异性导电胶与所述封装区粘结固定，且所述第一焊垫通过所述各向异性导电胶与所述接触端电连接；对于每一个所述封装区，在垂直于所述封装区的方向上，所述各向异性导电胶包围所有所述像素点，且与所述像素点不交叠。
  15. 根据权利要求14所述的封装方法，其特征在于，所述封装区包括第一区域以及包围所述第一区域的第二区域；所述第一区域为透光区域；所述影像传感芯片的第一表面包括：采集区域以及包围所述采集区域的非采集区域；所述采集区域与所述第一区域相对设置；所述第一焊垫位于所述非采集区域；
    所述通过各向异性导电胶，在所述封装区均粘结固定一个影像传感芯片包括：
    在每个所述封装区的周缘涂覆各向异性导电胶，并在所述各向异性导电胶上粘合一个所述影像传感芯片，对所述各向异性导电胶进行热压固化，使得所述影像传感芯片通过所述各向异性导电胶与所述基板固定，且与所述第一焊垫电连接；
    其中，所述各向异性导电胶位于所述非采集区域与所述第二区域之间。
  16. 根据权利要求15所述的封装方法，其特征在于，所述基板为透明材料；
    所述提供一板材包括：
    在所述板材表面形成预设图案结构的遮光层，所述预设图案结构的遮光层具有与所述第一区域一一对应的开口，所述开口用于露出对应的所述第一区域；
    在所述预设图案结构的遮光层背离所述板材的一侧表面形成所述布线线路以及所述接触端。
  17. 根据权利要求15所述的封装方法，其特征在于，所述基板为非透明材料；
    所述提供一板材包括：
    在每个所述封装区的第一区域形成贯穿所述封装区的窗口，所述窗口用于露出所有所述像素点。
  18. 根据权利要求17所述的封装方法，其特征在于，还包括：
    在每个所述窗口上固定透明盖板。
  19. 根据权利要求14所述的封装方法，其特征在于，在进行切割之前，还包括：
    在每个所述封装区背离所述影像传感芯片一侧的表面设置光源补偿装置。
  20. 根据权利要求14所述的封装方法，其特征在于，在进行切割之前，还包括：
    在每个所述封装区上形成与所述布线线路电连接的外接端子，所述外接端子用于与所述外部电路电连接；
    其中，所述外接端子与所述影像传感芯片位于所述板材的同一侧。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110265305A (zh) * 2019-05-17 2019-09-20 珠海市万州光电科技有限公司 一种贴片式红外支架及其生产工艺、红外接收头
CN112992956A (zh) * 2021-05-17 2021-06-18 甬矽电子(宁波)股份有限公司 芯片封装结构、芯片封装方法和电子设备

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230157536A (ko) * 2019-03-08 2023-11-16 데쿠세리아루즈 가부시키가이샤 접속 구조체의 제조 방법, 및 접속 구조체, 그리고 필름 구조체, 및 필름 구조체의 제조 방법

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050275048A1 (en) * 2004-06-14 2005-12-15 Farnworth Warren M Microelectronic imagers and methods of packaging microelectronic imagers
CN101236944A (zh) * 2007-02-01 2008-08-06 日月光半导体制造股份有限公司 光电芯片的增层封装构造及方法
CN106024823A (zh) * 2016-07-29 2016-10-12 格科微电子（上海）有限公司 Cmos图像传感器的封装方法
CN106653790A (zh) * 2017-02-20 2017-05-10 苏州晶方半导体科技股份有限公司 一种虹膜识别成像模组封装结构及其封装方法
CN107170769A (zh) * 2017-07-06 2017-09-15 苏州晶方半导体科技股份有限公司 一种影像传感芯片的封装结构及其封装方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7170062B2 (en) * 2002-03-29 2007-01-30 Oy Ajat Ltd. Conductive adhesive bonded semiconductor substrates for radiation imaging devices
JP2007299929A (ja) * 2006-04-28 2007-11-15 Matsushita Electric Ind Co Ltd 光学デバイス装置とそれを用いた光学デバイスモジュール
TWI437700B (zh) * 2010-05-31 2014-05-11 Kingpak Tech Inc 晶圓級影像感測器構裝結構之製造方法
CN109791267A (zh) * 2016-09-28 2019-05-21 夏普株式会社 光学设备及相机模块

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050275048A1 (en) * 2004-06-14 2005-12-15 Farnworth Warren M Microelectronic imagers and methods of packaging microelectronic imagers
CN101236944A (zh) * 2007-02-01 2008-08-06 日月光半导体制造股份有限公司 光电芯片的增层封装构造及方法
CN106024823A (zh) * 2016-07-29 2016-10-12 格科微电子（上海）有限公司 Cmos图像传感器的封装方法
CN106653790A (zh) * 2017-02-20 2017-05-10 苏州晶方半导体科技股份有限公司 一种虹膜识别成像模组封装结构及其封装方法
CN107170769A (zh) * 2017-07-06 2017-09-15 苏州晶方半导体科技股份有限公司 一种影像传感芯片的封装结构及其封装方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110265305A (zh) * 2019-05-17 2019-09-20 珠海市万州光电科技有限公司 一种贴片式红外支架及其生产工艺、红外接收头
CN110265305B (zh) * 2019-05-17 2024-04-12 珠海市万州光电科技有限公司 一种贴片式红外支架及其生产工艺、红外接收头
CN112992956A (zh) * 2021-05-17 2021-06-18 甬矽电子(宁波)股份有限公司 芯片封装结构、芯片封装方法和电子设备
CN112992956B (zh) * 2021-05-17 2022-02-01 甬矽电子(宁波)股份有限公司 芯片封装结构、芯片封装方法和电子设备

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