WO2018054315A1 - 封装结构以及封装方法 - Google Patents

封装结构以及封装方法 Download PDF

Info

Publication number
WO2018054315A1
WO2018054315A1 PCT/CN2017/102607 CN2017102607W WO2018054315A1 WO 2018054315 A1 WO2018054315 A1 WO 2018054315A1 CN 2017102607 W CN2017102607 W CN 2017102607W WO 2018054315 A1 WO2018054315 A1 WO 2018054315A1
Authority
WO
WIPO (PCT)
Prior art keywords
functional
substrate
chip
layer
package structure
Prior art date
Application number
PCT/CN2017/102607
Other languages
English (en)
French (fr)
Inventor
王之奇
沈志杰
耿志明
罗晓峰
Original Assignee
苏州晶方半导体科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201621080212.6U external-priority patent/CN206259337U/zh
Priority claimed from CN201610850385.XA external-priority patent/CN106298699A/zh
Application filed by 苏州晶方半导体科技股份有限公司 filed Critical 苏州晶方半导体科技股份有限公司
Publication of WO2018054315A1 publication Critical patent/WO2018054315A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/45184—Tungsten (W) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Definitions

  • the present application relates to the field of packaging technologies, and in particular, to a package structure and a packaging method.
  • the fan-out wafer level packaging technology mainly includes the following steps: first cutting the entire bare wafer to form a single discrete chip; providing a substrate, rearranging the cut individual chips on the substrate to form a chip spacing A suitable new wafer; then wafer-level packaging technology (WLP, Wafer Level Package), after the packaged test of the rearranged wafer, cut into a solder ball array chip larger than the original chip area.
  • WLP Wafer Level Package
  • Fan-out wafer-level packaging technology is advantageous for packaging small-sized, multi-electrode, and narrow-electrode pitches.
  • fan-out wafer-level packaging technology can also package different types of nitrogen at the same time, even if the number of solder balls is relatively close. Chip.
  • Fan-out wafer-level packaging technology better solves the problem of low reliability and matching with subsequent process PCBs compared to wafer-level chip-scale packages, where the reliability is low.
  • the problem may be due to excessive electrode concentration.
  • the present application provides a package structure, including: a substrate having opposite first and second faces, and having a circuit layer in the substrate; a first functional chip located on the first surface of the substrate
  • the first functional chip has an opposite first functional surface and a first back surface, the first functional surface has a pad, the first back surface is fixedly bonded to the first surface of the substrate, and the pad passes The wire is electrically connected to the circuit layer;
  • the second functional chip disposed on the second surface of the substrate is flip-chip mounted, the second functional chip has an opposite second functional surface and a second back surface, and the second functional surface Opposite the second surface of the substrate, and the portion of the circuit layer exposed by the second functional surface through the second surface of the substrate is electrically connected to the circuit layer;
  • the solder bump located on the second surface of the substrate The solder bump is electrically connected to the wiring layer through a portion of the wiring layer exposed by the second surface of the substrate.
  • the first function chip is an image sensing chip; the first functional surface further has an image sensing area, and the pad surrounds the image sensing area.
  • the package structure further includes: a hollow annular column on a first surface of the substrate, the hollow annular column surrounding the first functional chip; and a top disposed on the top of the hollow annular column a light plate, and the light transmissive plate, the hollow annular column and the substrate enclose a cavity, and the first functional chip is located in the cavity.
  • the top of the hollow annular column is higher than the first surface of the first functional chip.
  • an adhesive layer is further disposed between the top of the hollow annular column and the light transmissive plate.
  • the second function chip is a signal processing chip; the number of the second function chips is greater than or equal to 1.
  • the package structure further includes: a metal bump located on the second functional surface, The second functional surface and the wiring layer are electrically connected by the metal bump and a portion of the wiring layer exposed by the second surface of the substrate.
  • solder bumps are distributed around the second functional chip.
  • a distance between the top of the second solder bump and the second surface of the substrate is greater than a distance between the second back surface of the second functional chip and the second surface of the substrate.
  • the package structure further includes: an adhesive layer between the first back surface and the first surface.
  • the package structure further includes: an insulating layer on the second surface of the substrate portion, wherein the solder bump penetrates the insulating layer; a solder resist layer on the first surface of the substrate, and The wire penetrates the solder resist layer.
  • the package structure further includes: a plastic sealing layer on the second surface of the substrate and covering the sidewall of the second functional chip.
  • the present application further provides a packaging method, including: providing a plurality of first function chips and a second function chip, wherein the first function chip has an opposite first functional surface and a first back surface, and the first functional surface has a pad, the second functional chip has an opposite second functional surface and a second back surface; providing a substrate having a plurality of functional regions and a scribe lane region between adjacent functional regions, the substrates having opposite a first side and a second side, and the circuit board has a circuit layer; the first functional chip is disposed on the first surface of the substrate functional area, and the first back surface is fixedly engaged with the first surface; Forming a wire electrically connecting the pad and the circuit layer; disposing the second functional chip on a second surface of the substrate functional area, the second functional surface is opposite to the second surface, and The second functional surface is electrically connected to the circuit layer through a portion of the circuit layer exposed by the second surface of the substrate functional region; a solder bump is formed on the second surface of the substrate functional region, and the solder bump passes Sub
  • the first function chip is an image sensing chip; the first functional surface further has an image sensing area, and the pad surrounds the image sensing area; and the packaging method further includes: Forming a hollow annular column on the first surface of the substrate functional region, and after the first functional chip is disposed on the first surface of the substrate functional region, the hollow annular column surrounds the first functional chip; A light transmissive plate is disposed on the top of the hollow annular column, and the light transmissive plate, the hollow annular column and the substrate enclose a cavity, and the first functional chip is located in the cavity.
  • the hollow annular post is formed before the first functional chip is disposed on the first surface of the substrate functional area.
  • the hollow annular column is formed by a coating process and a photolithography process; or the hollow annular column is formed by a resin printing process.
  • the wire is formed by a wire bonding process.
  • the method further includes the steps of: on the second functional surface of the second functional chip or the substrate functional area Forming a metal bump on two sides; using a solder bonding process, electrically connecting the second functional surface to the circuit layer through the metal bump and a portion of the circuit layer exposed on the second side of the substrate functional region .
  • the method before the cutting the substrate, the method further includes the steps of: forming a plastic sealing layer on the second surface of the substrate functional region portion, and the plastic sealing layer covers the second functional chip sidewall.
  • the plastic sealing layer is formed before the solder bump is formed; or, after the solder bump is formed, the plastic sealing layer is formed.
  • the first functional chip and the second functional chip are respectively disposed on opposite sides of the substrate, and are disposed on the same surface of the substrate in parallel with the first functional chip and the second functional chip.
  • the size in the horizontal direction is significantly smaller, resulting in a higher integration of the package structure.
  • the solder bump and the second functional chip are disposed on the same surface of the substrate, thereby reducing The thickness of the package structure perpendicular to the horizontal plane is reduced, reducing the total thickness of the product.
  • 1 is a schematic structural view of a package structure
  • FIG. 2 is a schematic structural diagram of a package structure according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a packaging process by using the packaging method provided by the embodiment of the present application.
  • FIG. 1 is a schematic structural view of a package structure.
  • the package structure includes: a substrate 10 having opposing upper and lower surfaces, a circuit interconnection layer (not labeled) distributed in the substrate 10, and having the substrate 10 through the substrate 10
  • the light-transmissive plate 20 is adhered to the upper surface of the hollow 11 of the substrate 10; the first functional chip 30 electrically connected to the lower surface of the substrate 10 is flip-chip mounted, and the function of the first functional chip 30 is The region is located directly under the hollow 11 and the pads (not labeled) of the first functional chip 30 are electrically connected to the circuit interconnection layer;
  • the upper surface of the substrate 10 is electrically connected to the substrate 10 through the wires 40
  • a second function chip 50, the second function chip 50 is located on the side of the hollow 11;
  • a BGA solder ball 60 located on the lower surface of the substrate 30; is located on the surface of the substrate 10 and covers the sidewall of the second functional chip 50
  • the plastic seal layer 70 is located on the surface of the substrate
  • the above-mentioned package structure has a large size in the horizontal direction, resulting in low integration of the package structure, which is disadvantageous for satisfying the development trend of miniaturization and miniaturization of the device.
  • the package structure includes:
  • the substrate 101 has an opposite first surface (not labeled) and a second surface (not labeled), and the substrate 101 has a circuit layer 102 therein;
  • first functional chip 201 on a first side of the substrate 102, the first functional chip 201 has an opposite first functional surface (not labeled) and a first back surface (not labeled), the first functional surface Having a pad 202, the first back surface is fixedly bonded to the first surface, and the pad 202 is electrically connected to the circuit layer 102 through a wire 203;
  • the second function chip 301 flip-chip the second function chip 301 disposed on the second surface of the substrate 101, the second function chip 301 has an opposite second functional surface (not labeled) and a second back surface (not labeled), and the A portion of the circuit layer 102 exposed by the second functional surface of the second functional surface of the substrate 101 is electrically connected to the circuit layer 102;
  • a solder bump 401 on a second surface of the substrate 101 the solder bump 401 being electrically connected to the wiring layer 102 through a portion of the wiring layer 102 exposed by the second surface of the substrate 101.
  • the substrate 101 functions to support the first functional chip 201 and the second functional chip 301.
  • the substrate 101 also functions to electrically connect the first functional chip 201 and the second functional chip 301, and is also used for electrical connection with an external circuit or other components.
  • the substrate 101 may be a glass substrate, a metal substrate, a semiconductor substrate, or a polymer substrate.
  • the substrate 101 is a PCB substrate.
  • the substrate 101 also has a wiring layer 102 therein.
  • the wiring layer 102 is a multilayer wiring interconnection structure located in the substrate 101 according to wiring and electrical connection requirements.
  • the portion of the circuit layer 102 exposed by the first surface is for electrically connecting with the first functional chip 201; the portion of the circuit layer 102 exposed by the second surface is for electrically connecting with the second functional chip 301.
  • a first solder mask layer 103 may be disposed on the first surface of the substrate 101, and the solder resist layer 103 is located on the first surface of the substrate 101 and covers the circuit layer 102, and The solder resist layer 103 exposes a portion of the wiring layer 102 such that one end of the wire 203 is located at a portion of the exposed circuit layer 102, and the wire 203 is secured. Electrically connected to the circuit layer 102.
  • the material of the solder resist layer 103 is green oil.
  • the solder resist layer 103 serves to protect the circuit layer 102 from oxidation of the circuit layer 102 and prevent unnecessary electrical connection between the circuit layer 102 and other components.
  • the first function chip 201 is an image sensing chip, and the first functional surface further has an image sensing area 204, and the pad 202 surrounds the image sensing area 204.
  • the first functional surface is a surface having a pad 202 and an image sensing region 204, and the first back surface is a surface that is fixedly bonded to the second surface of the substrate 201.
  • the first functional chip 201 may have a metal interconnection structure (not shown) electrically connecting the image sensing area 204 and the pad 202.
  • the image sensing area 204 is formed with an image sensor unit and an image sensor.
  • the image-sensing area 204 receives and converts external light into an electrical signal, and passes the electrical signal through the metal interconnect structure and the pad 202, and the circuit layer 102 in the substrate 101 for transmission to the Within the two function chip 301.
  • the image sensing area 204 is located at an intermediate position of the first functional surface, the pad 202 is located at an edge position of the first functional surface, and the pad 202 is located in the image sensing area 204.
  • the four sides of the image sensing area 204 have a plurality of pads 202, and each of the pads 202 is electrically connected to the circuit layer 102 on the first side of the substrate 101 through wires 203. .
  • the apex of the wire 203 is higher than the first surface of the first functional chip 201.
  • One end of the wire 203 is electrically connected to the pad 202, and the other end of the wire 203 is electrically connected to the circuit layer 102 on the first surface of the substrate 101, so that the circuit and the first functional chip 201 are electrically connected.
  • the circuit layer 102 is electrically connected.
  • the wire 203 is connected between the pad 202 and the wiring layer 102, so that the wire 203 is bent.
  • the material of the wire 203 is a metal, and the metal includes copper, aluminum, tungsten, gold or silver.
  • a bonding property between the first faces of the board 101, an adhesive layer between the first back surface and the first face, and the adhesion between the first back surface and the first surface by the adhesive layer The ability to combine.
  • the image sensing area 204 is protected in the package structure in order to improve the protection of the image sensing area 204 on the first surface of the first functional chip 201.
  • the package structure further includes: a hollow annular column 104 on a first surface of the substrate 101, the hollow annular column 104 surrounding the first functional chip 201; and the hollow annular column
  • the light transmissive plate 105 at the top of the 104, and the light transmissive plate 105, the hollow annular post 104, and the substrate 101 enclose a cavity, and the first functional chip 201 is located in the cavity.
  • the top of the hollow annular column 104 is higher than the first surface of the first functional chip 201. Specifically, in the embodiment, the top of the hollow annular column 104 is higher than the first surface of the first functional chip 201.
  • the upper image sensing area 204 prevents the light transmissive plate 105 from touching the image sensing area 204.
  • the material of the hollow annular column 104 is a photoresist material or a resin material.
  • the apex of the wire 203 is higher than the top of the image sensing area 204, wherein the apex of the wire 203 is the point farthest from the first functional surface of the first functional chip 201 in the wire 203. .
  • the top of the hollow annular column 104 is higher than the apex of the wire 203. Since the solder resist layer 103 is provided on the first surface of the substrate 101, the conductive wire 203 penetrates the solder resist layer 103 to electrically connect the conductive line 203 with the wiring layer 102 on the first surface of the substrate 101.
  • the cavity wall of the cavity provides protection to the image sensing area 204 to prevent the image sensing area 204 from being damaged.
  • the top of the cavity is a light-transmitting plate 105, external light can be irradiated onto the image sensing area 204 via the light-transmitting plate 105, and the image sensing area 204 receives an external light signal to be converted into an electrical signal. .
  • the second function chip 301 is flip-chip disposed on the second surface of the substrate 101, and the second function chip 301 has an opposite second functional surface and a second back surface, wherein the second functional surface has a circuit The surface of the wiring layer.
  • the second function chip 301 is a signal processing chip, and the second function chip 301 is configured to process an electrical signal converted by the first function chip 201 by using an optical signal. For example, the electrical signal processing may be converted. To display the format signal required by the terminal.
  • the number of the second function chips 301 is greater than or equal to 1; in this embodiment, the number of the second function chips 301 is 1 as an example.
  • the package structure further includes: a metal bump 302 on the second functional surface, and the second portion of the circuit layer 102 exposed by the second surface of the substrate 101 is electrically connected to the second portion Functional surface and circuit layer 102.
  • the metal bump 302 is connected to the circuit wiring layer on the second functional surface of the second functional chip 301 such that the second functional surface and the second surface of the substrate 101 are exposed through the metal bump 302. Part of the electrical connection of the circuit layer 102.
  • the position and the number of the metal bumps 302 are determined according to the electrical connection requirements of the circuit wiring layers on the second functional surface of the second functional chip 301.
  • the material of the metal bump 302 is copper, aluminum, tungsten, gold or tin. In this embodiment, the material of the metal bump 302 is gold.
  • the package structure further includes: a plastic sealing layer 303 located on a second surface of the portion of the substrate 101 and covering the sidewall of the second functional chip 301.
  • the plastic sealing layer 303 functions to protect the second functional chip 301, preventing moisture from being intruded from the outside and electrically insulated from the outside, and preventing performance failure of the second functional chip 301 caused by the influence of the external environment;
  • the layer 303 also functions to further stabilize the bonding between the second functional chip 301 and the substrate 101, so that the second functional chip 301 is not easily detached from the substrate 101.
  • the plastic sealing layer 303 covers a portion of the sidewall of the second functional chip 301. In other embodiments, the plastic sealing layer may cover all sidewalls of the second functional chip, or the plastic sealing layer covers the second back surface of the second functional chip in addition to covering all sidewalls of the second functional chip.
  • the material of the plastic sealing layer 303 is a resin or a solder resist ink material, and the resin may be an epoxy resin or an acrylic resin.
  • the solder bump 401 is for electrically connecting with an external circuit or other device, and the second function chip 301 is electrically connected to an external circuit or other device through the solder bump 401.
  • the solder bumps 401 are distributed around the second functional chip 301.
  • the shape of the top surface of the solder bump 401 is curved, and the material of the solder bump 401 is tin.
  • the material of the solder bump may also be gold or a tin alloy, and the tin alloy may be tin silver, tin lead, tin silver copper, tin silver zinc, tin zinc, tin antimonide, tin indium. , Sikkim, tin-copper, tin-zinc-indium or tin-silver-tantalum.
  • the top of the solder bump 401 is higher than the second back surface of the second functional chip 301.
  • the package structure further includes: an insulating layer 402 on a second surface of the portion of the substrate 101, and the solder bumps 401 extend through the insulating layer 402.
  • the insulating layer 402 can protect a portion of the exposed wiring layer 102 from the problem of the wiring layer 102 being exposed to oxidation or unnecessary electrical connections that may be caused in the external environment.
  • the material of the insulating layer 402 is silicon oxide or resin.
  • the plastic sealing layer 303 is also located on the partial insulating layer 402 to ensure that the exposed wiring layer 102 is covered by the plastic sealing layer 303 or covered by the insulating layer 402.
  • the exposed circuit layer may be covered by only the plastic sealing layer.
  • the first function chip and the second function The package structure provided by the embodiment of the present application is horizontally oriented (the package structure provided by the embodiment of the present application is provided on the opposite sides of the substrate, and the first functional chip and the second functional chip are disposed on the same surface of the substrate.
  • the dimension parallel to the surface of the substrate is significantly smaller, resulting in a higher degree of integration of the package structure.
  • the solder bump and the second functional chip are disposed on the same surface of the substrate, the thickness dimension of the package structure perpendicular to the horizontal plane is reduced as much as possible, and the total thickness of the product is reduced. .
  • the embodiment of the present application further provides a packaging method, including: providing a plurality of first function chips and a second function chip, wherein the first function chip has a first first functional surface and a first back surface, and the first a functional surface having a pad, the second functional chip having an opposite second functional surface and a second back surface; providing a substrate having a plurality of functional regions and a scribe lane region between adjacent functional regions, The substrate has opposite first and second faces, and the substrate has a circuit layer therein; the first functional chip is disposed on the first surface of the substrate functional region, the first back surface and the first surface One side is fixedly bonded; forming a wire electrically connecting the pad and the circuit layer; and the second functional chip is flip-chip disposed on the second surface of the substrate functional area, the second functional surface and the second Oppositely, and the second functional surface is electrically connected to the circuit layer through a portion of the circuit layer exposed by the second surface of the substrate functional region; a solder bump is formed on the second surface of
  • the packaging method since the first functional chip and the second functional chip are disposed on opposite sides of the substrate, the size of the formed package structure in the horizontal direction is significantly reduced, thereby improving The integration of the package structure.
  • FIG. 3 is a schematic structural diagram of a packaging process by using the packaging method provided by the embodiment of the present application.
  • first functional chips 201 are provided, the first functional chip 201 having an opposite first functional surface and a first back surface, the first functional surface having pads 202.
  • a first functional wafer is provided; and the first functional wafer is cut to form a plurality of first functional chips 201.
  • the first function chip 201 is an image sensing chip, and the first functional surface further has an image sensing area 204.
  • the pad 202 and the image sensing area 204 reference may be made to the corresponding description of the foregoing embodiment, and details are not described herein again.
  • a plurality of second function chips 301 are provided, the second function chips 301 having opposite first and second back faces.
  • a second functional wafer is provided; the second functional wafer is cut to form a plurality of second functional chips 301.
  • the second function chip 301 is a signal processing chip
  • the second functional surface is a surface having a circuit wiring layer.
  • the method further includes the steps of: forming at least one metal bump 302 on the second functional surface of the second functional chip 301, and electrically connecting the metal bump 302 to the circuit wiring layer of the second functional surface .
  • the second functional surface of the second functional chip 301 is electrically connected to a portion of the circuit layer exposed by the second surface of the subsequently provided substrate by the metal bump 302.
  • the position and number of the metal bumps 302 formed on the second functional surface of the second functional chip 301 are set according to the requirement of electrical connection of the circuit wiring layer of the second functional surface of the second functional chip 301.
  • the material of the metal bump 302 is copper, aluminum, tungsten, gold or tin; the metal bump 302 is formed by a screen printing process or a ball bonding process.
  • metal bumps may not be formed on the second functional surface of the second functional chip, and the metal bumps may be formed on the circuit layer exposed on the second surface of the subsequently provided substrate. .
  • a substrate 101 which has a plurality of functional regions I and a phase
  • the scribe line region II between the adjacent functional regions I, the substrate 101 has opposite first and second faces, and the substrate 101 has a wiring layer 102 therein.
  • the substrate 101 is a glass substrate, a metal substrate, a semiconductor substrate, or a polymer substrate.
  • the substrate 101 is a PCB substrate.
  • the substrate 101 is cut along the scribe line area II, and is located.
  • the substrate 101 of the functional area I, the first functional chip 201, and the second functional chip 301 will be a plurality of single package structures.
  • the circuit layer 102 is a multi-layer wiring interconnection structure in the substrate 101 according to wiring and electrical connection requirements, wherein a portion of the circuit layer 102 exposed by the first surface is used for subsequent The first functional chip 201 is electrically connected, and a portion of the circuit layer 102 exposed by the second surface is used for subsequent electrical connection with the second functional chip 301.
  • the first surface of the substrate 101 is further formed with a solder resist layer 103.
  • the solder resist layer 103 is located on the first surface of the substrate 101 and also covers the circuit layer 102 to prevent the circuit layer 102 from being Oxidized or corroded.
  • the second surface of the substrate 102 is further formed with an insulating layer 402.
  • the insulating layer 402 is located on the second surface of the substrate 101 and covers the circuit layer 102 to prevent the circuit layer 102 from being oxidized or corroded.
  • a hollow annular post 104 is formed on the first surface of the functional region I of the substrate 101.
  • the hollow annular post 104 is subsequently used to provide protection to the first functional chip 201 (refer to FIG. 3 ), and after the light transmissive plate is disposed on the top of the hollow annular post 104 , the hollow annular post 104 is made
  • the light transmissive plate and the substrate 101 enclose a cavity, and the first functional chip 201 is located in the cavity to prevent the image sensing area 204 in the first functional chip 201 from being contaminated or damaged.
  • the material of the hollow annular column 104 is a photoresist, and the hollow annular column 104 is formed by a coating process and a photolithography process.
  • the hollow ring When the material of the column is a resin material, a resin printing process may also be employed to form the hollow annular column.
  • the thickness of the hollow annular column 104 is not too thin. After the first functional chip 201 is disposed on the first surface of the substrate 101, the top of the hollow annular column 104 should be higher. The image sensing area 204 prevents the subsequently disposed light transmissive plate from touching the image sensing area 204.
  • the hollow annular columns 104 between the adjacent functional areas I are independent of each other.
  • the formed hollow annular columns are also located in the cutting path area, and thus adjacent The hollow annular post between the functional zones is integral, and the hollow annular post located in the area of the cutting track is also subsequently cut when the substrate is cut along the cutting path.
  • the hollow annular column 104 is formed on the first surface of the functional region of the substrate 101 to avoid forming the hollow annular column. The process of 104 causes damage to the first functional chip 201.
  • the first functional chip 201 is disposed on a first surface of the functional area of the substrate 101, and the first back surface is fixedly bonded to the first surface; forming the electrical connection between the pad 202 and the circuit layer. Wire 203 of 102.
  • an adhesive layer (not shown) is disposed on the first back surface or the first surface, and the first back surface and the first surface are fixedly joined by the adhesive layer.
  • the adhesion layer is advantageous for improving the bonding force between the substrate 101 and the first functional chip 201.
  • the pad 202 is electrically connected to the circuit layer 102 of the first surface of the substrate 101.
  • the electrical connection between the pad 202 and the circuit layer 102 is realized by a wire 203, and one end of the wire 203 is The pads 202 are connected, and the other end of the wires 203 is connected to the wiring layer 102.
  • the wire 203 penetrates the solder resist layer 103, so that one end of the wire 203 and the functional area of the substrate 101 are first.
  • the planar circuit layer 102 is electrically connected.
  • the process of forming the wire 203 is a wire bonding process, and the wire 203 is made of metal.
  • the metal is copper, aluminum, tungsten, silver or gold.
  • the wire 203 is curved.
  • the apex of the wire 203 is lower than the top of the hollow annular column 104, thereby preventing the subsequently disposed light-transmitting plate from touching the wire 203.
  • a light-transmitting plate 105 is disposed on the top of the hollow annular column 104, and the light-transmitting plate 105, the hollow annular column 104, and the substrate 101 enclose a cavity, and the first functional chip 201 Located within the cavity.
  • a single of the light transmissive plates 105 may span at least one functional zone I.
  • a separate light transmissive plate 105 is formed above each functional area I.
  • the light transmissive plate may also span at least two functional areas, for example, a light transmissive plate is disposed over all of the functional areas.
  • the light transmissive plate 105 spans at least two functional areas I, the light transmissive plate 105 is also located above the scribe line area II, and subsequently when the substrate 101 is cut along the scribe line area II, The light transmissive plate 105 is also cut.
  • an adhesive layer (not shown) is further formed on the top of the hollow annular column 104, and the material of the adhesive layer may be UV tape or pyrolysis adhesive. tape.
  • the light transmissive plate 105 can also be fixedly engaged with the top of the hollow annular post 104 by direct bonding.
  • the second functional chip 301 is flip-chip disposed on the second surface of the functional area I of the substrate 101, the second functional surface is opposite to the second surface, and the second functional surface is passed A portion of the wiring layer 102 exposed by the second surface of the functional area I of the substrate 101 is electrically connected to the wiring layer 102.
  • a portion of the insulating layer 402 on the second surface of the functional area I of the substrate 101 is etched and removed. Exposing the second side of the functional area I of the substrate 101 and exposing the circuit layer 102 electrically connected to the second functional surface; and disposing the second functional chip 301 on the exposure The substrate 101 is separated from the second surface of the functional area I.
  • the number of second functional chips 301 flip-chip mounted on the second surface of the same functional area I of the substrate 101 is greater than or equal to one.
  • the number of the second function chips 301 flip-chip mounted on the second surface of the same functional area I of the substrate 101 is 1 as an example.
  • the electrical connection between the second functional surface and the circuit layer 102 exposed by the second surface of the functional area I of the substrate 101 is realized by the metal bump 302.
  • the metal bump 302 is fixedly bonded to the circuit layer 102 exposed on the second surface of the functional area I of the substrate 101 by a solder bonding process, wherein the solder bonding process is eutectic bonding, Ultrasonic hot pressing, hot press welding or ultrasonic pressure welding.
  • a solder bump 401 is formed on a second surface of the functional region I of the substrate 101, and the solder bump 401 passes through a portion of the wiring layer 102 and a circuit layer exposed by the second surface of the functional region I of the substrate 101. 102 electrical connection.
  • the solder bump 401 is electrically connected to the second functional chip 301, and the solder bump 401 is also used for external circuit or other device electrical connection, so that the second functional chip 301 and an external circuit or other The device is electrically connected.
  • the insulating layer 402 is further formed on the second surface of the functional region I of the substrate 101, a portion of the insulating layer 402 is etched away to expose the functional region of the substrate 101 before the solder bump 402 is formed. A portion of the wiring layer 102 on the second surface of the substrate; the solder bumps 401 are formed on the wiring layer 102 exposed on the second surface of the functional region I of the substrate 101.
  • the distance from the top of the solder bump 401 to the second surface of the substrate 101 is greater than the distance from the second back surface of the second functional chip 301 to the second surface of the substrate 101, ensuring that the solder bump 401 and the external circuit Or the second functional chip 301 is not squeezed when the device is electrically connected.
  • the distance from the top of the solder bump to the second side of the substrate may also be equal to or smaller than the distance from the second back surface of the second functional chip to the second surface of the substrate.
  • the top surface of the solder bump 401 has an arc shape, and the material of the solder bump 401
  • the tin alloy may be tin silver, tin lead, tin silver copper, tin silver zinc, tin zinc, tin antimonium indium, tin indium, tin gold, tin copper, tin zinc indium or tin silver crucible Wait.
  • the solder bump 401 is formed by a ball placement process.
  • the solder bumps may also be formed using a screen printing process and a reflow process.
  • a plastic encapsulation layer 303 is formed on the second surface of the functional area I of the substrate 101, and the plastic encapsulation layer 303 covers the sidewall of the second functional chip 301.
  • the plastic sealing layer 303 is located on the surface of the partial insulating layer 402 in addition to the portion of the circuit layer 102 exposed on the second surface of the functional area I of the substrate 101.
  • the plastic sealing layer 303 functions to protect the second functional chip 301 from moisture intrusion from the outside, so that the second functional chip 301 is electrically insulated from the outside. In addition, the plastic sealing layer 303 also functions to support the second functional chip 301 to improve the bonding between the second functional chip 301 and the substrate 101.
  • the plastic sealing layer 303 is formed by a molding process using a transfer method or a press-bonding method; the plastic sealing layer 303 may also be formed by a dispensing process.
  • the plastic sealing layer 303 covers a portion of the sidewall of the second functional chip 301. In other embodiments, the plastic sealing layer may cover all sidewalls of the second functional chip, or the plastic sealing layer covers the second back surface of the second functional chip in addition to covering all sidewalls of the second functional chip.
  • the plastic seal layer 303 is formed by using the entire module or a plurality of discrete modules.
  • the plastic sealing layer 303 is formed by using a plurality of discrete modules, that is, the plastic sealing layers 303 on the second surface of the adjacent functional area I are independent of each other.
  • the plastic sealing layer may also be formed by using the entire module, that is, forming a monolithic plastic sealing layer on the second surface of the entire substrate.
  • the method for forming the plastic sealing layer 303 by using a discrete module is: using a plurality of molds, each of which is filled with a material of the plastic sealing layer 303; and pressing the mold on the second surface of the functional area I of the substrate 101, After the drying process, the mold is removed to form a plastic seal layer 303 having a plurality of discrete modules.
  • the material of the plastic sealing layer 303 is a resin or a solder resist ink material, for example, an epoxy resin or an acrylic resin.
  • the plastic sealing layer 303 exposes the sidewall of the solder bump 401.
  • the plastic sealing layer may also cover the sidewalls of the solder bumps to protect the sidewalls of the solder bumps and further improve the bonding between the solder bumps and the substrate. .
  • the plastic sealing layer is formed by forming the soldering protrusion 401 first; in other embodiments, the plastic sealing layer may be formed first, and then the soldering bump is formed. And the plastic sealing layer may expose the solder bump sidewalls and may also cover the solder bump sidewalls.
  • the substrate 101 is cut along the scribe line region II to form a plurality of individual package structures as shown in FIG.
  • the substrate 101 is cut by a slicing knife cutting or laser cutting process to form a plurality of single package structures.
  • the first functional chip 201 and the second functional chip 301 are respectively located on opposite sides of the substrate 101. Specifically, the first functional chip 201 is located on the first surface of the substrate 101. The second function chip 301 is located on the second surface of the substrate 101. Therefore, the size of the package structure formed in this embodiment is significantly reduced in the horizontal direction, thereby improving the integration degree of the formed package structure.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

一种封装结构以及封装方法，封装结构包括：基板（101），具有相对的第一面和第二面，且基板（101）内具有线路层（102）；位于基板（101）第一面上的第一功能芯片（201），第一功能芯片（201）具有相对的第一功能面和第一背面，第一功能面上具有焊盘（202），第一背面与第一面固定接合，且焊盘（202）通过导线（203）与线路层（102）电连接；倒装设置在基板（101）第二面上的第二功能芯片（301），第二功能芯片（301）具有相对的第二功能面和第二背面，第二功能面与第二面相对，且第二功能面通过基板（101）第二面暴露出的线路层（102）的部分与线路层（102）电连接；位于基板（101）第二面上的焊接凸起（401），焊接凸起（401）通过基板（101）第二面暴露出的线路层（102）的部分与线路层（102）电连接。本申请减小了封装结构的尺寸，提高了封装结构的集成度。

Description

封装结构以及封装方法
本申请要求于2016年09月26日提交中国专利局、申请号为201610850385.X、发明名称为“封装结构以及封装方法”的中国专利申请，以及于2016年09月26日提交中国专利局、申请号为201621080212.6、发明名称为“封装结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及封装技术领域，特别涉及一种封装结构以及封装方法。
背景技术
随着电子产品功能的不断增强，芯片朝向高集成度、高像素化以及微型化趋势发展。为了应对这一挑战，提出了扇出型(fan out)晶圆级封装技术。
扇出型晶圆级封装技术主要包括以下步骤：先将整片裸晶圆进行切割，形成单颗分立的芯片；提供基板，将切割后的独立芯片在基板上重新排布，形成芯片间距更合适的新的晶圆；然后采用晶圆级封装技术(WLP，Wafer Level Package)，对重新排布的晶圆进行封装测试后，切割成比原始芯片面积大的焊球阵列芯片。扇出型晶圆级封装技术有利于封装体积小、多电极、电极间距窄的芯片；此外，扇出型晶圆级封装技术原则上还可以同时封装不同类型氮尺寸相同甚至焊球数量较为接近的芯片。
与晶圆级芯片尺寸封装相比，扇出型晶圆级封装技术更好的解决了可靠性低问题以及与后续制程PCB匹配的问题，其中，所述可靠性低的问 题可能是由于电极密集度过大造成的。
然而，现有技术的封装结构的尺寸较大，集成度有待提高。
发明内容
本申请提供一种封装结构，包括：基板，所述基板具有相对的第一面和第二面，且所述基板内具有线路层；位于所述基板第一面上的第一功能芯片，所述第一功能芯片具有相对的第一功能面和第一背面，所述第一功能面上具有焊盘，所述第一背面与所述基板的第一面固定接合，且所述焊盘通过导线与所述线路层电连接；倒装设置在所述基板第二面上的第二功能芯片，所述第二功能芯片具有相对的第二功能面和第二背面，所述第二功能面与所述基板的第二面相对，且所述第二功能面通过所述基板第二面暴露出的线路层的部分与所述线路层电连接；位于所述基板第二面上的焊接凸起，所述焊接凸起通过所述基板第二面暴露出的线路层的部分与所述线路层电连接。
可选的，所述第一功能芯片为影像传感芯片；所述第一功能面上还具有影像感应区，且所述焊盘环绕所述影像感应区。
可选的，所述封装结构还包括：位于所述基板第一面上的中空环状柱，所述中空环状柱包围所述第一功能芯片；设置在所述中空环状柱顶部的透光板，且所述透光板、中空环状柱以及所述基板围成空腔，所述第一功能芯片位于所述空腔内。
可选的，所述中空环状柱顶部高于所述第一功能芯片的第一面。
可选的，所述中空环状柱顶部与所述透光板之间还具有粘胶层。
可选的，所述第二功能芯片为信号处理芯片；所述第二功能芯片的数量大于或等于1。
可选的，所述封装结构还包括：位于所述第二功能面上的金属凸块， 通过所述金属凸块和所述基板第二面暴露出的线路层的部分电连接所述第二功能面与所述线路层。
可选的，所述焊接凸起分布在所述第二功能芯片周围。
可选的，所述第二焊接凸起顶部与所述基板第二面之间的距离大于所述第二功能芯片第二背面与所述基板第二面之间的距离。
可选的，所述封装结构还包括：位于所述第一背面与所述第一面之间的粘附层。
可选的，所述封装结构还包括：位于所述基板部分第二面上的绝缘层，且所述焊接凸起贯穿所述绝缘层；位于所述基板第一面上的防焊层，且所述导线贯穿所述防焊层。
可选的，所述封装结构还包括：位于所述基板第二面且覆盖第二功能芯片侧壁的塑封层。
本申请还提供一种封装方法，包括：提供若干个第一功能芯片以及第二功能芯片，所述第一功能芯片具有相对的第一功能面和第一背面，所述第一功能面上具有焊盘，所述第二功能芯片具有相对的第二功能面和第二背面；提供基板，所述基板具有若干功能区和位于相邻功能区之间的切割道区域，所述基板具有相对的第一面和第二面，且所述基板内具有线路层；将所述第一功能芯片设置在所述基板功能区第一面上，所述第一背面与所述第一面固定接合；形成电连接所述焊盘以及线路层的导线；将所述第二功能芯片倒装设置在所述基板功能区第二面上，所述第二功能面与所述第二面相对，且所述第二功能面通过所述基板功能区第二面暴露出的线路层的部分与所述线路层电连接；在所述基板功能区第二面上形成焊接凸起，所述焊接凸起通过所述基板功能区第二面暴露出的线路层的部分与所述线路层电连接；沿所述切割道区域切割所述基板，形成若干单颗封装结构。
可选的，所述第一功能芯片为影像传感芯片；所述第一功能面上还具有影像感应区，且所述焊盘环绕所述影像感应区；所述封装方法还包括：在所述基板功能区第一面上形成中空环状柱，且当所述第一功能芯片设置在所述基板功能区第一面上后，所述中空环状柱包围所述第一功能芯片；在所述中空环状柱顶部设置透光板，且所述透光板、中空环状柱以及基板围成空腔，且所述第一功能芯片位于所述空腔内。
可选的，在将所述第一功能芯片设置在所述基板功能区第一面上之前，形成所述中空环状柱。
可选的，采用涂布工艺以及光刻工艺，形成所述中空环状柱；或者，采用树脂印刷工艺，形成所述中空环状柱。
可选的，采用打线工艺，形成所述导线。
可选的，在将所述第二功能芯片倒装设置在所述基板功能区第二面上之前，还包括步骤：在所述第二功能芯片第二功能面上或者所述基板功能区第二面上形成金属凸块；采用焊接键合工艺，通过所述金属凸块和所述基板功能区第二面暴露出的线路层的部分实现所述第二功能面与所述线路层电连接。
可选的，在切割所述基板之前，还包括步骤：在所述基板功能区部分第二面上形成塑封层，且所述塑封层覆盖所述第二功能芯片侧壁。
可选的，在形成所述焊接凸起之前，形成所述塑封层；或者，在形成所述焊接凸起之后，形成所述塑封层。
在本申请一个实施例提供的封装结构中，第一功能芯片以及第二功能芯片分别设置在基板相对的两个面上，与第一功能芯片以及第二功能芯片并行设置在基板同一个面上的方案相比，在水平方向上(平行于基板表面方向上)的尺寸明显更小，从而使得封装结构的集成度更高。并且，由于所述焊接凸起与所述第二功能芯片设置在所述基板的同一面上，从而减 小了所述封装结构在垂直于水平面上的厚度尺寸，降低产品的总厚度。
附图说明
图1为一种封装结构的结构示意图；
图2为本申请实施例提供的封装结构的结构示意图；
图3至图10为采用本申请实施例提供的封装方法进行封装过程的结构示意图。
具体实施方式
图1为一种封装结构的结构示意图。参考图1，所述封装结构包括：具有相对的上表面以及下表面的基板10，所述基板10中分布有线路互连层(未标示)，且所述基板10中具有贯穿所述基板10的镂空11，所述透光板20粘贴于所述基板10镂空11的上表面；倒装电连接于所述基板10下表面的第一功能芯片30，且所述第一功能芯片30的功能区位于所述镂空11正下方，且所述第一功能芯片30的焊盘(未标示)与线路互连层电连接；位于所述基板10上表面且通过导线40与所述基板10电连接的第二功能芯片50，所述第二功能芯片50位于所述镂空11一侧；位于所述基板30下表面的BGA锡球60；位于所述基板10表面且覆盖第二功能芯片50侧壁的塑封层70。
上述封装结构在水平方向上的尺寸大，造成封装结构的集成度低，不利于满足器件小型化微型化的发展趋势。
本申请一实施例提供了一种封装结构，显著的减小封装结构的尺寸。参考图2，所述封装结构包括：
基板101，所述基板101具有相对的第一面(未标示)和第二面(未标示)，且所述基板101内具有线路层102；
位于所述基板102第一面上的第一功能芯片201，所述第一功能芯片201具有相对的第一功能面(未标示)和第一背面(未标示)，所述第一功能面上具有焊盘202，所述第一背面与所述第一面固定接合，且所述焊盘202通过导线203与所述线路层102电连接；
倒装设置在所述基板101第二面上的第二功能芯片301，所述第二功能芯片301具有相对的第二功能面(未标示)和第二背面(未标示)，且所述第二功能面通过所述基板101第二面暴露出来的线路层102的部分与所述线路层102电连接；
位于所述基板101第二面上的焊接凸起401，所述焊接凸起401通过所述基板101第二面暴露出的线路层102的部分与所述线路层102电连接。
以下将结合附图对本实施例提供的封装结构进行详细说明。
所述基板101起到支撑所述第一功能芯片201以及第二功能芯片301的作用。此外，所述基板101还起到电连接所述第一功能芯片201以及第二功能芯片301的作用，且还用于与外接电路或者其他部件进行电连接。
所述基板101可以为玻璃基板、金属基板、半导体基板或者聚合物基板。本实施例中，所述基板101为PCB基板。
所述基板101内还具有线路层102。本实施例中，根据布线以及电连接需求，所述线路层102为位于所述基板101内的多层布线互联结构。其中，所述第一面暴露出的线路层102的部分用于与第一功能芯片201电连接；所述第二面暴露出的线路层102的部分用于与第二功能芯片301电连接。
本实施例中，所述基板101第一面上还可以设置有防焊层(Solder Mask Layer)103，所述防焊层103位于所述基板101第一面并覆盖所述线路层102，并且，所述防焊层103暴露出所述线路层102的一部分，以使所述导线203的一端位于所述暴露出的线路层102的部分，保证所述导线203 与所述线路层102电连接。
所述防焊层103的材料为绿油。所述防焊层103用于对所述线路层102起到保护作用，避免线路层102被氧化，且防止所述线路层102与其他部件之间发生不必要的电连接。
本实施例中，所述第一功能芯片201为影像传感芯片，所述第一功能面上还具有影像感应区204，且所述焊盘202环绕所述影像感应区204。所述第一功能面为具有焊盘202以及影像感应区204的面，所述第一背面为与基板201的第二面固定接合的面。
所述第一功能芯片201内可以具有将所述影像感应区204和焊盘202电连接的金属互连结构(未图示)，所述影像感应区204内形成有影像传感器单元和与影像传感器单元相连接的关联电路，影像感应区204将外界光线接收并转换成电学信号，并将所述电学信号通过金属互连结构和焊盘202、以及基板101内的线路层102，以便传送至第二功能芯片301内。
为了便于布线，所述影像感应区204位于所述第一功能面的中间位置，所述焊盘202位于所述第一功能面的边缘位置，且所述焊盘202位于所述影像感应区204的四侧，呈矩形分布，所述影像感应区204的每一个侧边具有若干个焊盘202，且每一个焊盘202通过导线203与所述基板101第一面上的线路层102电连接。
所述导线203顶点高于所述第一功能芯片201第一面。所述导线203的一端与所述焊盘202电连接，所述导线203的另一端与所述基板101第一面上的线路层102电连接，从而使得所述第一功能芯片201电路与所述线路层102电连接。所述导线203连接于所述焊盘202与所述线路层102之间，因此所述导线203弯曲。
所述导线203的材料为金属，所述金属包括铜、铝、钨、金或银。
本实施例中，为了提高所述第一功能芯片201的第一背面与所述基 板101第一面之间的结合性能，所述第一背面与所述第一面之间还具有粘附层，通过所述粘附层提高所述第一背面与所述第一面之间的结合能力。
为了对所述第一功能芯片201第一面上的影像感应区204提高保护作用，防止影像感应区204受到损伤，本实施例中，所述封装结构中，所述影像感应区204受到保护。具体地，所述封装结构还包括：位于所述基板101第一面上的中空环状柱104，所述中空环状柱104包围所述第一功能芯片201；设置在所述中空环状柱104顶部的透光板105，且所述透光板105、中空环状柱104以及所述基板101围成空腔，所述第一功能芯片201位于所述空腔内。
所述中空环状柱104顶部高于所述第一功能芯片201的第一面，具体地，本实施例中，所述中空环状柱104顶部高于所述第一功能芯片201第一面上的影像感应区204，防止所述透光板105触碰到所述影像感应区204。
所述中空环状柱104的材料为光刻胶材料或者树脂材料。
本实施例中，所述导线203的顶点高于所述影像感应区204顶部，其中，所述导线203的顶点为距离所述导线203中距离第一功能芯片201第一功能面最远的点。为了避免所述透光板105触碰到所述导线203，所述中空环状柱104顶部高于所述导线203的顶点。由于所述基板101第一面上具有防焊层103，因此所述导线203贯穿所述防焊层103，以使所述导线203与所述基板101第一面的线路层102电连接。
由于所述第一功能芯片201位于所述空腔内，所述空腔的腔壁对所述影像感应区204提供保护作用，避免所述影像感应区204受到损伤。并且，由于所述空腔顶部为透光板105，使得外界光线可以经由所述透光板105照射到所述影像感应区204上，所述影像感应区204接收外界光信号以转化为电信号。
所述第二功能芯片301倒装设置在所述基板101第二面上，所述第二功能芯片301具有相对的第二功能面和第二背面，其中，所述第二功能面为具有电路布线层的表面。
本实施例中，所述第二功能芯片301为信号处理芯片，所述第二功能芯片301用于处理所述第一功能芯片201利用光信号转化的电信号，例如，可以将电信号处理转化为显示终端所要求的格式信号。所述第二功能芯片301的数量大于或等于1；本实施例中，以所述第二功能芯片301的数量为1作为示例。
所述第二功能面通过所述基板101第二面暴露出的线路层102的部分与线路层102电连接。所述封装结构还包括：位于所述第二功能面上的金属凸块302，通过所述金属凸块302和所述基板101第二面暴露出的线路层102的部分电连接所述第二功能面与线路层102。
所述金属凸块302与所述第二功能芯片301第二功能面上的电路布线层相连接，从而使得通过金属凸块302使所述第二功能面与所述基板101第二面暴露出的线路层102的部分电连接。
根据所述第二功能芯片301第二功能面上的电路布线层的电连接需求，确定所述金属凸块302的位置以及数量。所述金属凸块302的材料为铜、铝、钨、金或锡。本实施例中，所述金属凸块302的材料为金。
本实施例中，所述封装结构还包括：位于所述基板101部分第二面且覆盖所述第二功能芯片301侧壁的塑封层303。
所述塑封层303起到保护所述第二功能芯片301的作用，防止湿气由外部侵入、与外部电气绝缘，防止在外界环境的影响下造成的第二功能芯片301性能失效；所述塑封层303还起到进一步稳固所述第二功能芯片301与所述基板101之间结合性的作用，使得所述第二功能芯片301不易从基板101上脱落。
本实施例中，所述塑封层303覆盖第二功能芯片301部分侧壁。在其他实施例中，所述塑封层还可以覆盖第二功能芯片全部侧壁，或者，所述塑封层除覆盖第二功能芯片全部侧壁外还覆盖第二功能芯片第二背面。
所述塑封层303的材料为树脂或者防焊油墨材料，所述树脂可以为环氧树脂或者丙烯酸树脂。
所述焊接凸起401用于与外部电路或者其他器件电连接，通过所述焊接凸起401使所述第二功能芯片301与外部电路或其他器件电连接。本实施例中，所述焊接凸起401分布在所述第二功能芯片301周围。
本实施例中，所述焊接凸起401顶部表面形状为弧形，所述焊接凸起401的材料为锡。在其他实施例中，所述焊接凸起的材料还可以为金或者锡合金，所述锡合金可以为锡银、锡铅、锡银铜、锡银锌、锡锌、锡铋铟、锡铟、锡金、锡铜、锡锌铟或者锡银锑等。
为了避免当所述焊接凸起401与外部电路或者其他器件电连接时对第二功能芯片301造成损伤，所述焊接凸起401顶部高于所述第二功能芯片301的第二背面。
本实施例中，所述封装结构还包括：位于所述基板101部分第二面上的绝缘层402，且所述焊接凸起401贯穿所述绝缘层402。所述绝缘层402可以对暴露出的线路层102的部分起到保护作用，避免线路层102暴露在外界环境中可能引发的氧化或者不必要的电连接的问题。
所述绝缘层402的材料为氧化硅或者树脂。本实施例中，所述塑封层303还位于部分绝缘层402上，保证暴露出的线路层102被所述塑封层303覆盖或者被绝缘层402覆盖。
需要说明的是，在其他实施例中，还可以仅采用塑封层对暴露出的线路层进行覆盖。
本申请实施例提供的封装结构中，所述第一功能芯片以及第二功能 芯片分别设置在所述基板相对的两个面上，与第一功能芯片以及第二功能芯片并行设置在基板同一个面上的方案相比，本申请实施例提供的封装结构在水平方向上(平行于基板表面方向上)的尺寸明显更小，从而使得封装结构的集成度更高。
并且，由于所述焊接凸起与所述第二功能芯片设置在所述基板的同一面上，从而尽可能的减小了所述封装结构在垂直于水平面上的厚度尺寸，降低产品的总厚度。
相应的，本申请实施例还提供一种封装方法，包括：提供若干个第一功能芯片以及第二功能芯片，所述第一功能芯片具有相对的第一功能面和第一背面，所述第一功能面上具有焊盘，所述第二功能芯片具有相对的第二功能面和第二背面；提供基板，所述基板具有若干功能区和位于相邻功能区之间的切割道区域，所述基板具有相对的第一面和第二面，且所述基板内具有线路层；将所述第一功能芯片设置在所述基板功能区第一面上，所述第一背面与所述第一面固定接合；形成电连接所述焊盘以及线路层的导线；将所述第二功能芯片倒装设置在所述基板功能区第二面上，所述第二功能面与所述第二面相对，且所述第二功能面通过所述基板功能区第二面暴露出的线路层的部分与线路层电连接；在所述基板功能区第二面上形成焊接凸起，所述焊接凸起通过所述基板功能区第二面暴露出的线路层的部分与所述线路层电连接；沿所述切割道区域切割所述基板，形成若干单颗封装结构。
采用本申请实施例提供的封装方法，由于第一功能芯片以及第二功能芯片设置在所述基板相对的两个面上，从而使得形成的封装结构在水平方向上的尺寸显著减小，从而提高了封装结构的集成度。
图3至图10为采用本申请实施例提供的封装方法进行封装过程的结构示意图。
参考图3，提供若干个第一功能芯片201，所述第一功能芯片201具有相对的第一功能面和第一背面，所述第一功能面上具有焊盘202。
具体地，提供第一功能晶圆；切割所述第一功能晶圆形成多颗第一功能芯片201。
本实施例中，所述第一功能芯片201为影像传感芯片，所述第一功能面上还具有影像感应区204。有关所述焊盘202以及影像感应区204的描述可参考前述实施例的相应描述，在此不再赘述。
参考图4，提供若干个第二功能芯片301，所述第二功能芯片301具有相对的第一功能面和第二背面。
具体地，提供第二功能晶圆；切割所述第二功能晶圆形成多个第二功能芯片301。本实施例中，所述第二功能芯片301为信号处理芯片，所述第二功能面为具有电路布线层的面。
本实施例中，还包括步骤：在所述第二功能芯片301第二功能面上形成至少一个金属凸块302，且所述金属凸块302与所述第二功能面的电路布线层电连接。
利用所述金属凸块302使所述第二功能芯片301的第二功能面与后续提供的基板第二面暴露出的线路层的部分进行电连接。根据所述第二功能芯片301第二功能面的电路布线层进行电连接的需求，设置在所述第二功能芯片301第二功能面上形成的金属凸块302的位置和数量。
所述金属凸块302的材料为铜、铝、钨、金或锡；采用网板印刷工艺或者植球工艺，形成所述金属凸块302。
需要说明的是，在其他实施例中，还可以不在所述第二功能芯片第二功能面上形成金属凸块，在后续提供的基板第二面暴露出的线路层上形成所述金属凸块。
参考图5，提供基板101，所述基板101具有若干功能区I和位于相 邻功能区I之间的切割道区域II，所述基板101具有相对的第一面和第二面，且所述基板101内具有线路层102。
所述基板101为玻璃基板、金属基板、半导体基板或者聚合物基板。本实施例中，所述基板101为PCB基板。
后续在将第一功能芯片201(参考图3)以及第二功能芯片301(参考图4)设置在所述基板101功能区I后，会沿所述切割道区域II切割所述基板101，位于功能区I的基板101、第一功能芯片201以及第二功能芯片301将成为若干单颗的封装结构。
本实施例中，根据布线以及电连接需求，所述线路层102为具有所述基板101内的多层布线互联结构，其中，所述第一面暴露出的线路层102的部分用于后续与第一功能芯片201电连接，所述第二面暴露出的线路层102的部分用于后续与第二功能芯片301电连接。
本实施例中，所述基板101第一面还形成有防焊层103，所述防焊层103位于所述基板101第一面且还覆盖所述线路层102，防止所述线路层102被氧化或者被腐蚀。所述基板102第二面还形成有绝缘层402，所述绝缘层402位于所述基板101第二面且覆盖所述线路层102，防止所述线路层102被氧化或者被腐蚀。
参考图6，在所述基板101功能区I第一面上形成中空环状柱104。
所述中空环状柱104后续用于对所述第一功能芯片201(参考图3)提供保护，且在所述中空环状柱104顶部设置透光板后，使得所述中空环状柱104、透光板以及所述基板101围成空腔，且所述第一功能芯片201位于所述空腔内，避免第一功能芯片201中的影像感应区204受到污染或损伤。
本实施例中，所述中空环状柱104的材料为光刻胶，采用涂布工艺以及光刻工艺，形成所述中空环状柱104。在其他实施例中，所述中空环状 柱的材料为树脂材料时，还可以采用树脂印刷工艺，形成所述中空环状柱。
需要说明的是，所述中空环状柱104的厚度不宜过薄，后续当所述第一功能芯片201设置在所述基板101第一面上后，所述中空环状柱104顶部应高于影像感应区204，防止后续设置的透光板触碰到所述影像感应区204。
还需要说明的是，本实施例中，相邻功能区I之间的中空环状柱104为相互独立的，在其他实施例中，形成的中空环状柱还位于切割道区域，因此相邻功能区之间的中空环状柱为一体的，后续在沿切割道切割所述基板时还切割位于切割道区域的中空环状柱。
本实施例中，在所述基板101第一面上设置第一功能芯片201之前，在所述基板101功能区第一面上形成所述中空环状柱104，避免形成所述中空环状柱104的工艺对第一功能芯片201带来损伤。
参考图7，将所述第一功能芯片201设置在所述基板101功能区第一面上，所述第一背面与所述第一面固定接合；形成电连接所述焊盘202以及线路层102的导线203。
本实施例中，在所述第一背面或者所述第一面上设置粘附层(未图示)，通过所述粘附层实现所述第一背面与所述第一面的固定接合。在所述粘附层有利于提高所述基板101与所述第一功能芯片201之间的结合力。
所述焊盘202与所述基板101第一面的线路层102电连接，具体地，通过导线203实现所述焊盘202与所述线路层102的电连接，所述导线203一端与所述焊盘202相连，所述导线203另一端与所述线路层102相连。本实施例中，由于所述基板101第一面上形成有防焊层103，因此所述导线203贯穿所述防焊层103，从而使得所述导线203一端与所述基板101功能区第一面的线路层102电连接。
形成所述导线203的工艺为打线工艺，所述导线203的材料为金属， 所述金属为铜、铝、钨、银或金。
所述导线203弯曲。本实施例中，所述导线203顶点低于所述中空环状柱104顶部，从而防止后续设置的透光板触碰到所述导线203。
参考图8，在所述中空环状柱104顶部设置透光板105，且所述透光板105、中空环状柱104以及所述基板101围成空腔，且所述第一功能芯片201位于所述空腔内。
单个所述透光板105可以横跨至少一个功能区I。本实施例中，在每个功能区I上方形成单独的透光板105。
在其他实施例中，所述透光板还可以横跨至少两个功能区，例如，在所有功能区上方设置一块透光板。
需要说明的是，当所述透光板105横跨至少两个功能区I时，所述透光板105还位于切割道区域II上方，后续在沿切割道区域II切割所述基板101时，还切割所述透光板105。
本实施例中，在设置所述透光板105之前，还在所述中空环状柱104顶部形成粘胶层(未图示)，所述粘胶层的材料可以为UV胶带或者热解胶胶带。
在其他实施例中，还可以通过直接键合的方式，使所述透光板105与所述中空环状柱104顶部固定接合。
参考图9，将所述第二功能芯片301倒装设置在所述基板101功能区I第二面上，所述第二功能面与所述第二面相对，且所述第二功能面通过所述基板101功能区I第二面暴露出的线路层102的部分与线路层102电连接。
本实施例中，在将所述第二功能芯片301倒装在设置在所述基板101功能区I第二面之前，先刻蚀去除所述基板101功能区I第二面上的部分绝缘层402，暴露出所述基板101功能区I部分第二面，且暴露出与所述第二功能面电连接的线路层102；将所述第二功能芯片301倒装设置在所述暴露 出的基板101功能区I第二面上。
倒装在基板101同一功能区I第二面上的第二功能芯片301的数量大于或等于1。本实施例中，以倒装在基板101同一功能区I第二面上的第二功能芯片301的数量为1作为示例。
本实施例中，通过所述金属凸块302实现所述第二功能面与所述基板101功能区I第二面暴露出的线路层102之间的电连接。具体地，采用焊接键合工艺，使所述金属凸块302与所述基板101功能区I第二面暴露出的线路层102固定接合，其中，所述焊接键合工艺为共晶键合、超声热压、热压焊接或者超声波压焊等。
参考图10，在所述基板101功能区I第二面上形成焊接凸起401，所述焊接凸起401通过所述基板101功能区I第二面暴露出的线路层102的部分与线路层102电连接。
通过所述焊接凸起401与所述第二功能芯片301电连接，且所述焊接凸起401还用于外部电路或者其他器件电连接，从而使得所述第二功能芯片301与外电路或者其他器件电连接。
本实施例中，由于所述基板101功能区I第二面上还形成有绝缘层402，在形成所述焊接凸起402之前，先刻蚀去除部分绝缘层402，暴露出所述基板101功能区I第二面上的部分线路层102；在所述基板101功能区I第二面暴露出的线路层102上形成所述焊接凸起401。
所述焊接凸起401顶部至所述基板101第二面的距离大于所述第二功能芯片301第二背面至所述基板101第二面的距离，保证当所述焊接凸起401与外部电路或器件电连接时不会对第二功能芯片301造成挤压。在其他实施例中，所述焊接凸起顶部至所述基板第二面的距离还可以等于或小于所述第二功能芯片第二背面至所述基板第二面的距离。
所述焊接凸起401顶部表面形状为弧形，所述焊接凸起401的材料 为金、锡或者锡合金，所述锡合金可以为锡银、锡铅、锡银铜、锡银锌、锡锌、锡铋铟、锡铟、锡金、锡铜、锡锌铟或者锡银锑等。
本实施例中，采用植球工艺，形成所述焊接凸起401。在其他实施例中，还可以采用网板印刷工艺、以及回流工艺，形成所述焊接凸起。
继续参考图10，在所述基板101功能区I第二面上形成塑封层303，所述塑封层303覆盖所述第二功能芯片301侧壁。
本实施例中，所述塑封层303除覆盖所述基板101功能区I第二面暴露出的线路层102的部分外，还位于部分绝缘层402表面。
所述塑封层303起到保护第二功能芯片301的作用，防止湿气由外部侵入，使得所述第二功能芯片301与外部电气绝缘。此外，所述塑封层303还起到支撑第二功能芯片301的作用，提高第二功能芯片301与所述基板101之间的结合性。
采用塑封工艺(molding)形成所述塑封层303，所述塑封工艺采用转移方式或压合方式；还可以采用点胶工艺形成所述塑封层303。
本实施例中，所述塑封层303覆盖第二功能芯片301部分侧壁。在其他实施例中，所述塑封层还可以覆盖第二功能芯片全部侧壁，或者，所述塑封层除覆盖第二功能芯片全部侧壁外，还覆盖第二功能芯片第二背面。
采用整个模块或若干分立模块的方式形成所述塑封层303。本实施例中，采用若干个分立的模块的方式形成所述塑封层303，即相邻功能区I第二面上的塑封层303为相互独立的。在其他实施例中，还可以采用整个模块的方式形成所述塑封层，即对整块基板第二面上形成整块的塑封层。
具体地，采用分立模块的方式形成所述塑封层303的方法为：采用多个模具，且每个模具中填充塑封层303材料；将模具按压在所述基板101功能区I第二面上，进行烘干处理后撤除模具，形成具有若干分立模块的塑封层303。
所述塑封层303的材料为树脂或防焊油墨材料，例如，环氧树脂或丙烯酸树脂。
本实施例中，所述塑封层303暴露出所述焊接凸起401侧壁。在其他实施例中，所述塑封层还可以覆盖所述焊接凸起侧壁，从而对焊接凸起的侧壁起到保护作用，且进一步的提高焊接凸起与所述基板之间的结合性。
需要说明的是，本实施例中，以先形成所述焊接凸起401后形成所述塑封层为例；在其他实施例中，还可以先形成所述塑封层、后形成所述焊接凸起，且所述塑封层可以暴露出焊接凸起侧壁，还可以覆盖所述焊接凸起侧壁。
在形成所述焊接凸起401以及塑封层303之后，沿所述切割道区域II切割所述基板101，形成若干单颗如图2所示的封装结构。
本实施例中，采用切片刀切割或激光切割工艺切割所述基板101，形成若干单颗封装结构。
由于所述第一功能芯片201以及所述第二功能芯片301分别位于所述基板101相对的两个面上，具体地，所述第一功能芯片201位于所述基板101第一面上，所述第二功能芯片301位于所述基板101第二面上，因此本实施例形成的封装结构在水平方向上的尺寸明显减小了，从而提高了形成的封装结构的集成度。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (20)

  1. 一种封装结构，其特征在于，包括：
    基板，所述基板具有相对的第一面和第二面，且所述基板内具有线路层；
    位于所述基板第一面上的第一功能芯片，所述第一功能芯片具有相对的第一功能面和第一背面，所述第一功能面上具有焊盘，所述第一背面与所述基板的第一面固定接合，且所述焊盘通过导线与所述线路层电连接；
    倒装设置在所述基板第二面上的第二功能芯片，所述第二功能芯片具有相对的第二功能面和第二背面，所述第二功能面与所述基板的第二面相对，且所述第二功能面通过所述基板第二面暴露出的线路层的部分与所述线路层电连接；
    位于所述基板第二面上的焊接凸起，所述焊接凸起通过所述基板第二面暴露出的线路层的部分与所述线路层电连接。
  2. 如权利要求1所述的封装结构，其特征在于，所述第一功能芯片为影像传感芯片；所述第一功能面上还具有影像感应区，且所述焊盘环绕所述影像感应区。
  3. 如权利要求2所述的封装结构，其特征在于，所述封装结构还包括：
    位于所述基板第一面上的中空环状柱，所述中空环状柱包围所述第一功能芯片；
    设置在所述中空环状柱顶部的透光板，且所述透光板、中空环状柱以及所述基板围成空腔，所述第一功能芯片位于所述空腔内。
  4. 如权利要求3所述的封装结构，其特征在于，所述中空环状柱顶部高于所述第一功能芯片的第一面。
  5. 如权利要求2所述的封装结构，其特征在于，所述中空环状柱顶部与所述透光板之间还具有粘胶层。
  6. 如权利要求1所述的封装结构，其特征在于，所述第二功能芯片为信号处理芯片；所述第二功能芯片的数量大于或等于1。
  7. 如权利要求6所述的封装结构，其特征在于，所述封装结构还包括： 位于所述第二功能面上的金属凸块，通过所述金属凸块和所述基板第二面暴露出的线路层的部分电连接所述第二功能面与所述线路层。
  8. 如权利要求1所述的封装结构，其特征在于，所述焊接凸起分布在所述第二功能芯片周围。
  9. 如权利要求1所述的封装结构，其特征在于，所述第二焊接凸起顶部与所述基板第二面之间的距离大于所述第二功能芯片第二背面与所述基板第二面之间的距离。
  10. 如权利要求1所述的封装结构，其特征在于，所述封装结构还包括：位于所述第一背面与所述第一面之间的粘附层。
  11. 如权利要求1所述的封装结构，其特征在于，所述封装结构还包括：位于所述基板部分第二面上的绝缘层，且所述焊接凸起贯穿所述绝缘层；位于所述基板第一面上的防焊层，且所述导线贯穿所述防焊层。
  12. 如权利要求1所述的封装结构，其特征在于，所述封装结构还包括：位于所述基板第二面且覆盖第二功能芯片侧壁的塑封层。
  13. 一种封装方法，其特征在于，包括：
    提供若干个第一功能芯片以及第二功能芯片，所述第一功能芯片具有相对的第一功能面和第一背面，所述第一功能面上具有焊盘，所述第二功能芯片具有相对的第二功能面和第二背面；
    提供基板，所述基板具有若干功能区和位于相邻功能区之间的切割道区域，所述基板具有相对的第一面和第二面，且所述基板内具有线路层；
    将所述第一功能芯片设置在所述基板功能区第一面上，所述第一背面与所述第一面固定接合；
    形成电连接所述焊盘以及线路层的导线；
    将所述第二功能芯片倒装设置在所述基板功能区第二面上，所述第二功能面与所述第二面相对，且所述第二功能面通过所述基板功能区第二面暴露出的线路层的部分与所述线路层电连接；
    在所述基板功能区第二面上形成焊接凸起，所述焊接凸起通过所述基板功能区第二面暴露出的线路层的部分与所述线路层电连接；
    沿所述切割道区域切割所述基板，形成若干单颗封装结构。
  14. 如权利要求13所述的封装方法，其特征在于，所述第一功能芯片为影像传感芯片；所述第一功能面上还具有影像感应区，且所述焊盘环绕所述影像感应区；所述封装方法还包括：
    在所述基板功能区第一面上形成中空环状柱，且当所述第一功能芯片设置在所述基板功能区第一面上后，所述中空环状柱包围所述第一功能芯片；
    在所述中空环状柱顶部设置透光板，且所述透光板、中空环状柱以及基板围成空腔，且所述第一功能芯片位于所述空腔内。
  15. 如权利要求14所述的封装方法，其特征在于，在将所述第一功能芯片设置在所述基板功能区第一面上之前，形成所述中空环状柱。
  16. 如权利要求15所述的封装方法，其特征在于，采用涂布工艺以及光刻工艺，形成所述中空环状柱；或者，采用树脂印刷工艺，形成所述中空环状柱。
  17. 如权利要求13所述的封装方法，其特征在于，采用打线工艺，形成所述导线。
  18. 如权利要求13所述的封装方法，其特征在于，在将所述第二功能芯片倒装设置在所述基板功能区第二面上之前，还包括步骤：在所述第二功能芯片第二功能面上或者所述基板功能区第二面上形成金属凸块；采用焊接键合工艺，通过所述金属凸块和所述基板功能区第二面暴露出的线路层的部分实现所述第二功能面与所述线路层电连接。
  19. 如权利要求13所述的封装方法，其特征在于，在切割所述基板之前，还包括步骤：在所述基板功能区部分第二面上形成塑封层，且所述塑封层覆盖所述第二功能芯片侧壁。
  20. 如权利要求19所述的封装方法，其特征在于，在形成所述焊接凸起之前，形成所述塑封层；或者，在形成所述焊接凸起之后，形成所述塑封层。
PCT/CN2017/102607 2016-09-26 2017-09-21 封装结构以及封装方法 WO2018054315A1 (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201621080212.6U CN206259337U (zh) 2016-09-26 2016-09-26 封装结构
CN201610850385.X 2016-09-26
CN201610850385.XA CN106298699A (zh) 2016-09-26 2016-09-26 封装结构以及封装方法
CN201621080212.6 2016-09-26

Publications (1)

Publication Number Publication Date
WO2018054315A1 true WO2018054315A1 (zh) 2018-03-29

Family

ID=61690185

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/102607 WO2018054315A1 (zh) 2016-09-26 2017-09-21 封装结构以及封装方法

Country Status (1)

Country Link
WO (1) WO2018054315A1 (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108831861A (zh) * 2018-08-09 2018-11-16 苏州晶方半导体科技股份有限公司 堆叠式芯片封装方法及封装结构
CN108831860A (zh) * 2018-08-09 2018-11-16 苏州晶方半导体科技股份有限公司 堆叠式芯片封装方法及封装结构
CN110299332A (zh) * 2019-07-19 2019-10-01 安徽安努奇科技有限公司 芯片封装结构
CN111370431A (zh) * 2018-12-26 2020-07-03 中芯集成电路（宁波）有限公司 光电传感集成系统的封装方法
CN111977609A (zh) * 2020-08-28 2020-11-24 青岛歌尔智能传感器有限公司 传感器封装结构及传感器封装工艺
CN114649305A (zh) * 2022-03-17 2022-06-21 长电科技管理有限公司 半导体封装结构及其形成方法、导电治具及电镀设备
CN115148724A (zh) * 2022-07-12 2022-10-04 奇异摩尔(上海)集成电路设计有限公司 集成mim电容的扇出型系统封装及方法
CN117238781A (zh) * 2023-11-16 2023-12-15 江苏芯德半导体科技有限公司 一种晶圆级超薄四边无引脚芯片封装方法及芯片封装结构

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1463141A (zh) * 2002-05-28 2003-12-24 三星电机株式会社 图像传感器组件及其制造方法
CN1514493A (zh) * 2003-08-19 2004-07-21 ӡ�����Ƽ��ɷ����޹�˾ 小型影像感测处理模块的结构及其制造方法
CN101165894A (zh) * 2006-10-19 2008-04-23 三星Techwin株式会社 用于图像传感器的芯片封装及其制造方法
CN103325799A (zh) * 2012-03-20 2013-09-25 南茂科技股份有限公司 芯片堆迭结构及其制造方法
CN103681702A (zh) * 2012-09-07 2014-03-26 台湾积体电路制造股份有限公司 用于传感器模块的方法和装置
CN105047621A (zh) * 2015-06-26 2015-11-11 华天科技（西安）有限公司 一种传感芯片封装结构及其制备方法
CN105448944A (zh) * 2015-12-29 2016-03-30 苏州晶方半导体科技股份有限公司 影像传感芯片封装结构及其封装方法
CN106298699A (zh) * 2016-09-26 2017-01-04 苏州晶方半导体科技股份有限公司 封装结构以及封装方法
CN206259337U (zh) * 2016-09-26 2017-06-16 苏州晶方半导体科技股份有限公司 封装结构

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1463141A (zh) * 2002-05-28 2003-12-24 三星电机株式会社 图像传感器组件及其制造方法
CN1514493A (zh) * 2003-08-19 2004-07-21 ӡ�����Ƽ��ɷ����޹�˾ 小型影像感测处理模块的结构及其制造方法
CN101165894A (zh) * 2006-10-19 2008-04-23 三星Techwin株式会社 用于图像传感器的芯片封装及其制造方法
CN103325799A (zh) * 2012-03-20 2013-09-25 南茂科技股份有限公司 芯片堆迭结构及其制造方法
CN103681702A (zh) * 2012-09-07 2014-03-26 台湾积体电路制造股份有限公司 用于传感器模块的方法和装置
CN105047621A (zh) * 2015-06-26 2015-11-11 华天科技（西安）有限公司 一种传感芯片封装结构及其制备方法
CN105448944A (zh) * 2015-12-29 2016-03-30 苏州晶方半导体科技股份有限公司 影像传感芯片封装结构及其封装方法
CN106298699A (zh) * 2016-09-26 2017-01-04 苏州晶方半导体科技股份有限公司 封装结构以及封装方法
CN206259337U (zh) * 2016-09-26 2017-06-16 苏州晶方半导体科技股份有限公司 封装结构

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108831861A (zh) * 2018-08-09 2018-11-16 苏州晶方半导体科技股份有限公司 堆叠式芯片封装方法及封装结构
CN108831860A (zh) * 2018-08-09 2018-11-16 苏州晶方半导体科技股份有限公司 堆叠式芯片封装方法及封装结构
CN111370431A (zh) * 2018-12-26 2020-07-03 中芯集成电路（宁波）有限公司 光电传感集成系统的封装方法
CN111370431B (zh) * 2018-12-26 2023-04-18 中芯集成电路（宁波）有限公司 光电传感集成系统的封装方法
CN110299332A (zh) * 2019-07-19 2019-10-01 安徽安努奇科技有限公司 芯片封装结构
CN111977609A (zh) * 2020-08-28 2020-11-24 青岛歌尔智能传感器有限公司 传感器封装结构及传感器封装工艺
CN114649305A (zh) * 2022-03-17 2022-06-21 长电科技管理有限公司 半导体封装结构及其形成方法、导电治具及电镀设备
CN114649305B (zh) * 2022-03-17 2023-03-07 长电科技管理有限公司 半导体封装结构及其形成方法、导电治具及电镀设备
CN115148724A (zh) * 2022-07-12 2022-10-04 奇异摩尔(上海)集成电路设计有限公司 集成mim电容的扇出型系统封装及方法
CN117238781A (zh) * 2023-11-16 2023-12-15 江苏芯德半导体科技有限公司 一种晶圆级超薄四边无引脚芯片封装方法及芯片封装结构
CN117238781B (zh) * 2023-11-16 2024-02-23 江苏芯德半导体科技有限公司 一种晶圆级超薄四边无引脚芯片封装方法及芯片封装结构

Similar Documents

Publication Publication Date Title
WO2018054315A1 (zh) 封装结构以及封装方法
TWI700753B (zh) 晶片封裝體及其製造方法
US10304890B2 (en) Electronic device package and fabricating method thereof
TWI698968B (zh) 封裝結構以及封裝方法
US7619315B2 (en) Stack type semiconductor chip package having different type of chips and fabrication method thereof
US8766408B2 (en) Semiconductor device and manufacturing method thereof
JP2011101044A (ja) スタックパッケージ及びその製造方法
CN105977225B (zh) 封装结构以及封装方法
JP2009044110A (ja) 半導体装置及びその製造方法
US11502059B2 (en) Semiconductor package including a thermal pillar and heat transfer film
US20220392846A1 (en) Semiconductor package
US9825006B2 (en) Electronic component device and manufacturing method thereof
US9613894B2 (en) Electronic package
TW201603215A (zh) 封裝結構及其製法
TWI740305B (zh) 電子封裝件及其製法
CN106298699A (zh) 封装结构以及封装方法
WO2017114353A1 (zh) 影像传感芯片封装结构及其封装方法
KR20220030005A (ko) 반도체 패키지 및 반도체 패키지의 제조 방법
JP2003243605A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
TWI559464B (zh) 封裝模組及其基板結構
KR20210053392A (ko) 센서 소자
CN206259337U (zh) 封装结构
TWI712147B (zh) 電子封裝件及其製法
CN210245481U (zh) 一种影像传感芯片封装结构
CN206098376U (zh) 封装结构

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17852383

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17852383

Country of ref document: EP

Kind code of ref document: A1