WO2017114353A1 - 影像传感芯片封装结构及其封装方法 - Google Patents

影像传感芯片封装结构及其封装方法 Download PDF

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Publication number
WO2017114353A1
WO2017114353A1 PCT/CN2016/112080 CN2016112080W WO2017114353A1 WO 2017114353 A1 WO2017114353 A1 WO 2017114353A1 CN 2016112080 W CN2016112080 W CN 2016112080W WO 2017114353 A1 WO2017114353 A1 WO 2017114353A1
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Prior art keywords
image sensing
chip
sensing chip
substrate
electrically connected
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PCT/CN2016/112080
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English (en)
French (fr)
Inventor
王之奇
沈志杰
陈佳炜
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苏州晶方半导体科技股份有限公司
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Priority claimed from CN201521117238.9U external-priority patent/CN205452287U/zh
Priority claimed from CN201511008692.5A external-priority patent/CN105448944B/zh
Application filed by 苏州晶方半导体科技股份有限公司 filed Critical 苏州晶方半导体科技股份有限公司
Priority to US15/767,623 priority Critical patent/US20180308890A1/en
Priority to KR1020187011950A priority patent/KR20180061293A/ko
Priority to JP2018540203A priority patent/JP2018531525A/ja
Publication of WO2017114353A1 publication Critical patent/WO2017114353A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/1469—Assemblies, i.e. hybrid integration

Definitions

  • the present invention relates to semiconductor chip packaging technology, and more particularly to image sensing chip packaging technology.
  • the image sensor chip is used as a function chip for image acquisition and is commonly used in cameras for electronic products. Thanks to the continued growth of the Camera Phone, the future demand for the image sensor chip market will continue to rise. In addition, the popularity of network real-time communication services such as Skype, the rise of the security surveillance market, and the rapid growth of global automotive electronics have also created considerable application scale for image sensor chips. At the same time, the packaging technology of image sensor chips has also made great progress.
  • POP package-on-package
  • the invention integrates the package packaging technology into the image sensor chip package, provides a new image sensor chip package structure and packaging method, reduces the package structure size of the image sensor chip, and improves the integration degree of the image sensor chip. .
  • the invention provides an image sensor chip package structure, comprising an image sensor chip and a control chip for controlling the image sensor chip, the image sensor chip package structure further comprising: a substrate having a first opposite to each other a surface and a second surface; the image sensing chip is electrically connected to the substrate and located at a first surface of the substrate; the control chip is electrically connected to the substrate and located at a second surface of the substrate.
  • the image sensing chip has a first surface and a second surface opposite to each other, and the first surface of the image sensing chip is provided with a photosensitive area and a pad outside the photosensitive area, and the image sensing
  • the second side of the chip has solder balls electrically connected to the pads, and the image sensing chip is electrically connected to the substrate through the solder balls.
  • the first surface of the image sensing chip is covered with a protective cover, and a sealed cavity is formed between the protective cover and the image sensing chip, and the photosensitive region is located in the cavity.
  • the protective cover is an anti-reflective glass.
  • the second surface of the substrate is provided with a solder bump for electrically connecting with an external circuit, the height of the solder bump being greater than the height of the control chip, when the solder bump and the external circuit When electrically connected, there is a gap between the control chip and the external circuit.
  • control chip is flipped on the substrate.
  • control chip and the substrate are electrically connected by a bonding wire.
  • the present invention also provides a method for packaging an image sensing chip, comprising: providing an image sensing chip and a control chip for controlling the image sensing chip; further comprising: providing a substrate, the substrate having a first opposite to each other a surface and a second surface; electrically connecting the control chip to the second surface of the substrate; electrically connecting the image sensing chip to the first surface of the substrate.
  • the method before electrically connecting the image sensing chip to the substrate, includes: providing a wafer having an array of image sensing chips thereon, the image sensing chip having a first side opposite to each other And a second surface, the first surface of the image sensing chip is provided with a photosensitive area and a solder pad located outside the photosensitive area; and a protective cover is provided in the same size as the wafer, and one side of the protective cover is disposed An array of supporting units, each supporting unit corresponding to one image sensing chip; pressing the wafer and the protective cover to form a seal between each image sensing chip and the protective cover
  • the cavity is located in the cavity; a plurality of through silicon vias are formed on the second side of the image sensing chip by a through silicon via process, and each through hole corresponds to a pad, the silicon a bottom of the via hole exposing the solder pad; forming a metal wiring layer in the through silicon via, the metal wiring layer being electrically connected to the pad; forming a solder ball on a second side of
  • the protective cover is an anti-reflective glass.
  • control chip is electrically connected to the substrate using a flip chip process.
  • control chip is electrically connected to the substrate using a wire bonding process.
  • a solder bump for electrically connecting to an external circuit is disposed on a second surface of the substrate, the height of the solder bump being greater than a height of the control chip, when the solder bump is external to the solder When the circuit is electrically connected, there is a gap between the control chip and the external circuit.
  • a new image sensor chip package structure and a packaging method are provided, which reduces the package structure size of the image sensor chip and improves image transmission.
  • the integration of the chip is provided.
  • FIG. 1 is a schematic diagram of a package structure of an image sensing chip according to an embodiment of the invention.
  • FIGS. 2(a) to 2(g) are schematic diagrams showing a packaging process of an image sensing chip according to an embodiment of the invention Figure.
  • FIG. 1 is a schematic diagram of a package structure of an image sensing chip according to an embodiment of the invention.
  • the image sensor chip package structure includes an image sensor chip 10, a control chip 20, and a substrate 30.
  • the substrate 30 has a first surface 31 and a second surface 32 opposite to each other.
  • the image sensor chip 10 is electrically connected to the substrate 30 and located on the substrate 30.
  • the first surface 31; the control chip 20 is electrically connected to the substrate 30 and located on the second surface 31 of the substrate 30; the image sensing chip 10 and the control chip 20 are opposed to each other, thus forming a laminated package structure of the image sensing chip.
  • the stacked package structure of the above image sensing chip has high integration and a small package size.
  • the image sensing chip 10 is a semiconductor chip having at least an image sensing unit.
  • the image sensing unit can be a CMOS sensor or a CCD sensor.
  • the image sensor chip 10 may further have an associated circuit connected to the image sensing unit.
  • the control chip 20 is used to control the image sensing chip 10.
  • the present invention does not limit the specific function of the control chip 20, as long as the electrical signal transmission between the control chip 20 and the image sensing chip 10 satisfies the "control" of the present invention.
  • an electrical interconnection structure 34 is disposed on the substrate 30, and is formed between the image sensing chip 10 and the control chip 20 through the electrical interconnection structure 34. The vertical circuit is turned on.
  • the image sensor chip 10 in this embodiment is a semiconductor chip having a CMOS sensor.
  • the image sensor chip 10 has a first surface 101 and a second surface 102 opposite to each other.
  • the first surface 101 is provided with a photosensitive region 103 and a pad 104 located outside the photosensitive region 103.
  • the pad 104 is electrically connected to the photosensitive region 103 ( Not shown in Figure 1).
  • the image sensing chip 10 is electrically connected to the substrate 30 and is located on the first surface 31 of the substrate 30. Specifically, a solder ball 105 electrically connected to the pad 104 is formed on the second surface 102 of the image sensor chip 10, and the image sensor chip 10 is electrically connected to the substrate 30 by soldering the solder ball 105 to the substrate 30.
  • the first cover 101 of the image sensor chip 10 is covered with a protective cover 106, and a seal is formed between the protective cover 106 and the image sensor chip 10.
  • the cavity 107 and the photosensitive region 103 are located in the cavity 107 to prevent the contaminated photosensitive region 103 from being dusted or the like.
  • a support unit 108 is formed on the surface of the protective cover 106. The support unit 108 is located between the protective cover 106 and the image sensing chip 10, and the three surrounds the cavity 107.
  • the protective cover 106 is made of a light transmissive material.
  • the protective cover 106 is an anti-reflective glass that has better light transmission properties and facilitates light projection to the photosensitive region 103.
  • the material of the support unit 108 is a photoresist, which is formed on one side of the protective cover 106 by an exposure and development process.
  • Control chip 20 is electrically coupled to substrate 30 and is located on second surface 32 of substrate 30.
  • the control chip 20 has a plurality of electrical connection pads 21 on which the solder bumps 22 are formed.
  • the solder bumps 22 may be made of gold, tin-lead or other lead-free metal.
  • the control chip 20 is electrically connected to the substrate 30 by soldering the bumps 22 to form an electrical connection between the electrical connection pads 21 and the substrate 30 by using a flip chip process.
  • control chip 20 and the substrate 30 are electrically connected by wire bonding, that is, the two are electrically connected by a bonding wire.
  • the material of the wire can be copper, tungsten, aluminum, gold, Silver and other metal materials.
  • the control chip 20 and the bonding wires are molded to form a plastic sealing structure.
  • the substrate 30 is made of a plastic material.
  • an underfill process may be introduced during the process of electrically connecting the image sensor chip 10 and the control chip 20 to the substrate 30. As shown in FIG. 1, an underfill 23 is wrapped at a gap where the control chip 10 is electrically connected to the substrate 30 and around the control chip 20.
  • a solder bump 33 for electrically connecting to an external circuit is disposed on the second surface 32 of the substrate 30.
  • the height of the solder bumps 33 is greater than the height of the control chip 20, and the height of the solder bumps 33 is such that there is a gap between the control chip 20 and the external circuit when the solder bumps 33 are electrically connected to the external circuits.
  • An electrical interconnection structure 34 is disposed on the substrate 30, and electrical conduction is established between the image sensing chip 10, the control chip 20, and the solder bumps 33 through the electrical interconnection structure 34.
  • FIGS. 2(a) to 2(f) are schematic diagrams showing a packaging process of an image sensing chip according to an embodiment of the present invention.
  • an image sensing chip 10 and a control chip 20 for controlling the image sensing chip 10 are provided; and a substrate 30 having a first surface 31 and a second surface 32 opposite to each other is provided.
  • the control chip 20 is electrically connected to the second surface 32 of the substrate 30.
  • the control chip 20 has a plurality of electrical connection pads 21, and solder bumps 22 are formed on the electrical connection pads 21.
  • the material of the solder bumps 22 may be gold, tin-lead or other lead-free metal materials, and the flip chip process is adopted.
  • the electrical connection between the electrical connection pads 21 and the substrate 30 is achieved by solder bumps 22 to electrically connect the control chip 20 to the substrate 30.
  • the underfill film 23 is wrapped at the gap where the control chip 10 is electrically connected to the substrate 30 and around the control chip 20 by an underfill process.
  • control chip 20 and the substrate 30 are implemented by wire bonding.
  • the electrical connection that is, the two are electrically connected by a bonding wire
  • the material of the bonding wire may be a metal material such as copper, tungsten, aluminum, gold or silver.
  • the control chip 20 and the bonding wires are molded to form a plastic sealing structure.
  • a ball placement process is employed.
  • the second surface 32 of the substrate 30 is provided with solder bumps 33 for electrical connection with an external circuit.
  • the height of the solder bumps 33 is greater than the height of the control chip 20, and the height of the solder bumps 33 is satisfied when the solder bumps 33 and the external circuit are electrically When connected, there is a gap between the control chip 20 and the external circuit.
  • the image sensor chip 10 is covered with a protective cover 106.
  • the image sensing chip 10 in this embodiment is a semiconductor chip having a CMOS sensor.
  • the image sensing chip 10 has a first surface 101 and a second surface 102 opposite to each other.
  • the first surface 101 is provided with a photosensitive region 103 and is located at the photosensitive surface.
  • the pad 104 outside the region 103, the pad 104 is electrically connected to the photosensitive region 103.
  • one side of the protective cover is formed with an array of supporting units 108, each supporting unit 108 corresponding to an image sensing chip 10;
  • the protective cover 106 is pressed into the first surface 101 of the image sensor chip 10, and the support unit 108 is located between the protective cover 106 and the image sensor chip 10. Thereby, a sealed cavity 107 is formed between the protective cover 106 and each of the image sensing chips 10, and the photosensitive region 103 is located in the cavity 107 to prevent the contaminated photosensitive region 103 from being dusted or the like.
  • the protective cover 106 is made of a light transmissive material.
  • the protective cover 106 is an anti-reflective glass, which has better light transmittance and facilitates light projection to the photosensitive region 103.
  • the material of the support unit 108 may be a photoresist.
  • the second surface 102 of the image sensing chip 10 is formed with the pad 104 .
  • Electrically connected solder balls 105 Specifically, a plurality of through silicon vias are formed on the second side 102 of the image sensing chip 10 by using a through silicon via process, and each through silicon via corresponds to one of the pads 104. The bottom of the through silicon via exposes the pad 104.
  • a metal wiring layer 100 is formed in the through silicon via, and the metal wiring layer 100 is electrically connected to the pad 104. The metal wiring layer 100 extends to the second side 102 of the image sensing chip 10.
  • Solder balls 105 are formed on the second surface 102 of the image sensor chip 10, and the solder balls 105 are electrically connected to the metal wiring layer 100.
  • the wafer and the protective cover are cut to separate the plurality of image sensor chips 10 connected to each other.
  • the image sensor chip 10 is electrically connected to the first surface 31 of the substrate 30 , and the image sensor chip 10 is electrically connected to the substrate 30 by soldering the solder ball 105 to the substrate 30 .
  • the image sensor chip 10 and the control chip 20 are opposed to each other.
  • a new image sensing chip package structure and a packaging method are provided by incorporating a package package technology into an image sensor chip package, thereby reducing the package structure size of the image sensor chip and improving image transmission.
  • the integration of the chip is provided by incorporating a package package technology into an image sensor chip package, thereby reducing the package structure size of the image sensor chip and improving image transmission.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

一种影像传感芯片封装结构及其封装方法，影像传感芯片封装结构具有影像传感芯片以及用于控制影像传感芯片的控制芯片，影像传感芯片封装结构还包括：基板，具有彼此相对的第一表面以及第二表面；影像传感芯片电连接至基板，且位于基板的第一表面；控制芯片电连接至基板，且位于基板的第二表面。通过将层叠封装技术应用于影像传感芯片封装中，降低了影像传感芯片的封装结构尺寸，提高了影像传感芯片的集成度。

Description

影像传感芯片封装结构及其封装方法
本申请要求于2015年12月29日提交中国专利局、申请号为201511008692.5、发明名称为“影像传感芯片封装结构及其封装方法”，以及于2015年12月29日提交中国专利局、申请号为201521117238.9、发明名称为“影像传感芯片封装结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体芯片封装技术，尤其涉及影像传感芯片封装技术。
背景技术
影像传感芯片作为影像获取的功能芯片，常用于电子产品的摄像头中。受益于照相手机(Camera Phone)的持续蓬勃发展，影像传感芯片市场未来的需求将不断攀升。此外，Skype等网络实时通讯服务的流行、安全监控市场的兴起，以及全球汽车电子的快速成长，亦为影像传感芯片创造可观的应用规模。与此同时，影像传感芯片的封装技术也有着长足发展。
层叠封装技术(POP，package-on-package)是针对移动设备如智能手机、平板电脑等的IC封装而发展起来的可用于系统集成的非常受欢迎的三维叠加技术之一。
如何将层叠封装技术融入到影像传感芯片的封装领域成为本领域技术人员噬待解决的技术问题。
发明内容
本发明通过将层叠封装技术融入影像传感芯片封装中，提供一种新的影像传感芯片封装结构以及封装方法，降低了影像传感芯片的封装结构尺寸，提高了影像传感芯片的集成度。
本发明提供一种影像传感芯片封装结构，具有影像传感芯片以及用于控制所述影像传感芯片的控制芯片，所述影像传感芯片封装结构还包括：基板，具有彼此相对的第一表面以及第二表面；所述影像传感芯片电连接至所述基板，且位于所述基板的第一表面；所述控制芯片电连接至所述基板，且位于所述基板的第二表面。
可选地，所述影像传感芯片具有彼此相对的第一面以及第二面，所述影像传感芯片的第一面设置有感光区以及位于感光区外的焊垫，所述影像传感芯片的第二面具有与所述焊垫电连接的焊球，所述影像传感芯片通过所述焊球与所述基板电连接。
可选地，所述影像传感芯片的第一面上覆盖有保护盖板，所述保护盖板与所述影像传感芯片之间形成密封的腔体，所述感光区位于所述腔体内。
可选地，所述保护盖板为减反射玻璃。
可选地，所述基板的第二表面设置有用于与外部电路电连接的焊接凸块，所述焊接凸块的高度大于所述控制芯片的高度，当所述焊接凸块与所述外部电路电连接时，所述控制芯片与所述外部电路之间具有间距。
可选地，所述控制芯片倒装于所述基板上。
可选地，所述控制芯片与所述基板通过焊线实现电连接。
本发明还提供一种影像传感芯片的封装方法，包括：提供影像传感芯片以及用于控制所述影像传感芯片的控制芯片；还包括：提供基板，所述基板具有彼此相对的第一表面以及第二表面；将所述控制芯片电连接至所述基板的第二表面；将所述影像传感芯片电连接至所述基板的第一表面。
可选地，将影像传感芯片电连接至所述基板之前包括：提供晶圆，所述晶圆上具有阵列排布的影像传感芯片，所述影像传感芯片具有彼此相对的第一面以及第二面，所述影像传感芯片的第一面设置有感光区以及位于感光区外的焊垫；提供与所述晶圆尺寸一致的保护盖板，所述保护盖板的一面上设置有阵列排布的支撑单元，每一支撑单元对应一个影像传感芯片；将所述晶圆与所述保护盖板对位压合，在每一影像传感芯片与保护盖板之间形成密封的腔体，所述感光区位于所述腔体内；采用硅通孔工艺在所述影像传感芯片的第二面形成多个硅通孔，每一硅通孔对应一个焊垫，所述硅通孔的底部暴露所述焊垫；在所述硅通孔中形成金属布线层，所述金属布线层与所述焊垫电连接；在所述影像传感芯片的第二面形成焊球，所述焊球与所述金属布线层电连接；切割所述影像传感芯片以及所述保护盖板，使彼此相连的多个影像传感芯片分离。
可选地，所述保护盖板为减反射玻璃。
可选地，采用倒装工艺将所述控制芯片电连接至所述基板。
可选地，采用引线键合工艺将所述控制芯片电连接至所述基板。
可选地，在所述基板的第二表面设置用于与外部电路电连接的焊接凸块，所述焊接凸块的高度大于所述控制芯片的高度，当所述焊接凸块与所述外部电路电连接时，所述控制芯片与所述外部电路之间具有间距。
本发明实施例，通过将层叠封装技术应用于影像传感芯片封装中，提供了一种新的影像传感芯片封装结构以及封装方法，降低了影像传感芯片的封装结构尺寸，提高了影像传感芯片的集成度。
附图说明
图1为本发明一实施例的影像传感芯片封装结构示意图。
图2(a)-图2(g)为本发明一实施例影像传感芯片的封装流程示意 图。
具体实施方式
以下将结合附图对本发明的具体实施方式进行详细描述。但这些实施方式并不限制本发明，本领域的普通技术人员根据这些实施方式所做出的结构、方法、或功能上的变换均包含在本发明的保护范围内。
需要说明的是，提供这些附图的目的是为了有助于理解本发明的实施例，而不应解释为对本发明的不当的限制。为了更清楚起见，图中所示尺寸并未按比例绘制，可能会做放大、缩小或其他改变。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
请参考图1，为本发明一实施例的影像传感芯片封装结构示意图。影像传感芯片封装结构包括影像传感芯片10、控制芯片20以及基板30；基板30具有彼此相对的第一表面31以及第二表面32；影像传感芯片10电连接至基板30且位于基板30的第一表面31；控制芯片20电连接至基板30且位于基板30的第二表面31；影像传感芯片10与控制芯片20彼此相对，如此，形成了影像传感芯片的层叠封装结构。
上述影像传感芯片的层叠封装结构具有较高的集成度以及较小的封装尺寸。
影像传感芯片10为至少具有影像传感单元的半导体芯片。影像传感单元可以是CMOS传感器或者CCD传感器。影像传感芯片10中还可以具有与影像传感单元相连接的关联电路。
控制芯片20用于控制影像传感芯片10。本发明不限定控制芯片20的具体功能，只要是控制芯片20与影像传感芯片10之间建立电信号传输即满足本发明所说的“控制”。在一种实现方式中，在基板30上设置有电互联结构34，通过电互联结构34在影像传感芯片10和控制芯片20之间建 立电路导通。
本实施例中的影像传感芯片10为具有CMOS传感器的半导体芯片。影像传感芯片10具有彼此相对的第一面101以及第二面102，在第一面101设置有感光区103以及位于感光区103外的焊垫104，焊垫104与感光区103电连接(图1中未绘示)。
影像传感芯片10与基板30电连接且位于基板30的第一表面31。具体的，在影像传感芯片10的第二面102形成与焊垫104电连接的焊球105，通过焊球105与基板30焊接实现影像传感芯片10与基板30电连接。
为了保护影像传感芯片10且避免粉尘等污染感光区103，在影像传感芯片10的第一面101上覆盖保护盖板106，在保护盖板106与影像传感芯片10之间形成密封的腔体107，感光区103位于腔体107内，杜绝粉尘等污染感光区103。本实施例中，在保护盖板106的表面形成有支撑单元108，支撑单元108位于保护盖板106与影像传感芯片10之间，三者包围形成腔体107。
保护盖板106的材质为透光材料。在一种实现方式中，保护盖板106为减反射玻璃，其具有较好的透光性方便光线投射到感光区103。
在一种实现方式中，支撑单元108的材质为感光胶，采用曝光显影工艺形成于保护盖板106的一面上。
控制芯片20与基板30电连接且位于基板30的第二表面32。控制芯片20上具有多个电连接垫21，在电连接垫21上形成焊接凸点22。焊接凸点22的材质可以为金、锡铅或者其他无铅金属材质。采用倒装工艺通过焊接凸点22在电连接垫21与基板30之间建立电连接实现控制芯片20与基板30电连接。
另一实施例中，控制芯片20与基板30采用引线键合的方式实现电连接，即两者通过焊线实现电连接。焊线的材质可以是铜、钨、铝、金、 银等金属材质。更进一步，为了保护控制芯片20以及焊线，对控制芯片20以及焊线进行塑封形成塑封结构。
在一种实现方式中，基板30的材质为塑胶材质。为了消除应力影响，可以在影像传感芯片10以及控制芯片20与基板30电连接的过程中引入底部填充工艺。如图1所示，在控制芯片10与基板30电连接的间隙处以及控制芯片20的周围包裹有底部填充胶23。
为了实现影像传感芯片封装结构与其他外部电路电连接，于基板30的第二表面32设置有用于与外部电路电连接的焊接凸块33。焊接凸块33的高度大于控制芯片20的高度，焊接凸块33的高度满足当焊接凸块33与外部电路电连接时，控制芯片20与外部电路之间具有间距。
在基板30上设置有电互联结构34，通过电互联结构34在影像传感芯片10、控制芯片20以及焊接凸块33之间建立电路导通。
请参考图2(a)-图2(f)为本发明一实施例影像传感芯片的封装流程示意图。
请参考图2(a)，提供影像传感芯片10以及用于控制影像传感芯片10的控制芯片20；以及提供基板30，基板30具有彼此相对的第一表面31以及第二表面32。
请参考图2(b)，将控制芯片20电连接至基板30的第二表面32。具体的，控制芯片20上具有多个电连接垫21，在电连接垫21上形成焊接凸点22，焊接凸点22的材质可以为金、锡铅或者其他无铅金属材质，采用倒装工艺通过焊接凸点22在电连接垫21与基板30之间建立电连接实现控制芯片20与基板30电连接。
请参考图2(c)，采用底部填充工艺在控制芯片10与基板30电连接的间隙处以及控制芯片20的周围包裹底部填充胶23。
于另一实施例中，控制芯片20与基板30采用引线键合的方式实现 电连接，即两者通过焊线实现电连接，焊线的材质可以是铜、钨、铝、金、银等金属材质。更进一步，为了保护控制芯片20以及焊线，对控制芯片20以及焊线进行塑封形成塑封结构。
请参考图2(d)，在将所述控制芯片电连接至所述基板的第二表面之后且将所述影像传感芯片电连接至所述基板的第一表面之前，采用植球工艺在基板30的第二表面32设置用于与外部电路电连接的焊接凸块33，焊接凸块33的高度大于控制芯片20的高度，焊接凸块33的高度满足当焊接凸块33与外部电路电连接时，控制芯片20与外部电路之间具有间距。
请参考图2(e)，在影像传感芯片10上覆盖保护盖板106。
本实施例中的影像传感芯片10为具有CMOS传感器的半导体芯片，影像传感芯片10具有彼此相对的第一面101以及第二面102，在第一面101设置有感光区103以及位于感光区103外的焊垫104，焊垫104与感光区103电连接。
具体的，包括：
提供晶圆，晶圆上具有阵列排布的影像传感芯片10；
提供与晶圆尺寸一致的保护盖板106，保护盖板的一面上形成有阵列排布的支撑单元108，每一支撑单元108对应一个影像传感芯片10；
将保护盖板106对位压合至影像传感芯片10的第一面101上，支撑单元108位于保护盖板106与影像传感芯片10之间。从而，在保护盖板106与每一影像传感芯片10之间形成密封的腔体107，感光区103位于腔体107内，杜绝粉尘等污染感光区103。
保护盖板106的材质为透光材料。在一种实现方式中，保护盖板106为减反射玻璃，具有较好的透光性方便光线投射到感光区103。
支撑单元108的材质可以为感光胶。
请参考图2(f)，在影像传感芯片10的第二面102形成与焊垫104 电连接的焊球105。具体的，采用硅通孔工艺在影像传感芯片10的第二面102形成多个硅通孔，每一硅通孔对应一个焊垫104。所述硅通孔的底部暴露焊垫104。在所述硅通孔中形成金属布线层100，金属布线层100与焊垫104电连接。金属布线层100延伸至影像传感芯片10的第二面102。在影像传感芯片10的第二面102形成焊球105，焊球105与金属布线层100电连接。
切割所述晶圆以及所述保护盖板，使彼此相连的多个影像传感芯片10分离。
请参考图2(g)，将影像传感芯片10电连接至基板30的第一表面31，通过焊球105与基板30焊接实现影像传感芯片10与基板30电连接。且影像传感芯片10与控制芯片20彼此相对。
在本发明实施例中，通过将层叠封装技术融入影像传感芯片封装中，提供一种新的影像传感芯片封装结构以及封装方法，降低了影像传感芯片的封装结构尺寸，提高了影像传感芯片的集成度。
应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施方式中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。
上文所列出的一系列的详细说明仅仅是针对本发明的可行性实施方式的具体说明，它们并非用以限制本发明的保护范围，凡未脱离本发明技艺精神所作的等效实施方式或变更均应包含在本发明的保护范围之内。

Claims (13)

  1. 一种影像传感芯片封装结构，具有影像传感芯片以及用于控制所述影像传感芯片的控制芯片，其特征在于，所述影像传感芯片封装结构还包括：基板，具有彼此相对的第一表面以及第二表面，
    其中，所述影像传感芯片电连接至所述基板，且位于所述基板的第一表面；以及所述控制芯片电连接至所述基板，且位于所述基板的第二表面。
  2. 根据权利要求1所述的影像传感芯片封装结构，其特征在于，所述影像传感芯片具有彼此相对的第一面以及第二面，所述影像传感芯片的第一面设置有感光区以及位于感光区外的焊垫，所述影像传感芯片的第二面具有与所述焊垫电连接的焊球，所述影像传感芯片通过所述焊球与所述基板电连接。
  3. 根据权利要求2所述的影像传感芯片封装结构，其特征在于，所述影像传感芯片的第一面上覆盖有保护盖板，所述保护盖板与所述影像传感芯片之间形成密封的腔体，所述感光区位于所述腔体内。
  4. 根据权利要求3所述的影像传感芯片封装结构，其特征在于，所述保护盖板为减反射玻璃。
  5. 根据权利要求1所述的影像传感芯片封装结构，其特征在于，所述基板的第二表面设置有用于与外部电路电连接的焊接凸块，所述焊接凸块的高度大于所述控制芯片的高度，当所述焊接凸块与所述外部电路电连接时，所述控制芯片与所述外部电路之间具有间距。
  6. 根据权利要求1所述的影像传感芯片封装结构，其特征在于，所述控制芯片倒装于所述基板上。
  7. 根据权利要求1所述的影像传感芯片封装结构，其特征在于，所述控制芯片与所述基板通过焊线实现电连接。
  8. 一种影像传感芯片的封装方法，包括：提供影像传感芯片以及用于控制所述影像传感芯片的控制芯片；其特征在于，还包括：
    提供基板，所述基板具有彼此相对的第一表面以及第二表面；
    将所述控制芯片电连接至所述基板的第二表面；
    将所述影像传感芯片电连接至所述基板的第一表面。
  9. 根据权利要求8所述的影像传感芯片的封装方法，其特征在于，将影像传感芯片电连接至所述基板之前包括：
    提供晶圆，所述晶圆上具有阵列排布的影像传感芯片，所述影像传感芯片具有彼此相对的第一面以及第二面，所述影像传感芯片的第一面设置有感光区以及位于感光区外的焊垫；
    提供与所述晶圆尺寸一致的保护盖板，所述保护盖板的一面上设置有阵列排布的支撑单元，每一支撑单元对应一个影像传感芯片；
    将所述晶圆与所述保护盖板对位压合，在每一影像传感芯片与保护盖板之间形成密封的腔体，所述感光区位于所述腔体内；
    采用硅通孔工艺在所述影像传感芯片的第二面形成多个硅通孔，每一硅通孔对应一个焊垫，所述硅通孔的底部暴露所述焊垫；
    在所述硅通孔中形成金属布线层，所述金属布线层与所述焊垫电连接；
    在所述影像传感芯片的第二面形成焊球，所述焊球与所述金属布线层电连接；
    切割所述影像传感芯片以及所述保护盖板，使彼此相连的多个影像传感芯片分离。
  10. 根据权利要求9所述的影像传感芯片的封装方法，其特征在于，所述保护盖板为减反射玻璃。
  11. 根据权利要求8所述的影像传感芯片的封装方法，其特征在于，采用倒装工艺将所述控制芯片电连接至所述基板。
  12. 根据权利要求8所述的影像传感芯片的封装方法，其特征在于，采用引线键合工艺将所述控制芯片电连接至所述基板。
  13. 根据权利要求8所述的影像传感芯片的封装方法，其特征在于，还包括，在所述基板的第二表面设置用于与外部电路电连接的焊接凸块，所述焊接凸块的高度大于所述控制芯片的高度，当所述焊接凸块与所述外部电路电连接时，所述控制芯片与所述外部电路之间具有间距。
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