CN103325799A - 芯片堆迭结构及其制造方法 - Google Patents

芯片堆迭结构及其制造方法 Download PDF

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Publication number
CN103325799A
CN103325799A CN2012102589971A CN201210258997A CN103325799A CN 103325799 A CN103325799 A CN 103325799A CN 2012102589971 A CN2012102589971 A CN 2012102589971A CN 201210258997 A CN201210258997 A CN 201210258997A CN 103325799 A CN103325799 A CN 103325799A
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chip
signal processing
glass substrate
wafer
electrically connected
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CN103325799B (zh
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沈更新
陈雅琪
毛苡馨
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Chipmos Technologies Inc
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Chipmos Technologies Inc
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Abstract

本发明关于一芯片堆迭结构及其制造方法，将具有光学芯片的晶圆、以及具有信号处理芯片的玻璃基板彼此迭合后，再进行植球及切割，以制成堆迭的封装结构，其中光学芯片及信号处理芯片藉由玻璃基板的导电贯穿孔，于一表面上电性连接。

Description

芯片堆迭结构及其制造方法
技术领域
本发明关于一种芯片堆迭结构及其制造方法，该芯片堆迭结构特别是包含信号处理芯片及光学芯片的堆迭结构。
背景技术
随着人们生活习惯的演变及工艺技术的进步，图像传感器已广泛地应用于日常生活中。已知的图像传感器例如：互补金属氧化半导体（complementarymetal-oxide semiconductor，CMOS）图像传感器、及电荷耦合元件（charge coupleddevice，CCD）图像传感器等等。其中，CMOS图像传感器具有价格低廉、耗电量低等优点，通常较适用于低阶产品；而CCD图像传感器所撷取的影像品质较佳，则长期主宰了高阶图像传感器的市场。
然而，由于数字信号处理器（digital signal processor，DSP）芯片的加入，其与CMOS图像传感器的配合，恰补足了CMOS图像传感器的不足。详言之，DSP芯片可模拟人眼，来处理感光元件无法辨识的情况，并进一步利用演算法辅助CMOS图像传感器的影像效能。因此，组合CMOS图像传感器与DSP芯片的模组，已逐渐使用在数字摄影机及数字相机等高画素可携式产品。
请参考图1A至图1C，所示为现有的图像传感（CMOS imaging sensor，CIS）芯片11与数字信号处理器芯片12的封装结构1及其制造过程。如图1A所示，多个图像传感芯片11形成于一晶圆13上，再进行切割而成的单一图像传感芯片11，各图像传感芯片11具有多个第一接点111分布于图像传感芯片11的二侧。而同样地，多个数字信号处理器芯片12如图1B所示，亦是形成于一晶圆14上，再进行切割而成的单一数字信号处理器芯片12，各数字信号处理器芯片12具有多个第二接点121分布于二侧。
请参阅图1C，现有的技术是，将切割后的单一图像传感芯片11与单一数字信号处理器芯片12横向对齐排列定位于基板上，再以打线方式，将这些第一接点111与这些第二接点141依序电性连接。
可想见地，现有技术需先分别切割晶圆13及晶圆14，以制成单一且尺寸相应的图像传感芯片11及数字信号处理器芯片12，后续还需要分别固定图像传感芯片11及数字信号处理器芯片12，然后再进行打线连接。工艺上较为繁复且生产时间长，制造成本偏高。另外，图像传感芯片11及数字信号处理器芯片12的配置为横向并排设置于基板上，所占据面积较大，且打线结合可靠度不佳，容易产生接触不良或稳定性不佳的缺点。
有鉴于此，提供一种可改善工艺、缩减体积与所占面积、及提升可靠度的芯片堆迭结构及制造方法，乃为此一业界亟欲达成的目标。
发明内容
本发明的一目的在于节省芯片堆迭结构的配置空间，藉由堆迭芯片的封装结构，可避免现有封装结构平行排列时所占较大面积的问题，本发明的芯片堆迭结构除了可节省所占据的面积之外，所节省的空间更可提供给其它元件运用。
本发明的另一目的在于简化芯片堆迭结构的工艺。藉由将包含多个图像传感芯片的晶圆与包含多个数字信号处理器芯片的基板先予以连接对合，再进行切割，以制成单一芯片堆迭结构，而非先个别切割形成图像传感芯片及数字信号处理器芯片，故不需要现有的后续定位、打线连接等工艺，可大幅简化工艺及降低生产的成本。
本发明的又一目的在于提高芯片堆迭结构及其工艺的可靠度及稳定性，藉由以堆迭方式对合图像传感芯片与数字信号处理器芯片，并透过基板中内镀有金属材料的多个贯穿孔（through hole），电性连接于基板的外表面，使得整体的结构的稳定性及可靠度大幅提升。
为达上述目的，本发明提供一种芯片堆迭结构，包含：一信号处理芯片模组及一光学芯片模组，该信号处理芯片模组包含：一玻璃基板，具有一第一表面、以及与该第一表面相对的一第二表面，该第一表面上更形成一凹穴，其中，该玻璃基板的第一表面与该凹穴内分别形成有贯穿孔，并于该贯穿孔内镀有金属材料以电性连接该第一表面及该第二表面；及一信号处理芯片，设置于该凹穴中；该光学芯片模组包含一光学芯片，该光学芯片模组于该第一表面上与该信号处理芯片模组迭置，该光学芯片的面积大于该信号处理芯片的面积，以涵盖该信号处理芯片；其中，该信号处理芯片及该光学芯片更分别包含多个导电接点，相应地连接这些贯穿孔，以于该第二表面上电性连接。
本发明更提供一种制造芯片堆迭结构的方法，包含下列步骤：提供一玻璃基板，其中，该玻璃基板具有一第一表面、以及与该第一表面相对的一第二表面，并依据一布局于第一表面上形成多个凹穴，凹穴与第一表面上设有内镀金属材料的多个贯穿孔，其中，这些信号处理芯片嵌设于凹穴与贯穿孔电性连接；提供一晶圆，其中，该晶圆上设置有多个光学芯片；及迭合该玻璃基板及该晶圆，使对应的该光学芯片及该信号处理芯片，经由这些贯穿孔电性连接。
为让上述目的、技术特征、和优点能更明显易懂，下文以较佳实施例配合所附附图进行详细说明。
附图说明
图1A为现有制造图像传感芯片的示意图；
图1B为现有制造数字信号处理器芯片的示意图；
图1C为现有芯片封装结构的示意图；
图2为本发明芯片堆迭结构的示意图；
图3至图8为本发明制造芯片堆迭结构的示意图；及
图9为本发明制造芯片堆迭结构的流程图。
【主要元件符号说明】
11     图像传感芯片
111    第一接点
12     数字信号处理器芯片
121    第二接点
13     晶圆
14     晶圆
2      芯片堆迭结构
21     光学芯片模组
210    晶圆
213     光学芯片
213a    导电接点
23      信号处理芯片模组
231     玻璃基板
231a    第一表面
231b    第二表面
233     信号处理芯片
233a    导电接点
235     贯穿孔
237     凹穴
25      导电线路层
27      焊球
29      粘着层
901~907 步骤
具体实施方式
请参阅图2，所示为本发明第一实施例的芯片堆迭结构2的剖面示意图，其为包含一光学芯片模组21及一信号处理芯片模组23所堆迭组成的结构。
其中，信号处理芯片模组23包含一玻璃基板231及一信号处理芯片233，该信号处理芯片233较佳为一数字信号处理器（digital signal processor，DSP）芯片。为方便说明，进一步定义该玻璃基板231具有一第一表面231a、以及与该第一表面231a相对的一第二表面231b，玻璃基板231更形成有多个贯穿孔（through hole）235，其内镀有金属材料以连接该第一表面231a及该第二表面231b。
玻璃基板231的第一表面231a上更形成一凹穴237，以供信号处理芯片233设置于该凹穴237中。凹穴237内亦形成镀有金属材料的贯穿孔235，而该信号处理芯片233更包含多个导电接点233a，例如现有的凸块，相应地电性连接至对应的贯穿孔235。
较佳地，芯片堆迭结构2更包含一导电线路层25及多个焊球27，该导电线路层25形成于玻璃基板231的第二表面231b上，以选择性地电性连接这些贯穿孔235，而焊球27形成于该导电线路层25上的适当位置。
而光学芯片模组21包含一光学芯片213，较佳为一图像传感（CMOS imagingsensor，CIS）芯片，该光学芯片模组21于信号处理芯片模组23的第一表面231a上，与信号处理芯片模组23迭置，且该光学芯片213的面积大于该信号处理芯片233的面积，以涵盖该信号处理芯片233，使光学芯片213的导电接点233a得以准确地对应连接于信号处理芯片233外侧的部分贯穿孔235。同样地，该光学芯片213亦可包含多个导电接点213a，例如现有的凸块，相应地连接至对应的部分贯穿孔235。
为稳固地结合该信号处理芯片模组23与该光学芯片模组21，本发明的芯片堆迭结构2较佳更包含一粘着层29，施加于信号处理芯片模组23与光学芯片模组21的间。
如此一来，透过这些贯穿孔235及导电线路层25，光学芯片213与信号处理芯片233得以于玻璃基板231的第二表面231b上电性连接。
接下来将说明本发明的第二实施例，其用于制造前述芯片堆迭结构2的方法，以下将配合图3至图8的示意图以及图9的流程图，一并说明。
首先，如图9的步骤901及图3所示，提供一玻璃基板231，其上形成多个贯穿孔235及多个凹穴237以供多个信号处理芯片233设置；其中，该玻璃基板231具有第一表面231a、以及与该第一表面231a相对的第二表面231b，这些凹穴237依据一布局形成于第一表面231a上，凹穴237与第一表面231a上的这些贯穿孔235内镀金属材料，以于第一表面231a及第二表面231b上形成接点，这些信号处理芯片233分别嵌设于凹穴237内以与对应的贯穿孔235电性连接。
然后进行步骤902，于玻璃基板231的第二表面231b上形成导电线路层25，以选择性地电性连接这些贯穿孔235。
接着，如图9的步骤903及图4所示，提供一晶圆210（通常包含一硅基板），其中，该晶圆210上形成有多个光学芯片213。如第一实施例所说明，光学芯片213更包含并显露出多个导电接点213a，该导电接点213a可为现有的凸块，例如：金凸块、钖球、铜凸块、银凸块、复合金属凸块或结线凸块等等。
然后如图9的步骤904及图5所示，迭合玻璃基板231及晶圆210，使对应的光学芯片213及信号处理芯片233，经由这些贯穿孔235电性连接。更明确而言，此步骤将晶圆210贴合于玻璃基板231的第一表面231a上，使光学芯片213的导电接点213a，连接至相对应的贯穿孔235。
迭合后的结构，如图6的剖面图所示。其中，各光学芯片213包含多个导电接点213a，各信号处理芯片233包含多个导电接点233a，该迭合玻璃基板231及晶圆210的步骤，是将这些导电接点213a、233a对准并电性连接至对应的贯穿孔235。
较佳地，于进行步骤904的迭合工艺时，更施加粘着层29于玻璃基板231及晶圆210之间，以利其相互结合，其中，该粘着层29可为一填充胶材(Underfill)。于本发明的另一较佳实施例中，该粘着层29可为一半固化的两阶段特性粘胶(B-Stage)预设于晶圆凸块的周围，于迭合玻璃基板231及晶圆210时一并固化该粘着层29，以增加该光学芯片213与信号处理芯片23彼此间的结合性。
接下来，如图9的步骤905及图7所示，研磨晶圆210背面，以减少其整体厚度。
最后，如图8所示，先执行步骤906，于导电线路层25上植入多个焊球27，再执行步骤907，切割迭合后的玻璃基板231及晶圆，而最终制成第一实施例的芯片堆迭结构2。无疑地，芯片堆迭结构2包含光学芯片21及信号处理芯片23所组成，光学芯片21如图像传感（CMOS imaging sensor，CIS）芯片，信号处理芯片23如数字信号处理器（digital signal processor，DSP）芯片。
综上所述，本发明所揭露的芯片堆迭结构及其制造方法，改以于晶圆时直接堆迭后切割以形成堆迭芯片的封装结构，不仅可节省芯片堆迭结构的配置空间及所占面积，亦可大幅简化工艺及降低成本，更可提高芯片堆迭结构的可靠度及稳定性。
上述的实施例仅用来例举本发明的实施态样，以及阐释本发明的技术特征，并非用来限制本发明的保护范畴。任何熟悉此技术者可轻易完成的改变或均等性的安排均属于本发明所主张的范围，本发明的权利保护范围应以权利要求为准。

Claims (10)

1.一种芯片堆迭结构，包含：
一信号处理芯片模组，包含：
一玻璃基板，具有一第一表面、以及与该第一表面相对的一第二表面，该第一表面上更形成一凹穴，其中，该玻璃基板的第一表面与该凹穴内分别形成有贯穿孔，并于该贯穿孔内镀有金属材料以电性连接该第一表面及该第二表面；及
一信号处理芯片，设置于该凹穴中与该多个贯穿孔电性连接；及
一光学芯片模组，包含一光学芯片，该光学芯片模组于该第一表面上与该信号处理芯片模组迭置，该光学芯片的面积大于该信号处理芯片的面积，以涵盖该信号处理芯片；
其中，该信号处理芯片及该光学芯片更分别包含多个导电接点相应地连接这些贯穿孔，以于该第二表面上电性连接。
2.如权利要求1所述的芯片堆迭结构，其特征在于，这些导电接点为多个凸块。
3.如权利要求1所述的芯片堆迭结构，其特征在于，更包含一导电线路层及多个焊球，该导电线路层形成于该第二表面上，以选择性地电性连接这些贯穿孔，而该多个焊球形成于该导电线路层上。
4.如权利要求1所述的芯片堆迭结构，其特征在于，更包含一粘着层，施加于该信号处理芯片模组与该光学芯片模组之间，以结合该信号处理芯片模组与该光学芯片模组。
5.一种制造一芯片堆迭结构的方法，包含下列步骤：
提供一玻璃基板，其中，该玻璃基板具有一第一表面、以及与该第一表面相对的一第二表面，并依据一布局于第一表面上形成多个凹穴，这些凹穴与该第一表面上设有内镀金属材料的多个贯穿孔，其中，这些信号处理芯片分别嵌设于这些凹穴中以与这些贯穿孔电性连接；
提供一晶圆，其中，该晶圆上形成有多个光学芯片；及
迭合该玻璃基板及该晶圆，使对应的该光学芯片及该信号处理芯片，经由这些贯穿孔电性连接。
6.如权利要求5所述的方法，其特征在于，该迭合该玻璃基板及该晶圆的步骤，是将该晶圆贴合于该玻璃基板的第一表面上。
7.如权利要求6所述的方法，其特征在于，该迭合该玻璃基板及该晶圆的步骤，包含：
施加一粘着层于该玻璃基板及该晶圆之间。
8.如权利要求5所述的方法，其特征在于，该提供一玻璃基板的步骤，更包含：
于该第二表面上形成一导电线路层，以选择性地电性连接这些贯穿孔。
9.如权利要求5所述的方法，其特征在于，于该迭合该玻璃基板及该晶圆的步骤之后，更包含：
研磨该晶圆；
于该导电线路层上，植入多个焊球；以及
切割迭合后的该玻璃基板及该晶圆。
10.如权利要求5所述的方法，其特征在于，各该信号处理芯片及各该光学芯片更分别包含多个导电接点，该迭合该玻璃基板及该晶圆的步骤，是将这些导电接点对准并电性连接至这些贯穿孔。
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