CN102104035A - 堆叠半导体封装及其制造方法以及包括该封装的系统 - Google Patents

堆叠半导体封装及其制造方法以及包括该封装的系统 Download PDF

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Publication number
CN102104035A
CN102104035A CN2010105942754A CN201010594275A CN102104035A CN 102104035 A CN102104035 A CN 102104035A CN 2010105942754 A CN2010105942754 A CN 2010105942754A CN 201010594275 A CN201010594275 A CN 201010594275A CN 102104035 A CN102104035 A CN 102104035A
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China
Prior art keywords
connector
substrate
semiconductor chip
semiconductor
chip
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CN2010105942754A
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English (en)
Inventor
权兴奎
罗珉玉
朴晟佑
朴智贤
朴寿珉
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from KR1020100052827A external-priority patent/KR101685652B1/ko
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN102104035A publication Critical patent/CN102104035A/zh
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Abstract

本发明提供一种堆叠半导体封装及其制造方法以及包括该封装的系统。一种装置包括具有第一焊区的第一衬底和具有第二焊区的第二衬底。第一塑封料设置于第一衬底和第二衬底之间。第一半导体芯片设置于第一衬底上且接触第一塑封料。第一连接器接触第一焊区，第二连接器接触第二焊区。第二连接器设置在第一连接器上。第二连接器的体积大于第一连接器的体积。第一半导体芯片的表面被暴露。第一塑封料接触第二连接器，并且第二连接器的至少一部分被第一塑封料围绕。

Description

堆叠半导体封装及其制造方法以及包括该封装的系统
技术领域
本公开涉及堆叠半导体封装，更具体地，涉及堆叠半导体封装及其制造方法。
背景技术
封装上封装(package on package，PoP)是一种集成电路封装技术，其允许垂直地组合离散的逻辑和存储器球栅阵列(BGA)封装。两个或更多封装被堆叠，在它们之间有传送信号的界面(interface)。在例如移动电话/PDA市场中，这允许较高的密度。在PoP中，两个或更多存储封装可以堆叠在彼此上。备选地，存储封装可以堆叠在逻辑封装上。使用PoP技术，可以节省母板(motherboard)中的空间。
发明内容
示范性实施例涉及堆叠半导体芯片封装、制造堆叠半导体芯片封装的方法和/或采用堆叠半导体芯片封装的系统。
根据示范性实施例，一种装置包括：第一衬底，包括第一焊区；第二衬底，包括第二焊区；第一塑封料(molding compound)，设置于第一衬底和第二衬底之间；第一半导体芯片，设置于第一衬底上且接触第一塑封料；第一连接器，接触第一焊区；以及第二连接器，接触第二焊区，第二连接器设置在第一连接器上，其中第二连接器的体积大于第一连接器的体积，第一半导体芯片的表面被暴露，第一塑封料接触第二连接器，第二连接器的至少一部分被第一塑封料围绕。
第一连接器可以设置在第一塑封料中。
第二连接器的一部分可以不设置在第一塑封料中。
装置还可以包括设置在第二衬底上的第二半导体芯片。
装置还可以包括接触第二半导体芯片的第二塑封料。
第一衬底和第二衬底可以包括印刷电路板(PCB)或者陶瓷衬底。
第一连接器和第二连接器可以配置来传输功率或信号。
第一半导体芯片可以包括逻辑器件，第二半导体芯片包括存储器件。
第一连接器和第二连接器可以是焊料球(solder ball)。
第一半导体芯片可以包括在其中的多个垂直穿透硅通孔(through silicon via，TSV)。
装置还可以包括设置在第一连接器和第二连接器之间的第三连接器。
根据一示范性实施例，一种电子系统包括：控制单元；输入单元，配置来传输电信号到控制单元；输出单元，配置来接收来自控制单元的电信号且输出电子系统的处理结果；存储单元，配置来存储待处理或者已经被控制单元处理的数据；以及通讯单元，配置来接收来自控制单元的电信号且传输电信号到另一电子系统或者接收来自另一电子系统的电信号，其中控制单元、输入单元、输出单元、存储单元和通讯单元中的至少一个包括一种装置，该装置包括：第一衬底，包括第一焊区；第二衬底，包括第二焊区；第一塑封料，设置于第一衬底和第二衬底之间；第一半导体芯片，设置于第一衬底上且接触第一塑封部分；第一连接器，接触第一焊区；以及第二连接器，接触第二焊区，第二连接器设置在第一连接器上，其中第二连接器的体积大于第一连接器的体积，第一半导体芯片的表面被暴露，第一塑封料接触第二连接器，第二连接器的至少一部分被第一塑封料围绕。
控制单元可以包括中央处理单元(CPU)、主控制单元(MCU)和半导体模块中的至少一种。
输入单元可以包括键盘、键板、鼠标、触摸垫和图像识别器中的至少一种。
输出单元可以包括监视器、打印机和束发射器中的至少一种。
存储单元可以包括半导体存储器、磁存储器件、光学存储器件和具有数据存储功能的服务器中的至少一种。
通讯单元可以包括有线收发器、无线收发器和红外端口(IR)中的至少一种。
电子系统可以是计算机、网络服务器、网络打印机、扫描仪、无线控制器、移动通讯终端、开关系统、或者能编程操作的任何电子器件。
根据一示范性实施例，一种方法可以包括：在第一衬底上设置第一半导体芯片；在第一衬底的焊区上设置第一连接器；将第一塑封料置于第一衬底上且接触第一半导体芯片和第一连接器；暴露第一衬底的表面；以及形成穿过第一塑封料的开口以暴露第一连接器的一部分。
该方法还可以包括设置第二连接器和第二半导体芯片在第二衬底上，并将第一连接器耦接到第二连接器。
第二连接器可以具有比第一连接器更大的体积。
该方法还可以包括设置第二塑封料接触第二半导体芯片和第二连接器。
该方法还可以包括将第二连接器浸入到焊料助熔剂(solder flux)中。
第一连接器和第二连接器可以是焊料球。
第二连接器可以具有比第一连接器更大的半径。
根据一示范性实施例，一种方法可以包括：在第一衬底上设置第一半导体芯片和第一焊料球；将塑封料置于第一衬底上且接触第一半导体芯片和第一焊料球；形成穿过塑封料的开口从而暴露第一焊料球的一部分；在第二衬底上设置第二半导体芯片和第二焊料球；以及将第一焊料球耦接到第二焊料球，其中第二焊料球的半径大于第一焊料球的半径。
该方法还可以包括暴露第一衬底的表面。
第二焊料球可以具有比第一焊料球更大的体积。
该方法还可以包括设置第二塑封料接触第二半导体芯片和第二焊料球。
该方法还可以包括将第二焊料球浸入焊料助熔剂中。
附图说明
本发明的示范性实施例可以从下面结合附图进行的描述得到更详细的理解，附图中：
图1A是根据本发明构思实施例的下半导体封装的示意性平面图；
图1B是根据本发明构思实施例的下半导体封装的示意性平面图；
图2A至2H是根据本发明构思的实施例的装置的示意性纵向截面图；
图3A和3B是根据本发明构思实施例的包括芯片连接器的装置的示意性纵向截面图；
图4是根据本发明构思实施例的装置的示意性纵向截面图；
图5A至5D是根据本发明构思实施例的芯片连接器及其连接结构的示意性纵向截面图；
图6A至6D是根据本发明构思实施例的芯片连接器及其连接结构的示意性纵向截面图；
图7A至7D是根据本发明构思实施例的各种封装间连接器的示意性纵向截面图；
图8A至8I是根据总的发明构思的封装堆叠结构的各种连接器的真实形状的示意图；
图9A至9I是根据总的发明构思的封装堆叠结构的通孔和各种连接器的形状的示意图；
图10A至10F是示意性纵向剖视图，示出在制造根据总的发明构思的半导体封装的堆叠结构的方法中形成上封装的工艺；
图11A至11L是示意性纵向剖视图，示出根据总的发明构思的制造半导体封装的堆叠结构的方法；
图12A和12B是根据总的发明构思的包括半导体封装的堆叠结构的半导体模块的示意图；以及
图13是根据总的发明构思的包括半导体封装的堆叠结构的电子系统的示意图。
具体实施方式
将参照附图描述本发明构思的示范性实施例。
尽管示出并描述了本发明构思的一些示范性实施例，但是本领域普通技术人员将意识到，可以在这些示范性实施例中进行改变而不偏离示范性实施例的原理和思想，示范性实施例的范围在权利要求及其等同物中限定。
将理解，当元件或层被称为“在”另一元件或层“上”时，该元件或层可以直接在另一元件或层上或者存在插入的元件或层。相反，当元件被称为“直接在”另一元件或层“上”时，则没有插入的元件或层存在。相似的附图标记始终表示相似的元件。这里使用时，术语“和/或”包括相关所列项的一种或者更多的任意和全部组合。
这里使用的术语仅用于描述特定实施例，无意成为对本发明的限制。这里使用时，单数形式“一”、“一个”和“该”旨在也包括复数形式，除非上下文清楚地另外表明。还将理解，当在本说明书中使用时术语“包括”和/或“包含”指明所列特征、整体、步骤、操作、元件和/或组元的存在，但是不排除一种或更多其它特征、整体、步骤、操作、元件、组元和/或其组的存在或添加。
将理解，尽管术语第一、第二、第三等可在这里用来描述各种元件、组元、区域、层和/或部分，但是这些元件、组元、区域、层和/或部分不应被这些术语限制。这些术语仅用于将一个元件、组元、区域、层或部分与另一区域、层或部分区别开。因此，下面论述的第一元件、组元、区域、层或部分可以用术语第二元件、组元、区域、层或部分表示而不偏离示范性实施例的教导。
这里参照截面图描述本发明构思的示范性实施例，这些截面图是本发明构思的示范性实施例(以及中间结构)的示意图。这样，例如制造技术和/或容差引起的图示形状的变化是可以预期的。因此，示范性实施例不应理解为局限于这里示出的区域的特定形状，而是将包括例如制造引起的形状偏差。
图1A是根据本发明构思实施例的下半导体封装的示意性平面图。在图1A中，下半导体芯片被揭示。图1B是根据示范性实施例的下半导体封装的示意性平面图。在图1B中，下半导体芯片未被揭示。
参照图1A，下半导体封装105L可以包括：下封装衬底110L；下半导体芯片115L，设置于下封装衬底110L上；以及多个封装间连接器(inter-package connector)150，设置于下半导体芯片115L周围。参照图1B，虚线表示配置来接收下半导体芯片115L的位置。根据一实施例，下半导体封装105L可以包括设置在下封装衬底110L和下半导体芯片115L之间的多个倒装芯片连接垫(flip chip landing pad)185。倒装芯片连接垫185可以被多个封装间连接器150围绕。倒装芯片连接垫185可以例如通过诸如穿透硅通孔(through silicon via)、穿透硅通孔插塞(through silicon via plug)和/或导电芯片凸块(bump)电连接到其它元件。
图2A至2H是根据本发明构思实施例的装置的示意性纵向截面图。
参照图2A，装置100a包括下半导体封装105L、上半导体封装105U以及封装间连接器150a，封装间连接器150a配置来电连接下半导体封装105L和上半导体封装105U。上半导体封装105U堆叠在下半导体封装105L上。部分封装间连接器150a可以是下半导体封装105L的一部分。封装间连接器150a的另一部分可以是上半导体封装105U的一部分。
下半导体封装105L可以包括：下封装衬底110L；下半导体芯片115L，设置在下封装衬底110L的顶表面上；下塑封料130L；以及导电焊料球125，设置在下封装衬底110L的底表面上。下半导体封装105L可以利用例如倒装芯片技术形成。下封装衬底110L可以包括例如印刷电路板(PCB)或陶瓷衬底。
下半导体芯片115L可以包括逻辑器件例如微处理器。下半导体芯片115L可以设置在下封装衬底110L的一个表面上。下半导体芯片115L可以通过导电芯片凸块120电连接到焊料球125。导电芯片凸块120可以设置在下半导体衬底110L的顶表面上。也就是说，根据本发明构思的实施例，下半导体芯片115L可以包括具有栅格阵列的倒装芯片连接结构。
导电芯片凸块120可以插置在下封装衬底110L和下半导体芯片115L之间。导电芯片凸块120可以电连接下封装衬底110L和下半导体芯片115L。导电芯片凸块120可以包括焊料材料。因此，导电芯片凸块120可以使用例如焊接工艺形成。
导电焊料球125配置来将装置100a电连接到模块板或者主电路板。
下塑封料130L覆盖导电芯片凸块120。粘合剂可以形成在导电芯片凸块120周围。例如，粘合剂可以设置在下半导体芯片115L和下封装衬底110L之间。下塑封料130L围绕下半导体芯片115L的侧表面。例如，下半导体芯片115L可以利用粘合剂粘结到下半导体封装105L的顶表面，下塑封料130L可以围绕下半导体芯片115L的侧表面。
在一实施例中，粘合剂可以包括在下塑封料130L中。在一实施例中，下塑封料130L可以围绕封装间连接器150a的侧表面。在一实施例中，下半导体芯片115L的顶表面可以不覆盖有下塑封料130L。换言之，下半导体芯片115L的顶表面被暴露。在一实施例中，下塑封料130L的顶表面与下半导体芯片115L的顶表面共平面(coplanar)。在一实施例中，由于下半导体封装105L的厚度减小，所以装置100a的厚度也减小。由于下半导体芯片115L的顶部被暴露，所以热能够散去而不被环氧塑封料(EMC)妨碍。因而，能够改善热辐射性质。由于与被EMC覆盖的封装相比，下半导体封装105L具有对高温工艺更好的容忍性或抵抗力，所以下半导体封装105L可以具有对翘曲或变形更好的容忍性或抵抗力，从而能够改善下半导体封装105L和下半导体芯片115L的平坦度。
由于物理压力可以直接施加到下半导体芯片115L的顶表面而不经过塑封材料，所以栅格阵列技术或者多层塑封技术可以稳定地进行。当下塑封料130L的厚度减小时，封装间连接器150a的整个高度可以减小。由于封装间连接器150a利用焊接工艺(例如回流工艺)形成，所以当封装间连接器150a的整个高度减小时，封装间连接器150a的最大水平宽度可以减小。这是因为利用焊工艺形成的结构可以基本是球形的。当封装间连接器150a的最大水平宽度减小时，封装间连接器150a的体积可以减小。这样，封装间连接器150a之间的间距(interval)或节距(pitch)可以减小。于是，当下塑封料130L的厚度减小时，更多数量的封装间连接器150a可以形成在给定区域中。根据本发明构思的实施例，可以形成具有更精细和更等距隔开的封装间连接器150a的装置100a。
上半导体封装105U可以包括上封装衬底110U和上半导体芯片115U。上封装衬底110U可以包括例如PCB或陶瓷衬底。
上半导体芯片115U可以包括存储器件例如动态随机存取存储器(DRAM)或闪存器件。上半导体芯片115U可以具有比下半导体芯片115L更大的水平宽度。当上半导体芯片115U在水平方向上比下半导体芯片115L更宽时，由于封装间连接器150a占据的面积可以增大，所以半导体封装的堆叠结构100a可以形成为更小尺寸。当封装间连接器150a占据的面积增大时，可以形成大量封装间连接器150a。备选地，当形成相同数量的封装间连接器150a时，半导体封装的堆叠结构可以减小。
上半导体芯片115U可以设置在上封装衬底110U的顶表面上。上半导体芯片115U可以通过结合垫135、结合导线140和导线垫145电连接到上封装衬底110U。
结合垫135可以形成在上半导体芯片115U的顶表面上。导线垫145可以形成在上封装衬底110U的顶表面上。结合导线140可以将结合垫135分别电连接到导线垫145。
上半导体芯片115U可以覆盖有上塑封料130U。
封装间连接器150a可以将下半导体封装105L与上半导体封装105U物理或电连接。封装间连接器150a可以分别包括下连接器160a和上连接器180a。下连接器160a和上连接器180a可以包括焊料材料。
上半导体芯片115U可以具有比下半导体芯片115L更大的水平宽度。根据本发明构思一实施例，封装间连接器150a可以形成在下封装衬底110L的形成下半导体芯片115L的顶表面上方或之上。封装间连接器150a可以形成在上封装衬底110U的没有形成上半导体芯片115U的底表面之下或之上。因此，封装间连接器150a会受到下半导体芯片115L的尺寸影响。半导体封装的堆叠结构100a的面积标准可以基于半导体标准规范例如电子工程设计发展联合协会(JEDEC)规范来确定。于是，当下半导体芯片115L尺寸大于上半导体芯片115U时，对可形成封装间连接器150a的地方的空间的限制会增加，效率降低。根据本发明构思的一实施例，当上半导体芯片115U尺寸大于下半导体芯片115L时，空间限制可以减少，效率可以得到改善。因此，根据本发明构思的一实施例，上半导体芯片115U可以形成得尺寸大于下半导体芯片115L。参照图2B，装置100b可以包括下半导体封装105L、上半导体封装105U以及配置来电连接下半导体封装105L和上半导体封装105U的封装间连接器150b。封装间连接器150b可以包括下连接器160b和上连接器180b。下连接器160b和上连接器180b可以包括焊料材料。下连接器160b可以具有半球形。
参照图2C，装置100c可以包括下半导体封装105L、上半导体封装105U、以及配置来电连接下半导体封装105L和上半导体封装105U的封装间连接器150c。上半导体封装105U堆叠在下半导体封装105L上。封装间连接器150c可以包括底连接器165c和上连接器180c。每个底连接器165c可以形成为台或柱形。例如，每个底连接器165c可以形成为圆形、圆柱或多边柱形。
底连接器165c可以附着到下封装衬底110L的顶表面。例如，底连接器165c可以包括金属。底连接器165c可以使用例如铸(casting)工艺、沉积工艺、结合(bonding)工艺或镀覆工艺形成。
金属阻挡层可以形成在底连接器165c的表面上。例如，底连接器165c的主体可以包括铜(Cu)，镍(Ni)阻挡层可以形成在底连接器165c的表面上。
尽管示出上连接器180c尺寸大于底连接器165c，但是本发明构思不限于此。
与焊接工艺相比，在下封装衬底110L的顶表面上将底连接器165c形成为台形的工艺可以较少地受到底连接器165c之间的距离的影响。因此，底连接器165c可以以各种形状形成。例如，与图2C所示的相比，每个底连接器165c可以具有更小的水平尺寸和更大的垂直尺寸。在该情况下，上连接器180c的仅小部分可以形成在下塑封料130L的表面之下。换言之，上连接器180c的中心可以形成在下塑封料130L的顶表面之上。尽管示出每个上连接器180c具有几乎圆形截面形状，但是本发明构思不限于此。例如，每个上连接器180c可以具有椭圆截面形状。上连接器180c可以包括焊料材料。
参照图2D，装置100d可以包括下半导体封装105L、上半导体封装105U、以及配置来电连接下半导体封装105L和上半导体封装105U的封装间连接器150d。上半导体封装105U堆叠在下半导体封装105L上。封装间连接器150d可以包括下连接器160d、中间连接器170d和上连接器180d。每个下连接器160d可以具有圆形或半圆形。每个下连接器160d的假想中心可以形成在下封装衬底110L的顶表面之上或之下。中间连接器170d可以具有台形且附着到下连接器160d的顶表面。中间连接器170d可以包括铜(Cu)。金属阻挡层例如镍(Ni)阻挡层可以形成在中间连接器170d的表面上。下连接器160d和上连接器180d可以包括焊料材料。
参照图2E，装置100e可以包括下半导体封装105L、上半导体封装105U、以及配置来电连接下半导体封装105L和上半导体封装105U的封装间连接器150e。上半导体封装105U堆叠在下半导体封装105L上。封装间连接器150e可以包括下连接器160e、中间连接器170e、中间粘合部件175e和上连接器180e。下连接器160e和中间连接器170e可以参照对图2B至2D所示的下连接器160b和160d、底连接器165c以及中间连接器170d的描述来理解。中间粘合部件175e可以形成在中间连接器170e上。尽管每个中间粘合部件175e具有椭圆截面形状，但是本发明构思不限于此。例如，每个中间粘合部件175e可以具有球形或半球形。在该情况下，中间粘合部件175e的形状可以参照对图2B和2D所示的下连接器160b和160d的描述来理解。在一实施例中，中间粘合部件175e的中心可以形成在中间连接器170e的顶表面之上或之下。下连接器160e、中间粘合部件175e和上连接器180e可以包括焊料材料。
参照图2F，装置100f可以包括下半导体封装105L、上半导体封装105U以及配置来电连接下半导体封装105L和上半导体封装105U的封装间连接器150f。上半导体封装105U堆叠在下半导体封装105L上。封装间连接器150f可以包括下连接器160f和封装凸块190f。下连接器160f可以参照图2A以及对其的描述来理解。每个封装凸块190f可以包括金属，并可以具有大头钉(stud)、棒(stick)或柱形。封装凸块190f可以利用额外工艺制造且附着或固定到上封装衬底110U。封装凸块190f可以包括铜(Cu)。包括例如镍(Ni)阻挡层的金属阻挡层可以形成在封装凸块190f的表面上。下连接器160d和上连接器180d可以包括焊料材料。
参照图2G，装置100g可以包括下半导体封装105L、上半导体封装105U以及配置来电连接下半导体封装105L和上半导体封装105U的封装间连接器150g。上半导体封装105U堆叠在下半导体封装105L上。封装间连接器150g可以包括底连接器165g、中间连接器175g和封装凸块190g。底连接器165g、中间连接器175g和封装凸块190g可以参照图2C至2G以及对它们的描述来理解。
参照图2H，装置100h可以包括下半导体封装105L、上半导体封装105U以及配置来电连接下半导体封装105L和上半导体封装105U的封装间连接器150h。上半导体封装105U堆叠在下半导体封装105L上。封装间连接器150h可以包括下连接器160h、中间连接器170h、中间粘合部件175h和封装凸块190h。下连接器160h、中间连接器170h、中间粘合部件175h和封装凸块190h可以参照图2B至2G以及对它们的描述来理解。
图3A和3B是根据本发明构思实施例的包括芯片连接器的装置的示意性纵向截面图。
参照图3A，装置200a可以包括下半导体封装205L、上半导体封装205U以及配置来电连接下半导体封装205L和上半导体封装205U的封装间连接器250，下半导体封装205L包括具有芯片连接器281的下半导体芯片215L。上半导体封装205U堆叠在下半导体封装205L上。下半导体封装205L可以包括下塑封料230La，下塑封料230La暴露下半导体芯片215L的顶表面。芯片连接器281可以设置在下半导体芯片215L的顶表面上且物理和/或电连接到上封装衬底210U的底表面。芯片连接器281可以电连接下半导体芯片215L和上半导体芯片215U。下半导体芯片215L可以包括垂直地穿过主体形成的穿透硅通孔(TSV)280。TSV 280可以电连接芯片凸块220和芯片连接器281。尽管示出芯片连接器281与芯片凸块220对准，但是芯片连接器281可以不与芯片凸块220对准。在一示范性实施例中，重分布互连可以形成在下半导体芯片215L上从而电连接芯片凸块281和TSV 280。
芯片连接器281可以传输时钟信号、指令信号、地址信号和/或数据信号。封装间连接器250可以传输电源电压、地电压和/或测试信号。在一示范性实施例中，芯片连接器281可以传输电源电压或地电压，封装间连接器250可以传输有效信号。根据示范性实施例，芯片连接器281可以传输地电压，封装间连接器250可以传输电源电压。根据示范性实施例，当下半导体芯片215L是逻辑器件且上半导体芯片215U是存储器件时，芯片连接器281可以电连接下半导体芯片215L的屏蔽接地互连和上半导体芯片215U的接地互连线。屏蔽接地互连可以设置于逻辑器件中的信号传输线之间。屏蔽接地互连可以防止或减少通过信号传输线传输的电信号的干扰。在示范性实施例中，地电压可以通过封装间连接器250传输。在示范性实施例中，芯片连接器281和封装间连接器250可以进行不同信号传输功能。
芯片连接器281可以包括焊料材料。
参照图3B，装置200b可以包括下半导体封装205L、上半导体封装205U、以及配置来电连接下半导体封装205L和上半导体封装205U的封装间连接器250，下半导体封装205L包括具有芯片连接器281的下半导体芯片215L。上半导体封装205U堆叠在下半导体封装205L上。下半导体封装205L可以包括下塑封料230Lb，下塑封料230Lb覆盖下半导体芯片215L的顶表面。下塑封料230Lb可以围绕芯片连接器281的底表面和/或侧表面。换言之，下塑封料230Lb暴露部分芯片连接器281。
图4是根据本发明构思实施例的装置的示意性纵向截面图。
参照图4，装置300可以包括下半导体封装305L、上半导体封装305U、以及配置来电连接下半导体封装305L和上半导体封装305U的封装间连接器350，下半导体封装305L包括下封装衬底310L和下半导体芯片315L。上半导体封装305U堆叠在下半导体封装305L上。下封装衬底310L和下半导体芯片315L可以通过结合导线340L彼此电连接。根据示范性实施例，下半导体封装305L和上半导体封装305U的每个可以包括存储器件。也就是说，下半导体芯片315L和上半导体芯片315U的每个可以是存储器件。在示范性实施例中，每个封装间连接器350可以包括下连接器360和上连接器380。也就是说，每个封装间连接器350可以包括至少两个组元的堆叠结构。在示范性实施例中，下连接器360可以小于上连接器380。在示范性实施例中，下连接器360和上连接器380之间的边界(或者尖端(cusp)或腰部(waist))可以设置在下半导体芯片315L的顶表面之下。根据示范性实施例，当下连接器360的尺寸减小且上连接器380的尺寸增大时，封装间连接器350的布置可以更精细，使得每个封装间连接器之间的距离更靠近。
参照图4描述的装置也可以应用到参照图2B至3B描述的各种装置100b至100h、200a和200b。换言之，图2A至3B的各种封装连接器150a至150h、250和250中的每个可以包括上组元和下组元，下组元可以形成在下半导体芯片的顶表面之下。上组元可以包括上连接器180a至180e和280或者封装凸块190f至190h。下组元可以选择性地包括下连接器160a、160b、160d至160f、160h和260，底连接器165c和165g，中间连接器170d至170e和170h，和/或中间粘合部件175e、175g和175h。在实施例中，当下组元的最大高度低于下半导体芯片315L的顶表面的高度时，上组元的最大高度可以增大。随着上组元的高度增大，形成半导体封装的装置100b至100h、200a和200b的工艺可以稳定化。
图5A至5D是根据本发明构思实施例的芯片连接器及其连接结构的示意性纵向截面图。图5A至5D示出芯片连接器形成在下半导体芯片和上封装衬底之间，下半导体芯片的顶表面被暴露。
参照图5A，芯片连接器281可以包括在下半导体芯片215L和上封装衬底210U之间的单个球形体。芯片连接器281可以包括焊料材料。根据示范性实施例，下半导体芯片215L的侧表面可以被塑封料230围绕，下半导体芯片215L的顶表面可以被暴露。芯片连接器281可以电连接到TSV 280。芯片连接器281可以通过重分布互连279电连接到TSV 280。从平面图看，重分布互连279可以具有例如垫、条(bar)或线形状。垫可以电连接至少两个芯片连接器281或TSV 280。图5A的芯片连接器281、重分布互连279和/或TSV 280可以应用到图2A至2H的装置100a至100h。也就是说，装置100a至100h还可以包括芯片连接器281、重分布互连279和/或TSV 280。
参照图5B，包括下芯片连接器283和上芯片连接器284的芯片连接器282可以形成在下半导体芯片215L和上封装衬底210L之间。下芯片连接器283和上芯片连接器284可以包括焊料材料。下芯片连接器283可以参照图2A、2B、2D、2F和2H所示的下连接器160a、160b、160d、160e、160f和160h理解。上芯片连接器284可以参照图2A至2E的上连接器180a至180e理解。在一示范性实施例中，可以形成重分布互连279和TSV 280。
参照图5C，包括底芯片连接器286和上芯片连接器284的芯片连接器285可以形成在下半导体芯片215L和上封装衬底210U之间。底芯片连接器286可以形成为台或柱形。底芯片连接器286可以附着到下半导体芯片215L的一个表面。底芯片连接器286可以包括金属。底芯片连接器286可以参照图2C、2D、2E和2H所示的底连接器165c、165d、165e、165g和165h理解。上芯片连接器284可以参照图2A至2E和图5B的上连接器180a至180e理解。在一示范性实施例中，可以形成重分布互连279和TSV 280。
参照图5D，包括下芯片连接器283和芯片连接凸块288的芯片连接器287可以形成在下半导体芯片215L和上封装衬底210U之间。下芯片连接器283可以参照图2A、2B、2D、2E、2F和2H以及图5B的下连接器160a、160b、160d、160e、160f和160h来理解。芯片连接凸块288可以包括例如金属。芯片连接凸块288可以具有大头钉(stud)、棒(stick)或柱形。芯片连接凸块288可以利用额外工艺制造且固定到上封装衬底210U。芯片连接凸块288可以参照图2F、2G和2H的封装凸块190f、190g和190h来理解。在示范性实施例中，可以形成重分布互连279和TSV 280。
图6A至6D是根据本发明构思的实施例的芯片连接器及其连接结构的示意性纵向截面图。图6A至6D示出芯片连接器形成在下半导体芯片和上封装衬底之间，下半导体芯片的顶表面部分或完全覆盖有下塑封料。现在将示出和描述的各种芯片连接器可以具有与图2A至2H的封装间连接器150a至150h和/或图5A至5D的芯片连接器281、282、285和287类似的结构形状。根据示范性实施例，芯片连接器的尺寸可以根据设计规范不同地确定。
参照图6A至6D，下塑封料230La可以覆盖下半导体芯片215L的顶表面。因此，芯片连接器281、282、285和287的底表面和侧表面可以被下塑封料230La部分或全部围绕。在一示范性实施例中，芯片连接器281、282、285和287的底表面和/或侧表面可以从下塑封料230La部分暴露。根据一示范性实施例，可以形成重分布互连279和TSV 280。
图7A至7D是根据本发明构思实施例的各种封装间连接器的示意性纵向截面图。基本圆化的或圆的形状是在进行回流工艺之前各种封装间连接器和/或芯片连接器的形状。
各种连接器可以指的是图1A至6D所示的各种封装间连接器和芯片连接器中的任一个或部分。
参照图7A，连接器50a可以包括下连接器60a和上连接器80a。在示范性实施例中，上连接器80a可以具有比下连接器60a更大的体积。在示范性实施例中，上连接器80a的垂直高度H1可以大于下连接器60a的垂直高度H2。在示范性实施例中，上连接器80a的水平宽度D1可以大于下连接器60a的水平宽度D2。从平面图或截面图看，水平宽度D1和D2可以分别理解为上连接器80a和下连接器60a的直径。在示范性实施例中，上连接器80a的半径或曲率r1可以大于下连接器60a的半径或曲率r2。下连接器60a和上连接器80a可以包括焊料材料。因此，下连接器60a和上连接器80a可以利用焊接工艺形成，上连接器80a和下连接器60a可以具有球形或半球形。
参照图7B，连接器50b可以包括下连接器60b和上连接器80b，上连接器80b可以具有比下连接器60b更大的体积。下连接器60b的假想中心C1可以设置在与底表面10相同的水平。假想中心C1可以理解为下连接器60b的假想半径或曲率r3的中心。下连接器60b和上连接器80b可以包括焊料材料。在示范性实施例中，下连接器60b可以具有半球形状。
参照图7C，连接器50c可以包括下连接器60c和上连接器80c。在示范性实施例中，上连接器80c可以具有比下连接器60c更大的体积。下连接器60c的假想中心C2可以在比底表面10更低的水平。假想中心C2可以理解为下连接器60c的假想半径或曲率r4的中心。
参照图7D，连接器50d可以包括下连接器60d和上连接器80d，上连接器80d可以具有比下连接器60d更大的体积。下连接器60d的假想中心C3可以在比底表面10更高的水平。假想中心C3可以理解为下连接器60d的假想半径或曲率r5的中心。
根据本发明构思的实施例，上连接器80a至80d可以形成得高于，宽于且大于下连接器60a至60d。根据示范性实施例，下连接器60a至60d可以利用丝网印刷工艺或焊接工艺(soldering process)形成。根据示范性实施例，上连接器80a和80b可以利用焊接工艺形成。根据示范性实施例，连接上连接器80a至80d与下连接器60a至60d的工艺可以在利用激光钻孔工艺形成的通孔内进行。通孔的形成可以包括选择性去除塑封料从而部分暴露下连接器60a至60d的表面。与丝网印刷工艺相比，激光钻孔工艺能够形成更精细且更等距离隔开的通孔。因此，激光钻孔工艺可以进行来实现连接器50a的精巧布置。随着下连接器60a至60d的尺寸减小，丝网印刷工艺可能不有助于精巧布置下连接器60a至60d，随着上连接器80a至80d的尺寸增大，激光钻孔工艺可以有助于精巧地布置上连接器80a至80d。因此，上连接器80a至80d可以具有比下连接器60a至60d更大的尺寸，从而使连接器50a至50d更精巧。例如，连接器能形成得在它们之间有基本相等的距离。例如，更多连接器可以以形成在给定区域中。在示范性实施例中，在进行回流工艺以分别连接下连接器60a至60d与上连接器80a至80d之前，上连接器80a至80d可以浸在助熔剂(flux)中。足量助熔剂可以施加到上连接器80a至80d的表面从而回流工艺能稳定进行。换言之，随着上连接器80a至80d的尺寸增大，大量助熔剂可以施加到上连接器80a至80d的表面。因此，上连接器80a至80d可以形成至最大可能尺寸，同时最小化上连接器80a至80d之间的距离。通常，上封装衬底110U可以是不平的。在半导体封装制造工艺期间，上封装衬底110U可以不保持平坦。也就是说，上封装衬底110U可以弯曲。因此，当上连接器80a至80d没有形成得具有足够大的尺寸时，足量助熔剂可能没有施加到上连接器80a至80d的表面。因此，根据本发明构思的示范性实施例，上连接器80a至80d形成得具有比下连接器60a至60d更大的尺寸。
图8A至8I是根据本发明构思的实施例的封装堆叠结构的各种连接器的形状。这里，形状可以理解为各组元的最终形成的形状。各种连接器可以指的是图1A至6D所示的各种封装间连接器和芯片连接器的任一个或部分。一般地，连接器的这些形状在回流工艺之后产生。当下连接器形成在衬底上时，能使用回流工艺。当上连接器形成在衬底上时，能使用回流工艺。当下连接器和上连接器结合时，能使用回流工艺。
参照图8A，连接器51a可以包括腰部Wa且形成得物理和/或电连接下焊区(land)12a和上焊区17a。腰部Wa指的是连接器51a的纤细部分。腰部Wa可以将连接器51a假想地和/或视觉上分为上部和下部。换言之，腰部Wa可以将连接器51a分为上连接器81a和下连接器61a。上连接器81a的最大宽度Da1可以大于下连接器61a的最大宽度Da2。腰部Wa的宽度Da3可以小于下连接器61a的最大宽度Da2。因此，腰部Wa指的是具有最小宽度Da3的部分，其插置于下连接器61a的最大宽度Da2和上连接器81a的最大宽度Da1之间。上连接器81a的高度Ha1可以定义为上焊区17a或部分覆盖上焊区17a的上绝缘材料18a的表面与腰部Wa之间的距离。下连接器61a的高度Ha2可以定义为下焊区12a或部分覆盖下焊区12a的下绝缘材料13a的表面与腰部Wa之间的距离。上连接器81a的高度Ha1可以大于下连接器61a的高度Ha2。在实施例中，上连接器81a可以具有比下连接器61a更大的体积。在实施例中，上连接器81a的最大宽度Da1可以设置在上连接器81a的中部以上。腰部Wa可以沿水平方向形成。上连接器81a和下连接器61a可以包括焊料材料。上连接器81a和下连接器61a可以具有球形或半球形。因此，从平面面或截面图看，水平宽度Da1、Da2和Da3可以指的是圆的直径。
参照图8B，连接器51b可以包括腰部Wb，上连接器81b通过腰部Wb与下连接器61b分开，下连接器61b的假想中心C可以设置在比下焊区12b的表面更低的水平。可以参照图8A理解下连接器61b的假想中心C可以设置在比下焊区12b的表面更高的水平的情况。上连接器81b的最大宽度Db1可以大于腰部Wb的宽度Db2。上连接器81b的高度Hb1可以大于下连接器61b的高度。
参照图8C，连接器51c可以包括台形底连接器61c和球形上连接器81c，上连接器81c的高度Hc1可以大于底连接器61c的高度Hc2。上连接器81c的最大宽度Dc1可以大于底连接器61c的宽度Dc2。台形底连接器61c的部分顶表面可以不接触上连接器81c。也就是说，台形底连接器61c可以被暴露。
参照图8D，连接器51d可以包括球形或半球形下连接器61d、台形中间连接器71d和球形上连接器81d。上连接器81d的高度Hd1可以大于中间连接器71d的高度Hd2或者下连接器61d的高度Hd3。在实施例中，上连接器81d的高度Hd1可以大于中间连接器71d的高度Hd2和下连接器61d的高度Hd3的总和(Hd2+Hd3)。上连接器81d的最大宽度Dd1可以大于底连接器61d的宽度Dd2。中间连接器71d的部分顶表面可以不接触上连接器81d。也就是说，中间连接器71d的部分顶表面可以被暴露。中间连接器71d的侧表面的下部分可以被下连接器61d部分覆盖。
参照图8E，连接器51e可以包括下连接器61e、中间连接器71e、中间粘合单元76e和上连接器81e。上连接器81e和中间粘合单元76e可以基于腰部We视觉上彼此区分开。上连接器81e的最大宽度可以大于中间粘合单元76e的最大宽度De2。中间粘合单元76e的最大宽度可以大于腰部We的宽度。各组元的高度可以不同地确定。例如，尽管示出上连接器81e具有最大高度，但是本发明构思不限于此。当连接器51e具有多层结构时，各组元的相对高度、宽度或尺寸可以不同地应用。
参照图8F，连接器51f可以包括下连接器61f和凸块部分81f。凸块部分81f可以包括具有大头针或柱形状的金属。凸块部分81f的高度Hf1可以大于下连接器61f的高度Hf2。凸块部分81f的侧表面的下部分可以覆盖有下连接器61f。下连接器61f可以形成为球形或半球形。下连接器61f的假想中心可以设置在下焊区12f的表面之上或之下。
参照图8G，连接器51g可以包括底连接器66g、中间粘合单元76g和凸块部分91g。凸块部分91g的高度Hg1可以大于中间粘合单元76g的高度Hg2或底连接器66g的高度Hg3。
参照图8H，连接器51h可以包括下连接器61h、中间连接器71h、中间粘合单元76h和凸块部分91h。凸块部分91h的高度Hh1可以大于中间粘合单元76h的高度Hh2、中间连接器71h的高度Hh3或者下连接器61h的高度Hh4。
参照图8I，连接器51i可以包括腰部Wi，上连接器81i通过腰部Wi与下连接器61i分开，下连接器61i可以包括具有平坦部分SWi的侧壁。平坦部分SWi可以对应于下连接器61i的部分侧壁。平坦部分SWi可以延伸到下连接器61i的底部。
图8A至8I的上焊区17a至17i可以包括在图2A至2H、3A和/或3B的上封装105U和205U中，下焊区12a至12h可以包括在下封装105L和205L或者下半导体芯片115L和215L中。
图9A至9I是在根据本发明构思的实施例的装置中的各种连接器和通孔的形状。
参照图9A，连接器52a可以包括下连接器62a和上连接器82a，上连接器82a可以形成在通孔Va内，通孔Va配置来部分暴露下连接器62a的表面。通孔Va的底端Vla的宽度Dva可以小于下连接器62a的最大宽度Dla。间隙Ga可以形成在通孔Va和腰部Wa之间。
参照图9B，连接器52b可以包括下连接器62b和上连接器82b，上连接器82b可以形成在通孔Vb内，通孔Vb配置来基本或完全暴露下连接器62b的表面。下连接器62b可以包括具有平坦部分SWb的侧壁。通孔Vb的底端的宽度Dvb可以大于下连接器62b的底端的宽度Dlb。因此，间隙Gb1可以形成在通孔Vb与下连接器62b的底部之间。
参照图9C，连接器52c可以包括下连接器62c和上连接器82c，上连接器82c可以形成在通孔Vc内，通孔Vc配置来基本或完全暴露下连接器62c的表面。下连接器62c可以包括具有平坦部分SWc的侧壁。平坦部分SWc可以延伸到底表面23c。
间隙Ga、Gb和Gc可以形成在图9A至9C所示的连接器52a、52b和52c的腰部Wa、Wb和Wc与通孔Va、Vb和Vc的侧壁之间。通孔Va、Vb和Vc的侧壁可以倾斜使得通孔Va、Vb和Vc的直径可以朝向其下部减小。通孔Va、Vb和Vc的侧壁可以分别以不同角度倾斜。例如，考虑到通孔Va、Vb和Vc以及其它相邻连接器之间的间隔或节距，通孔Va、Vb和Vc的倾斜侧壁中的每个可以确定在约10°至约30°的角度。通孔Va、Vb和Vc可以垂直穿透塑封料32a、32b和32c且部分暴露下连接器62a、62b和62c的顶表面和/或侧表面或者下绝缘材料23a、23b和23c的表面。
参照图9D，连接器52d可以包括下连接器62d、台形连接器67d和上连接器82d，上连接器82d可以形成在通孔Vd内，通孔Vd配置来部分暴露台形连接器67d的表面。通孔Vd的底端的宽度Dvd可以大于台形连接器67d的水平宽度Dmd。间隙Gd可以形成在台形连接器67d的部分表面上。
参照图9E，连接器52e可以包括下连接器62e、台形连接器67e和上连接器82e，上连接器82e可以形成在通孔Ve内，通孔Ve配置来部分暴露台形连接器67e的侧表面。通孔Ve的底端的宽度Dve可以等于台形连接器67e的水平宽度。间隙Ge可以形成在台形连接器67e的部分侧表面与通孔Ve的侧壁之间。
参照图9F，连接器52f可以包括下连接器62f、台形连接器67f和上连接器82f，上连接器82f可以形成在通孔Vf内，通孔Vf配置来完全暴露台形连接器67f的侧表面。通孔Vf可以部分暴露下连接器62f的顶表面。间隙Gf可以形成在台形连接器67f的部分侧表面与通孔Vf的侧壁之间。
根据实施例，在图9D至9F中，通孔Vd、Ve和Vf的侧壁可以倾斜，使得通孔Vd、Ve和Vf的直径可以朝向其下部减小。通孔Vd、Ve和Vf可以垂直穿透塑封料32d、32e和32f且部分或完全暴露台形连接器67d、67e和67f的顶表面和/或侧表面。
参照图9G，连接器52g可以包括下连接器62g、台形连接器67g、中间连接器77g和上连接器82g。上连接器82g可以形成在通孔Vg内，通孔Vg配置来部分暴露中间连接器77g的表面。间隙Gg可以形成在中间连接器77g的部分表面与通孔Vg的侧壁之间。
参照图9H，连接器52h可以包括下连接器62h、台形连接器67h、中间连接器77h和上连接器82h。上连接器82h可以形成在通孔Vh内，通孔Vh配置来部分暴露台形连接器67h的表面。通孔Vh还可以暴露台形连接器67h的部分侧表面。间隙Gh可以形成在台形连接器67h的部分表面与通孔Vh的侧壁之间。
参照图9I，连接器52i可以包括下连接器62i、台形连接器67i、中间连接器77i和上连接器82i。上连接器82i可以形成在通孔Vi内，通孔Vi配置来部分暴露下连接器62i的表面。间隙Gi可以形成在下连接器62i的部分表面与通孔Vi的侧壁之间。
根据实施例，在图9G至9I中，通孔Vg、Vh和Vi的侧壁可以倾斜，使得通孔Vg、Vh和Vi的直径可以朝向其下部减小。通孔Vg、Vh和Vi可以垂直穿透塑封料32g、32h和32i且部分或完全暴露中间连接器77h的表面，部分或完全暴露台形连接器67h的表面，以及部分或完全暴露下连接器62h的表面。间隙Gb1和Ga至Gi可以指的是气隙。
图10A至10F是示出根据本发明构思的实施例形成上封装的工艺的示意性纵向截面图。
参照图10A，可以制备包括上焊区155U和导线垫145的上封装衬底110U。上焊区155U可以分别电连接到导线垫145。上焊区155U和导线垫145可以利用例如丝网印刷工艺、沉积工艺、结合工艺或镀工艺形成。
参照图10B，多个上半导体芯片115U可以安装在上封装衬底110U上。绝缘粘合剂可以插设于上封装衬底110U和上半导体芯片115U之间。上半导体芯片115U可以包括结合垫135。
参照图10C，结合垫135可以利用结合导线140电连接到导线垫145。
参照图10D，上塑封料130U可以形成得覆盖多个上半导体芯片115U并且分开到所述多个上半导体芯片115U中。上塑封料130U可以包括环氧树脂或聚酰亚胺。上塑封料130U的分开可以利用例如锯开工艺或切割工艺进行。
参照图10E，上半导体封装105U可以被上下翻转，上连接器180可以分别形成在上焊区155U上。
根据本发明构思的示范性实施例，参照图10F，封装凸块190可以分别形成在上焊区155U上。
图11A至11I示出制造根据本发明构思实施例的装置的方法。
参照图11A，下焊区155L可以形成在下封装衬底110L上。下焊区155L可以利用丝网印刷技术形成。备选地，下焊区可以利用沉积技术、结合技术、镀技术或喷墨技术形成。在实施例中，芯片凸块焊区121可以利用与形成下焊区155L的工艺相同或不同的工艺形成。也就是说，下焊区155L和芯片凸块焊区121可以形成在下封装衬底110L上。
参照图11B，导电芯片凸块120可以形成在下封装衬底110L上。导电芯片凸块120可以利用丝网印刷工艺、喷墨工艺或焊接工艺形成。导电芯片凸块120可以分别电连接到芯片凸块焊区121。
参照图11C，下连接器160可以形成在下焊区155L上。下连接器160可以利用例如丝网印刷技术、喷墨技术或焊接技术形成。下连接器160可以在形成导电芯片凸块120期间形成。换言之，导电芯片凸块120和下连接器160可以同时形成。尽管图11C示出下连接器160可以形成在与导电芯片凸块120大约相同的水平，但是本发明构思不限于此。下连接器160可以形成在比导电芯片凸块120足够更高的水平。当导电芯片凸块120和下连接器在相同的水平时，导电芯片凸块120和下连接器160同时形成。此外，当导电芯片凸块120和下连接器160在不同的水平时，导电芯片凸块120和下连接器160利用不同的工艺形成。
参照图11D，下半导体芯片115L可以安装在导电芯片凸块120上。下半导体芯片115L可以形成为倒装芯片形且可以是逻辑器件。下连接器160可以在安装下半导体芯片115L之前形成。例如，当下连接器160利用丝网印刷技术形成时，下连接器160可以在安装下半导体芯片115L之前形成。然而，当下连接器160利用焊接技术形成时，下连接器160的形成可以在安装下半导体芯片115L之后进行。
参照图11E，塑封控制膜135可以形成在下半导体芯片115L上。塑封控制膜135可以紧密粘合到下半导体芯片115L的顶表面。在塑封控制膜135和下封装衬底110L之间可以确保空间。空间可以确保在塑封控制膜135和下连接器160的表面之间。塑封控制膜135可以是带，包括例如纤维素、醋酸盐(acetate)、聚乙烯(polyvinyl)或聚亚安酯。
参照图11F，塑封控制膜135与下封装衬底110L之间的空间可以用下塑封料130L填充。下塑封料130L可以形成得覆盖下封装体160，围绕下半导体芯片115L的侧表面，且填充塑封控制膜135之下的区域。下塑封料130L可以仅形成在半导体芯片凸块120周围。换言之，下塑封料130L可以仅填充下封装衬底110L与下半导体芯片115L之间的空间。也就是说，下半导体芯片115L的侧表面可以暴露到空气。在实施例中，下塑封料130L可以是绝缘粘合剂。备选地，下半导体芯片115L的下部侧表面可以被下塑封料130L围绕，而其上部侧表面可以暴露到空气。在实施例中，下塑封料130L可以覆盖下连接器160的表面。换言之，下塑封料130L可以半填充(fill half)塑封控制膜135与下封装衬底110L之间的空间。
参照图11G，可以去除塑封控制膜，并可以进行激光钻孔工艺以暴露下连接器160的表面。在激光钻孔工艺期间，下塑封料130L可以被选择性去除，开口O可以形成为部分或完全暴露下连接器160的表面。下连接器160的顶表面与塑封料130L的顶表面之间的距离可以大于下封装衬底110L的表面与下连接器160的顶表面之间的距离。备选地，开口O的空间可以大于下连接器160的体积。当将开口O视为通孔时，通孔的内部空间可以大于下连接器160的体积。在实施例中，根据垂直长度、水平最大宽度和最大直径中的任一项，开口O的空间或者通孔的内部空间可以大于下连接器160的体积。
参照图11H，焊料球125可以形成在下封装衬底110L的底表面上。焊料球125可以分别电连接到导电芯片凸块120。焊料球125可以利用焊接工艺形成。根据本发明构思的实施例，形成焊料球125的工艺可以在激光钻孔工艺之前进行。
参照图11I，下封装衬底110L和下塑封料130L可以分离成单个下半导体封装105L。该分离工艺可以利用例如锯工艺、钻工艺(drilling process)或切割工艺进行。
参照图11J，图10E的上半导体封装105U的上连接器180可以浸到容纳在容器T中的焊料助熔剂F中。在实施例中，容器T的顶表面可以接触或靠近上封装衬底110U的表面。容器T的顶表面可以用来确定上连接器180浸入到焊料助熔剂F中的深度。在实施例中，当上连接器180具有足够大的尺寸时，上连接器180可以充分浸入在焊料助熔剂F中。随着上连接器180的尺寸增大，上连接器180浸入在焊料助熔剂F中的表面积亦增大。这样，能够改善上连接器180与下连接器160之间的物理或电连接。上连接器180的尺寸或表面积可以指的是形成在上封装衬底110U的表面上的上连接器180的高度。根据本发明构思的实施例，上连接器180可以形成得尺寸或表面积大于下连接器160。根据实施例，提供了在物理和电方面上更稳定的连接结构。上封装衬底110U可以具有稍微或基本扭曲或弯曲的形状。上封装衬底110U可以在制造期间弯曲。当上连接器180没有形成得具有足够大尺寸时，一些上连接器180不能浸入在焊料助熔剂F中，或者上封装衬底110U的表面会接触焊料助熔剂F。这样，上封衬底110U的表面会被污染。因此，当根据本发明构思实施例的上连接器180形成得具有足够大尺寸时，可以充分去除由于上封装衬底110U的翘曲引起的不稳定因素。
参照图11K，上半导体封装105U和下半导体封装105L可以被堆叠。上连接器180的表面充分附着有液体F。在实施例中，下连接器160和上连接器180可以被加热且在压力下在开口O中彼此接合并且物理和电地彼此结合和/或连接。这里，结合下连接器160和上连接器180可以理解为一体地形成下连接器160和上连接器180。
参照图11L，图10F的上半导体封装105U的封装凸块190可以浸入在焊料助熔剂F中。随后的工艺可以参照图11K理解。
在焊接工艺期间，焊料材料可以由于表面张力而具有球形。因此，当组元被描述或示出为球形或半球形时，组元可以利用焊接工艺形成。本领域技术人员参照以上附图和对附图的描述可以理解，下连接器160和上连接器180可以以各种形状形成。
图12A和12B是包括根据本发明构思的实施例形成的装置的半导体模块的示意图。
参照图12A和12B，半导体模块500a和500b中的每个可以包括模块板510a或510b以及安装在模块板510a或510b上的多个半导体器件520。多个半导体器件520中的至少一个可以包括根据本发明构思的实施例的装置。模块板510a和510b中的每个可以是PCB。半导体模块500a或500b可以包括形成在模块板510a或510b的侧表面中的多个接触端子530。每个接触端子530可以电连接到半导体器件520。
图13是包括根据本发明构思的实施例的装置的电子系统的示意图。
参照图13，根据示范性实施例，电子系统600可以包括控制单元610、输入单元620、输出单元630、存储单元640和通讯单元650。
控制单元610可以同时控制电子系统600和各组元。控制单元610可以是中央处理单元(CPU)或主控制单元(MCU)且包括根据本发明构思的实施例的半导体模块500。控制单元610可以包括根据本发明构思的实施例的半导体封装的堆叠结构。
输入单元620可以传输电指令信号到控制单元610。输入单元620可以包括例如键盘、键板、鼠标、触摸板、图像识别器例如扫描仪、或者各种输入传感器之一。输入单元620可以包括根据本发明构思的实施例的半导体封装的堆叠结构。
输出单元630可以接收来自控制单元610的电指令信号且输出电子系统600的处理结果。输出单元630可以包括例如监视器、打印机或束发射器。输出单元630可以包括根据本发明构思的实施例的半导体封装的堆叠结构。
存储单元640可以是配置来临时或永久存储即将被控制单元610处理或者已经被控制单元610处理的电信号的组元。存储单元640可以物理且电地连接到控制单元610或者与控制单元610组合。存储单元640可以包括例如半导体存储器、磁存储器例如硬盘、以及光学存储器例如光盘、或者具有数据存储功能的服务器。存储单元640可以包括根据本发明构思的实施例的半导体封装的堆叠结构。
通讯单元650可以接收来自控制单元610的电指令信号且传输电信号到另一电子系统或者接收来自另一电子系统的电信号。通讯单元650可以包括例如有线收发器件例如调制解调器或局域网(LAN)卡、无线收发器例如无线宽带(WiBro)接口、或者红外(IR)端口。通讯单元650可以包括根据本发明构思的实施例的半导体封装的堆叠结构。
根据本发明构思的实施例的电子系统600可以包括例如计算机、网络服务器、网络打印机、扫描仪、无线控制器、移动通讯终端、开关系统或能编程操作的任何电子器件。
根据如上所述的本发明构思的实施例，半导体封装的堆叠结构可以包括封装间连接器，即使当封装间连接器之间的距离基本较小时，封装间连接器也能稳定地形成。
尽管这里已经参照附图描述了本发明的示范性实施例，但是将理解，本发明不应局限于这些精确的实施例，相关领域的普通技术人员可以在实施例中实现各种其它改变和修改而不偏离本发明的范围或思想。所有这样的改变和修改旨在包括在本发明的由权利要求书限定的范围内。

Claims (30)

1.一种装置，包括：
第一衬底，具有第一焊区；
第二衬底，具有第二焊区；
第一塑封料，设置于所述第一衬底和所述第二衬底之间；
第一半导体芯片，设置于所述第一衬底上且接触所述第一塑封料；
第一连接器，接触所述第一焊区；以及
第二连接器，接触所述第二焊区，该第二连接器设置在所述第一连接器上，
其中所述第二连接器的体积大于所述第一连接器的体积，所述第一半导体芯片的表面被暴露，所述第一塑封料接触所述第二连接器，所述第二连接器的至少一部分被所述第一塑封料围绕。
2.如权利要求1所述的装置，其中所述第一连接器设置在所述第一塑封料中。
3.如权利要求2所述的装置，其中所述第二连接器的一部分不设置在所述第一塑封料中。
4.如权利要求1所述的装置，还包括：
第二半导体芯片，设置在所述第二衬底上。
5.如权利要求4所述的装置，还包括：
第二塑封料，接触所述第二半导体芯片。
6.如权利要求1所述的装置，其中所述第一衬底和所述第二衬底包括印刷电路板或者陶瓷衬底。
7.如权利要求1所述的装置，其中所述第一连接器和所述第二连接器配置来传输功率或信号。
8.如权利要求4所述的装置，其中所述第一半导体芯片包括逻辑器件，所述第二半导体芯片包括存储器件。
9.如权利要求1所述的装置，其中所述第一连接器和所述第二连接器是焊料球。
10.如权利要求1所述的装置，其中所述第一半导体芯片包括在其中的多个垂直穿透硅通孔。
11.如权利要求1所述的装置，还包括：
第三连接器，设置在所述第一连接器和所述第二连接器之间。
12.一种电子系统，包括：
控制单元；
输入单元，配置来传输电信号到所述控制单元；
输出单元，配置来接收来自所述控制单元的电信号且输出所述电子系统的处理结果；
存储单元，配置来存储即将被所述控制单元处理或者已经被所述控制单元处理的数据；以及
通讯单元，配置来接收来自所述控制单元的电信号且传输电信号到另一电子系统或者接收来自另一电子系统的电信号，
其中所述控制单元、所述输入单元、所述输出单元、所述存储单元和所述通讯单元中的至少一个包括权利要求1所述的装置。
13.如权利要求12所述的电子系统，其中所述控制单元包括：
中央处理单元、主控制单元和半导体模块中的至少一种。
14.如权利要求12所述的电子系统，其中所述输入单元包括：
键盘、键板、鼠标、触摸板和图像识别器中的至少一种。
15.如权利要求12所述的电子系统，其中所述输出单元包括：
监视器、打印机和束发射器中的至少一种。
16.如权利要求12所述的电子系统，其中所述存储单元包括：
半导体存储器、磁存储器件、光学存储器件和具有数据存储功能的服务器中的至少一种。
17.如权利要求12所述的电子系统，其中所述通讯单元包括：
有线收发器、无线收发器和红外端口中的至少一种。
18.如权利要求12所述的电子系统，其中所述电子系统是计算机、网络服务器、网络打印机、扫描仪、无线控制器、移动通讯终端、开关系统、或者能编程操作的任何电子器件。
19.一种方法，包括：
在第一衬底上设置第一半导体芯片；
在所述第一衬底的焊区上设置第一连接器；
将第一塑封料置于所述第一衬底上且接触所述第一半导体芯片和所述第一连接器；
暴露所述第一衬底的表面；以及
形成穿过所述第一塑封料的开口以暴露所述第一连接器的一部分。
20.如权利要求19所述的方法，还包括：
在第二衬底上设置第二连接器和第二半导体芯片，并将所述第一连接器耦接到所述第二连接器。
21.如权利要求20所述的方法，其中所述第二连接器具有比所述第一连接器更大的体积。
22.如权利要求20所述的方法，还包括：
设置第二塑封料接触所述第二半导体芯片和所述第二连接器。
23.如权利要求20所述的方法，还包括：
将所述第二连接器浸入到焊料助熔剂中。
24.如权利要求20所述的方法，其中所述第一连接器和所述第二连接器是焊料球。
25.如权利要求20所述的方法，其中所述第二连接器具有比所述第一连接器更大的半径。
26.一种方法，包括：
在第一衬底上设置第一半导体芯片和第一焊料球；
将塑封料置于所述第一衬底上且接触所述第一半导体芯片和所述第一焊料球；
形成穿过所述塑封料的开口从而暴露所述第一焊料球的一部分；
在第二衬底上设置第二半导体芯片和第二焊料球；以及
将所述第一焊料球耦接到所述第二焊料球，
其中所述第二焊料球的半径大于所述第一焊料球的半径。
27.如权利要求26所述的方法，还包括：
暴露所述第一衬底的表面。
28.如权利要求26所述的方法，其中所述第二焊料球具有比所述第一焊料球更大的体积。
29.如权利要求26所述的方法，还包括：
设置第二塑封料接触所述第二半导体芯片和所述第二焊料球。
30.如权利要求26所述的方法，还包括：
将所述第二焊料球浸入焊料助熔剂中。
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