CN103996630A - 封装半导体器件和封装器件及方法 - Google Patents

封装半导体器件和封装器件及方法 Download PDF

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Publication number
CN103996630A
CN103996630A CN201310188263.5A CN201310188263A CN103996630A CN 103996630 A CN103996630 A CN 103996630A CN 201310188263 A CN201310188263 A CN 201310188263A CN 103996630 A CN103996630 A CN 103996630A
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spherical
conductor
substrate
integrated circuit
face
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CN103996630B (zh
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林俊成
蔡柏豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了封装半导体器件和封装器件及方法。在一个实施例中，一种封装半导体器件的方法包括提供第一集成电路管芯，该第一集成电路管芯与包括多个设置在其上的衬底通孔(TSV)的衬底的第一表面相连接。导体球状件与衬底的第二表面上的多个TSV中的每个相连接，第二表面与衬底的第一表面相反。第二集成电路管芯与衬底的第二表面相连接，并且模塑料形成在导体球状件、第二集成电路管芯和衬底的第二表面之上。模塑料被从导体球状件的顶面上去除，并且导体球状件的顶面被形成凹部。在导体球状件的顶面和模塑料上方形成有再分配层(RDL)。

Description

封装半导体器件和封装器件及方法
相关申请的交叉参考
本发明涉及以下共同待决和共同受让的专利申请，该专利申请的全部公开内容通过引用结合到本文中：2013年1月29日提交的第13/753,204号专利申请“A PoP Device”。
技术领域
本发明涉及半导体领域，更具体地，本发明涉及一种封装半导体器件和封装器件及方法。
背景技术
半导体器件被使用在各种电子应用，诸如，个人计算机、手机、数码相机，以及其他电子设备中。通常通过在半导体衬底上方连续地沉积绝缘或介电层、导电层、以及半导体材料层，并且使用光刻图案化各种材料层从而形成电路部件及其上的元件来制造半导体器件。通常在一个半导体晶圆上制造有数十或数百个集成电路并且通过在两个集成电路之间沿着切割线进行切割来将晶圆上的各个管芯切割成单个的。通常是在例如，多芯片模式下或其他类型的封装方式下分别封装各个管芯。
半导体工业通过允许将更多部件集成到给定区域上的最小尺寸的不断减小来持续地改进各个电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成密度。在一些应用中，这些更小的电子部件也需要比原来的封装件占据更少空间的更小的封装件。3DIC和封装件上封装件(PoP)器件是最近的一些设计，其中将多个管芯垂直堆叠在一个封装件中。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种封装半导体器件的方法，所述方法包括：提供第一集成电路管芯，所述第一集成电路管芯与衬底的第一表面相连接，所述衬底中设置有多个衬底通孔(TSV)；在所述衬底的第二表面上将导体球状件与所述多个TSV中的每一个相连接，所述第二表面相对于所述衬底的所述第一表面；将第二集成电路管芯与所述衬底的所述第二表面相连接；在所述导体球状件、所述第二集成电路管芯和所述衬底的所述第二表面之上形成模塑料；去除所述导体球状件的顶面上方的所述模塑料；使所述导体球状件的顶面凹陷；以及在所述导体球状件的顶面和所述模塑料之上形成再分配层(RDL)。
在所述方法中，去除所述导体球状件的顶面上方的所述模塑料进一步包括：去除设置在所述第二集成电路管芯上的导电凸块的顶面之上的所述模塑料。
在所述方法中使所述导体球状件的顶面凹陷进一步包括：使设置在所述第二集成电路管芯上的所述导电凸块的顶面凹陷。
在所述方法中形成所述RDL包括：将部分所述RDL与设置在所述第二集成电路管芯上的所述导电凸块相连接。
在所述方法中使所述导体球状件的顶面凹陷包括：蚀刻所述导体球状件。
在所述方法中去除所述模塑料包括：研磨所述模塑料。
在所述方法中形成所述RDL包括：将部分所述RDL与所述导体球状件相连接。
根据本发明的另一方面，提供了一种封装半导体器件的方法，所述方法包括：将第一集成电路管芯附接至载体晶圆，其中，所述第一集成电路管芯与衬底相连接，所述衬底中设置有多个衬底通孔(TSV)，所述衬底包括第一表面和与所述第一表面相对的第二表面，所述第一集成电路与所述衬底的所述第一表面相连接，所述多个TSV从所述衬底的所述第一表面延伸至所述第二表面；在所述衬底的所述第二表面上将第一导体球状件与所述多个TSV中的每一个相连接；将所述第二集成电路管芯与所述衬底的所述第二表面相连接；在所述第一导体球状件、所述第二半导体电路管芯和所述衬底的所述第二表面之上形成模塑料层；研磨所述模塑料层，以暴露出所述第一导体球状件的顶面；使所述第一导体球状件的顶面凹陷；在所述第一导体球状件的顶面和所述模塑料的顶面之上形成再分配层(RDL)；在所述RDL之上形成多个第二导体球状件；以及去除所述载体晶圆。
在所述方法中，使所述第一导体球状件的顶面凹陷包括：使所述第一导体球状件的顶面凹陷大约10μm或更小。
在所述方法中，研磨所述模塑料层包括：机械研磨所述模塑料层。
在所述方法中，研磨所述模塑料层的步骤在所述模塑料层的顶面上和所述第一导体球状件的顶面上留下了残留物。
在所述方法中，使所述导体球状件的顶面凹陷包括化学蚀刻工艺，并且所述化学蚀刻工艺将所述残留物从所述模塑料层的顶面和所述第一导体球状件的顶面上去除。
在所述方法中，研磨所述模塑料层的步骤暴露设置在所述第二集成电路管芯上的多个导电凸块的顶面，并且形成所述RDL包括：在所述第一导体球状件的顶面、所述模塑料层的顶面和所述多个导电凸块的顶面之上形成第一钝化层；图案化所述第一钝化层，暴露出所述第一导体球状件的顶面和所述多个导电凸块的顶面；在所述第一钝化层、所述第一导体球状件的顶面和所述多个导电凸块的顶面之上形成第一导电材料；图案化所述第一导电材料；在经过图案化的所述第一导电材料和所述第一钝化层之上形成第二钝化层；图案化所述第二钝化层；在经过图案化的所述第二钝化层之上形成第二导电材料；以及图案化所述第二导电材料。
在所述方法中，形成所述第一导电材料和图案化所述第一导电材料包括：形成所述RDL的接触件和扇出区域，其中，形成所述第二导电材料和图案化所述第二导电材料包括：形成球下金属化(UBM)结构，并且在所述RDL之上形成所述多个第二导体球状件包括：将所述多个第二导体球状件和所述UBM结构相连接。
根据本发明的又一方面，提供了一种封装器件，包括：衬底，包括设置在其中的多个衬底通孔(TSV)；导体球状件，与所述多个TSV中的每一个相连接；模塑料层，设置在所述衬底和部分所述导体球状件之上，其中，使所述导体球状件的顶面凹陷为低于所述模塑料层的顶面；以及再分配层(RDL)，设置在所述模塑料层之上，部分所述RDL与所述导体球状件的凹陷顶面相连接。
在所述封装器件中，所述导电球状件包括焊料、Cu或Cu核心。
根据本发明的又一方面，提供了一种封装半导体器件，包括上述封装器件，其中，所述衬底包括第一表面和与所述第一表面相对的第二表面，所述导体球状件与所述第一表面相连接，所述半导体器件包括与所述衬底的所述第一表面相连接的第一集成电路管芯，并且所述第一集成电路管芯的导电凸块与部分所述RDL相连接。
在所述封装半导体器件中，所述第一集成电路的所述导电凸块的顶面与所述模塑料层的顶面基本共面。
在所述封装半导体器件中，使所述第一集成电路管芯的所述导电凸块凹陷为低于所述模塑料的顶面。
在所述封装半导体器件中，进一步包括：与所述衬底的所述第二表面相连接的第二集成电路管芯。
附图说明
为了更全面地理解实施例及其优势，现将结合附图所进行的描述作为参考，其中：
图1至图13是示出了根据一些实施例封装集成电路管芯的方法的截面图；
图14和图15示出了图13中所示的封装半导体器件部分的更为详细的截面图；以及
图16是流程图，示出了根据一些实施例封装半导体器件的方法。
除非另行指出，否则不同附图中的相应的标号和标识涉及的是相应的部分。为了清楚地说明实施例的相关方面而绘制这些附图且不必按照比例绘制。
具体实施方式
下面，详细讨论本发明各实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式，而不用于限制本发明的范围。
本发明的一些实施例涉及的是封装半导体器件。在此将描述新式封装方法、封装器件以及封装的半导体器件。
图1至图13是示出了根据一些实施例封装集成电路管芯的方法的截面图。首先参考图1，提供给了部分封装的半导体器件100。部分封装的半导体器件100包括附接在中介层衬底102上的一个或更多第一集成电路管芯114a和114b。根据一些实施例，将利用第二封装电路管芯130(见图4)封装部分封装的半导体器件100。
再次参考图1，衬底102包括例如，硅衬底、硅或玻璃中介层、印刷电路板(PCB)、有机物复合衬底或其他类型的衬底。衬底102包括设置在其中的多个衬底通孔(TSV)104。TSV104从衬底102的第一面106延伸至衬底102的第二面108。TSV104包括导电材料并且提供了从衬底102的第一面106至第二面108的垂直电连接。接合焊盘110与衬底102的第一面106上的一个或更多TSV相连接，并且接触焊盘112与衬底102的第二面108上的一个或更多TSV相连接。
集成电路管芯114a与衬底102的集成电路管芯装配区域113中的衬底102相连接。集成电路管芯114a可以使用粘合、胶粘(tape)或其他方式附接在衬底102上。集成电路管芯114a使用引线接合116a与接合焊盘110电连接。集成电路管芯114b可以使用粘合、胶粘或其他方式附接在集成电路管芯114a的顶面上。集成电路管芯114b使用引线接合116b与接合焊盘110电连接。在附图中，出于简化目的将集成电路管芯114a和114b显示成与相同的接合焊盘110相连接，然而，在一些实施例中，集成电路管芯114a和114b分别与衬底102上的不同接合焊盘110相连接。
在一些实施例中，部分封装半导体器件100可以包括一个集成电路管芯114a，或部分封装半导体器件100可以包括两个堆叠半导体管芯114a和114b，它们可以包括不同的尺寸或相同的尺寸。集成电路管芯114a和114b可以包括例如，一个或更多半导体材料层，一个或更多导电材料层，一个或更多介电材料层，或它们的组合。模塑料118形成在垂直堆叠的集成电路管芯114a和114b之上，引线接合116a和116b之上，以及衬底102的暴露部分之上。
如图2所示，为了封装带有另一个集成电路管芯130的部分封装的半导体器件100而提供载体晶圆。在一些实施例中，载体晶圆120包括硅衬底、硅或玻璃中介层、PCB、有机复合衬底。可选地，载体晶圆120可以包括其他类型的晶圆或材料。粘合物被涂覆在载体晶圆120上。作为实例，粘合物120可以包括胶、复合涂层、薄膜或其他粘合物。如图3所示，图1中所示的部分封装半导体器件100(或其他类型的部分封装的集成电路)被翻转并且附接在载体晶圆120上的粘合物122上。多个部分封装半导体器件100附接在载体晶圆120上的粘合物122上且被处理，并且在封装工艺完成之后，将封装半导体器件单分出来(singulated)，这些将在此被进一步地描述。
也如图3所示，多个导体球状件124被附接在衬底102的第二面108上的接触焊盘112上。导体球状件124包括例如，焊料、Cu或其他共熔导电材料。在一些实施例中，如另一个实例，导体球状件124包括焊料、Cu或Cu核心。导体球状件124可以形成在例如，衬底102的周长周围或沿着衬底102的两个或更多面形成。导体球状件124可以形成在例如，围绕衬底102的第二面108上的集成电路装配区域126的周长的一个或更多行中。导体球状件124可以例如，形成在各种球栅阵列(BGA)布置中。可选地，导体球状件124和接触焊盘112可以被布置在其他配置中。
如图4所示，第二集成电路管芯130使用粘合物128附接在衬底102的集成电路管芯装配区域126上。集成电路管芯130包括多个设置在其上的导电凸块132。导电凸块132可以包括例如，焊料凸块、控制熔塌芯片连接(controlled collapse chip connection)(C4)凸块、Cu凸块或其他类型的共熔材料。
如图5所示，在第二集成电路管芯130、导体球状件124和衬底102的暴露部分之上形成有模塑料134。模塑料134包括绝缘材料，诸如，聚合物、成型底部填充材料，或其他绝缘体。模塑料134在此(例如，在一些权利要求中)还涉及了模塑料层134。
然后，如图6所示，使用研磨工艺136从导体球状件124的顶面上去除模塑料134的顶部。在一些实施例中，研磨工艺136还导致模塑料134被从集成电路130的导电凸块132的顶面上去除。在一些实施例中，研磨工艺136包括机械研磨工艺。可选地可以使用其他类型的研磨工艺136。去除模塑料134的顶部在一些实施例中包括，例如，研磨模塑料134。
在一些实施例中，研磨工艺136可能在模塑料134的顶面、导体球状件124和/或导电凸块132上留下残留物138。在其他实施例中，残留物138由于研磨工艺136不形成在例如，模塑料134的顶面上。残留物138可以包括例如，模塑料134、导体球状件124和/或导电凸块132的材料。残留物138可以包括例如，一种或更多导电和/或绝缘材料。在一些实施例中，残留物的至少一些部分包括SnOx。
然后，如图7所示，使用蚀刻工艺140形成导体球状件124的凹部。为了简化附图，图7和剩余的附图中仅仅示出了一个部分封装的半导体器件100和集成电路管芯130。蚀刻工艺140包括，例如，用来在导体球状件124中形成凹部而不在模塑料134中形成凹部的化学蚀刻工艺。在一些实施例中，蚀刻工艺140包括，例如，选择性蚀刻导体球状件124的材料的蚀刻工艺。在一些实施例中蚀刻工艺140可以包括软化学蚀刻(softchemical etch)，且可以包括例如，KOH、甲酸、H2SO4、HF和HNO3混合物或HClO4和H3COOH混合物，然而，可选地可以使用其他类型的蚀刻化学药剂。在一些实施例中，蚀刻工艺140在导体球状件124的顶面中形成凹部142。在导体球状件124的顶面形成凹部在一些实施例中包括例如，蚀刻导体球状件124。
图8中示出了形成在导体球状件124中的凹部142的更详细的截面图。在一些实施例中，在导体球状件124的顶面形成凹部包括，例如，在研磨工艺136之后在模塑料134以下以大约10μm或更小的尺寸d1在第一导体球状件的顶面形成凹部。可选地，凹部142的尺寸d1可以包括其他值。
如图9中的更详细的截面图中所示的那样，在一些实施例中，蚀刻工艺140还导致在集成电路管芯130的导电凸块132的顶面中形成凹部144。导电凸块132的顶面中的凹部144在模塑料134的顶面以下可以包括尺寸d1，其中，导电凸块132的凹部144的尺寸d1基本上可与例如，导体球状件124的凹部142的尺寸d1相同或不同。在其他实施例中，蚀刻工艺140不导致导电凸块132的顶面中形成凹部144。
在一些实施例中，蚀刻工艺140优选地导致残留物138被从模塑料134、导体球状件124和/或导电凸块132的顶面上去除。在一些其中部分残留物138包括导电材料的实施例中，通过被用来在导体球状件124中形成凹部142和被用于去除残留物138的新式蚀刻工艺来防止封装件中的短路和/或电流泄露。
下面参考图10和图11，在模塑料134的顶面，被形成凹部的导体球状件124的顶面以及根据一些实施例可能或可能没有被形成凹部的导电凸块的顶面上方形成再分配层(RDL)。在一些实施例中，形成RDL154包括，例如，将部分RDL154与设置在集成电路管芯130上的导体球状件124和/或导电凸块132相连接。
如图10所示，为了形成RDL154，包括一个或更多绝缘材料或绝缘材料层的第一钝化层146形成在模塑料134，形成有凹部的导体球状件124的顶面和导电凸块132的顶面之上。第一钝化层146可以包括例如，聚合物、二氧化硅、氮化硅、其他绝缘材料，或多个层或它们的组合。可选地第一钝化层146可以包括其他材料。
第一钝化层146被图案化，从而暴露出导体球状件124的顶面和导电凸块132的顶面的至少一些部分。可以使用光刻，通过在第一钝化层146之上形成光刻胶层(未示出)，将光刻胶层暴露于从在其上具有所需的图案的光刻掩模中传输或通过其传输的能量或光线，以及显影光刻胶层来图案化第一钝化层146。例如，根据光刻胶层是正性光刻胶或负性光刻胶来将光刻胶层的暴露的或未暴露的区域烧成灰烬或蚀刻掉。然后将光刻胶层用作为蚀刻掩模，同时将第一钝化层146的一些部分蚀刻掉。例如，在一些其中第一钝化层146包括感光材料的实施例中可选地可以使用其他方法(诸如，直接图案化方法)来图案化第一钝化层146。
如图10中所示，在图案化的第一钝化层146上方还形成有第一导电材料148。第一导电材料148包括例如，导电体，诸如，Cu、Al、Ti或他们的组合或多层。第一导电材料148可选地可以包括其他材料。使用光刻将第一导电材料148图案化成所需要的图案，如图11所示。第一导电材料148的部分保留在第一钝化层146的图案中，从而形成将导体球状件124的顶面与导电凸块132电连接的接触件或通孔。在一些实施例中，第一钝化层146的顶面上的部分第一导电材料148可以包括例如，扇出(fan-out)区域，这些区域形成RDL154的横向的或水平的引线和连接。
如图11中所示，在图案化的第一导电材料148和图案化的第一钝化层146之上形成有第二钝化层150。第二钝化层150可以包括例如，类似于被描述用于第一钝化层146的材料。使用类似于被描述用于第一钝化层146的方法来图案化第二钝化层150，并且在图案化的第二钝化层150上方形成第二导电材料152。第二导电材料152包括例如，类似于被描述用于第一导电材料148的材料。然后使用光刻图案化第二导电材料152。在一些实施例中，第二导电材料152的部分包括例如，球下金属化(UBM)结构。
如图12所示，在RDL154的第二导电材料152的部分上形成多个第二导体球状件156。可以使用例如，落球(ball drop)或球装配工艺来形成导体球状件156。导体球状件156包括例如，焊料或其他共熔材料。可选地，导体球状件156可以包括其他材料并且使用其他方法形成。
然后，如图13中所示使用去接合工艺从封装的半导体器件160中去除载体晶圆120和粘合物122，图13示出了翻转封装件之后的封装半导体器件160。使用管芯锯或其他切割方法切割封装的半导体器件160，从而形成多个独立的封装的半导体器件160。封装的半导体器件160包括多个PoP器件，它们每个均包括多个部分封装的半导体器件100和一个与部分封装的半导体器件100相连接的内嵌的集成电路管芯130。RDL154提供了用于封装的半导体器件160的引线和电连接的扇出区域。
图14和图15是图13中所示的封装半导体器件160的多个部分的更详细的截面图。图14示出了由第一导电材料148构成的接触件，该第一导电材料与在其表面上包括有凹部142的导体球状件124相连接。部分第一导电材料148填充了导体球状件124中的凹部。根据一些实施例，部分第一钝化材料146还填充了部分凹部142。导体球状件124与衬底102上的接触焊盘112相连接，并且导电焊盘112与设置在衬底102内的TSV104相连接。
图15示出了由第一导电材料构成的接触件，该第一导电材料与集成电路管芯130的在其表面上包括有凹部144的导电凸块132相连接。部分第一导电材料148填充了导电凸块132中的凹部144。根据一些实施例，部分第一钝化材料146还填充了部分凹部144。导电凸块132被设置在集成电路管芯130上且通过模塑料134封装。
在一些实施例中，在截面图中导体球状件124和导电凸块132中的凹部142和144分别是弯曲的。凹部142和144可以是例如，中央区域更深而边缘区域较浅的。可选地，凹部142和144在截面图中可以是正方形的或梯形的，但图中没有示出。根据例如，蚀刻工艺140的类型和/或导体球状件124和导电凸块132的材料，凹部142和144可选地可以包括其他形状。
在一些实施例中，在模塑料134的表面以下集成电路管芯130上的导电凸块132没有形成凹部。在这些实施例中，集成电路管芯130上的导电凸块132包括例如，基本上与模塑料134的顶面共面的顶面。
图16是示出了根据一些实施例封装半导体器件的方法的流程图170。在步骤172中，提供了第一集成电路管芯114a，该第一集成电路管芯114a与包括多个设置在其上的衬底通孔(TSV)104的衬底102的第一表面106相连接。在步骤174中，导体球状件124与衬底102的第二表面108上的多个TSV中的每个相连接，第二表面108与衬底102的第一表面相反。在步骤176中，第二集成电路管芯130与衬底102的第二表面108相连接。在步骤178中，模塑料134形成在导体球状件134、第二集成电路管芯130和衬底102的第二表面108之上。在步骤180中，模塑料134被从导体球状件124的顶面上去除并且在步骤182中，在导体球状件124的顶面形成凹部。在步骤184中，在导体球状件124的顶面和模塑料134之上形成RDL154。
在此所描述的集成电路管芯114a、114b和130可以包括有源部件或电路，但未示出。集成电路管芯114a、114b和130可以包括带有例如，形成在其上的有源部件或电路的硅或其他类型的半导体材料。集成电路管芯114a、114b和130可以包括导电材料层、绝缘材料层、以及半导体元件，诸如，晶体管、二极管、电容器、电感器、电阻器等。在一些实施例中，如一个实例，集成电路管芯114a、114b包括存储器件，而集成电路管芯130包括逻辑器件或处理器。可选地，集成电路管芯114a、114b和130可以包括其他类型的功能性电路。
本发明的一些实施例公开了一种封装半导体器件的方法，并且还包括封装的半导体器件160，该封装的半导体器件已经被在此所述的新式封装方法进行了封装。其他实施例包括有新式封装器件。
例如，参考图13，根据一些实施例，封装器件包括衬底，该衬底包括设置在其中的TSV104。衬底102包括位于一个面106上的集成电路管芯装配区域113以及位于与面106相反的另一个面108上的集成电路管芯装配区域126。导体球状件124与TSV104之一相连接，而模塑料134被设置在衬底102和部分导体球状件124之上。导体球状件124的顶面包括凹部142且在模塑料134的表面以下形成凹部。RDL154被设置在模塑料134之上，并且RDL154的部分(例如，部分第一导电材料148)与导体球状件124的形成凹部的顶面相连接。在一些实施例中，衬底102包括与TSV104之一相连接的导电焊盘112，并且每个导体球状件124均与导电焊盘112相连接。
本发明的一些实施例包括封装半导体器件160，该封装半导体器件包括在此所述的封装器件。封装半导体器件160包括与衬底102的与导体球状件124相连接的表面108相连接的集成电路管芯130。集成电路管芯130的导电凸块132与封装器件的RDL154的部分相连接。根据一些实施例，还在模塑料134的顶面以下为导电凸块132形成凹部。在一些实施例中，封装半导体器件160还包括与衬底102的表面106相连接的集成电路管芯114a和/或114b。
本发明的一些实施例的优点包括提供新式封装方法和器件，其中，使用新式蚀刻工艺140来去除通过用于模塑料134的研磨工艺136而形成的残留物138，该蚀刻工艺防止和/或减少了集成电路管芯114a、114b和130之间的短路和电流泄漏。由于去除了残留物138，改进了RDL154的第一钝化层146与模塑料134的粘合。部分残留物138可以包括SnOx，并且蚀刻工艺140优选地去除了SnOx，从而在导体球状件124和导电凸块132之上得到了改进了的导电界面。
由于实施了减少封装件翘曲的蚀刻工艺140，可以减小模塑料134的热预算，从而避免需要用于模塑料134的高固化温度。例如，通过实施本发明的实施例的蚀刻工艺140来避免在CMP工艺过程中的高温固化温度工艺，该高温固化温度工艺能够避免残留物易被困在软磨塑料(已被高温固化过)内。
只需要一个衬底102，并且在例如，不需要额外的中介层衬底的条件下集成电路管芯130被嵌在封装系统中。公开了一种具有新式扇出互连结构的低廉的3D封装系统。另外，该新式封装器件和方法在制造和封装工艺流程中是容易实施的。
根据本发明的一些实施例，一种封装半导体器件的方法包括：提供第一集成电路管芯，该第一集成电路管芯与包括多个设置在其上的TSV的衬底的第一表面相连接。导体球状件与衬底的第二表面上的多个TSV中的每个相连接，第二表面与衬底的第一表面相反。第二集成电路管芯与衬底的第二表面相连接，并且模塑料形成在导体球状件、第二集成电路管芯和衬底的第二表面之上。模塑料被从导体球状件的顶面上去除，并且导体球状件的顶面被形成凹部。在导体球状件的顶面和模塑料之上形成RDL。
根据其他实施例，封装半导体器件的方法包括：将第一集成电路管芯附接在载体晶圆上，其中，第一集成电路管芯与衬底相连接。衬底包括多个设置在其上的TSV并且包括第一表面和与第一表面相反的第二表面。第一集成电路与衬底的第一表面相连接，并且多个TSV从衬底的第一表面延伸至第二表面。该方法包括将第一导体球状件与衬底的第二表面上的多个TSV中的每个相连接，从而将第二集成电路管芯与衬底的第二表面相连接，并且从而在第一导体球状件、第二半导体电路管芯以及衬底的第二表面之上形成模塑料层。该方法包括研磨模塑料层从而暴露出第一导体球状件的顶面，从而为第一导体球状件的顶面形成凹部，并且从而在第一导体球状件的顶面和模塑料的顶面之上形成RDL。将多个第二导体球状件形成在RDL之上并且将载体晶圆去除。
根据其他实施例，一种封装器件包括衬底，该衬底包括设置在其上的多个TSV，以及与多个TSV中的每个相连接的导体球状件。模塑料层形成在衬底和部分导体球状件之上，其中，在模塑料层的顶面以下导体球状件的顶面被形成凹部。在模塑料层之上设置有RDL。部分RDL与导体球状件的形成了凹部的顶面相连接。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。

Claims (10)

1.一种封装半导体器件的方法，所述方法包括：
提供第一集成电路管芯，所述第一集成电路管芯与衬底的第一表面相连接，所述衬底中设置有多个衬底通孔(TSV)；
在所述衬底的第二表面上将导体球状件与所述多个TSV中的每一个相连接，所述第二表面相对于所述衬底的所述第一表面；
将第二集成电路管芯与所述衬底的所述第二表面相连接；
在所述导体球状件、所述第二集成电路管芯和所述衬底的所述第二表面之上形成模塑料；
去除所述导体球状件的顶面上方的所述模塑料；
使所述导体球状件的顶面凹陷；以及
在所述导体球状件的顶面和所述模塑料之上形成再分配层(RDL)。
2.根据权利要求1所述的方法，其中，去除所述导体球状件的顶面上方的所述模塑料进一步包括：去除设置在所述第二集成电路管芯上的导电凸块的顶面之上的所述模塑料。
3.根据权利要求2所述的方法，其中，使所述导体球状件的顶面凹陷进一步包括：使设置在所述第二集成电路管芯上的所述导电凸块的顶面凹陷。
4.根据权利要求2所述的方法，其中，形成所述RDL包括：将部分所述RDL与设置在所述第二集成电路管芯上的所述导电凸块相连接。
5.根据权利要求1所述的方法，其中，使所述导体球状件的顶面凹陷包括：蚀刻所述导体球状件。
6.根据权利要求1所述的方法，其中，去除所述模塑料包括：研磨所述模塑料。
7.根据权利要求1所述的方法，其中，形成所述RDL包括：将部分所述RDL与所述导体球状件相连接。
8.一种封装半导体器件的方法，所述方法包括：
将第一集成电路管芯附接至载体晶圆，其中，所述第一集成电路管芯与衬底相连接，所述衬底中设置有多个衬底通孔(TSV)，所述衬底包括第一表面和与所述第一表面相对的第二表面，所述第一集成电路与所述衬底的所述第一表面相连接，所述多个TSV从所述衬底的所述第一表面延伸至所述第二表面；
在所述衬底的所述第二表面上将第一导体球状件与所述多个TSV中的每一个相连接；
将所述第二集成电路管芯与所述衬底的所述第二表面相连接；
在所述第一导体球状件、所述第二半导体电路管芯和所述衬底的所述第二表面之上形成模塑料层；
研磨所述模塑料层，以暴露出所述第一导体球状件的顶面；
使所述第一导体球状件的顶面凹陷；
在所述第一导体球状件的顶面和所述模塑料的顶面之上形成再分配层(RDL)；
在所述RDL之上形成多个第二导体球状件；以及
去除所述载体晶圆。
9.一种封装器件，包括：
衬底，包括设置在其中的多个衬底通孔(TSV)；
导体球状件，与所述多个TSV中的每一个相连接；
模塑料层，设置在所述衬底和部分所述导体球状件之上，其中，使所述导体球状件的顶面凹陷为低于所述模塑料层的顶面；以及
再分配层(RDL)，设置在所述模塑料层之上，部分所述RDL与所述导体球状件的凹陷顶面相连接。
10.一种封装半导体器件，包括根据权利要求9所述的封装器件，其中，所述衬底包括第一表面和与所述第一表面相对的第二表面，所述导体球状件与所述第一表面相连接，所述半导体器件包括与所述衬底的所述第一表面相连接的第一集成电路管芯，并且所述第一集成电路管芯的导电凸块与部分所述RDL相连接。
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