US20050012195A1 - BGA package with stacked semiconductor chips and method of manufacturing the same - Google Patents

BGA package with stacked semiconductor chips and method of manufacturing the same Download PDF

Info

Publication number
US20050012195A1
US20050012195A1 US10850154 US85015404A US20050012195A1 US 20050012195 A1 US20050012195 A1 US 20050012195A1 US 10850154 US10850154 US 10850154 US 85015404 A US85015404 A US 85015404A US 20050012195 A1 US20050012195 A1 US 20050012195A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
package
plurality
substrate
semiconductor chip
solder balls
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US10850154
Other versions
US7262080B2 (en )
Inventor
Jun-Young Go
Byung-Seok Jun
Jae-Hong Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Abstract

A package with two or more stacked semiconductor chips and a method of manufacturing the same. In the method, an upper semiconductor chip package and a lower semiconductor chip package are prepared. Solder balls are formed on a substrate of the lower package to connect the upper and lower packages. A semiconductor chip and the solder balls are molded and then ground until the solder balls are exposed. Solder balls are formed on the bottom of a substrate of the upper package. The upper package is stacked on the lower package such that the solder balls of the lower package are in contact with the solder balls of the upper package. A reflow process is performed on the lower package and the upper package, which are stacked, to physically connect the upper and lower packages.

Description

  • This application claims the benefit of priority of Korean Patent Application No. 2003-49137, filed on Jul. 18, 2003, in the Korean Intellectual Property Office, the disclosure of which are herein incorporated by reference in their entirety by reference.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a semiconductor package, and more particularly, to a ball grid array (BGA) package with two or more stacked semiconductor chips and a method of manufacturing the same.
  • 2. Description of the Related Art
  • A semiconductor chip packaging process may be a process of manufacturing semiconductor chips. Semiconductor chip packages may be used to electrically connect semiconductor chips to external apparatuses, protect the semiconductor chips from external enviroment by molding, and/or to dissipate heat. There are a variety of methods of electrically connecting semiconductor chips to external apparatuses; a BGA packaging process is an example. BGA packaging processes are used to manufacture high-speed, high-performance semiconductor packages by increasing the number of external connection terminals.
  • Recently, to increase the performance of electronic products including semiconductor chips, the semiconductor chips have been scaled down and/or become lighter. To achieve this, various semiconductor packaging methods have been developed. For example, flip chip package (FCP), chip scale package (CSP), or multi chip package (MCP) methods are widely used.
  • In the MCP method, two or more semiconductor chips of the same or different type are mounted on a single substrate. Semiconductor chips in an MCP may be arranged in series on the same level and/or be sequentially stacked in a vertical direction. The stacking of semiconductor chips may be better for small-sized electronic products since the area occupied by a package can be reduced to enable the CSP method.
  • FIG. 1 is a cross-sectional view of a conventional package with stacked semiconductor chips, which is disclosed in Korean Patent Laid-open Publication No. 2001-0056937.
  • Referring to FIG. 1, semiconductor chips 10 and 12, beneath which bonding pads 11 and 13 are respectively mounted, may be adhered to lead frames 20 and 50 having inner leads 21 and 51 and outer leads 22 and 52. A plurality of protrusions 23 and 53 may be formed in the center of the bottoms of the lead frames 20 and 50. Epoxy molding compounds (EMCs) 60 and 61 may cover the sides and the top surfaces of the semiconductor chips 10 and 12. The outer leads 22 and 52 may be exposed on both sides of the EMCs 60 and 61, and portions (for example, the bottom as shown in FIG. 1) of the protrusions 23 and 53 may also be exposed. An upper penetration hole 24 and a lower penetration hole 54, which are formed in the outer leads 22 and 52, respectively, may be electrically connected to each other by solder balls 70. Also, solder balls 71 for connecting external terminals are mounted on the protrusions 53 of the lower lead frame 50.
  • In a conventional package with stacked semiconductor chips, semiconductor chips may be stacked on lead frames that all have the same shape, and it may be possible to reinforce the adhesion between the stacked semiconductor chips. However, conventional packages with stacked semiconductor chips may have the following disadvantages.
  • First, because an EMC may cover the top surface of a semiconductor chip (as shown in FIG. 1), the height of a package with stacked semiconductor chips may be greater than the sum of the thicknesses of the lead frames (or substrates) and the semiconductor chips. This leads to an increase in the thickness of the overall semiconductor packages, which may hinder the manufacture of thinner semiconductor packages.
  • Second, solder balls for connecting packages may be exposed to an external environment. That is, because portions for connecting packages are not molded by an EMC, the reliability of the conventional package with stacked semiconductor chips may be degraded after using the package for many hours.
  • Korean Patent Laid-open Publication No. 2002-0043435 and Korean Patent Registration No. 0271656 propose examples of packages with stacked semiconductor chips and methods of manufacturing the same, which may have the same disadvantages as the package shown in FIG. 1. Further, a conductive post disclosed in Korean Patent Laid-open Publication No. 2002-0043435 may be inadequate for mass production considering the manufacturing cost and/or process complexity.
  • SUMMARY OF THE INVENTION
  • The exemplary embodiments of the present invention provide a BGA package with stacked semiconductor chips, which is thinner and/or more reliable and/or permits less expensive mass production.
  • The exemplary embodiments of the present invention also provide a method of manufacturing the BGA package with stacked semiconductor chips.
  • In an exemplary embodiment of the present invention, the BGA package comprises a first package and a second package stacked on the first package.
  • The first semiconductor chip package may includes a first substrate, a first semiconductor chip, a plurality of inner solder balls for connecting packages, solder balls for connecting external terminals, and a first EMC. The first substrate may include first land pads, which have bottoms exposed by through holes, and first interconnection pads, which are formed outside the first land pads and have top surfaces and bottom surfaces that may be exposed by upper grooves and lower grooves, respectively. The first semiconductor chip may be adhered to the first substrate such that a circuit forming surface of the first semiconductor chip faces the first substrate. The inner solder balls for connecting packages may be formed on the upper grooves of the first substrate, and the solder balls for connecting external terminals may be formed on the through holes and the lower grooves of the first substrate. The first semiconductor chip and the inner solder balls may be molded by a EMC and may be ground to be at the same level and expose contact parts of the inner solder balls.
  • The second package may have same structure as the first package except the second package need not have a plurality of solder balls formed on the land pads of the second substrate and may not have a plurality of inner solder balls formed on the plurality of upper grooves of the second substrate. The outer solder balls may be formed on the lower grooves of the second package and connected to the inner solder balls of the first package one-to-one corresponding to the same.
  • In another exemplary embodiment of the present invention, a method of manufacturing a BGA package with stacked semiconductor chips comprises preparing the first package and the second package; stacking the second package on the first package such that the outer solder balls of the second package correspond to the inner solder balls of the first package; and reflowing the first package and the second package such that the outer solder balls of the second package are connected to the inner solder balls of the first package.
  • In an exemplary embodiment of the present invention, a method of manufacturing a BGA package with stacked semiconductor chips comprises preparing the first package and the second package; stacking the second package on the first package such that the outer solder balls of the second package correspond to the inner solder balls of the first package; reflowing the first package and the second package such that the outer solder balls of the second package are connected to the inner solder balls of the first package; and grinding a surface opposing the active surface of the second semiconductor chip.
  • In exemplary embodiments of the present invention, solder balls may be formed on the sides of upper and lower semiconductor chips so as to connect semiconductor chip packages. The semiconductor chips and the solder balls may be molded and ground until the solder balls are exposed. As a result, thin and/or lightweight packages with stacked semiconductor chips may be manufactured.
  • In another exemplary embodiment of the present invention, a semiconductor chip package includes a first substrate having an upper surface and a lower surface, at least one partially ground semiconductor chip mounted on the upper surface of the first substrate, a plurality of partially ground solder balls, each including exposed contact portions, formed on the upper surface of the first substrate and electrically connected to the first substrate; and a partially ground epoxy protecting all but a top surface of the at least one partially ground semiconductor chip and the exposed contact portions.
  • In another exemplary embodiment of the present invention, a method of manufacturing a stacked package includes preparing a first package including a first substrate having an upper surface and a lower surface, at least one partially ground semiconductor chip mounted on the upper surface of the first substrate, a plurality of partially ground solder balls, each including exposed contact portions, formed on the upper surface of the first substrate and electrically connected to the first substrate, and a partially ground epoxy protecting all but a top surface of the at least one partially ground semiconductor chip and the exposed contact portions; preparing a second package including a second substrate having an upper surface and a lower surface, at least one partially ground semiconductor chip mounted on the upper surface of the second substrate, a partially ground epoxy protecting all but a top surface of the at least one additional semiconductor chip and the exposed contact portions; preparing a plurality of solder balls for connecting the first package to the second package; stacking the second package on the first package by connecting the plurality of partially ground solder balls of the first substrate and the plurality of solder balls; and reflowing the first package and the second package.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and/or other features of the present invention will become readily apparent by from the description of the exemplary embodiments that follows with reference to the attached drawings in which:
  • FIG. 1 is a cross-sectional view of a conventional BGA package with stacked semiconductor chips.
  • FIG. 2 is a flowchart illustrating a method of manufacturing a BGA package with stacked semiconductor chips according to an exemplary embodiment of the present invention.
  • FIG. 3 is an example flowchart illustrating preparing first and second packages shown in FIG. 2.
  • FIG. 4 is a flowchart illustrating a method of manufacturing a BGA package with stacked semiconductor chips according to another exemplary embodiment of the present invention.
  • FIG. 5 is an example flowchart illustrating preparing a second package shown in FIG. 4.
  • FIGS. 6 through 12 are example cross-sectional views illustrating exemplary portions described in the flow chart of FIG. 2.
  • FIG. 13 is an example cross-sectional view illustrating exemplary portions described in the flow chart of FIG. 5.
  • DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS OF THE INVENTION
  • The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. However, the present invention may be embodied in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided for the purpose of illustration; the present invention covers various changes in form and details as will be readily contemplated by those ordinarily skilled in the art.
  • It should also be noted that the thicknesses of various layers and regions in the stacked package have been exaggerated in the drawings for the purpose of clarity and the same drawing reference numerals are used for the same elements even in different drawings.
  • It should also be noted that a layer is considered as being formed “on” another layer or substrate when formed either directly on the referenced layer or the substrate or formed on other layers or patterns overlaying the referenced layer.
  • FIG. 2 is a flowchart illustrating a method of manufacturing a BGA package with stacked semiconductor chips according to an exemplary embodiment of the present invention. Referring to FIG. 2, a first package and a second package may be prepared (S110). In a BGA package with stacked semiconductor chips, the first package may be positioned first and include inner solder balls for connecting external terminals. The second package may be positioned above the first package and may be electrically connected to the inner solder balls of the first package by outer solder balls.
  • FIG. 3 is an example flowchart that illustrates S110 of FIG. 2 in more detail. FIGS. 6 through 10B are example cross-sectional views illustrating S110. For simplicity, the second semiconductor chip package is illustrated together with the first semiconductor chip package in FIGS. 3-10B.
  • Referring to FIGS. 3 and 6, semiconductor chips 120, 220 may be adhered to substrates 110, 210 using adhesives 130, 230 (S111). The adhesives 130 and 230 may be formed of an insulating material. The semiconductor chips 120, 220 may be adhered to the substrate 110, 210 such that an active surface having a circuit formed thereon of the semiconductor chips 120, 220, on which bonding pads (not shown) are formed, face the substrates 110 and 210. Accordingly, exemplary embodiments of the present invention may be applied to a flip chip package (FCP).
  • The substrates 110, 210 may include insulating substrates 112, 212, land pads 114, 214, photo solder resists (PSRs) 116, 216, and/or interconnection pads 115 and 215. The insulating substrates 112 and 212 may be any insulating substrates, which are used for a printed circuit board (PCB) in the field of semiconductor packages. For example, the insulating substrates 112 and 212 may be formed of cured plastic insulating materials, such as epoxy resin or flexible materials such as polyimide films.
  • Each of the insulating substrates 112 and 212 may have an opening, through which a bonding wire is formed, and concave portions for exposing the interconnection pads 115 and 215. Upper grooves R1 may be spaces formed by the concave portions. The upper grooves R1 may be formed in edges on both sides of each of the substrates 110 and 210.
  • Interconnections may be formed on a surface of the insulating substrates 112, 212 or inside the insulating substrates 112, 212. In the an exemplary embodiment, the interconnections may include the land pads 114, 214 and the interconnection pads 115, 215 and may be formed on the bottoms of the insulating substrates 112, 212. The land pads 114, 214 may be portions of the interconnections, which may be connected to the solder balls (not shown) for connecting external terminals, and the interconnection pads 115, 215 may be other portions of the interconnections, which electrically connect the first package to the second package, such that the second package is electrically connected to external terminals.
  • The interconnection pattern of the first package may be shaped differently from that of the second package. For example, the interconnection of the first package may have any interconnection pattern formed on a substrate of conventional BGA packages. However, the interconnection pattern of the second package may be shaped such that the land pads 214 correspond one-to-one to and are electrically connected to the interconnection pads 215.
  • The PSRs 116, 216 may be formed on the bottoms of the insulating substrates 112, 212. The PSRs 116, 216 may include concave portions that expose the land pads 114, 214 and the interconnection pads 115, 215. Through holes R3 may be spaces formed by some concave portions to expose the land pads 114, 214, and lower grooves R2 may be spaces formed by the other concave portions to expose the interconnection pads 115, 215. The lower grooves R2 may positionally correspond to the upper grooves R1. However, the PSR 216 of the second package need not include the through holes R3 that expose the land pads 214.
  • Referring to FIGS. 3 and 6, wire bonding may be performed to connect the bonding pads (not shown) of the semiconductor chips 120, 220 to the interconnections of the substrates 110, 220 by wires (S112), for example gold wires. Bonding wires 135, 235 may be connected to the interconnections via the openings of the substrates 110, 210. Protective members 140, 240 may be formed on the bonding wires 135, 235 to cover the bonding wires 135, 235.
  • Referring to FIGS. 3 and 7, inner solder balls 150, 250 may be formed on the upper grooves R1 of the substrates 110, 210. The inner solder balls 150, 250 may be formed of, for example, an alloy of tin and lead. Although the inner solder balls 150, 250 may be formed to be lower than a top surface of the semiconductor chip 120, 220, exemplary embodiments of the present invention are not limited thereto. In exemplary embodiments of the present invention, the height h2 between a top surface of the substrates 110, 210 and a top of the inner solder balls 150, 250 may be less than the height h1 between a top surface of the substrates 110, 210 and a top surface of the semiconductor chips 120, 220, i.e., the opposing sides of the active surfaces of the semiconductor chips 120, 220.
  • The formation of the inner solder balls 150 and 250 may be part of a first package preparing process and optional to a second package preparing process, which is, thus, illustrated with a dotted line in FIG. 3. For example, if the inner solder balls 250 are formed in the second package preparing process, since the first package preparing process and the second package preparing process may be the same, the overall packaging process may facilitate mass production. However, in a package with two stacked semiconductor chips, the inner solder balls 250 of the second package may be unnecessary and, thus, may be omitted.
  • Referring to FIGS. 3 and 8, a molding process may be performed such that the semiconductor chips 120, 220 and the inner solder balls 150, 250 are molded by epoxy molding compounds (EMCs) 160, 260 (S114). The molding process may be any molding process, such as transfer molding. In an exemplary embodiment, the EMCs 160 and 260 are formed sufficiently thick to mold the entire inner solder balls 150 and 250. However, the EMCs 160, 260 need not be formed to cover a top surface of the semiconductor chips 120, 220 or a top surface of inner solder balls 150 and 250, as shown in FIG. 8.
  • Referring to FIGS. 3 and 9, a top surface of the semiconductor chips 120, 220, i.e., the opposing sides of the active surfaces of the semiconductor chips 120, 220, may be ground (S115). The grinding process may be performed until inner solder balls 150 a are exposed. If the semiconductor chip 220 of the second package without inner solder balls 250 a is ground, the grinding process may be performed so as not to damage a circuit formed on the semiconductor chip 220. After the grinding process, semiconductor chips 120 a, 220 a and the inner solder balls 150 a, 250 a may have a height h3 lower than the height h1 between a top surface of the substrates 110, 210 and a top surface of the semiconductor chips 120, 220 or the height h2 between a top surface of the substrates 110, 210 and a top surface of the inner solder balls 150, 250.
  • As described above, because a top surface of the semiconductor chips 120 and 220 may be ground, the height of the entire package of stacked semiconductor chips can be reduced. Also, the grinding process may be performed after the inner solder balls 150 and 250 are molded by the EMCs 160 and 260, such that remaining part of the inner solder balls 150, 250 except for contact portions are not exposed to the external environment.
  • Referring to FIGS. 3 and 10, solder balls 170 a and 170 b for connecting external terminals may be formed on the through holes R3 and/or the lower grooves R2 of the substrates 110 (S116). This process may be applied to the first package preparing process. The solder balls 170 a for connecting external terminals may be formed on the through holes R3 and connected to the interconnection pads 115 in order to connect the semiconductor chip 220 a of the second package to external terminals. Thus, the first package shown in FIG. 10 may be completed.
  • Referring to FIGS. 3 and 11, outer solder balls 280 may be formed on the lower grooves R2 of the substrate 210 (S116). This process may be applied to the second package preparing process. The outer solder balls 280 may be connected to the interconnection pads 215 and electrically connected to the land pads 214, which correspond one-to-one to the interconnection pads 215. Thus, the second package shown in FIG. 11 may be completed.
  • Referring again to FIG. 2, the completed second package may be stacked on the completed first package (S120). As shown in FIG. 12, at S120, the inner solder balls 150 a of the first package may be in contact with the outer solder balls 280 of the second package.
  • A reflow process may be performed on the first package and the second package (S130). In the reflow process, the inner solder balls 150 a and the outer solder balls 280 may be melted by applying an appropriate heat and then cooled such that the inner solder balls 150 a are adhered to the outer solder balls 280. Thus, the BGA package with two stacked semiconductor chips may be completed.
  • FIG. 4 is a flowchart illustrating a method of manufacturing a BGA package with stacked semiconductor chips according to another embodiment of the present invention. Referring to FIG. 4, a first package and a second package may be prepared in the same manner as the first exemplary embodiment (S210). In the BGA package with stacked semiconductor chips, the first package may be positioned below and includes inner solder balls for connecting external terminals. The second package may be positioned above and electrically connected to the inner solder balls of the first package by outer solder balls. In the present exemplary embodiment, because step S210 is performed in the same manner as step S110 of the first exemplary embodiment shown in the flowchart of FIG. 3, a description thereof will not be repeated here.
  • FIG. 5 is an example flowchart illustrating the second package preparing process (S210) of FIG. 4 in more detail. The flowchart of FIG. 5 will be described with reference to FIGS. 6 through 8 and 13. Here, the same process steps as in the first exemplary embodiment will be briefly described.
  • Referring to FIGS. 5 and 6, a semiconductor chip 220 may be adhered to a substrate 210 by using an insulating adhesive 230 (S211). The semiconductor chip 220 may be adhered to the substrate 210 such that an active surface having a circuit formed thereon of the semiconductor chip 220 faces the substrate 210. Wire bonding may be performed to cover a bonding wire 235 with a protective member 240. Referring to FIGS. 5 and 7, inner solder balls 250 may be formed on upper grooves R1 of the substrate 210 (S213). As described above, the inner solder balls 250 may be omitted in the second package. Referring to FIGS. 5 and 8, the semiconductor chip 220 and/or the inner solder balls 250 may be molded by an EMC 260 (S214).
  • Referring to FIGS. 5 and 13, outer solder balls 280 may be formed on lower grooves R2 of the substrate 210. Unlike the first exemplary embodiment, the outer solder balls 280 may be formed before a grinding process. Thus, the second package preparing process is completed.
  • Referring again to FIG. 4, the second package may be stacked on the completed first package (S220) such that the inner solder balls 150 a of the first package are in contact with the outer solder balls 280 of the second package. A reflow process may be performed on the first package and the second package, which are sequentially stacked (S230). Thereafter, the grinding process may be performed on the second package (S240). Thus, the BGA package with stacked semiconductor chip of the present exemplary embodiment may be completed.
  • In the exemplary present embodiment, the grinding of the second package may be performed after stacking the first and second packages. After the grinding process is performed, an uppermost semiconductor chip of the entire stacked packages may be ground. Thus, the thickness of a portion that is not ground in the present embodiment is thicker than that of a portion that is not ground in the first embodiment, so as to facilitate the grinding process. Also, it is possible to more finely control the amount of grinding performed in the grinding process of the semiconductor chip.
  • Exemplary embodiments of the present invention facilitate the manufacture of a BGA package with stacked semiconductor chips using conventional package apparatuses and methods.
  • Also, in exemplary embodiments of the present invention, the BGA package with stacked semiconductor chips can be finely controlled to a thin thickness. Accordingly, the BGA package with stacked semiconductor chips may exhibit higher performance and/or can be used in lightweight and/or thin electronics products, such as mobile devices.
  • Further, since portions for connecting upper and lower packages are more completely molded by EMCs or PSRs, the reliability of the BGA package with stacked semiconductor chips improves.
  • Although exemplary embodiments of the present invention illustrate two stacked semiconductor chip packages, any number of semiconductor chip packages may be stacked, as would be known to one of ordinary skill in the art.
  • Although exemplary embodiments of the present invention illustrate several, varying, combinations of preparing, grinding, stacking, and reflowing various semiconductor chip packages, any combination or subcombination of these actions may be taken in any order, based on the description provided herein and all such combinations and subcombinations are considered part of the present invention.
  • It will be apparent to those skilled in the art that other changes and modifications may be made in the above-described exemplary embodiments without departing from the scope of the invention herein, and it is intended that all matter contained in the above description shall be interpreted in an illustrative and not a limiting sense.

Claims (38)

  1. 1. A stacked package, comprising:
    at least two semiconductor packages including a first semiconductor chip package and a second semiconductor chip package stacked on the first semiconductor chip package, wherein:
    the first semiconductor chip package includes:
    a first substrate having an upper surface and a lower surface,
    a first semiconductor chip mounted on the upper surface of the first substrate having an active surface having a circuit formed thereon and a surface opposing the active surface, the active surface facing the upper face of the substrate,
    a plurality of inner solder balls formed on the upper surface of the first substrate and electrically connected to the first substrate, and
    a plurality of outer solder balls formed on the lower surface of the first substrate,
    wherein the first semiconductor chip and the plurality of inner solder balls are molded by a first epoxy and the surface opposing the active surface of the first semiconductor chip and the plurality of inner solder balls are ground, whereby the plurality of inner solder balls and the first semiconductor chip have same height and the plurality of inner solder balls have exposed contact portions; and
    the second package includes:
    a second substrate having an upper surface and a lower surface,
    a second semiconductor chip mounted on the upper surface of the first substrate having an active surface having a circuit formed thereon and a surface opposing the active surface, the active surface facing the upper face of the second substrate,
    a plurality of outer solder balls formed on the lower surface of the second substrate and electrically connected to the plurality of inner solder balls formed on the first substrate, and
    a second epoxy molding the second semiconductor chip.
  2. 2. The package of claim 1, wherein the first substrate is formed with a plurality of land pads and a plurality of interconnection pads formed outside the plurality of land pads, the plurality of interconnection pads having top surfaces exposed by a plurality of upper grooves formed on the upper surface of the first substrate and bottom surfaces exposed by a plurality of lower grooves formed on the lower surface of the first substrate, the plurality of land pads exposed on the lower surface of the first substrate by a plurality of through holes formed on the lower surface of the first substrate.
  3. 3. The package of claim 2, wherein the plurality of inner solder balls of the first semiconductor chip package are formed on the upper grooves of the first substrate, the plurality of outer solder balls of the first semiconductor chip are formed on the plurality of lower grooves and the plurality of through holes of the first substrate.
  4. 4. The package of claim 1, wherein the second substrate is formed with a plurality of land pads and a plurality of interconnection pads corresponding and electrically connected one to one to the plurality of land pads, the plurality of interconnection pads having top surfaces exposed by a plurality of upper grooves formed on the upper surface of the second substrate and bottom surfaces exposed by a plurality of lower grooves formed on the lower surface of the second substrate.
  5. 5. The package of claim 4, wherein the plurality of outer solder balls of the second semiconductor chip package are formed on the lower grooves of the second substrate.
  6. 6. The package of claim 1, wherein the second semiconductor chip package further comprises a plurality of inner solder balls formed on the upper surface of the second substrate, the plurality of inner solder balls of the second substrate are molded by the second epoxy molding compound molding the second semiconductor chip, the surface opposing the active surface of the first semiconductor chip and the plurality of inner solder balls are ground, whereby the plurality of inner solder balls and the first semiconductor chip have same height and the plurality of inner solder balls have exposed contact portions.
  7. 7. The package of claim 1, wherein the second semiconductor chip package further comprises a plurality of inner solder balls formed on the upper surface of the second substrate and electrically connected to the plurality of outer solder balls of the second substrate.
  8. 8. The package of claim 1, wherein each of the first package and the second package is a flip chip package.
  9. 9. The package of claim 1, further comprising a third semiconductor chip package stacked on the second package and having the same structure as the second semiconductor chip package.
  10. 10. The package of claim 9, further comprising a fourth semiconductor chip package stacked on the third semiconductor chip package and having the same structure as the second semiconductor chip package.
  11. 11. A method of manufacturing a stacked package, comprising
    preparing a first package having a plurality of first inner solder balls and a first semiconductor chip formed on an upper face of a first substrate, a plurality of first outer solder balls formed on a lower surface of the first substrate, wherein the plurality of first inner solder balls and the chip are molded by a first epoxy molding compound, the plurality of first inner solder balls having exposed contact portions, the first semiconductor chip having an active surface facing the upper surface of the first substrate and a surface opposing the active surface;
    preparing a second package having a plurality of second outer solder balls formed on a lower surface of a second substrate, a second semiconductor chip formed on an upper surface of the second substrate, the second semiconductor chip having an active surface facing the upper surface of the second substrate, a surface opposing the active surface, the second semiconductor chip being molded by a second epoxy molding compound;
    stacking the second package on the first package by electrically connecting the plurality of first inner solder balls of the first substrate and the plurality of second outer solder balls; and
    reflowing the first package and the second package.
  12. 12. The method of claim 11, wherein the preparing of the first package comprises grinding the surface opposing the active surface of the first semiconductor chip and the plurality of first inner solder balls molded by the first epoxy molding compound.
  13. 13. The method of claim 11, wherein the preparing of the second package comprising grinding the surface opposing the active surface of the second semiconductor chip.
  14. 14. The method of claim 12, wherein the preparing of the first package comprises:
    adhering the first semiconductor chip to the first substrate;
    forming the plurality of inner solder balls on a plurality of upper grooves of the first substrate which expose a plurality of interconnection pads;
    molding the first semiconductor chip and the inner solder balls using the first epoxy molding compound such that the first epoxy molding compound is formed to be higher than the top surface of the first semiconductor chip and tops of the plurality of inner solder balls;
    grinding the surface opposing the active surface of the first semiconductor chip and the first epoxy molding compound until the inner solder balls are exposed; and
    forming the plurality of outer solder balls for connecting external terminals on a plurality of through holes which expose a plurality of land pads of the first substrate and a plurality of lower grooves which expose the plurality of interconnection pads of the first substrate.
  15. 15. The method of claim 14, wherein the grinding is performed after the forming of the plurality of outer solder balls for connecting external terminals.
  16. 16. The method of claim 13, wherein the preparing of the second package comprises:
    adhering the second semiconductor chip to the second substrate;
    molding the second semiconductor chip using the second epoxy molding compound such that the second epoxy molding compound is formed to be higher than the top surface of the second semiconductor chip;
    grinding the surface opposing the active surface of the second semiconductor chip; and
    forming the plurality of outer solder balls on a plurality of lower grooves which expose a plurality of interconnection pads of the second substrate.
  17. 17. The method of claim 16, further comprising forming a plurality of inner solder balls on a plurality of upper grooves which expose the plurality of interconnection pads of the second substrate before the molding of the second semiconductor chip,
    wherein the grinding of the second semiconductor chip is performed until the plurality of inner solder balls of the second package are exposed.
  18. 18. The method of claim 17, further comprising stacking a third package which has the same structure as the second package on the second package and connecting the third package to the second package.
  19. 19. The method of claim 18, further comprising stacking a fourth package which has the same structure as the second package on the third package and connecting the fourth package to the third package.
  20. 20. A method of manufacturing a stacked package,
    comprising:
    preparing a first package having a plurality of first inner solder balls and a first semiconductor chip formed on an upper face of a first substrate, a plurality of first outer solder balls formed on a lower surface of the first substrate, wherein the plurality of first inner solder balls and the chip are molded by a first epoxy molding compound, the plurality of first inner solder balls having exposed contact portions, the first semiconductor chip having an active surface facing the upper surface of the first substrate and a surface opposing the active surface;
    preparing a second package having a plurality of second outer solder balls formed on a lower surface of a second substrate, a second semiconductor chip formed on an upper surface of the second substrate, the second semiconductor chip having an active surface facing the upper surface of the second substrate, a surface opposing the active surface, the second semiconductor chip being molded by a second epoxy molding compound;
    stacking the second package on the first package by electrically connecting the plurality of first inner solder balls of the first substrate and the plurality of second outer solder balls; and
    reflowing the first package and the second package.
    grinding the surface opposing the active surface of the second semiconductor chip.
  21. 21. The method of claim 20, wherein the preparing of the first package comprises grinding the surface opposing the active surface of the first semiconductor chip.
  22. 22. The method of claim 21, wherein the preparing of the first package comprises:
    adhering the first semiconductor chip to the first substrate;
    forming the plurality of inner solder balls on a plurality of upper grooves of the first substrate which expose a plurality of interconnection pads;
    molding the first semiconductor chip and the inner solder balls using the first epoxy molding compound such that the first epoxy molding compound is formed to be higher than the top surface of the first semiconductor chip and tops of the plurality of inner solder balls;
    grinding the surface opposing the active surface of the first semiconductor chip and the first epoxy molding compound until the inner solder balls are exposed; and
    forming the plurality of outer solder balls for connecting external terminals on a plurality of through holes which expose a plurality of land pads of the first substrate and a plurality of lower grooves which expose the plurality of interconnection pads of the first substrate.
  23. 23. The method of claim 22, wherein the grinding of the first semiconductor chip and the first epoxy molding compound is performed after the forming of the plurality of solder balls for connecting external terminals.
  24. 24. The method of claim 20, wherein the preparing of the second package comprises:
    adhering the second semiconductor chip to the second substrate;
    molding the second semiconductor chip using the second epoxy molding compound such that the second epoxy molding compound is formed to be higher than the top surface of the second semiconductor chip;
    grinding the surface opposing the active surface of the second semiconductor chip; and
    forming the plurality of outer solder balls on a plurality of lower grooves which expose a plurality of interconnection pads of the second substrate.
  25. 25. The method of claim 24, further comprising forming the plurality of inner solder balls on the plurality of upper grooves of the second substrate before the molding of the second semiconductor chip,
    wherein the grinding of the second semiconductor chip is performed until the inner solder balls of the second package are exposed.
  26. 26. The method of claim 25, further comprising stacking a third package, which has the same structure as the second package, on the second package and connecting the third package to the second package.
  27. 27. The method of claim 26, further comprising stacking a fourth package which has the same structure as the second package on the third package and connecting the fourth package to the third package.
  28. 28. A semiconductor chip package comprising:
    a first substrate having an upper surface and a lower surface;
    at least one partially ground semiconductor chip mounted on the upper surface of the first substrate;
    a plurality of partially ground solder balls, each including exposed contact portions, formed on the upper surface of the first substrate and electrically connected to the first substrate; and
    a partially ground epoxy protecting all but a top surface of the at least one partially ground semiconductor chip and the exposed contact portions.
  29. 29. A stacked package including the semiconductor chip package of claim 28, said stacked package further comprising:
    at least one additional ground semiconductor chip package each including
    a second substrate having an upper surface and a lower surface;
    at least one partially ground semiconductor chip mounted on the upper surface of the second substrate;
    a partially ground epoxy protecting all but a top surface of the at least one additional semiconductor chip and the exposed contact portions; and
    a plurality of solder balls for connecting the semiconductor chip package to the at least one additional semiconductor chip package.
  30. 30. The stacked package of claim 29, said at least one additional ground semiconductor chip package further including a plurality of partially ground solder balls, each including exposed contact portions, formed on the upper surface of the second substrate and electrically connected to the second substrate.
  31. 31. A method of manufacturing a stacked package, comprising
    preparing a first package including a first substrate having an upper surface and a lower surface, at least one partially ground semiconductor chip mounted on the upper surface of the first substrate, a plurality of partially ground solder balls, each including exposed contact portions, formed on the upper surface of the first substrate and electrically connected to the first substrate, and a partially ground epoxy protecting all but a top surface of the at least one partially ground semiconductor chip and the exposed contact portions;
    preparing a second package including a second substrate having an upper surface and a lower surface, at least one partially ground semiconductor chip mounted on the upper surface of the second substrate, a partially ground epoxy protecting all but a top surface of the at least one additional semiconductor chip and the exposed contact portions;
    preparing a plurality of solder balls for connecting the first package to the second package;
    stacking the second package on the first package by connecting the plurality of partially ground solder balls of the first substrate and the plurality of solder balls; and
    reflowing the first package and the second package.
  32. 32. The method of claim 31, wherein the plurality of solder balls are part of the first package.
  33. 33. The method of claim 31, wherein the plurality of solder balls are part of the second package.
  34. 34. The method of claim 31, wherein the second package is prepared before the stacking and reflowing.
  35. 35. The method of claim 31, wherein the second package is prepared after the stacking and reflowing.
  36. 36. A stacked package formed from the method of claim 11.
  37. 37. A stacked package formed from the method of claim 20.
  38. 38. A stacked package formed from the method of claim 31.
US10850154 2003-07-18 2004-05-21 BGA package with stacked semiconductor chips and method of manufacturing the same Active US7262080B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR20030049137A KR100493063B1 (en) 2003-07-18 2003-07-18 BGA package with stacked semiconductor chips and manufacturing method thereof
KR2003-49137 2003-07-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11603216 US7528475B2 (en) 2003-07-18 2006-11-22 BGA package with stacked semiconductor chips and method of manufacturing the same

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11603216 Division US7528475B2 (en) 2003-07-18 2006-11-22 BGA package with stacked semiconductor chips and method of manufacturing the same

Publications (2)

Publication Number Publication Date
US20050012195A1 true true US20050012195A1 (en) 2005-01-20
US7262080B2 US7262080B2 (en) 2007-08-28

Family

ID=34056897

Family Applications (2)

Application Number Title Priority Date Filing Date
US10850154 Active US7262080B2 (en) 2003-07-18 2004-05-21 BGA package with stacked semiconductor chips and method of manufacturing the same
US11603216 Active US7528475B2 (en) 2003-07-18 2006-11-22 BGA package with stacked semiconductor chips and method of manufacturing the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
US11603216 Active US7528475B2 (en) 2003-07-18 2006-11-22 BGA package with stacked semiconductor chips and method of manufacturing the same

Country Status (3)

Country Link
US (2) US7262080B2 (en)
JP (2) JP2005045251A (en)
KR (1) KR100493063B1 (en)

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060192292A1 (en) * 2004-10-28 2006-08-31 Utac - United Test And Assembly Test Center Ltd. Semiconductor chip package and method of manufacture
US20060278970A1 (en) * 2005-06-10 2006-12-14 Sharp Kabushiki Kaisha Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device
US20070040261A1 (en) * 2004-02-23 2007-02-22 Wolfgang Hetzel Semiconductor component comprising an interposer substrate and method for the production thereof
US20070102816A1 (en) * 2005-11-08 2007-05-10 Samsung Electronics Co., Ltd. Board structure, a ball grid array (BGA) package and method thereof, and a solder ball and method thereof
US20070158815A1 (en) * 2004-04-02 2007-07-12 Chen Fung L Multi-chip ball grid array package and method of manufacture
US20070164457A1 (en) * 2006-01-19 2007-07-19 Elpida Memory Inc. Semiconductor package, substrate with conductive post, stacked type semiconductor device, manufacturing method of semiconductor package and manufacturing method of stacked type semiconductor device
US20070216006A1 (en) * 2006-03-17 2007-09-20 Stats Chippac Ltd. Integrated circuit package on package system
DE102005030946B4 (en) * 2005-06-30 2007-09-27 Infineon Technologies Ag Semiconductor device having the wiring substrate, and solder balls as a connecting element and method of manufacturing the semiconductor device
US20080001266A1 (en) * 2006-06-29 2008-01-03 Sandisk Corporation Method of stacking and interconnecting semiconductor packages
US20080001303A1 (en) * 2006-06-29 2008-01-03 Sandisk Corporation Stacked, interconnected semiconductor packages
US20080012084A1 (en) * 2006-07-14 2008-01-17 Samsung Electronics Co., Ltd Image sensor package and method of fabricating the same
US20080136003A1 (en) * 2006-12-07 2008-06-12 Stats Chippac, Inc. Multi-layer semiconductor package
US20080157301A1 (en) * 2007-01-03 2008-07-03 Stats Chippac, Inc. Leadframe package for mems microphone assembly
US20080272477A1 (en) * 2007-05-04 2008-11-06 Stats Chippac, Ltd. Package-on-Package Using Through-Hole Via Die on Saw Streets
US20100237482A1 (en) * 2009-03-20 2010-09-23 Joungin Yang Integrated circuit packaging system with layered packaging and method of manufacture thereof
US20110156269A1 (en) * 2009-12-31 2011-06-30 Hynix Semiconductor Inc. Semiconductor package and stack semiconductor package having the same
CN102646668A (en) * 2011-02-17 2012-08-22 三星电子株式会社 Semiconductor package having tsv interposer and method of manufacturing same
CN102931169A (en) * 2011-08-10 2013-02-13 快捷半导体(苏州)有限公司 Embedded semiconductor power module and package thereof
US20140319683A1 (en) * 2013-01-29 2014-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged Semiconductor Devices and Packaging Devices and Methods
US20140332955A1 (en) * 2009-12-10 2014-11-13 Stats Chippac, Ltd. Integrated Circuit Package System with Removable Backing Element Having Plated Terminal Leads and Method of Manufacture Thereof
US20150123290A1 (en) * 2013-11-07 2015-05-07 Sangwon Kim Semiconductor packages having trench-shaped opening and methods for fabricating the same
CN104979298A (en) * 2015-06-26 2015-10-14 江西芯创光电有限公司 Package substrate and production process thereof
US9177848B2 (en) 2007-05-04 2015-11-03 Stats Chippac, Ltd. Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer
US9524938B2 (en) 2007-05-04 2016-12-20 STATS ChipPAC Pte. Ltd. Package-in-package using through-hole via die on saw streets
US20170040271A1 (en) * 2014-08-28 2017-02-09 Taiwan Semiconductor Manufacturing Company Limited Semiconductor Package and Method of Forming the Same
US9589941B1 (en) * 2016-01-15 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip package system and methods of forming the same
US9953907B2 (en) 2013-01-29 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. PoP device

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006041438A (en) * 2004-07-30 2006-02-09 Shinko Electric Ind Co Ltd Semiconductor chip built-in substrate, and its manufacturing method
KR100775931B1 (en) 2005-07-12 2007-11-13 김경미 3D stack method using reflow solder
KR100674411B1 (en) 2005-09-29 2007-01-29 삼성전기주식회사 Semiconductor package using core ball and manufacturing method thereof
KR100722634B1 (en) 2005-10-06 2007-05-21 삼성전기주식회사 High density semiconductor package and the manufacturing method thereof
KR100746362B1 (en) * 2005-12-13 2007-08-06 삼성전기주식회사 Package on package substrate and the manufacturing method thereof
US7536233B1 (en) * 2006-01-30 2009-05-19 Advanced Micro Devices, Inc. Method and apparatus for adjusting processing speeds based on work-in-process levels
US7714453B2 (en) * 2006-05-12 2010-05-11 Broadcom Corporation Interconnect structure and formation for package stacking of molded plastic area array package
US8581381B2 (en) * 2006-06-20 2013-11-12 Broadcom Corporation Integrated circuit (IC) package stacking and IC packages formed by same
KR100800477B1 (en) * 2006-07-12 2008-02-04 삼성전자주식회사 Semiconductor package having advantage for stacking and stack type semiconductor package thereof
US7868440B2 (en) * 2006-08-25 2011-01-11 Micron Technology, Inc. Packaged microdevices and methods for manufacturing packaged microdevices
US20080073769A1 (en) * 2006-09-27 2008-03-27 Yen-Yi Wu Semiconductor package and semiconductor device
US8143101B2 (en) 2007-03-23 2012-03-27 Advanced Semiconductor Engineering, Inc. Semiconductor package and the method of making the same
JP5003260B2 (en) 2007-04-13 2012-08-15 日本電気株式会社 Semiconductor device and manufacturing method thereof
US8120811B2 (en) 2007-11-21 2012-02-21 Quad/Graphics, Inc. System and method for adding data to a printed publication
US7687920B2 (en) * 2008-04-11 2010-03-30 Stats Chippac Ltd. Integrated circuit package-on-package system with central bond wires
US8158888B2 (en) * 2008-07-03 2012-04-17 Advanced Semiconductor Engineering, Inc. Circuit substrate and method of fabricating the same and chip package structure
US8012797B2 (en) * 2009-01-07 2011-09-06 Advanced Semiconductor Engineering, Inc. Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
US20100171206A1 (en) * 2009-01-07 2010-07-08 Chi-Chih Chu Package-on-Package Device, Semiconductor Package, and Method for Manufacturing The Same
US8076765B2 (en) * 2009-01-07 2011-12-13 Advanced Semiconductor Engineering, Inc. Stackable semiconductor device packages including openings partially exposing connecting elements, conductive bumps, or conductive conductors
KR101056747B1 (en) 2009-04-14 2011-08-16 앰코 테크놀로지 코리아 주식회사 The semiconductor package and a method of manufacturing the same
US20110049704A1 (en) * 2009-08-31 2011-03-03 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with integrated heatsinks
US8198131B2 (en) * 2009-11-18 2012-06-12 Advanced Semiconductor Engineering, Inc. Stackable semiconductor device packages
US8115293B2 (en) * 2009-12-08 2012-02-14 Stats Chippac Ltd. Integrated circuit packaging system with interconnect and method of manufacture thereof
US8508954B2 (en) 2009-12-17 2013-08-13 Samsung Electronics Co., Ltd. Systems employing a stacked semiconductor package
US8405212B2 (en) * 2009-12-31 2013-03-26 Advanced Semiconductor Engineering, Inc. Semiconductor package
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8823156B2 (en) * 2010-02-10 2014-09-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having stacking functionality and including interposer
US8405213B2 (en) 2010-03-22 2013-03-26 Advanced Semiconductor Engineering, Inc. Semiconductor package including a stacking element
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8569885B2 (en) 2010-10-29 2013-10-29 Advanced Semiconductor Engineering, Inc. Stacked semiconductor packages and related methods
US9093392B2 (en) * 2010-12-10 2015-07-28 Stats Chippac Ltd. Integrated circuit packaging system with vertical interconnection and method of manufacture thereof
US8643167B2 (en) 2011-01-06 2014-02-04 Advanced Semiconductor Engineering, Inc. Semiconductor package with through silicon vias and method for making the same
US9171792B2 (en) 2011-02-28 2015-10-27 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having a side-by-side device arrangement and stacking functionality
US9064781B2 (en) * 2011-03-03 2015-06-23 Broadcom Corporation Package 3D interconnection and method of making same
US8508045B2 (en) 2011-03-03 2013-08-13 Broadcom Corporation Package 3D interconnection and method of making same
US8432028B2 (en) * 2011-03-21 2013-04-30 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
US8928153B2 (en) 2011-04-21 2015-01-06 Tessera, Inc. Flip-chip, face-up and face-down centerbond memory wirebond assemblies
US9013033B2 (en) 2011-04-21 2015-04-21 Tessera, Inc. Multiple die face-down stacking for two or more die
US8633576B2 (en) 2011-04-21 2014-01-21 Tessera, Inc. Stacked chip-on-board module with edge connector
US8952516B2 (en) 2011-04-21 2015-02-10 Tessera, Inc. Multiple die stacking for two or more die
US9418947B2 (en) 2012-02-27 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming connectors with a molding compound for package on package
US9082780B2 (en) * 2012-03-23 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layer
US9209164B2 (en) 2012-11-13 2015-12-08 Delta Electronics, Inc. Interconnection structure of package structure and method of forming the same
US9159699B2 (en) * 2012-11-13 2015-10-13 Delta Electronics, Inc. Interconnection structure having a via structure
US9412723B2 (en) 2013-03-14 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Package on-package structures and methods for forming the same
KR20140141927A (en) 2013-06-03 2014-12-11 삼성전자주식회사 Semiconductor devices having terminals with superior joint reliability and methods for fabricating the same
KR20150004005A (en) 2013-07-02 2015-01-12 에스케이하이닉스 주식회사 Stacked semiconductor package and manufacturing method of the same

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020000648A1 (en) * 1998-02-26 2002-01-03 Leong Chew Weng Thin integrated circuit unit
US6451626B1 (en) * 2001-07-27 2002-09-17 Charles W.C. Lin Three-dimensional stacked semiconductor package
US6451624B1 (en) * 1998-06-05 2002-09-17 Micron Technology, Inc. Stackable semiconductor package having conductive layer and insulating layers and method of fabrication
US20020135057A1 (en) * 2001-03-26 2002-09-26 Yoichiro Kurita Thin planar semiconductor device having electrodes on both surfaces and method of fabricating same
US6548330B1 (en) * 1999-11-17 2003-04-15 Sony Corporation Semiconductor apparatus and method of fabricating semiconductor apparatus
US6740546B2 (en) * 2002-08-21 2004-05-25 Micron Technology, Inc. Packaged microelectronic devices and methods for assembling microelectronic devices
US7071028B2 (en) * 2001-07-31 2006-07-04 Sony Corporation Semiconductor device and its manufacturing method

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03295266A (en) * 1990-04-12 1991-12-26 Hitachi Ltd High integrated semiconductor device
US6072233A (en) * 1998-05-04 2000-06-06 Micron Technology, Inc. Stackable ball grid array package
KR100271656B1 (en) 1998-05-30 2000-11-15 김영환 Bga semiconductor package and fabrication method thereof
KR100587041B1 (en) * 1999-12-17 2006-06-07 주식회사 하이닉스반도체 Chip scale stack package
JP2001339011A (en) * 2000-03-24 2001-12-07 Shinko Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP2001298115A (en) * 2000-04-13 2001-10-26 Seiko Epson Corp Semiconductor device, manufacturing method for the same, circuit board as well as electronic equipment
JP3666576B2 (en) * 2000-07-12 2005-06-29 松下電器産業株式会社 Multi-layer module and a method of manufacturing the same
JP4562153B2 (en) * 2000-08-10 2010-10-13 イビデン株式会社 A method of manufacturing a semiconductor module
JP3798620B2 (en) 2000-12-04 2006-07-19 富士通株式会社 A method of manufacturing a semiconductor device
JP2002329810A (en) * 2001-04-26 2002-11-15 Shinko Electric Ind Co Ltd Semiconductor package assembly and its manufacturing method
JP3847602B2 (en) * 2001-10-30 2006-11-22 シャープ株式会社 The stacked semiconductor device and a manufacturing method of a manufacturing method and a semiconductor device mounting a motherboard and a semiconductor device equipped with a motherboard
JP2003174122A (en) * 2001-12-04 2003-06-20 Toshiba Corp Semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020000648A1 (en) * 1998-02-26 2002-01-03 Leong Chew Weng Thin integrated circuit unit
US6451624B1 (en) * 1998-06-05 2002-09-17 Micron Technology, Inc. Stackable semiconductor package having conductive layer and insulating layers and method of fabrication
US6548330B1 (en) * 1999-11-17 2003-04-15 Sony Corporation Semiconductor apparatus and method of fabricating semiconductor apparatus
US20020135057A1 (en) * 2001-03-26 2002-09-26 Yoichiro Kurita Thin planar semiconductor device having electrodes on both surfaces and method of fabricating same
US6451626B1 (en) * 2001-07-27 2002-09-17 Charles W.C. Lin Three-dimensional stacked semiconductor package
US7071028B2 (en) * 2001-07-31 2006-07-04 Sony Corporation Semiconductor device and its manufacturing method
US6740546B2 (en) * 2002-08-21 2004-05-25 Micron Technology, Inc. Packaged microelectronic devices and methods for assembling microelectronic devices

Cited By (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070040261A1 (en) * 2004-02-23 2007-02-22 Wolfgang Hetzel Semiconductor component comprising an interposer substrate and method for the production thereof
US8624372B2 (en) * 2004-02-23 2014-01-07 Infineon Technologies Ag Semiconductor component comprising an interposer substrate
US7851899B2 (en) * 2004-04-02 2010-12-14 Utac - United Test And Assembly Test Center Ltd. Multi-chip ball grid array package and method of manufacture
US20070158815A1 (en) * 2004-04-02 2007-07-12 Chen Fung L Multi-chip ball grid array package and method of manufacture
US20080251938A1 (en) * 2004-10-28 2008-10-16 Utac - United Test And Assembly Center Ltd. Semiconductor chip package and method of manufacture
US7678610B2 (en) * 2004-10-28 2010-03-16 UTAC-United Test and Assembly Test Center Ltd. Semiconductor chip package and method of manufacture
US20060192292A1 (en) * 2004-10-28 2006-08-31 Utac - United Test And Assembly Test Center Ltd. Semiconductor chip package and method of manufacture
US20060278970A1 (en) * 2005-06-10 2006-12-14 Sharp Kabushiki Kaisha Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device
US7723839B2 (en) 2005-06-10 2010-05-25 Sharp Kabushiki Kaisha Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device
DE102005030946B4 (en) * 2005-06-30 2007-09-27 Infineon Technologies Ag Semiconductor device having the wiring substrate, and solder balls as a connecting element and method of manufacturing the semiconductor device
US7791195B2 (en) * 2005-11-08 2010-09-07 Samsung Electronics Co., Ltd. Ball grid array (BGA) package and method thereof
US20070102816A1 (en) * 2005-11-08 2007-05-10 Samsung Electronics Co., Ltd. Board structure, a ball grid array (BGA) package and method thereof, and a solder ball and method thereof
US20070164457A1 (en) * 2006-01-19 2007-07-19 Elpida Memory Inc. Semiconductor package, substrate with conductive post, stacked type semiconductor device, manufacturing method of semiconductor package and manufacturing method of stacked type semiconductor device
US8367465B2 (en) * 2006-03-17 2013-02-05 Stats Chippac Ltd. Integrated circuit package on package system
US20070216006A1 (en) * 2006-03-17 2007-09-20 Stats Chippac Ltd. Integrated circuit package on package system
US8110439B2 (en) * 2006-06-29 2012-02-07 Sandisk Technologies Inc. Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packages
US7550834B2 (en) 2006-06-29 2009-06-23 Sandisk Corporation Stacked, interconnected semiconductor packages
US20090256249A1 (en) * 2006-06-29 2009-10-15 Cheemen Yu Stacked, interconnected semiconductor package
US8053880B2 (en) 2006-06-29 2011-11-08 SanDisk Technologies, Inc. Stacked, interconnected semiconductor package
US20080001303A1 (en) * 2006-06-29 2008-01-03 Sandisk Corporation Stacked, interconnected semiconductor packages
US7615409B2 (en) * 2006-06-29 2009-11-10 Sandisk Corporation Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packages
US20080001266A1 (en) * 2006-06-29 2008-01-03 Sandisk Corporation Method of stacking and interconnecting semiconductor packages
US20100055835A1 (en) * 2006-06-29 2010-03-04 Cheemen Yu Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packages
US20100055836A1 (en) * 2006-06-29 2010-03-04 Cheeman Yu Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packages
US8053276B2 (en) 2006-06-29 2011-11-08 SanDisk Technologies, Inc. Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packages
US20080012084A1 (en) * 2006-07-14 2008-01-17 Samsung Electronics Co., Ltd Image sensor package and method of fabricating the same
US20100007002A1 (en) * 2006-12-07 2010-01-14 Pendse Rajendra D Multi-layer semiconductor package
US7994626B2 (en) 2006-12-07 2011-08-09 Stats Chippac, Inc. Multi-layer semiconductor package with vertical connectors and method of manufacture thereof
US7608921B2 (en) * 2006-12-07 2009-10-27 Stats Chippac, Inc. Multi-layer semiconductor package
US20080136003A1 (en) * 2006-12-07 2008-06-12 Stats Chippac, Inc. Multi-layer semiconductor package
US7795078B2 (en) 2007-01-03 2010-09-14 Stats Chippac, Ltd. Leadframe package for MEMS microphone assembly
US7550828B2 (en) 2007-01-03 2009-06-23 Stats Chippac, Inc. Leadframe package for MEMS microphone assembly
US20090263937A1 (en) * 2007-01-03 2009-10-22 Stats Chippac, Inc. Leadframe package for mems microphone assembly
US20080157301A1 (en) * 2007-01-03 2008-07-03 Stats Chippac, Inc. Leadframe package for mems microphone assembly
US9177848B2 (en) 2007-05-04 2015-11-03 Stats Chippac, Ltd. Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer
US20100193931A1 (en) * 2007-05-04 2010-08-05 Stats Chippac, Ltd. Package-on-Package Using Through-Hole Via Die on Saw Streets
US20080272477A1 (en) * 2007-05-04 2008-11-06 Stats Chippac, Ltd. Package-on-Package Using Through-Hole Via Die on Saw Streets
US9847253B2 (en) 2007-05-04 2017-12-19 STATS ChipPAC Pte. Ltd. Package-on-package using through-hole via die on saw streets
US9524938B2 (en) 2007-05-04 2016-12-20 STATS ChipPAC Pte. Ltd. Package-in-package using through-hole via die on saw streets
US7723159B2 (en) * 2007-05-04 2010-05-25 Stats Chippac, Ltd. Package-on-package using through-hole via die on saw streets
US20100237482A1 (en) * 2009-03-20 2010-09-23 Joungin Yang Integrated circuit packaging system with layered packaging and method of manufacture thereof
US7863100B2 (en) * 2009-03-20 2011-01-04 Stats Chippac Ltd. Integrated circuit packaging system with layered packaging and method of manufacture thereof
US9337161B2 (en) * 2009-12-10 2016-05-10 Stats Chippac, Ltd. Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereof
US20140332955A1 (en) * 2009-12-10 2014-11-13 Stats Chippac, Ltd. Integrated Circuit Package System with Removable Backing Element Having Plated Terminal Leads and Method of Manufacture Thereof
US20110156269A1 (en) * 2009-12-31 2011-06-30 Hynix Semiconductor Inc. Semiconductor package and stack semiconductor package having the same
US8390128B2 (en) * 2009-12-31 2013-03-05 Hynix Semiconductor Inc. Semiconductor package and stack semiconductor package having the same
CN102646668A (en) * 2011-02-17 2012-08-22 三星电子株式会社 Semiconductor package having tsv interposer and method of manufacturing same
CN102931169A (en) * 2011-08-10 2013-02-13 快捷半导体(苏州)有限公司 Embedded semiconductor power module and package thereof
US9728496B2 (en) 2013-01-29 2017-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US20140319683A1 (en) * 2013-01-29 2014-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged Semiconductor Devices and Packaging Devices and Methods
US9111821B2 (en) * 2013-01-29 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9953907B2 (en) 2013-01-29 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. PoP device
US9385109B2 (en) * 2013-11-07 2016-07-05 Samsung Electronics Co., Ltd. Semiconductor packages having trench-shaped opening and methods for fabricating the same
US20150123290A1 (en) * 2013-11-07 2015-05-07 Sangwon Kim Semiconductor packages having trench-shaped opening and methods for fabricating the same
US20170040271A1 (en) * 2014-08-28 2017-02-09 Taiwan Semiconductor Manufacturing Company Limited Semiconductor Package and Method of Forming the Same
US10008460B2 (en) * 2014-08-28 2018-06-26 Taiwan Semiconductor Manufacturing Company Limited Semiconductor package and method of forming the same
CN104979298A (en) * 2015-06-26 2015-10-14 江西芯创光电有限公司 Package substrate and production process thereof
US9589941B1 (en) * 2016-01-15 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip package system and methods of forming the same
US9911724B2 (en) 2016-01-15 2018-03-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip package system and methods of forming the same

Also Published As

Publication number Publication date Type
KR20050009846A (en) 2005-01-26 application
US20070063332A1 (en) 2007-03-22 application
JP2011101044A (en) 2011-05-19 application
KR100493063B1 (en) 2005-06-02 grant
US7528475B2 (en) 2009-05-05 grant
US7262080B2 (en) 2007-08-28 grant
JP2005045251A (en) 2005-02-17 application

Similar Documents

Publication Publication Date Title
US7394148B2 (en) Module having stacked chip scale semiconductor packages
US6982485B1 (en) Stacking structure for semiconductor chips and a semiconductor package using it
US6731009B1 (en) Multi-die assembly
US6701614B2 (en) Method for making a build-up package of a semiconductor
US6268650B1 (en) Semiconductor device, ball grid array connection system, and method of making
US7298033B2 (en) Stack type ball grid array package and method for manufacturing the same
US7253511B2 (en) Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package
US7982298B1 (en) Package in package semiconductor device
US6462274B1 (en) Chip-scale semiconductor package of the fan-out type and method of manufacturing such packages
US6861761B2 (en) Multi-chip stack flip-chip package
US6518089B2 (en) Flip chip semiconductor device in a molded chip scale package (CSP) and method of assembly
US6984544B2 (en) Die to die connection method and assemblies and packages including dice so connected
US7545047B2 (en) Semiconductor device with a wiring substrate and method for producing the same
US5894107A (en) Chip-size package (CSP) using a multi-layer laminated lead frame
US20010010627A1 (en) Semiconductor device and manufacturing method therefor
US6713857B1 (en) Low profile stacked multi-chip semiconductor package with chip carrier having opening and fabrication method of the semiconductor package
US6492726B1 (en) Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
US6731013B2 (en) Wiring substrate, semiconductor device and package stack semiconductor device
US20050133916A1 (en) Multiple chip package module having inverted package stacked over die
US20040178508A1 (en) Stacked semiconductor device
US20090206461A1 (en) Integrated circuit and method
US20110057327A1 (en) Semiconductor device and method of manufacturing the same
US20030038356A1 (en) Semiconductor devices including stacking spacers thereon, assemblies including the semiconductor devices, and methods
US20070096284A1 (en) Methods for a multiple die integrated circuit package
US6265783B1 (en) Resin overmolded type semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: SAMSUNG ELECTRONICS, KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GO, JUN-YOUNG;JUN, BYUNG-SEOK;KIM, JAE-HONG;REEL/FRAME:015379/0836

Effective date: 20040427

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8