US8508954B2 - Systems employing a stacked semiconductor package - Google Patents

Systems employing a stacked semiconductor package Download PDF

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Publication number
US8508954B2
US8508954B2 US12/910,415 US91041510A US8508954B2 US 8508954 B2 US8508954 B2 US 8508954B2 US 91041510 A US91041510 A US 91041510A US 8508954 B2 US8508954 B2 US 8508954B2
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Prior art keywords
connector
connectors
package
chip
semiconductor
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US12/910,415
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US20110149493A1 (en
Inventor
Heung-Kyu Kwon
Min-ok NA
Sung-Woo Park
Ji-Hyun Park
Su-min Park
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from KR1020100052827A external-priority patent/KR101685652B1/ko
Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NA, MIN-OK, PARK, SU-MIN, PARK, SUNG-WOO, KWON, HEUNG-KYU, PARK, JI-HYUN
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Priority to CN2010105942754A priority Critical patent/CN102104035A/zh
Publication of US20110149493A1 publication Critical patent/US20110149493A1/en
Priority to US13/934,942 priority patent/US9042115B2/en
Publication of US8508954B2 publication Critical patent/US8508954B2/en
Application granted granted Critical
Priority to US14/693,352 priority patent/US20150228627A1/en
Priority to US15/241,452 priority patent/US9978721B2/en
Priority to US15/971,600 priority patent/US10403606B2/en
Priority to US16/448,392 priority patent/US10593652B2/en
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Definitions

  • the first and second substrates may comprise a PCB or a ceramic substrate.
  • the first and second connectors can be configured to transmit power or signals.
  • the first semiconductor chip may comprise a plurality of vertical TSVs therein.
  • the electronic system can be at least one of a computer, a network server, a networking printer, a scanner, a wireless controller, a mobile communication terminal, a switching system, or any electronic device capable of programmed operations.
  • a method may comprise disposing a first semiconductor chip on a first substrate, disposing a first connector on a land of the first substrate, placing a first molding compound on the first substrate and in contact with the first semiconductor chip and the first connector, exposing a surface of the first substrate, and forming an opening through the first molding compound to expose a portion of the first connector.
  • the method may further comprise disposing a second connector and a second semiconductor chip on a second substrate, and coupling the first connector to the second connector.
  • the first and second connectors can be solder balls.
  • FIGS. 9A through 9I are schematic diagrams of shapes of various connectors and via holes of package stack structures according to the general inventive concepts
  • FIG. 13 is a schematic diagram of an electronic system including a stack structure of semiconductor packages according to the general inventive concepts.
  • the lower semiconductor package 105 L may include a lower package substrate 110 L, a lower semiconductor chip 115 L disposed on a top surface of the lower package substrate 110 L, a lower molding compound 130 L, and conductive solder balls 125 disposed on a bottom surface of the lower package substrate 110 L.
  • the lower semiconductor package 105 L may be formed using, for example, a flip-chip technique.
  • the lower package substrate 110 L may comprise, for example, a printed circuit board (PCB) or a ceramic substrate.
  • a grid array technique or a multilayered molding technique can be stably performed.
  • the entire height of the inter-package connectors 150 a may be reduced.
  • the inter-package connectors 150 a are formed using a soldering process (e.g., a reflow process), when the entire height of the inter-package connectors 150 a is reduced, the maximum horizontal width of the inter-package connectors 150 a may be reduced. This is because structures formed using the soldering process may be substantially spherical.
  • the upper semiconductor chip 115 U may be disposed on a top surface of the upper package substrate 110 U.
  • the upper semiconductor chip 115 U may be electrically connected to the upper package substrate 110 U through bonding pads 135 , bonding wires 140 , and wire pads 145 .
  • the upper semiconductor chip 115 U may be covered with an upper molding compound 130 U.
  • the intermediate connectors 170 d may have a mesa shape and attached to top surfaces of the lower connectors 160 d .
  • the intermediate connectors 170 d may comprise copper (Cu).
  • a metallic barrier layer for example, a nickel (Ni) barrier layer, may be formed on the surfaces of the intermediate connectors 170 d .
  • the lower and upper connectors 160 d and 180 d may comprise a solder material.
  • the intermediate adhesion parts 175 e may be formed on the intermediate connectors 170 e .
  • each of the intermediate adhesion parts 175 e has an elliptical sectional shape, the inventive concepts is not limited thereto.
  • each of the intermediate adhesion parts 175 e may have a spherical or hemispherical shape.
  • the shape of the intermediate adhesion parts 175 e may be understood with reference to the descriptions of the lower connectors 160 b and 160 d shown in FIGS. 2B and 2D .
  • the center of the intermediate adhesion parts 175 e may be formed above or below top surfaces of the intermediate connectors 170 e .
  • the lower connectors 160 e , the intermediate adhesion parts 175 e , and the upper connectors 180 e may include a solder material.
  • the chip connectors 281 may transmit a clock signal, command signals, an address signal, and/or data signals.
  • the inter-package connectors 250 may transmit supply voltages, ground voltages, and/or test signals.
  • the chip connectors 281 may transmit the supply voltages or ground voltages, and the inter-package connectors 250 may transmit the effective signals.
  • the chip connectors 281 may transmit the ground voltages, and the inter-package connectors 250 may transmit the supply voltages.
  • the chip connectors 281 may comprise a solder material.
  • chip connectors 281 may comprise a single spherical body between a lower semiconductor chip 215 L and an upper package substrate 210 U.
  • the chip connectors 281 may comprise a solder material.
  • a lateral surface of the lower semiconductor chip 215 L may be surrounded by a molding compound 230 , and a top surface of the lower semiconductor chip 215 L may be exposed.
  • the chip connectors 281 may be electrically connected to TSVs 280 .
  • the chip connectors 281 may be electrically connected to the TSVs 280 by redistribution interconnections 279 . From a plan view, the redistribution interconnections 279 may have, for example, a pad, bar, or line shape.
  • a connector 50 c may include a lower connector 60 c and an upper connector 80 c .
  • the upper connector 80 c may have a greater volume than the lower connector 60 c .
  • An imaginary center C 2 of the lower connector 60 c may be at a lower level than a bottom surface 10 .
  • the imaginary center C 2 may be interpreted as the center of an imaginary radius or curvature r 4 of the lower connector 60 c.
  • the connectors can be formed with substantially equal distances between them. For example, more numbers of connectors can be formed in a given area.
  • the upper connectors 80 a to 80 d may be dipped in a flux. A sufficient amount of flux may be applied to the surfaces of the upper connectors 80 a to 80 d so that the reflow process can be stably carried out. In other words, as the size of the upper connectors 80 a to 80 d increases, a larger amount of flux may be applied to the surfaces of the upper connectors 80 a to 80 d .
  • a connector 51 d may include a spherical or hemispherical lower connector 61 d , a mesa shape intermediate connector 71 d , and a spherical upper connector 81 d .
  • a height Hd 1 of the upper connector 81 d may be greater than a height Hd 2 of the intermediate connector 71 d or a height Hd 3 of the lower connector 61 d .
  • the height He 1 of the upper connector 81 d may be greater than the sum (Hd 2 +Hd 3 ) of the height Hd 2 of the intermediate connector 71 d and the height Hd 3 of the lower connector 61 d .
  • a connector 51 e may include a lower connector 61 e , an intermediate connector 71 e , an intermediate adhesion unit 76 e , and an upper connector 81 e .
  • the upper connector 81 e and the intermediate adhesion unit 76 e may be visually distinguished from each other on the basis of a waist portion We.
  • the maximum width of the upper connector 81 e may be greater than the maximum width De 2 of the intermediate adhesion unit 76 e .
  • the greatest width of the intermediate adhesion unit 76 e may be greater than the width of the waist portion We.
  • the heights of respective components may be variously determined. For example, although it is illustrated that the upper connector 81 e has a greatest height, the inventive concepts is not limited thereto.
  • the relative heights, widths, or sizes of respective components may be variously applied.
  • a connector 52 d may include a lower connector 62 d , a mesa shape connector 67 d and an upper connector 82 d , and the upper connector 82 d may be formed within a via hole Vd configured to partially expose the surface of the mesa shape connector 67 d .
  • a width Dvd of a bottom end of the via hole Vd may be greater than a horizontal width Dmd of the mesa shape connector 67 d .
  • a gap Gd may be formed on a portion of the surface of the mesa shape connector 67 d.
  • a connector 52 g may include a lower connector 62 g , a mesa shape connector 67 g , an intermediate connector 77 g , and an upper connector 82 g .
  • the upper connector 82 g may be formed within a via hole Vg configured to partially expose the surface of the intermediate connector 77 g .
  • a gap Gg may be formed between a portion of the surface of the intermediate connector 77 g and a sidewall of the via hole Vg.
  • a connector 52 h may include a lower connector 62 h , a mesa shape connector 67 h , an intermediate connector 77 h , and an upper connector 82 h .
  • the upper connector 82 h may be formed within a via hole Vh configured to partially expose the surface of the mesa shape connector 67 h .
  • the via hole Vh may further expose a portion of the lateral surface of the mesa shape connector 67 h .
  • a gap Gh may be formed between the portion of the surface of the mesa shape connector 67 h and a sidewall of the via hole Vh.
  • a connector 52 i may include a lower connector 62 i , a mesa shape connector 67 i , an intermediate connector 77 i , and an upper connector 82 i .
  • the upper connector 82 i may be formed within a via hole Vi configured to partially expose the surface of the lower connector 62 i .
  • a gap Gi may be formed between the portion of the surface of the lower connector 62 i and a sidewall of the via hole Vi.
  • sidewalls of the via holes Vg, Vh, and Vi may be inclined such that the diameters of the via holes Vg, Vh, and Vi may be reduced toward lower portions thereof.
  • the via holes Vg, Vh, and Vi may vertically penetrate molding compounds 32 g , 32 h , and 32 i and partially or wholly expose the surface of the intermediate connector 77 h , partially or wholly expose the surface of the mesa shape connector 67 h , and partially or wholly expose the surface of the lower connector 62 h .
  • the gaps Gb 1 and Ga to Gi may refer to air gaps.
  • an upper molding compound 130 U may be formed to cover the upper semiconductor chips 115 U and separated into the upper semiconductor chips 115 U.
  • the upper molding compound 130 U may comprise an epoxy resin or polyimide.
  • the separation of the upper molding compound 130 U may be performed using, for example, a sawing process or a cutting process.
  • lower lands 155 L may be formed on a lower package substrate 110 L.
  • the lower lands 155 L may be formed using a screen printing technique.
  • the lower lands 155 L may be formed using a deposition technique, a bonding technique, a plating technique, or an inkjet technique.
  • chip bump lands 121 may be formed using the same process as or a different process from the process of forming the lower lands 155 L. That is, the lower lands 155 L and the chip bump lands 121 may be formed on the lower package substrate 110 L.
  • a molding control film 135 may be formed on the lower semiconductor chips 115 L.
  • the molding control film 135 may be closely adhered to top surfaces of the lower semiconductor chips 115 L. A space may be ensured between the molding control film 135 and the lower package substrate 110 L. A space may be ensured between the molding control film 135 and the surfaces of the lower connectors 160 .
  • the molding control film 135 may be a tape comprising, for example, cellulose, acetate, polyvinyl, or polyurethane.
  • the space between the molding control film 135 and the lower package substrate 110 L may be filled with a lower molding compound 130 L.
  • the lower molding compound 130 L may be formed to cover the lower connectors 160 , surround a lateral surface of the lower semiconductor chip 115 L, and fill a lower region of the molding control film 135 .
  • the lower molding compound 130 L may be formed only around the conductive chip bumps 120 . In other words, the lower molding compound 130 L may only fill spaces between the lower package substrate 110 L and the lower semiconductor chips 115 L. That is, lateral surfaces of the lower semiconductor chips 115 L may be exposed to the air.
  • the lower molding compound 130 L may be an insulating adhesive.
  • lower lateral surfaces of the lower semiconductor chips 115 L may be surrounded by the lower molding compound 130 L, while upper lateral surfaces thereof may be exposed to the air.
  • the lower molding compound 130 L may cover the surfaces of the lower connectors 160 .
  • the lower molding compound 130 L may fill half the space between the molding control film 135 and the lower package substrate 110 L.
  • the upper connectors 180 of the upper semiconductor package 105 U of FIG. 10E may be dipped in a solder flux F contained in a container T.
  • a top surface of the container T may be in contact with or close to the surface of the upper package substrate 110 U.
  • the top surface of the container T may function to determine the depth of the solder flux F in which the upper connectors 180 are dipped.
  • the upper connectors 180 when the upper connectors 180 have a sufficiently large size, the upper connectors 180 may be sufficiently dipped in the solder flux F. As the size of the upper connections 180 increases, the surface areas of the upper connections 180 dipped in the solder flux F also increase.
  • a solder material may have a spherical shape due to surface tension.
  • the component may be formed using a soldering process. It will be understood by those skilled in the art with reference to the above drawings and the descriptions thereof that the lower and upper connectors 160 and 180 may be formed in various shapes.
  • FIG. 13 is a schematic diagram of an electronic system including an apparatus according to embodiments of the inventive concepts.
  • the output unit 630 may receive the electrical command signal from the control unit 610 and output a processing result of the electronic system 600 .
  • the output unit 630 may comprise, for example, a monitor, a printer, or a beam emitter.
  • the output unit 630 may include a stack structure of semiconductor packages according to embodiments of the inventive concepts.
  • a stack structure of semiconductor packages may include inter-package connectors stably formed even when a distance between the inter-package connectors is substantially small.
US12/910,415 2009-12-17 2010-10-22 Systems employing a stacked semiconductor package Active 2031-08-11 US8508954B2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
CN2010105942754A CN102104035A (zh) 2009-12-17 2010-12-17 堆叠半导体封装及其制造方法以及包括该封装的系统
US13/934,942 US9042115B2 (en) 2009-12-17 2013-07-03 Stacked semiconductor packages
US14/693,352 US20150228627A1 (en) 2009-12-17 2015-04-22 Stacked semiconductor packages, methods for fabricating the same, and /or systems employing the same
US15/241,452 US9978721B2 (en) 2009-12-17 2016-08-19 Apparatus for stacked semiconductor packages and methods of fabricating the same
US15/971,600 US10403606B2 (en) 2009-12-17 2018-05-04 Method of fabricating a semiconductor package
US16/448,392 US10593652B2 (en) 2009-12-17 2019-06-21 Stacked semiconductor packages

Applications Claiming Priority (4)

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KR10-2009-0126345 2009-12-17
KR20090126345 2009-12-17
KR1020100052827A KR101685652B1 (ko) 2009-12-17 2010-06-04 반도체 패키지들, 그들의 적층 구조와 그 제조 방법들
KR10-2010-0052827 2010-06-04

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US20110149493A1 US20110149493A1 (en) 2011-06-23
US8508954B2 true US8508954B2 (en) 2013-08-13

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US13/934,942 Active US9042115B2 (en) 2009-12-17 2013-07-03 Stacked semiconductor packages
US14/693,352 Abandoned US20150228627A1 (en) 2009-12-17 2015-04-22 Stacked semiconductor packages, methods for fabricating the same, and /or systems employing the same
US15/241,452 Active US9978721B2 (en) 2009-12-17 2016-08-19 Apparatus for stacked semiconductor packages and methods of fabricating the same
US15/971,600 Active US10403606B2 (en) 2009-12-17 2018-05-04 Method of fabricating a semiconductor package
US16/448,392 Active US10593652B2 (en) 2009-12-17 2019-06-21 Stacked semiconductor packages

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US14/693,352 Abandoned US20150228627A1 (en) 2009-12-17 2015-04-22 Stacked semiconductor packages, methods for fabricating the same, and /or systems employing the same
US15/241,452 Active US9978721B2 (en) 2009-12-17 2016-08-19 Apparatus for stacked semiconductor packages and methods of fabricating the same
US15/971,600 Active US10403606B2 (en) 2009-12-17 2018-05-04 Method of fabricating a semiconductor package
US16/448,392 Active US10593652B2 (en) 2009-12-17 2019-06-21 Stacked semiconductor packages

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US20150228627A1 (en) 2015-08-13
US20180331071A1 (en) 2018-11-15
US9042115B2 (en) 2015-05-26
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