TWI462266B - 晶片堆疊結構及其製造方法 - Google Patents

晶片堆疊結構及其製造方法 Download PDF

Info

Publication number
TWI462266B
TWI462266B TW101109411A TW101109411A TWI462266B TW I462266 B TWI462266 B TW I462266B TW 101109411 A TW101109411 A TW 101109411A TW 101109411 A TW101109411 A TW 101109411A TW I462266 B TWI462266 B TW I462266B
Authority
TW
Taiwan
Prior art keywords
wafer
glass substrate
signal processing
optical
holes
Prior art date
Application number
TW101109411A
Other languages
English (en)
Other versions
TW201340292A (zh
Inventor
Geng Shin Shen
Ya Chi Chen
I Hsin Mao
Original Assignee
Chipmos Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipmos Technologies Inc filed Critical Chipmos Technologies Inc
Priority to TW101109411A priority Critical patent/TWI462266B/zh
Priority to CN201210258997.1A priority patent/CN103325799B/zh
Priority to US13/801,255 priority patent/US8809088B2/en
Publication of TW201340292A publication Critical patent/TW201340292A/zh
Application granted granted Critical
Publication of TWI462266B publication Critical patent/TWI462266B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32052—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/14335—Digital signal processor [DSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Description

晶片堆疊結構及其製造方法
本發明係關於一種晶片堆疊結構及其製造方法，該晶片堆疊結構特別是包含訊號處理晶片及光學晶片的堆疊結構。
隨著人們生活習慣的演變及製程技術的進步，影像感測器已廣泛地應用於日常生活中。已知的影像感測器例如：互補金屬氧化半導體(complementary metal-oxide semiconductor，CMOS)影像感測器、及電荷耦合元件(charge coupled device，CCD)影像感測器等等。其中，CMOS影像感測器具有價格低廉、耗電量低等優點，通常較適用於低階產品；而CCD影像感測器所擷取的影像品質較佳，則長期主宰了高階影像感測器的市場。
然而，由於數位訊號處理器(digital signal processor，DSP)晶片的加入，其與CMOS影像感測器的配合，恰補足了CMOS影像感測器的不足。詳言之，DSP晶片可模擬人眼，來處理感光元件無法辨識的情況，並進一步利用演算法輔助CMOS影像感測器的影像效能。因此，組合CMOS影像感測器與DSP晶片之模組，已逐漸使用在數位攝影機及數位相機等高畫素可攜式產品。
請參考第1A圖至第1C圖，所示為習知的影像感測(CMOS imaging sensor，CIS)晶片11與數位訊號處理器晶片12的封裝結構1及其製造過程。如第1A圖所示，複數個影像感測晶片11係形成於一晶圓13上，再進行切割而成之單一影像感測晶片11，各影像感測晶片11具有多個第一接點111分佈於影像感測晶片11之二側。而同樣地，複數個數位訊號處理器晶片12如第1B圖所示，亦是形成於一晶圓14上，再進行切割而成之單一數位訊號處理器晶片12，各數位訊號處理器晶片12具有多個第二接點121分佈於二側。
請參閱第1C圖，習知的技術是，將切割後的單一影像感測晶片11與單一數位訊號處理器晶片12橫向對齊排列定位於基板上，再以打線方式，將該等第一接點111與該等第二接點141依序電性連接。
可想見地，習知技術需先分別切割晶圓13及晶圓14，以製成單一且尺寸相應的影像感測晶片11及數位訊號處理器晶片12，後續還需要分別固定影像感測晶片11及數位訊號處理器晶片12，然後再進行打線連接。製程上較為繁複且生產時間長，製造成本偏高。另外，影像感測晶片11及數位訊號處理器晶片12的配置係為橫向並排設置於基板上，所佔據面積較大，且打線結合可靠度不佳，容易產生接觸不良或穩定性不佳的缺點。
有鑑於此，提供一種可改善製程、縮減體積與所佔面積、及提升可靠度之晶片堆疊結構及製造方法，乃為此一業界亟欲達成之目標。
本發明之一目的在於節省晶片堆疊結構的配置空間，藉由堆疊晶片之封裝結構，可避免習知封裝結構平行排列時所占較大面積之問題，本發明之晶片堆疊結構除了可節省所佔據的面積之外，所節省的空間更可提供給其它元件運用。
本發明之另一目的在於簡化晶片堆疊結構之製程。藉由將包含多個影像感測晶片之晶圓與包含多個數位訊號處理器晶片之基板先予以連接對合，再進行切割，以製成單一晶片堆疊結構，而非先個別切割形成影像感測晶片及數位訊號處理器晶片，故不需要習知的後續定位、打線連接等製程，可大幅簡化製程及降低生產的成本。
本發明之又一目的在於提高晶片堆疊結構及其製程的可靠度及穩定性，藉由以堆疊方式對合影像感測晶片與數位訊號處理器晶片，並透過基板中內鍍有金屬材料的複數貫穿孔(through hole)，電性連接於基板的外表面，使得整體之結構的穩定性及可靠度大幅提昇。
為達上述目的，本發明提供一種晶片堆疊結構，包含：一訊號處理晶片模組及一光學晶片模組，該訊號處理晶片模組包含：一玻璃基板，具有一第一表面、以及與該第一表面相對之一第二表面，該第一表面上更形成一凹穴，其中，該玻璃基板的第一表面與該凹穴內分別形成有貫穿孔，並於該貫穿孔內鍍有金屬材料以電性連接該第一表面及該第二表面；及一訊號處理晶片，設置於該凹穴中；該光學晶片模組包含一光學晶片，該光 學晶片模組於該第一表面上與該訊號處理晶片模組疊置，該光學晶片之面積係大於該訊號處理晶片之面積，以涵蓋該訊號處理晶片；其中，該訊號處理晶片及該光學晶片更分別包含複數導電接點，相應地連接該等貫穿孔，以於該第二表面上電性連接。
本發明更提供一種製造晶片堆疊結構之方法，包含下列步驟：提供一玻璃基板，其中，該玻璃基板具有一第一表面、以及與該第一表面相對之一第二表面，並依據一佈局於第一表面上形成複數個凹穴，凹穴與第一表面上設有內鍍金屬材料之複數貫穿孔，其中，該等訊號處理晶片嵌設於凹穴與貫穿孔電性連接；提供一晶圓，其中，該晶圓上設置有複數個光學晶片；及疊合該玻璃基板及該晶圓，使對應之該光學晶片及該訊號處理晶片，經由該等貫穿孔電性連接。
為讓上述目的、技術特徵、和優點能更明顯易懂，下文係以較佳實施例配合所附圖式進行詳細說明。
11‧‧‧影像感測晶片
111‧‧‧第一接點
12‧‧‧數位訊號處理器晶片
121‧‧‧第二接點
13‧‧‧晶圓
14‧‧‧晶圓
2‧‧‧晶片堆疊結構
21‧‧‧光學晶片模組
210‧‧‧晶圓
213‧‧‧光學晶片
213a‧‧‧導電接點
23‧‧‧訊號處理晶片模組
231‧‧‧玻璃基板
231a‧‧‧第一表面
231b‧‧‧第二表面
233‧‧‧訊號處理晶片
233a‧‧‧導電接點
235‧‧‧貫穿孔
237‧‧‧凹穴
25‧‧‧導電線路層
27‧‧‧銲球
29‧‧‧黏著層
901~907‧‧‧步驟
第1A圖係為習知製造影像感測晶片之示意圖；第1B圖係為習知製造數位訊號處理器晶片之示意圖；第1C圖係習知晶片封裝結構之示意圖；第2圖係本發明晶片堆疊結構之示意圖；第3圖至第8圖係本發明製造晶片堆疊結構之示意圖；及第9圖係本發明製造晶片堆疊結構之流程圖。
請參閱第2圖，所示為本發明第一實施例之晶片堆疊結構2之剖面示意圖，其係為包含一光學晶片模組21及一訊號處理晶片模組23所堆疊組成之結構。
其中，訊號處理晶片模組23係包含一玻璃基板231及一訊號處理晶片233，該訊號處理晶片233較佳係一數位訊號處理器(digital signal processor，DSP)晶片。為方便說明，進一步定義該玻璃基板231具有一第一表面231a、以及與該第一表面231a相對之一第二表面231b，玻璃基板231更形成有複數貫穿孔(through hole)235，其內鍍有金屬材料以連接該第一表面231a及該第二表面231b。
玻璃基板231之第一表面231a上更形成一凹穴237，以供訊號處理晶片233設置於該凹穴237中。凹穴237內亦形成鍍有金屬材料之貫穿孔235，而該訊號處理晶片233更包含複數導電接點233a，例如習知之凸塊，相應地電性連接至對應之貫穿孔235。
較佳地，晶片堆疊結構2更包含一導電線路層25及複數銲球27，該導電線路層25形成於玻璃基板231之第二表面231b上，以選擇性地電性連接該等貫穿孔235，而銲球27係形成於該導電線路層25上之適當位置。
而光學晶片模組21係包含一光學晶片213，較佳係為一影像感測(CMOS imaging sensor，CIS)晶片，該光學晶片模組21係於訊號處理晶片模組23之第一表面231a上，與訊號處理晶片模組23疊置，且該光學晶片213之面積係大於該訊號處理晶片233之面積， 以涵蓋該訊號處理晶片233，使光學晶片213之導電接點233a得以準確地對應連接於訊號處理晶片233外側的部分貫穿孔235。同樣地，該光學晶片213亦可包含複數導電接點213a，例如習知之凸塊，相應地連接至對應之部分貫穿孔235。
為穩固地結合該訊號處理晶片模組23與該光學晶片模組21，本發明之晶片堆疊結構2較佳更包含一黏著層29，施加於訊號處理晶片模組23與光學晶片模組21之間。
如此一來，透過該等貫穿孔235及導電線路層25，光學晶片213與訊號處理晶片233得以於玻璃基板231之第二表面231b上電性連接。
接下來將說明本發明之第二實施例，其係用於製造前述晶片堆疊結構2之方法，以下將配合第3圖至第8圖之示意圖以及第9圖之流程圖，一併說明。
首先，如第9圖之步驟901及第3圖所示，提供一玻璃基板231，其上形成複數貫穿孔235及複數個凹穴237以供複數個訊號處理晶片233設置；其中，該玻璃基板231具有第一表面231a、以及與該第一表面231a相對之第二表面231b，該等凹穴237係依據一佈局形成於第一表面231a上，凹穴237與第一表面231a上之該等貫穿孔235係內鍍金屬材料，以於第一表面231a及第二表面231b上形成接點，該等訊號處理晶片233分別嵌設於凹穴237內以與對應之貫穿孔235電性連接。
然後進行步驟902，於玻璃基板231之第二表面231b上形成導電線路層25，以選擇性地電性連接該等貫穿孔235。
接著，如第9圖之步驟903及第4圖所示，提供一晶圓210(通常包含一矽基板)，其中，該晶圓210上形成有複數個光學晶片213。如第一實施例所說明，光學晶片213更包含並顯露出複數導電接點213a，該導電接點213a可為習知之凸塊，例如：金凸塊、鍚球、銅凸塊、銀凸塊、複合金屬凸塊或結線凸塊等等。
然後如第9圖之步驟904及第5圖所示，疊合玻璃基板231及晶圓210，使對應之光學晶片213及訊號處理晶片233，經由該等貫穿孔235電性連接。更明確而言，此步驟係將晶圓210貼合於玻璃基板231之第一表面231a上，使光學晶片213之導電接點213a，連接至相對應之貫穿孔235。
疊合後之結構，如第6圖之剖面圖所示。其中，各光學晶片213包含複數導電接點213a，各訊號處理晶片233包含複數導電接點233a，該疊合玻璃基板231及晶圓210之步驟，係將該等導電接點213a、233a對準並電性連接至對應之貫穿孔235。
較佳地，於進行步驟904之疊合製程時，更施加黏著層29於玻璃基板231及晶圓210之間，以利其相互結合，其中，該黏著層29可為一填充膠材(Underfill)。於本發明之另一較佳實施例中，該黏著層29可為一半固化之兩階段特性黏膠(B-Stage)預設於晶圓凸塊之周圍，於疊合玻璃基板231及晶圓210時一併固化該黏著層29，以增加該光學晶片213與訊號處理晶片23彼此間之結合性。
接下來，如第9圖之步驟905及第7圖所示，研磨晶圓210背面，以減少其整體厚度。
最後，如第8圖所示，先執行步驟906，於導電線路層25上植入複數銲球27，再執行步驟907，切割疊合後之玻璃基板231及晶圓，而最終製成第一實施例之晶片堆疊結構2。無疑地，晶片堆疊結構2包含光學晶片21及訊號處理晶片23所組成，光學晶片21如影像感測(CMOS imaging sensor，CIS)晶片，訊號處理晶片23如數位訊號處理器(digital signal processor，DSP)晶片。
綜上所述，本發明所揭露之晶片堆疊結構及其製造方法，改以於晶圓時直接堆疊後切割以形成堆疊晶片之封裝結構，不僅可節省晶片堆疊結構的配置空間及所佔面積，亦可大幅簡化製程及降低成本，更可提高晶片堆疊結構的可靠度及穩定性。
上述之實施例僅用來例舉本發明之實施態樣，以及闡釋本發明之技術特徵，並非用來限制本發明之保護範疇。任何熟悉此技術者可輕易完成之改變或均等性之安排均屬於本發明所主張之範圍，本發明之權利保護範圍應以申請專利範圍為準。
2‧‧‧晶片堆疊結構
21‧‧‧光學晶片模組
213‧‧‧光學晶片
213a‧‧‧導電接點
23‧‧‧訊號處理晶片模組
231‧‧‧玻璃基板
231a‧‧‧第一表面
231b‧‧‧第二表面
233‧‧‧訊號處理晶片
233a‧‧‧導電接點
235‧‧‧貫穿孔
237‧‧‧凹穴
25‧‧‧導電線路層
27‧‧‧銲球
29‧‧‧黏著層

Claims (10)

  1. 一種晶片堆疊結構，包含：一訊號處理晶片模組，包含：一玻璃基板，具有一第一表面、以及與該第一表面相對之一第二表面，該第一表面上更形成一凹穴，其中，該玻璃基板的第一表面與該凹穴內分別形成有貫穿孔(through hole)，並於該貫穿孔內鍍有金屬材料以電性連接該第一表面及該第二表面；及一訊號處理晶片，設置於該凹穴中與該些貫穿孔電性連接；及一光學晶片模組，包含一光學晶片，該光學晶片模組於該第一表面上與該訊號處理晶片模組疊置，該光學晶片之面積係大於該訊號處理晶片之面積，以涵蓋該訊號處理晶片；其中，該訊號處理晶片及該光學晶片更分別包含複數導電接點相應地連接該等貫穿孔，以於該第二表面上電性連接。
  2. 如請求項1所述之晶片堆疊結構，其中該等導電接點係為複數凸塊。
  3. 如請求項1所述之晶片堆疊結構，更包含一導電線路層及複數銲球，該導電線路層形成於該第二表面上，以選擇性地電性連接該等貫穿孔，而該複數銲球形成於該導電線路層上。
  4. 如請求項1所述之晶片堆疊結構，更包含一黏著層，施加於該訊號處理晶片模組與該光學晶片模組之間，以結合該訊號處理晶片 模組與該光學晶片模組。
  5. 一種製造一晶片堆疊結構之方法，包含下列步驟：提供一玻璃基板，其中，該玻璃基板具有一第一表面、以及與該第一表面相對之一第二表面，並依據一佈局於第一表面上形成複數個凹穴，該等凹穴與該第一表面上設有內鍍金屬材料之複數貫穿孔，其中，複數個訊號處理晶片分別嵌設於該等凹穴中以與該等貫穿孔電性連接；提供一晶圓，其中，該晶圓上形成有複數個光學晶片；及疊合該玻璃基板及該晶圓，使對應之該光學晶片及該訊號處理晶片，經由該等貫穿孔電性連接。
  6. 如請求項5所述之方法，其中，該疊合該玻璃基板及該晶圓之步驟，係將該晶圓貼合於該玻璃基板之第一表面上。
  7. 如請求項6所述之方法，其中該疊合該玻璃基板及該晶圓之步驟，包含：施加一黏著層於該玻璃基板及該晶圓之間。
  8. 如請求項5所述之方法，其中該提供一玻璃基板之步驟，更包含：於該第二表面上形成一導電線路層，以選擇性地電性連接該等貫穿孔。
  9. 如請求項5所述之方法，其中於該疊合該玻璃基板及該晶圓之步驟之後，更包含：研磨該晶圓； 於該導電線路層上，植入複數銲球；以及切割疊合後之該玻璃基板及該晶圓。
  10. 如請求項5所述之方法，其中各該訊號處理晶片及各該光學晶片更分別包含複數導電接點，該疊合該玻璃基板及該晶圓之步驟，係將該等導電接點對準並電性連接至該等貫穿孔。
TW101109411A 2012-03-20 2012-03-20 晶片堆疊結構及其製造方法 TWI462266B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW101109411A TWI462266B (zh) 2012-03-20 2012-03-20 晶片堆疊結構及其製造方法
CN201210258997.1A CN103325799B (zh) 2012-03-20 2012-07-24 芯片堆迭结构及其制造方法
US13/801,255 US8809088B2 (en) 2012-03-20 2013-03-13 Structure of stacking chips and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW101109411A TWI462266B (zh) 2012-03-20 2012-03-20 晶片堆疊結構及其製造方法

Publications (2)

Publication Number Publication Date
TW201340292A TW201340292A (zh) 2013-10-01
TWI462266B true TWI462266B (zh) 2014-11-21

Family

ID=49194456

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101109411A TWI462266B (zh) 2012-03-20 2012-03-20 晶片堆疊結構及其製造方法

Country Status (3)

Country Link
US (1) US8809088B2 (zh)
CN (1) CN103325799B (zh)
TW (1) TWI462266B (zh)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8832283B1 (en) 2010-09-16 2014-09-09 Google Inc. Content provided DNS resolution validation and use
US9721872B1 (en) 2011-02-18 2017-08-01 Amkor Technology, Inc. Methods and structures for increasing the allowable die size in TMV packages
JP6015508B2 (ja) * 2013-03-18 2016-10-26 富士通株式会社 高周波モジュール
KR102144367B1 (ko) * 2013-10-22 2020-08-14 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
CN103904039B (zh) * 2014-03-31 2016-07-06 华进半导体封装先导技术研发中心有限公司 超薄凹式玻璃基板的封装结构及方法
CN103943605B (zh) * 2014-03-31 2017-02-15 华进半导体封装先导技术研发中心有限公司 基于超薄玻璃的封装结构及方法
CN104538373B (zh) * 2014-12-30 2017-05-03 华天科技（昆山）电子有限公司 三维集成传感芯片封装结构及封装方法
US9881850B2 (en) 2015-09-18 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and method of forming the same
WO2018054315A1 (zh) * 2016-09-26 2018-03-29 苏州晶方半导体科技股份有限公司 封装结构以及封装方法
US9761547B1 (en) 2016-10-17 2017-09-12 Northrop Grumman Systems Corporation Crystalline tile
US10134793B1 (en) * 2017-05-16 2018-11-20 Xerox Corporation Method of forming two-dimensional and three-dimensional semiconductor chip arrays
DE102017129611B4 (de) * 2017-12-12 2021-04-22 RF360 Europe GmbH Elektrische Vorrichtung mit zwei oder mehr Chipkomponenten
US12002781B2 (en) 2020-12-25 2024-06-04 Tokyo Institute Of Technology Semiconductor device and method for manufacturing same
CN115881654B (zh) * 2023-01-31 2023-08-22 深圳新声半导体有限公司 埋入式滤波器和射频前端模组的封装结构及其制备方法
CN117410238B (zh) * 2023-12-14 2024-09-13 青岛泰睿思微电子有限公司 内埋芯片的打线种球封装结构

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201007914A (en) * 2008-08-06 2010-02-16 Ind Tech Res Inst Three-dimensional conducting structure and method of fabricating the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6384473B1 (en) * 2000-05-16 2002-05-07 Sandia Corporation Microelectronic device package with an integral window
US6934065B2 (en) * 2003-09-18 2005-08-23 Micron Technology, Inc. Microelectronic devices and methods for packaging microelectronic devices
KR100809718B1 (ko) * 2007-01-15 2008-03-06 삼성전자주식회사 이종 칩들을 갖는 적층형 반도체 칩 패키지 및 그 제조방법
JP2009010261A (ja) * 2007-06-29 2009-01-15 Fujikura Ltd 半導体パッケージおよびその製造方法
US8193632B2 (en) 2008-08-06 2012-06-05 Industrial Technology Research Institute Three-dimensional conducting structure and method of fabricating the same
CN101656248A (zh) * 2008-08-19 2010-02-24 南茂科技股份有限公司 具有凹槽的基板的芯片堆叠封装结构及其封装方法
US8508954B2 (en) * 2009-12-17 2013-08-13 Samsung Electronics Co., Ltd. Systems employing a stacked semiconductor package
US8546900B2 (en) * 2011-06-09 2013-10-01 Optiz, Inc. 3D integration microelectronic assembly for integrated circuit devices
US10115671B2 (en) * 2012-08-03 2018-10-30 Snaptrack, Inc. Incorporation of passives and fine pitch through via for package on package

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201007914A (en) * 2008-08-06 2010-02-16 Ind Tech Res Inst Three-dimensional conducting structure and method of fabricating the same

Also Published As

Publication number Publication date
US8809088B2 (en) 2014-08-19
CN103325799A (zh) 2013-09-25
CN103325799B (zh) 2016-12-28
US20130249042A1 (en) 2013-09-26
TW201340292A (zh) 2013-10-01

Similar Documents

Publication Publication Date Title
TWI462266B (zh) 晶片堆疊結構及其製造方法
JP7289956B2 (ja) 指紋感知モジュール及びその方法
TWI332790B (en) Image sensor module with a three-dimensional dies-stacking structure
JP3960479B1 (ja) 両面電極構造の半導体装置の製造方法
US20040027477A1 (en) Camera module and method for manufacturing the same
US20130221442A1 (en) Embedded power stage module
TW201711144A (zh) 具有可路由囊封的傳導基板的半導體封裝及方法
CN105140253B (zh) 一种背照式影像芯片晶圆级3d堆叠结构及封装工艺
TW200901435A (en) Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components
US9099450B2 (en) Package structure and method for manufacturing same
TWI599009B (zh) 半導體晶片封裝元件，半導體模組，半導體封裝元件之製造方法及半導體模組之製造方法
TW201143005A (en) Embedded component substrate, semiconductor package structure using the same and fabrication methods thereof
US20100314744A1 (en) Substrate having single patterned metal layer exposing patterned dielectric layer, chip package structure including the substrate, and manufacturing methods thereof
JP2014049477A5 (zh)
JP2010199148A (ja) 半導体センサデバイス及びその製造方法、パッケージ及びその製造方法、モジュール及びその製造方法、並びに電子機器
CN111312690A (zh) 系统级封装及其制备方法
TW201340300A (zh) 光感測器裝置及其製造方法
JP2009246006A (ja) 半導体装置およびその製造方法ならびに半導体装置の実装構造
TWI429043B (zh) 電路板結構、封裝結構與製作電路板的方法
CN105518853B (zh) 嵌入式电子封装和相关联的方法
US9543279B2 (en) Method of manufacturing a single light-emitting structure
TW201705426A (zh) 樹脂密封型半導體裝置及其製造方法
CN109729240B (zh) 摄像模组及其扩展布线封装感光组件和电子设备
CN206558504U (zh) 图像传感器模组
CN110323176B (zh) 一种芯片的三维封装方法及封装结构