US20130221442A1 - Embedded power stage module - Google Patents
Embedded power stage module Download PDFInfo
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- US20130221442A1 US20130221442A1 US13/406,257 US201213406257A US2013221442A1 US 20130221442 A1 US20130221442 A1 US 20130221442A1 US 201213406257 A US201213406257 A US 201213406257A US 2013221442 A1 US2013221442 A1 US 2013221442A1
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- 239000011888 foil Substances 0.000 claims abstract description 89
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims abstract description 32
- 230000005669 field effect Effects 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 238000009713 electroplating Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 239000003990 capacitor Substances 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 5
- 238000013459 approach Methods 0.000 description 11
- 239000012778 molding material Substances 0.000 description 9
- 238000003475 lamination Methods 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 3
- 238000005553 drilling Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000005422 blasting Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000002459 sustained effect Effects 0.000 description 1
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
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- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
Definitions
- the present invention relates to integrated circuit packaging. More specifically, it relates to an integrated circuit package with a power stage module that is embedded in a printed circuit board or a laminated dielectric substrate.
- a DC/DC converter is a circuit that converts an electrical current from one voltage level to another. Such circuits are used in a wide variety of electrical devices. By way of example, different components in the same electrical device may have different voltage requirements, which can be managed using one or more converters.
- a component of a DC/DC converter is the power stage.
- a common type of power stage is the H-bridge configuration.
- FETs asymmetric field effect transistors
- HFET high side FET
- LSFET low side FET
- Some approaches for forming power converters involve placing a FET on a metallic leadframe.
- the FET can be connected to the leadframe using wirebonds.
- the FET can be connected to the leadframe with solder bumps in a flip chip-style arrangement.
- a smaller HSFET is stacked on a larger LSFET that is in turn mounted on the leadframe.
- a single FET is embedded in a printed circuit board (PCB).
- PCB printed circuit board
- Various conductive traces and vias are interspersed between the dielectric layers that make up the substrate.
- a passive device (such as an inductor) may be mounted on the PCB. Portions of the PCB or the passive device may be encapsulated in molding material.
- a method for forming a power stage module is described. Initially, a first field effect transistor (FET) module is provided.
- the first FET module includes a FET that is encased in a laminated, dielectric substrate. Multiple metallic posts are formed on surfaces of the FET.
- the dielectric substrate is formed from multiple dielectric layers that cover the metallic posts and the FET. The top and bottom surfaces of the dielectric substrate are covered with top and bottom foil layers.
- the entire surface of the FET can be metalized and the vias are drilled and then filled. That is, the FETs themselves need not have discrete vias in them
- the holes may be formed, for example, using a laser.
- Metal is electroplated into the holes to form electrically conductive vias.
- each foil layer on the dielectric substrate is electrically connected to the FET through one or more of the vias.
- a second FET is positioned over the first FET module such that the second FET is in electrical and physical contact with the top foil layer on the first FET module.
- a drain of the first FET is electrically connected to a source of the second FET through the top foil layer.
- the first and second FETs are low and high side FETs in an H-bridge configuration. (This approach assumes that both FETs are N-Channel FETs, although other approaches are also possible.)
- Additional dielectric and/or foil layers are positioned around the second FET.
- holes are formed and electroplated with metal to form additional vias.
- the additional layers cooperate to form a second FET module.
- the first and second FET modules are laminated together to form a power stage module.
- the second FET module may be formed gradually by sequentially depositing one or more layers and/or components on the first FET module. One or more lamination operations may be used to bond these layers together with the first FET module.
- the second FET module may be separately formed and then attached as a single structure to the first FET module. That is, multiple dielectric layers, foil layers and an encased FET can be laminated together to form the second FET module. Afterward, the second FET module is aligned over and laminated together with the first FET module.
- Some implementations involve attaching an active or passive device, such as a capacitor, inductor or integrated circuit.
- an inductor or integrated circuit can be mounted over a laminate structure that contains the two FETs.
- portions of the active/passive device and/or the structure are encapsulated in molding material.
- Another aspect of the present invention relates to an integrated circuit package formed using at least some of the steps of the above method.
- FIG. 1 is a diagrammatic side view of an integrated circuit package with an embedded power stage according to a particular embodiment of the present invention.
- FIG. 2 is a diagrammatic bottom view of the integrated circuit package illustrated in FIG. 1 .
- FIG. 3 is a method for forming the integrated circuit package illustrated in FIG. 1 according to a particular embodiment of the present invention.
- FIGS. 4A-4H are diagrammatic side views of various steps in the method described in FIG. 3 .
- FIG. 5 is a diagrammatic side view of an integrated circuit package with an embedded power stage and an attached electrical device according to a particular embodiment of the present invention.
- FIG. 6A is a diagrammatic side view of a panel containing multiple FET modules according to a particular embodiment of the present invention.
- FIG. 6B is a diagrammatic side view of two FET module panels being aligned over one another according to a particular embodiment of the present invention.
- the present invention relates generally to the packaging of integrated circuits. More specifically, the present invention relates to a power stage module that is embedded in printed circuit board or a laminated dielectric substrate.
- a power stage module involves two field effect transistors (FET), a high side FET (HSFET) and a low side FET (LSFET).
- FET field effect transistor
- HSFET high side FET
- LSFET low side FET
- the LSFET and HSFET are electrically coupled such that the drain of the LSFET is connected to the source of the HSFET (i.e., the switch node.)
- FET field effect transistors
- HSFET high side FET
- LSFET low side FET
- an HSFET is stacked over an LSFET, which is in turn mounted on a leadframe.
- the electrical connections in such designs typically involve either bonding wires or solder bumps. Bonding wires, however, have relatively high electrical resistance. Solder bumps are generally better conductors than bonding wires, but they have other limitations. There is a limit to how many solder bumps can be placed in a given area, since there needs to be some amount of mechanical clearance between the bumps. They also require additional processing steps (e.g., the printing of solder paste, a reflow operation, etc.) In a flip chip, leadframe-based package, there is limited flexibility in the design of the electrical interconnects within the package.
- a power stage module including high side and low side FETs is embedded in a laminated dielectric substrate.
- Conductive vias and foil layers electrically connect the FETs with one another and/or contacts on the exterior of the package.
- the vias are formed through laser drilling and electroplating.
- the foil layers can be etched from metallic foils that are laminated together with the dielectric layers in the package. Accordingly, the power density can be greater and there is greater flexibility in the design of the electrical interconnects in the package. That is, the electrical connections can be formed more precisely and arranged more densely than is the case with solder bumps or bonding wires. As a result, power losses and heat generation within the package can be reduced.
- the package 100 includes a power stage made of a low side field effect transistor (LSFET) 102 and a high side field effect transistor (HSFET) 104 .
- the LSFET 102 and HSFET 104 are electrically coupled to one another and are encapsulated in a laminated dielectric substrate 106 (e.g., printed circuit board.)
- the LSFET 102 and HSFET 104 are arranged in an H-bridge configuration.
- the package includes multiple conductive vias and foil layers (i.e., first foil layer 108 a , second foil layer 108 b , third foil layer 108 c , first via 110 a and second via 110 b ).
- Each foil layer includes multiple conductive traces that are etched from a metallic foil. Each of these traces is arranged to route electrical signals between the FETs or from a FET to a contact on the exterior of the package.
- the foil layers are laminated together with the dielectric substrate 106 and can be positioned above or below any FET in the package.
- the vias can be formed in almost any location in the package and can be arranged to electrically connect a foil layer to another underlying foil layer or to an external contact.
- the LSFET 102 and HSFET 104 are electrically coupled with one another through the second foil layer 108 b , which is sandwiched between the LSFET 102 and the HSFET 104 .
- a drain contact 112 on the top surface of the LSFET 102 is physically and electrically coupled to the second foil layer 108 b , which is in turn connected to a source contact 114 on the bottom surface of the HSFET 104 .
- This LS drain/HS source connection i.e.
- the switch node is further physically and electrically coupled to contact 118 on the bottom surface of the package 100 via the second foil layer 108 b and the second via 110 b .
- a gate contact 116 on the bottom surface of the HSFET 104 is electrically coupled to a contact (contact 124 in FIG. 2 ) on the exterior of the package via the second foil layer and another via (not shown.)
- a source contact 126 and a gate contact 128 on the bottom surface of the LSFET 102 are attached via conductive vias to exposed contacts 122 and 120 , respectively, in the first foil layer 108 a at the bottom of the package 100 .
- a drain contact 130 on the top surface of the HSFET 104 is electrically and physically connected to another exposed contact 132 in the first foil layer 108 a through the third foil layer 108 c and the first via 110 a that extends between and directly connects the first and third foil layers.
- FIG. 1 represents only a single embodiment of the present invention.
- the present invention also contemplates a wide variety of alternative embodiments that depart from what is shown in FIG. 1 .
- the foil layers and vias may intersect at different locations or be arranged in different ways.
- the LSFET 102 and HSFET 104 may be stacked such that their respective top and bottom surfaces directly face one another or they may be offset from one another.
- the foil layers may be arranged along parallel planes and/or be offset from one another.
- the third foil layer 108 c is covered with dielectric material, in other embodiments at least portions of it are exposed and/or are used to form contact pads for connecting the package to an external electrical device.
- the LSFET 102 and HSFET 104 may have similar or different sizes.
- the footprint of the HSFET 104 is larger than the LSFET 102 .
- the bottom surface of the HSFET 104 is larger than, completely covers and extends beyond the periphery of the top surface of the LSFET 102 .
- Stacked dice in various conventional leadframe-based packages tend not to be arranged in this manner. That is, in such packages, the lower die, which is mounted on the leadframe, generally has a larger footprint than the upper die so that the upper die is properly supported during the packaging process.
- the sizes of the FETs may vary, depending on the duty cycle and the application. For example, in a step down DC/DC converter the HS FET may be smaller than the LS FET.
- the exposed first foil layer 108 a has been etched to form multiple isolated electrical contacts that can be used to attach the package to external electrical devices. These contacts are connected to the internal circuitry of the package through various vias and foil layers as illustrated in FIG. 1 .
- contact 132 is electrically connected to the drain contact 130 on the top surface of the HSFET 104 illustrated in FIG. 1 .
- Contact 122 is electrically coupled to the source contact 126 on the bottom surface of the LSFET 102 . (In various implementations this contact is electrically grounded.)
- Contact 118 is electrically connected to the source contact 114 and the drain contact 112 on the HSFET 104 and the LSFET 102 , respectively.
- Contacts 120 and 124 are connected, respectively, to the gate contact 128 on the bottom surface of the HSFET 104 and the gate contact 116 on the bottom surface of the LSFET 102 .
- FIGS. 1 and 2 illustrate a package in which only a single (bottom) surface includes contacts
- contacts may be formed on other surfaces of the package as well (e.g., the opposing top surface as well as the bottom surface.)
- the contacts may have any suitable shape or size.
- the contacts are arranged in a ball grid array and are arranged to be soldered to an underlying substrate.
- an active device e.g., an integrated circuit
- a passive device e.g., a capacitor or inductor
- FIG. 5 A particular example of such a design is shown in FIG. 5 . Either of these approaches can provide a means for a low resistance, inductance interconnect from an external device to the power stage electrical nodes.
- FIG. 5 illustrates a package that includes two FETs (LSFET 102 and HSFET 104 ) that are embedded in a laminated dielectric substrate 106 and an electrical device 136 that is mounted on the laminated structure.
- the arrangement of the components in the dielectric substrate 106 can be similar or identical to the substrate 106 illustrated in FIG. 1 .
- the electrical device 136 is encapsulated in molding material 138 (although this is optional.)
- FIG. 5 illustrates only one design involving an additional electrical device and that many other arrangements are also possible. In some implementations, for example, no molding material is used and the electrical device is exposed. In another embodiment, the electrical device and the top and side surfaces of the dielectric substrate are encapsulated in molding material while the bottom surface of the substrate is left exposed.
- the foil layers and vias can be made of any electrically conductive material, such as copper.
- the dielectric substrate 106 is formed from any suitable dielectric material (e.g., printed circuit board, a prepreg material, polymer or a non-conductive epoxy material.)
- the dimensions of the various components may vary widely between different implementations.
- each foil layer may have a thickness of approximately between 20-30 microns.
- Each FET may have a thickness of between 200 and 250 microns, although thinner and thicker FETs may also be used.
- a method 300 for forming the package illustrated in FIG. 1 will be described.
- a first field effect resistor (FET) module 402 of FIG. 4A is provided (step 302 of FIG. 3 .)
- the field effect resistor module 402 includes a first FET 404 a that is encased in one or more dielectric layers that are laminated together to form a dielectric substrate 408 .
- the substrate 106 is sandwiched between two foil layers, first foil layer 108 a and the second foil layer 108 b .
- the foil layers have been etched to form multiple conductive paths or pads.
- the metallic posts 406 On the top and bottom surfaces of the encased FET are multiple metallic posts 406 .
- the metallic posts 406 range from approximately 3 to 7 microns in thickness, although the posts may also be thicker or thinner.
- Metallic posts with a thickness of approximately 5 microns or less work well for various applications.
- the thickness of the posts in some designs are between 3 and 5 microns, as at thicknesses lower than 3 microns there may be a danger of the laser blasting into the device.
- Any suitably conductive metal may be used to form the posts, such as copper.
- the metallic posts 406 are also covered and encased in the dielectric substrate 408 .
- the posts 406 serve as electrical contacts for the first FET 404 a and are physically connected to the circuitry within the FET.
- holes 410 are drilled or formed in the first FET module 402 .
- the holes 410 penetrate through the foil layers and into the dielectric substrate 408 to expose the metallic posts 406 .
- the holes 410 may be formed using any suitable technique. In various implementations, a laser is used to form the holes and ablate away the dielectric material.
- a metal is electroplated into the holes (step 306 of FIG. 3 ).
- a seed layer is applied over each hole.
- the seed layers are covered using a suitable photoresist, which may be positive or negative.
- the photoresist is then patterned and developed to form various open regions in which the seed layer is exposed.
- An electrical current is run through the seed layer, which causes metal to accumulate within the holes. This accumulation of metal forms electrically conductive vias (e.g., see vias 412 in FIG. 4C ) that are connected to the metallic posts 406 on the top and bottom surfaces of the first FET 404 a.
- Additional layers and components are then built over the module. This may be done gradually, layer by layer. Alternatively, additional layers and a second FET may be pre-laminated together to form a second FET module. This second FET module may then be aligned with and laminated together with the FET module. Examples of both approaches will be discussed below.
- a second FET 404 b is positioned on the first FET module 402 .
- the second FET 404 b has metallic posts 414 on its bottom surface, which in some embodiments have the same dimensions and characteristics as the metallic posts 406 in FIGS. 4A-4B . These metallic posts 414 electrically and physically connect the second FET 404 b to the traces of the second foil layer 108 b (step 308 of FIG. 3 )
- Additional layers are then positioned around the second FET using any technique known to persons of ordinary skill in the field of integrated circuit packaging and printed circuit board fabrication ( FIGS. 4E and 4F and step 310 of FIG. 3 )
- the additional layers can include one or more dielectric and/or foil layers.
- a dielectric layer 416 is positioned over the first FET module and the second foil layer.
- the dielectric layer 416 which includes an aperture, is positioned such that the second FET 404 b fits within the aperture.
- a third foil layer 108 c of FIG. 4F and one or more additional dielectric layers are then positioned over the dielectric layer 416 and the second FET 404 b .
- the additional layers and the second FET 404 b collectively form a second FET module.
- the first and second FET modules once suitably aligned and positioned over one another, are laminated together (step 312 of FIG. 3 and FIG. 4F .)
- the lamination process involves subjecting the two modules to substantial amounts of heat and pressure (e.g., pressures between 150 and 650 psi and temperatures between 125° C. and 200° C. for up to 3-4 hours. In some lamination processes, a temperature of approximately around 200° C. or 180-200° C. works well.)
- the lamination causes the two modules to form a single structure that encases the multiple FETs.
- one or more additional vias are formed at this stage.
- vias 110 a and 110 b can be formed using the techniques described earlier to form vias 412 of FIG. 4C (e.g., laser drilling, electroplating, etc.) Such vias can be formed before or after the aforementioned lamination step (step 312 of FIG. 3 ).
- the resulting package is illustrated in FIG. 4H , which can be identical to the package 100 illustrated in FIG. 1 .
- FIG. 4G Another approach for forming the integrated circuit package 100 is to preform and prelaminate the second FET module, and then to laminate the second FET module together with the first FET module.
- a preformed, second FET module 418 is illustrated.
- the preformed second FET module 418 includes one or more dielectric layers that have been pre-laminated around the second FET 404 b .
- One or more foil layers are interspersed between dielectric layers in the second FET module 418 .
- the layers and components of the second FET module 418 have been pre-laminated together prior to attachment to the first FET module 402 .
- the second FET module 418 is then aligned over the first FET module 402 .
- the via 420 b in the second FET module 418 is aligned with the via 420 a in the first FET module 402 .
- the traces and/or contacts on the foil layer on the bottom surface of the second FET module 418 are also aligned with traces and/or contacts on the second foil layer 108 b on the top surface of the first FET module 402 .
- the first and second FET modules 402 / 418 are then positioned onto one another and laminated together. As a result, the two vias 420 a and 420 b cooperate to create the first via 110 a and the integrated circuit package 100 of FIGS. 1 and 4H is formed.
- one or more additional electrical devices can be attached to the structure (step 314 of FIG. 3 and FIG. 5 )
- an electrical device 136 e.g., an inductor
- the contact pads 422 are connected with one or more vias that electrically couple the electrical device 136 with one of the FETs.
- the electrical device 136 can be any suitable passive or active device, such as a capacitor or an integrated circuit. There may also be more than one component that is added at this stage.
- a portion of the laminated structure is encapsulated in molding material (step 316 of FIG. 3 ).
- molding material 138 encapsulates the electrical device 136 and the top surface of the laminated structure.
- molding material covers the top and side surfaces of the laminated structure, while leaving the bottom surface and its associated contact pads uncovered.
- no molding material is used and the laminated structure is exposed.
- FIG. 6A illustrates an example panel 424 with multiple device areas.
- Each device area includes the components (e.g., dielectric substrate 106 , first FET 404 a , first foil layer 108 a , second foil layer 108 b ) illustrated in FIG. 4A .
- the operations described in FIG. 3 and FIGS. 4B-4F and 5 can be applied substantially simultaneously over each of the device areas such that each device area supports a laminated structure as illustrated in FIG. 4F or FIG. 5 . That is, the panel 424 then includes multiple such laminated structures that are part of a single, continuous panel.
- the panel 424 is then singulated to form individual, integrated circuit packages that are similar or identical to package 100 of FIG. 1 or FIG. 4F .
- FIG. 6B illustrates a similar panel-level approach involving the techniques described in connection with FIG. 4G . That is, the first laminated panel 424 also includes multiple device areas, each of which supports the first module 402 of FIG. 4G .
- the second laminated panel 426 includes multiple device areas, each of which supports the second module 418 of FIG. 4G .
- the device areas of the first and second panels are then aligned with one another and laminated together to form a single, larger panel. This panel is then singulated into multiple individual integrated circuit packages (e.g., each identical to the package 100 of FIG. 1 ) as discussed above.
- the present invention should not be understood as being limited to these illustrations in any way.
- Almost any technique known in the field of PCB manufacturing can be used to attach or embed second FET 418 of FIGS. 4E-4H .
- a dielectric layer may be added over the first module that is prelaminated with other dielectric layers, an etched foil layer, and/or an active or passive component. Fewer or more lamination operations may be used relative to what was previously described.
- Any reference to the word “lamination” can, in various embodiments, be understood as referring to the use of sustained, high pressures and temperatures to bond together disparate components e.g., pressures between 150 and 650 psi and temperatures between 125° C. and 200° C.
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Abstract
Description
- The present invention relates to integrated circuit packaging. More specifically, it relates to an integrated circuit package with a power stage module that is embedded in a printed circuit board or a laminated dielectric substrate.
- A DC/DC converter is a circuit that converts an electrical current from one voltage level to another. Such circuits are used in a wide variety of electrical devices. By way of example, different components in the same electrical device may have different voltage requirements, which can be managed using one or more converters.
- A component of a DC/DC converter is the power stage. A common type of power stage is the H-bridge configuration. In the H-bridge configuration, two asymmetric field effect transistors (FETs), a high side FET (HSFET) and a low side FET (LSFET) are coupled with one another and an inductor.
- Some approaches for forming power converters involve placing a FET on a metallic leadframe. The FET can be connected to the leadframe using wirebonds. Alternatively, the FET can be connected to the leadframe with solder bumps in a flip chip-style arrangement. In some implementations, a smaller HSFET is stacked on a larger LSFET that is in turn mounted on the leadframe.
- In another design, a single FET is embedded in a printed circuit board (PCB). Various conductive traces and vias are interspersed between the dielectric layers that make up the substrate. A passive device (such as an inductor) may be mounted on the PCB. Portions of the PCB or the passive device may be encapsulated in molding material.
- Although the above approaches work well for various applications, there are continuing efforts to improve the efficiency and reliability of power converters.
- In one aspect of the present invention, a method for forming a power stage module is described. Initially, a first field effect transistor (FET) module is provided. The first FET module includes a FET that is encased in a laminated, dielectric substrate. Multiple metallic posts are formed on surfaces of the FET. The dielectric substrate is formed from multiple dielectric layers that cover the metallic posts and the FET. The top and bottom surfaces of the dielectric substrate are covered with top and bottom foil layers. In some embodiments, the entire surface of the FET can be metalized and the vias are drilled and then filled. That is, the FETs themselves need not have discrete vias in them
- Multiple holes are formed through the foil layers and the dielectric substrate to expose the metallic posts on the top and bottom surfaces of the FET. The holes may be formed, for example, using a laser. Metal is electroplated into the holes to form electrically conductive vias. As a result, each foil layer on the dielectric substrate is electrically connected to the FET through one or more of the vias. A second FET is positioned over the first FET module such that the second FET is in electrical and physical contact with the top foil layer on the first FET module. As a result, a drain of the first FET is electrically connected to a source of the second FET through the top foil layer. In various embodiments, the first and second FETs are low and high side FETs in an H-bridge configuration. (This approach assumes that both FETs are N-Channel FETs, although other approaches are also possible.)
- Additional dielectric and/or foil layers are positioned around the second FET. Optionally, holes are formed and electroplated with metal to form additional vias. The additional layers cooperate to form a second FET module. The first and second FET modules are laminated together to form a power stage module.
- A wide variety of techniques may be used to form the aforementioned power stage module. For example, the second FET module may be formed gradually by sequentially depositing one or more layers and/or components on the first FET module. One or more lamination operations may be used to bond these layers together with the first FET module. Alternatively, the second FET module may be separately formed and then attached as a single structure to the first FET module. That is, multiple dielectric layers, foil layers and an encased FET can be laminated together to form the second FET module. Afterward, the second FET module is aligned over and laminated together with the first FET module.
- Some implementations involve attaching an active or passive device, such as a capacitor, inductor or integrated circuit. By way of example, an inductor or integrated circuit can be mounted over a laminate structure that contains the two FETs. In some approaches, portions of the active/passive device and/or the structure are encapsulated in molding material.
- Another aspect of the present invention relates to an integrated circuit package formed using at least some of the steps of the above method.
- The invention and the advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings in which:
-
FIG. 1 is a diagrammatic side view of an integrated circuit package with an embedded power stage according to a particular embodiment of the present invention. -
FIG. 2 is a diagrammatic bottom view of the integrated circuit package illustrated inFIG. 1 . -
FIG. 3 is a method for forming the integrated circuit package illustrated inFIG. 1 according to a particular embodiment of the present invention. -
FIGS. 4A-4H are diagrammatic side views of various steps in the method described inFIG. 3 . -
FIG. 5 is a diagrammatic side view of an integrated circuit package with an embedded power stage and an attached electrical device according to a particular embodiment of the present invention. -
FIG. 6A is a diagrammatic side view of a panel containing multiple FET modules according to a particular embodiment of the present invention. -
FIG. 6B is a diagrammatic side view of two FET module panels being aligned over one another according to a particular embodiment of the present invention. - In the drawings, like reference numerals are sometimes used to designate like structural elements. It should also be appreciated that the depictions in the figures are diagrammatic and not to scale.
- The present invention relates generally to the packaging of integrated circuits. More specifically, the present invention relates to a power stage module that is embedded in printed circuit board or a laminated dielectric substrate.
- A power stage module involves two field effect transistors (FET), a high side FET (HSFET) and a low side FET (LSFET). The LSFET and HSFET are electrically coupled such that the drain of the LSFET is connected to the source of the HSFET (i.e., the switch node.) In various applications, it is desirable to minimize the electrical resistance at the switch node. However, in other applications, this is less of a priority, as arranging the electrical connections in the power stage module to reduce conduction losses can result in an increase in the size of the package.
- When the LSFET and HSFET are stacked over one another, it can be particularly advantageous to improve the efficiency of the power stage module. Power losses generate increased heat within the package, and the heat tends to travel directly through the stacked integrated circuits.
- In various prior art designs, an HSFET is stacked over an LSFET, which is in turn mounted on a leadframe. The electrical connections in such designs typically involve either bonding wires or solder bumps. Bonding wires, however, have relatively high electrical resistance. Solder bumps are generally better conductors than bonding wires, but they have other limitations. There is a limit to how many solder bumps can be placed in a given area, since there needs to be some amount of mechanical clearance between the bumps. They also require additional processing steps (e.g., the printing of solder paste, a reflow operation, etc.) In a flip chip, leadframe-based package, there is limited flexibility in the design of the electrical interconnects within the package. That is, in such packages most or all of the electrical routing takes place at the level of the leadframe. Also, in some prior art designs, most of the materials used involve high lead materials (non-ROHS). Various embodiments of the present invention involve an approach to achieve low power loss, i.e., “green” interconnect at a system level.
- Various embodiments of the present invention address these issues. In a particular implementation, a power stage module including high side and low side FETs is embedded in a laminated dielectric substrate. Conductive vias and foil layers electrically connect the FETs with one another and/or contacts on the exterior of the package. In some implementations, the vias are formed through laser drilling and electroplating. The foil layers can be etched from metallic foils that are laminated together with the dielectric layers in the package. Accordingly, the power density can be greater and there is greater flexibility in the design of the electrical interconnects in the package. That is, the electrical connections can be formed more precisely and arranged more densely than is the case with solder bumps or bonding wires. As a result, power losses and heat generation within the package can be reduced.
- Referring now to
FIG. 1 , anintegrated circuit package 100 according to a particular embodiment of the present invention will be described. Thepackage 100 includes a power stage made of a low side field effect transistor (LSFET) 102 and a high side field effect transistor (HSFET) 104. TheLSFET 102 andHSFET 104 are electrically coupled to one another and are encapsulated in a laminated dielectric substrate 106 (e.g., printed circuit board.) In various designs, theLSFET 102 andHSFET 104 are arranged in an H-bridge configuration. The package includes multiple conductive vias and foil layers (i.e.,first foil layer 108 a,second foil layer 108 b,third foil layer 108 c, first via 110 a and second via 110 b). Each foil layer includes multiple conductive traces that are etched from a metallic foil. Each of these traces is arranged to route electrical signals between the FETs or from a FET to a contact on the exterior of the package. - The foil layers are laminated together with the
dielectric substrate 106 and can be positioned above or below any FET in the package. The vias can be formed in almost any location in the package and can be arranged to electrically connect a foil layer to another underlying foil layer or to an external contact. - The above arrangement allows for a wide variety of electrical interconnect designs. In the illustrated embodiment, for example, the
LSFET 102 andHSFET 104 are electrically coupled with one another through thesecond foil layer 108 b, which is sandwiched between theLSFET 102 and theHSFET 104. In the example illustrated inFIG. 1 , adrain contact 112 on the top surface of theLSFET 102 is physically and electrically coupled to thesecond foil layer 108 b, which is in turn connected to asource contact 114 on the bottom surface of theHSFET 104. This LS drain/HS source connection (i.e. the switch node) is further physically and electrically coupled to contact 118 on the bottom surface of thepackage 100 via thesecond foil layer 108 b and the second via 110 b. Additionally, agate contact 116 on the bottom surface of theHSFET 104 is electrically coupled to a contact (contact 124 inFIG. 2 ) on the exterior of the package via the second foil layer and another via (not shown.) Asource contact 126 and agate contact 128 on the bottom surface of theLSFET 102 are attached via conductive vias to exposedcontacts first foil layer 108 a at the bottom of thepackage 100. Adrain contact 130 on the top surface of theHSFET 104 is electrically and physically connected to another exposedcontact 132 in thefirst foil layer 108 a through thethird foil layer 108 c and the first via 110 a that extends between and directly connects the first and third foil layers. - It should be appreciated, however, that
FIG. 1 represents only a single embodiment of the present invention. The present invention also contemplates a wide variety of alternative embodiments that depart from what is shown inFIG. 1 . By way of example, the foil layers and vias may intersect at different locations or be arranged in different ways. TheLSFET 102 andHSFET 104 may be stacked such that their respective top and bottom surfaces directly face one another or they may be offset from one another. The foil layers may be arranged along parallel planes and/or be offset from one another. Although in the illustrated embodiment thethird foil layer 108 c is covered with dielectric material, in other embodiments at least portions of it are exposed and/or are used to form contact pads for connecting the package to an external electrical device. - The
LSFET 102 andHSFET 104 may have similar or different sizes. In a particular design, the footprint of theHSFET 104 is larger than theLSFET 102. More specifically, the bottom surface of theHSFET 104 is larger than, completely covers and extends beyond the periphery of the top surface of theLSFET 102. Stacked dice in various conventional leadframe-based packages tend not to be arranged in this manner. That is, in such packages, the lower die, which is mounted on the leadframe, generally has a larger footprint than the upper die so that the upper die is properly supported during the packaging process. The sizes of the FETs may vary, depending on the duty cycle and the application. For example, in a step down DC/DC converter the HS FET may be smaller than the LS FET. - Referring next to
FIG. 2 , the bottom surface of the package illustrated inFIG. 1 will be described. The exposedfirst foil layer 108 a has been etched to form multiple isolated electrical contacts that can be used to attach the package to external electrical devices. These contacts are connected to the internal circuitry of the package through various vias and foil layers as illustrated inFIG. 1 . - There are numerous ways in which the internal components of the package can be connected to the contacts on the exterior of the package. In the illustrated embodiment, for example, contact 132 is electrically connected to the
drain contact 130 on the top surface of theHSFET 104 illustrated inFIG. 1 . Contact 122 is electrically coupled to thesource contact 126 on the bottom surface of theLSFET 102. (In various implementations this contact is electrically grounded.) Contact 118 is electrically connected to thesource contact 114 and thedrain contact 112 on theHSFET 104 and theLSFET 102, respectively.Contacts gate contact 128 on the bottom surface of theHSFET 104 and thegate contact 116 on the bottom surface of theLSFET 102. The contacts are separated from one another by portions of thedielectric substrate 106. Many other arrangements are also possible. AlthoughFIGS. 1 and 2 illustrate a package in which only a single (bottom) surface includes contacts, contacts may be formed on other surfaces of the package as well (e.g., the opposing top surface as well as the bottom surface.) The contacts may have any suitable shape or size. In some embodiments the contacts are arranged in a ball grid array and are arranged to be soldered to an underlying substrate. - Some designs involve adding additional electrical components to the package. For example, an active device (e.g., an integrated circuit) or a passive device (e.g., a capacitor or inductor) can be embedded in the package or mounted on a surface of the substrate illustrated in
FIG. 1 . A particular example of such a design is shown inFIG. 5 . Either of these approaches can provide a means for a low resistance, inductance interconnect from an external device to the power stage electrical nodes. -
FIG. 5 illustrates a package that includes two FETs (LSFET 102 and HSFET 104) that are embedded in a laminateddielectric substrate 106 and anelectrical device 136 that is mounted on the laminated structure. Generally, the arrangement of the components in thedielectric substrate 106 can be similar or identical to thesubstrate 106 illustrated inFIG. 1 . In the illustrated embodiment, theelectrical device 136 is encapsulated in molding material 138 (although this is optional.) It should be appreciated thatFIG. 5 illustrates only one design involving an additional electrical device and that many other arrangements are also possible. In some implementations, for example, no molding material is used and the electrical device is exposed. In another embodiment, the electrical device and the top and side surfaces of the dielectric substrate are encapsulated in molding material while the bottom surface of the substrate is left exposed. - Generally, the foil layers and vias can be made of any electrically conductive material, such as copper. The
dielectric substrate 106 is formed from any suitable dielectric material (e.g., printed circuit board, a prepreg material, polymer or a non-conductive epoxy material.) The dimensions of the various components may vary widely between different implementations. By way of example, each foil layer may have a thickness of approximately between 20-30 microns. Each FET may have a thickness of between 200 and 250 microns, although thinner and thicker FETs may also be used. - Referring next to
FIG. 3 andFIGS. 4A-4H , amethod 300 for forming the package illustrated inFIG. 1 will be described. Initially, a first field effect resistor (FET)module 402 ofFIG. 4A is provided (step 302 ofFIG. 3 .) The fieldeffect resistor module 402 includes afirst FET 404 a that is encased in one or more dielectric layers that are laminated together to form adielectric substrate 408. Thesubstrate 106 is sandwiched between two foil layers,first foil layer 108 a and thesecond foil layer 108 b. The foil layers have been etched to form multiple conductive paths or pads. - On the top and bottom surfaces of the encased FET are multiple
metallic posts 406. In some embodiments, themetallic posts 406 range from approximately 3 to 7 microns in thickness, although the posts may also be thicker or thinner. Metallic posts with a thickness of approximately 5 microns or less work well for various applications. For example, the thickness of the posts in some designs are between 3 and 5 microns, as at thicknesses lower than 3 microns there may be a danger of the laser blasting into the device. Any suitably conductive metal may be used to form the posts, such as copper. Themetallic posts 406 are also covered and encased in thedielectric substrate 408. Theposts 406 serve as electrical contacts for thefirst FET 404 a and are physically connected to the circuitry within the FET. - In
step 304 ofFIG. 3 andFIG. 4B , holes 410 are drilled or formed in thefirst FET module 402. Theholes 410 penetrate through the foil layers and into thedielectric substrate 408 to expose the metallic posts 406. Theholes 410 may be formed using any suitable technique. In various implementations, a laser is used to form the holes and ablate away the dielectric material. - Afterward, a metal is electroplated into the holes (step 306 of
FIG. 3 ). For example, in a particular implementation, a seed layer is applied over each hole. The seed layers are covered using a suitable photoresist, which may be positive or negative. The photoresist is then patterned and developed to form various open regions in which the seed layer is exposed. An electrical current is run through the seed layer, which causes metal to accumulate within the holes. This accumulation of metal forms electrically conductive vias (e.g., see vias 412 inFIG. 4C ) that are connected to themetallic posts 406 on the top and bottom surfaces of thefirst FET 404 a. - Additional layers and components are then built over the module. This may be done gradually, layer by layer. Alternatively, additional layers and a second FET may be pre-laminated together to form a second FET module. This second FET module may then be aligned with and laminated together with the FET module. Examples of both approaches will be discussed below.
- In an example of a more gradual approach, in
FIG. 4D asecond FET 404 b is positioned on thefirst FET module 402. Thesecond FET 404 b hasmetallic posts 414 on its bottom surface, which in some embodiments have the same dimensions and characteristics as themetallic posts 406 inFIGS. 4A-4B . Thesemetallic posts 414 electrically and physically connect thesecond FET 404 b to the traces of thesecond foil layer 108 b (step 308 ofFIG. 3 ) - Additional layers are then positioned around the second FET using any technique known to persons of ordinary skill in the field of integrated circuit packaging and printed circuit board fabrication (
FIGS. 4E and 4F and step 310 ofFIG. 3 ) The additional layers can include one or more dielectric and/or foil layers. In the illustrated embodiment ofFIG. 4E , for example, adielectric layer 416 is positioned over the first FET module and the second foil layer. Thedielectric layer 416, which includes an aperture, is positioned such that thesecond FET 404 b fits within the aperture. Athird foil layer 108 c ofFIG. 4F and one or more additional dielectric layers are then positioned over thedielectric layer 416 and thesecond FET 404 b. The additional layers and thesecond FET 404 b collectively form a second FET module. - Afterward, the first and second FET modules, once suitably aligned and positioned over one another, are laminated together (step 312 of
FIG. 3 andFIG. 4F .) The lamination process involves subjecting the two modules to substantial amounts of heat and pressure (e.g., pressures between 150 and 650 psi and temperatures between 125° C. and 200° C. for up to 3-4 hours. In some lamination processes, a temperature of approximately around 200° C. or 180-200° C. works well.) The lamination causes the two modules to form a single structure that encases the multiple FETs. - In some embodiments, one or more additional vias are formed at this stage. For example, vias 110 a and 110 b can be formed using the techniques described earlier to form vias 412 of
FIG. 4C (e.g., laser drilling, electroplating, etc.) Such vias can be formed before or after the aforementioned lamination step (step 312 ofFIG. 3 ). The resulting package is illustrated inFIG. 4H , which can be identical to thepackage 100 illustrated inFIG. 1 . - Another approach for forming the
integrated circuit package 100 is to preform and prelaminate the second FET module, and then to laminate the second FET module together with the first FET module. InFIG. 4G , for example, a preformed,second FET module 418 is illustrated. The preformedsecond FET module 418 includes one or more dielectric layers that have been pre-laminated around thesecond FET 404 b. One or more foil layers are interspersed between dielectric layers in thesecond FET module 418. In this example, there is a foil layer on the bottom surface of thesecond FET module 418 that is arranged to be electrically and physically coupled to thesecond foil layer 108 b on the top surface of thefirst FET module 402. There may also be one or more vias that have been formed (e.g., using the drilling/electroplating techniques discussed earlier) in thesecond FET module 418. The layers and components of thesecond FET module 418 have been pre-laminated together prior to attachment to thefirst FET module 402. - The
second FET module 418 is then aligned over thefirst FET module 402. In the illustrated embodiment, the via 420 b in thesecond FET module 418 is aligned with the via 420 a in thefirst FET module 402. The traces and/or contacts on the foil layer on the bottom surface of thesecond FET module 418 are also aligned with traces and/or contacts on thesecond foil layer 108 b on the top surface of thefirst FET module 402. The first andsecond FET modules 402/418 are then positioned onto one another and laminated together. As a result, the twovias integrated circuit package 100 ofFIGS. 1 and 4H is formed. - Optionally, one or more additional electrical devices can be attached to the structure (step 314 of
FIG. 3 andFIG. 5 ) InFIG. 5 , for example, an electrical device 136 (e.g., an inductor) is soldered to contact pads 422 on the top surface of the laminated structure. (The laminated structure may be almost identical to and/or have any of the features of thepackage 100 illustrated inFIG. 1 or 4H.) The contact pads 422 are connected with one or more vias that electrically couple theelectrical device 136 with one of the FETs. Theelectrical device 136 can be any suitable passive or active device, such as a capacitor or an integrated circuit. There may also be more than one component that is added at this stage. - In another optional step, a portion of the laminated structure is encapsulated in molding material (step 316 of
FIG. 3 ). In the embodiment illustrated inFIG. 5 , for example,molding material 138 encapsulates theelectrical device 136 and the top surface of the laminated structure. In another embodiment, molding material covers the top and side surfaces of the laminated structure, while leaving the bottom surface and its associated contact pads uncovered. In still other embodiments, no molding material is used and the laminated structure is exposed. - Although the above figures illustrate the formation of a single package using two FETs, it should be appreciated that such packages are preferably formed on a panel level in which multiple packages can be formed concurrently.
FIG. 6A illustrates anexample panel 424 with multiple device areas. Each device area includes the components (e.g.,dielectric substrate 106,first FET 404 a,first foil layer 108 a,second foil layer 108 b) illustrated inFIG. 4A . The operations described inFIG. 3 andFIGS. 4B-4F and 5 can be applied substantially simultaneously over each of the device areas such that each device area supports a laminated structure as illustrated inFIG. 4F orFIG. 5 . That is, thepanel 424 then includes multiple such laminated structures that are part of a single, continuous panel. Thepanel 424 is then singulated to form individual, integrated circuit packages that are similar or identical to package 100 ofFIG. 1 orFIG. 4F . -
FIG. 6B illustrates a similar panel-level approach involving the techniques described in connection withFIG. 4G . That is, the firstlaminated panel 424 also includes multiple device areas, each of which supports thefirst module 402 ofFIG. 4G . The secondlaminated panel 426 includes multiple device areas, each of which supports thesecond module 418 ofFIG. 4G . The device areas of the first and second panels are then aligned with one another and laminated together to form a single, larger panel. This panel is then singulated into multiple individual integrated circuit packages (e.g., each identical to thepackage 100 ofFIG. 1 ) as discussed above. - Although only a few embodiments of the invention have been described in detail, it should be appreciated that the invention may be implemented in many other forms without departing from the spirit or scope of the invention. The figures depict specific arrangements of vias, foil layers, contact pads, integrated circuits and dielectric layers. However, it should be appreciated that these components can be arranged in a wide variety of ways that depart from what is shown in the figures. By way of example, the present invention contemplates FETs that are stacked directly over one another as well as offset. There may be more or fewer vias and foil layers. Additional passive and active components can be mounted on any surface of the package or embedded within the dielectric substrate. While particular steps for making the integrated circuit package are shown in
FIGS. 4-6 , the present invention should not be understood as being limited to these illustrations in any way. Almost any technique known in the field of PCB manufacturing can be used to attach or embedsecond FET 418 ofFIGS. 4E-4H . By way of example, a dielectric layer may be added over the first module that is prelaminated with other dielectric layers, an etched foil layer, and/or an active or passive component. Fewer or more lamination operations may be used relative to what was previously described. Any reference to the word “lamination” can, in various embodiments, be understood as referring to the use of sustained, high pressures and temperatures to bond together disparate components e.g., pressures between 150 and 650 psi and temperatures between 125° C. and 200° C. (e.g., around 180-200° C.) for up to 3-4 hours. Therefore, the present embodiments should be considered as illustrative and not restrictive and the invention is not limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.
Claims (20)
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