CN111599696A - Semiconductor module packaging method and semiconductor module - Google Patents
Semiconductor module packaging method and semiconductor module Download PDFInfo
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- CN111599696A CN111599696A CN202010466820.5A CN202010466820A CN111599696A CN 111599696 A CN111599696 A CN 111599696A CN 202010466820 A CN202010466820 A CN 202010466820A CN 111599696 A CN111599696 A CN 111599696A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
Abstract
The application provides a semiconductor module packaging method and a semiconductor module. The semiconductor module packaging method comprises the following steps: attaching the chip, the passive component and the plurality of conductive columns to a first conductive metal layer of the DBC board; mounting a DBC plate on a carrier plate; the packaging layer covers the whole carrier plate, and the chip, the passive component, the conductive post and the DBC plate are subjected to plastic packaging to form a packaging structural component; and forming a rewiring structure on the first surface of the encapsulation structure, wherein the back surface of the chip is directly and electrically connected with the rewiring structure, and the passive component and the front surface of the chip are respectively and electrically connected with the rewiring structure through different conductive columns. The semiconductor module is manufactured by the semiconductor module packaging method. The semiconductor module has excellent heat dissipation effect, has the advantages of small volume, compact structure and high reliability, and is suitable for small-sized light-weight electronic equipment; compared with the traditional lead bonding packaging mode, the packaging method has the advantages of small impedance and strong current capacity.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor module packaging method and a semiconductor module.
Background
The plastic package type IPM module (intelligent power module) is a novel control module integrating an IGBT (insulated gate bipolar transistor) chip, a driving circuit thereof, a control circuit thereof, and protection circuits such as overcurrent, undervoltage, short circuit, and overheat.
The plastic packaging type IPM module is a complex and advanced power module, can automatically realize complex protection functions of overcurrent, undervoltage, short circuit, overheating and the like, and has intelligent characteristics. Meanwhile, the device has the advantages of low cost, miniaturization, high reliability, easy use and the like, is widely applied to the fields of variable frequency household appliances, inverter power supplies, industrial control and the like, and has considerable social and economic benefits.
For the plastic package type IPM module, as shown in fig. 1, a DBC board 30 ' and a lead frame 40 ' are usually disposed inside the module, a package structure is fabricated by fixing a chip 11 ' and a passive component 12 ' on the lead frame 40 ', and an electrical connection function is completed by bonding a lead 20 ', and then the package structure is fixed on the DBC board 30 ', and the DBC board 30 ' and the lead frame 40 ' are fixed and electrically connected by soldering, and finally, an external electrical connection is achieved through a lead 41 ' of the lead frame 40 '.
However, the IPM module in the prior art has poor heat dissipation effect and large volume due to the need of the lead frame, and has the problems of low yield efficiency and poor current-carrying capacity due to the interconnection of the electronic components in the package structure and the lead frame through leads.
Disclosure of Invention
One aspect of the present application provides a semiconductor module packaging method, which includes:
s1: attaching a chip, a passive component and a plurality of conductive columns to a first conductive metal layer of a DBC board, wherein the plurality of conductive columns are respectively arranged corresponding to the chip and the passive component, the front surface of the chip faces the first conductive metal layer of the DBC board, the front surface of the chip is electrically connected with the corresponding conductive columns through the first conductive metal layer of the DBC board, and the passive component is electrically connected with the corresponding conductive columns through the first conductive metal layer of the DBC board;
s2: attaching the DBC board to a carrier board, wherein a second conductive metal layer arranged opposite to the first conductive metal layer in the DBC board faces the carrier board;
s3: covering the whole carrier plate by an encapsulating layer, and plastically packaging the chip, the driven piece, the conductive column and the DBC plate to form an encapsulating structural member;
s4: and forming a rewiring structure on the first surface of the encapsulation structure, wherein the back surface of the chip is directly and electrically connected with the rewiring structure, and the driven piece and the front surface of the chip are respectively and electrically connected with the rewiring structure through different conductive columns.
Optionally, the enclosing structure includes the first surface and the second surface disposed oppositely, and the second surface faces the carrier plate, in step S3, the method includes:
and grinding the first surface of the encapsulating structure member to expose one end, far away from the DBC plate, of the conductive column to the first surface of the encapsulating structure member.
Optionally, in step S4, the method includes:
s41: sequentially forming a first redistribution layer and a conductive convex column on the first surface of the encapsulation structure, wherein the back surface of the chip and one end, far away from the DBC plate, of the conductive column are electrically connected with the first redistribution layer;
s42: and forming a first dielectric layer on the first redistribution layer and the exposed first surface of the encapsulation structure, and exposing one end of the conductive pillar, which is far away from the first redistribution layer, on one surface of the first dielectric layer, which is far away from the encapsulation structure.
Optionally, step S42 includes:
forming a first dielectric layer on the first redistribution layer, the conductive posts, and the exposed first surface of the encapsulation structure;
and grinding a surface of the first dielectric layer far away from the encapsulation structure, so that one end of the conductive convex column far away from the first rewiring layer is exposed out of a surface of the first dielectric layer far away from the encapsulation structure.
Optionally, after step S42, the method further includes:
s43: forming a second rewiring layer on the first dielectric layer and the conductive posts;
s44: and forming a second dielectric layer on the first dielectric layer, and exposing one end of the second rewiring layer, which is far away from the conductive convex column, on one surface of the second dielectric layer, which is far away from the first dielectric layer.
Optionally, step S44 includes:
forming a second dielectric layer on the second rewiring layer and the exposed first dielectric layer;
and grinding one surface of the second dielectric layer far away from the encapsulation structure, so that one end of the second rewiring layer far away from the first rewiring layer is exposed out of one surface of the second dielectric layer far away from the encapsulation structure.
Optionally, after step S4, the method further includes:
s5: and forming a metal connecting layer on one side of the rewiring structure far away from the encapsulation structure, wherein the metal connecting layer is directly connected with the rewiring structure.
Optionally, in step S5, the metal connection layer is located on a side of the conductive pillar away from the first redistribution layer and directly connected to the conductive pillar.
Optionally, before step S5, the method further includes: stripping the carrier plate; alternatively, the first and second electrodes may be,
after step S5, the method further includes: and stripping the carrier plate.
A second aspect of the present application provides a semiconductor module, comprising:
the encapsulation structure comprises a first surface and a second surface which are opposite, and is provided with an inwards concave cavity, the DBC plate, the chip, the driven piece and the conductive posts are all positioned in the cavity, the conductive posts are respectively arranged corresponding to the chip and the driven piece, the DBC board comprises a first conductive metal layer and a second conductive metal layer which are oppositely arranged, the chip, the driven piece and the conductive column are fixed on the first conductive metal layer of the DBC board, the second conductive metal layer of the DBC plate is exposed out of the second surface of the encapsulation structure, the chip comprises a front surface and a back surface which are oppositely arranged, the back surface of the chip faces the bottom of the cavity, the front surface of the chip is electrically connected with the corresponding conductive posts through the first conductive metal layer of the DBC plate, the driven piece is electrically connected with the corresponding conductive columns through the first conductive metal layer of the DBC board;
and the rewiring structure is formed on the first surface of the encapsulation structure corresponding to the back surface of the chip, the back surfaces of the chip and the conductive columns, which are electrically connected with the rewiring structure, are directly and electrically connected with the rewiring structure, and the driven piece and the front surface of the chip are respectively and electrically connected with the rewiring structure through different conductive columns.
Optionally, the semiconductor module further includes a metal connection layer, where the metal connection layer is located on a surface of the rewiring structure away from the encapsulation structure and is directly connected to the rewiring structure.
Optionally, in the thickness direction of the semiconductor module, the thickness of the conductive pillar is not less than the thickness of the chip and not less than the thickness of the driven member; one end of the conductive column, which is far away from the DBC plate, is exposed out of the first surface of the encapsulation structure.
Optionally, the rewiring structure includes:
the first redistribution layer is formed on the first surface of the encapsulation structure, and the back surface of the chip and one end, far away from the DBC board, of the conductive column are electrically connected with the first redistribution layer;
the conductive convex column is formed on one side, away from the encapsulation structure, of the first rewiring layer;
the first dielectric layer is formed on the first rewiring layer, the conductive convex column and the exposed first surface of the encapsulation structure, and one end, far away from the encapsulation structure, of the conductive convex column is exposed on one surface, far away from the encapsulation structure, of the first dielectric layer.
Optionally, the metal connection layer is located on a side of the conductive pillar away from the first redistribution layer, and the metal connection layer is directly connected to the conductive pillar.
Optionally, the rewiring structure further includes:
a second rewiring layer formed on the first dielectric layer, the second rewiring layer being electrically connected to the conductive posts;
and the second dielectric layer is formed on the first dielectric layer, and one end of the second rewiring layer, which is far away from the conductive convex column, is exposed out of one surface of the second dielectric layer, which is far away from the first dielectric layer.
Compared with the prior art, the semiconductor module and the packaging method thereof provided by the embodiment of the application do not need a lead frame, so that the overall volume and the product cost of the semiconductor module are greatly reduced, and the semiconductor module has the advantages of small volume and compact structure and is suitable for small-sized light-weight electronic equipment; double-sided heat dissipation is realized through the DBC board and the rewiring structure; moreover, due to the leadless interconnection, the impedance can be reduced, the current capacity can be increased, and the layout is more free and flexible; meanwhile, the thickness of the product is freely controllable, an independent plastic package mold is not needed, and the size of the product is freely switched.
The embodiment is applied to the packaging of a semiconductor module with signals on both sides (front and back) of a chip, the electrical leading-out of the front of the chip is realized by leading out a corresponding conductive column to a rewiring structure, and the electrical leading-out of the back of the chip is realized by directly electrically connecting the rewiring structure. Meanwhile, the back surface of the chip is much smaller than the number of I/O (Input/Output, full name) on the front surface (active surface), specifically, the front surface of the chip is generally provided with a plurality of I/O (such as a plurality of sources and a plurality of gates), while the back surface is generally provided with only one I/O (such as a drain), and different I/O require different lines to be led out, so that the wiring patterns on the front surface of the chip are more dispersed, and the wiring patterns on the back surface of the chip are not very dispersed, so that a larger-area heat dissipation area can be formed on the back surface of the chip, and a better heat dissipation effect is achieved.
Drawings
Fig. 1 is a cross-sectional view of an IPM module in the prior art.
Fig. 2 is a flowchart of a semiconductor module packaging method proposed according to embodiment 1 of the present application.
Fig. 3(a) -3 (t) are process flow diagrams of a middle semiconductor module packaging method proposed according to embodiment 1 of the present application.
Fig. 4 is a schematic structural diagram of a semiconductor module obtained by the semiconductor module packaging method according to embodiment 1 of the present application.
Fig. 5(a) -5 (j) are process flow diagrams of a semiconductor module packaging method according to embodiment 2 of the present application.
Fig. 6 is a schematic structural diagram of a semiconductor module obtained by the semiconductor module packaging method according to embodiment 2 of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. The use of the terms "a" or "an" and the like in the description and in the claims of this application do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" means two or more. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper" and/or "lower," and the like, are used for convenience of description and are not limited to a single position or orientation in space. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
As shown in fig. 2, 3(a) -3 (t) and 4, the present application provides a semiconductor module packaging method and a semiconductor module 1.
Fig. 2 is a flowchart of a semiconductor module packaging method according to an exemplary embodiment of the present application. As shown in fig. 2, the semiconductor module packaging method includes the steps of:
step 100: attaching a chip, a passive component and a plurality of conductive columns to a first conductive metal layer of a DBC board, wherein the plurality of conductive columns are respectively arranged corresponding to the chip and the passive component, the front surface of the chip faces the first conductive metal layer of the DBC board, the front surface of the chip is electrically connected with the corresponding conductive columns through the first conductive metal layer of the DBC board, and the passive component is electrically connected with the corresponding conductive columns through the first conductive metal layer of the DBC board;
step 200: attaching the DBC board to a carrier board, wherein a second conductive metal layer arranged opposite to the first conductive metal layer in the DBC board faces the carrier board;
step 300: covering the whole carrier plate by an encapsulating layer, and plastically packaging the chip, the driven piece, the conductive column and the DBC plate to form an encapsulating structural member;
step 400: forming a rewiring structure on the first surface of the encapsulation structure, wherein the back surface of the chip is directly and electrically connected with the rewiring structure, and the driven piece and the front surface of the chip are respectively and electrically connected with the rewiring structure through different conductive columns;
step 500: and forming a metal connecting layer on one side of the rewiring structure far away from the encapsulation structure, wherein the metal connecting layer is directly connected with the rewiring structure.
Compared with the prior art, the semiconductor module packaging method of the embodiment greatly reduces the whole volume and the product cost of the semiconductor module 1 because a lead frame is not needed in the semiconductor module 1, so that the semiconductor module 1 has the advantages of small volume and compact structure and is suitable for small-sized light-weight electronic equipment; double-sided heat dissipation is realized through the DBC board and the rewiring structure; moreover, due to the leadless interconnection, the impedance can be reduced, the current capacity can be increased, and the layout is more free and flexible; meanwhile, the thickness of the product is freely controllable, an independent plastic package mold is not needed, and the size of the product is freely switched.
The present embodiment is applied to the packaging of the semiconductor module 1 in which signals are present on both sides (front and back sides) of the chip, the electrical lead-out of the front side of the chip is realized by leading out the corresponding conductive column to the rewiring structure, and the electrical lead-out of the back side of the chip is realized by directly electrically connecting the rewiring structure. Meanwhile, the back surface of the chip is much smaller than the number of I/O (Input/Output, full name) on the front surface (active surface), specifically, the front surface of the chip is generally provided with a plurality of I/O (such as a plurality of sources and a plurality of gates), while the back surface is generally provided with only one I/O (such as a drain), and different I/O require different lines to be led out, so that the wiring patterns on the front surface of the chip are more dispersed, and the wiring patterns on the back surface of the chip are not very dispersed, so that a larger-area heat dissipation area can be formed on the back surface of the chip, and a better heat dissipation effect is achieved.
In step 100, as shown in fig. 3(a) to 3(c), the chip 11, the passive component 12, and the conductive pillar 13 are mounted on the first conductive metal layer 141 of the DBC board 14. The chip 11, the passive component 12, and the conductive pillar 13 are all electronic components, that is, a plurality of electronic components are mounted on the first conductive metal layer 141 of the DBC board 14. The DBC plate 14 includes a first conductive metal layer 141, an insulating layer 143, and a second conductive metal layer 142 stacked in sequence, where the first conductive metal layer 141 and the second conductive metal layer 142 are disposed opposite to each other. The first conductive metal layer 141 is a patterned metal layer, and the first conductive metal layer 141 is composed of a plurality of conductive bumps 1411 isolated from each other. The specific pattern of the first conductive metal layer 141 corresponds to the design of the electrical leads of the electronic component mounted thereon. The first conductive metal layer 141 and the second conductive metal layer 142 may be made of the same material, such as a metal material like copper; the material of the insulating layer 143 may be a ceramic material.
The chip 11 includes a front surface 11a (active surface) provided with the bonding pads 111, and a back surface disposed opposite to the front surface 11a, and the back surface 11b is provided with a metal layer (not shown), so that the front surface 11a and the back surface 11b of the chip 11 are electrically led out.
In step 100, the method specifically includes:
as shown in fig. 3(a), the pads 111 of the front surface 11a of the chip 11 are fixed on the conductive blocks 1411 of the first conductive metal layer 141 of the DBC plate 14 corresponding to the pads 111 of the chip 11 by a spot welding process, and as can be seen from fig. 3(a), the pads 111 of the chip 11 are fixed on the conductive blocks 1411 corresponding thereto according to the requirement of electrical lead-out of the front surface 11a of the chip 11; in this way, while the chip 11 is fixed, the pads 111 on the front surface 11a of the chip 11 are electrically connected to the DBC board 14, in this embodiment, the back surface 11b of the chip 11 faces upward, and the front surface 11a of the chip 11 faces the first conductive metal layer 141 of the DBC board 14; it should be noted that, if the front surface 11a of the chip 11 needs to have different electrical leading requirements, different pads 111 and the corresponding conductive blocks 1141 may be electrically connected according to design requirements;
as shown in fig. 3(b), the solder tails 121 of the driven member 12 are fixed on the conductive blocks 1141 of the first conductive metal layer 141 of the DBC board 14 corresponding to the solder tails 121 of the driven member 12 by a reflow soldering process, or the solder tails 121 of the driven member 12 are fixed on the conductive blocks 1141 of the first conductive metal layer 141 of the DBC board 14 corresponding to the solder tails 121 of the driven member 12 by attaching a conductive adhesive, so as to achieve electrical connection with the DBC board 14 while fixing the driven member 12, specifically, the solder tails 121 on both sides of the main body 120 of the driven member 12 are respectively attached on different conductive blocks 1411 of the first conductive metal layer 141 on the DBC board 14 corresponding to two solder tails 121;
as shown in fig. 3(c), a plurality of conductive pillars 13 (only 1 conductive pillar 13 is labeled in the figure) are fixed on the first conductive metal layer 141 of the DBC board 14 by a reflow process, and the plurality of conductive pillars 13 are respectively disposed corresponding to the chip 11 and the passive component 12; specifically, the conductive pillars 13 corresponding to the chip 11 are fixed on the conductive blocks 1411a of the first conductive metal layer 141 of the DBC plate 14 corresponding to the pads 111 of the chip 11, so that the front surface 11a of the chip 11 is electrically connected to the conductive pillars 13 corresponding thereto through the first conductive metal layer 141 (conductive blocks 1411a) of the DBC plate 14; conductive pillars (not labeled) corresponding to the passive component 12 are fixed on the conductive blocks of the first conductive metal layer 141 of the DBC board 14 corresponding to the passive component 12, so that the passive component 12 is electrically connected to the conductive pillars corresponding thereto through the first conductive metal layer 141 of the DBC board 14.
In other embodiments, the conductive pillars 13 corresponding to the chip 11 may also be fixed on the conductive blocks of the first conductive metal layer 141 corresponding to the conductive pillars 13, and the conductive blocks corresponding to the conductive pillars 13 are electrically connected with the conductive blocks corresponding to the chip 11, so as to electrically lead out the front surface of the chip 11; similarly, the conductive pillar 13 corresponding to the passive component 12 may be fixed to the conductive block of the first conductive metal layer 141 corresponding to the conductive pillar 13, and the conductive block corresponding to the conductive pillar 13 and the conductive block corresponding to the passive component 12 may be electrically connected to each other, thereby electrically leading out the passive component 12.
The driven member 12 includes one or more of a capacitor, a resistor, and an inductor. The number of the chips 11 may be one or more; the number of the driven members 12 may be one or more; the number of chips 11 and the number of passive components 12 can be adjusted according to design requirements. Similarly, the number of the conductive posts 13 is determined according to the design requirement of the connection between the chip 11, the passive component 12 and the redistribution structure, and is not limited herein. The number of chips 11, the number of passive components 12, and the number of conductive pillars 13 may be adjusted according to design requirements. As shown in fig. 3(a), the number of chips 11 is 2, and they are placed on the DBC plate 14 at predetermined arrangement positions.
In step 200, as shown in fig. 3(d), the DBC board 14 is attached to the carrier board 2 through an adhesive layer (not shown), and the second conductive metal layer 142 of the DBC board 14 faces the carrier board 2.
The adhesive layer is used to bond the DBC board 14 and the carrier board 2, and the adhesive layer may be made of a material that is easily peeled off so that the carrier board 2 and the DBC board 14 are peeled off in a subsequent process, for example, a thermal release material that can be made to lose its adhesiveness by heating may be used.
In other embodiments, the adhesive layer may have a two-layer structure, i.e., a thermal release material layer and an adhesive layer, the thermal release material layer is adhered to the carrier plate 2 and loses its adhesiveness when heated, so that the thermal release material layer can be peeled off from the carrier plate 2, and the adhesive layer has an adhesive material layer and can be used for adhering the DBC board 14. After the DBC board 14 is peeled off from the carrier board 2, the adhesion layer thereon can be removed by chemical cleaning. In one embodiment, the adhesive layer may be formed on the carrier plate 2 by lamination, printing, or the like.
In step 300, as shown in fig. 3(e), the entire carrier board 2 is covered by the encapsulating layer 16, and the chip 11, the passive component 12, the conductive pillars 13, and the DBC board 14 are plastically molded to form the encapsulating structure 10. The encapsulated structure 10 is a flat plate structure on which the rewiring and encapsulation are performed.
In the present embodiment, the encapsulating layer 16 may be formed by laminating an epoxy resin film or a Molding film, or may be formed by Injection Molding (Injection Molding), Compression Molding (Compression Molding) or Transfer Molding (Transfer Molding) of an epoxy resin compound.
The encapsulation structure 10 comprises a first surface 10a and a second surface 10b, which are oppositely disposed, wherein the first surface 10a of the encapsulation structure 10 corresponds to the back surface 11b of the chip 11, and the second surface 10b faces the carrier plate 2.
As shown in fig. 3(f), in this step, the first surface 10a of the encapsulation structure 10 is further ground to reduce the thickness of the encapsulation structure 10, so that one end of the conductive pillar 13 away from the DBC board 14 is exposed at the first surface 10a of the encapsulation structure 10. Thus, on the one hand, it is convenient to electrically connect the conductive post 13 with the re-wiring structure 20 formed later; on the other hand, the overall volume of the final semiconductor module 1 can be further reduced by thinning the encapsulating structure 10.
It should be noted that, since the thickness of the conductive pillar 13 is not less than the thickness of the chip 11 and not less than the thickness of the driven component 12 along the thickness direction T of the semiconductor module 1, when the thickness of the encapsulation structure 10 is reduced to expose one end of the conductive pillar 13 away from the DBC plate 14 to the first surface 10a of the encapsulation structure 10, both the chip 11 and the driven component 12 are still in the encapsulation layer 16 and are not exposed to the first surface 10a of the encapsulation structure 10.
In step 400, a redistribution structure 20 is formed on the first surface 10a of the encapsulation structure 10, the back surface 11b of the chip 11 is electrically connected to the redistribution structure 20, and the passive component 12 and the front surface 11a of the chip 11 are electrically connected to the redistribution structure 20 through different conductive pillars 13. The electrical lead-out of the back surface 11b of the chip 11 is realized by the direct electrical connection of the metal layer of the back surface 11b of the chip 11 and the rewiring structure 20; the electrical lead-out of the front surface 11a of the chip 11 is implemented by electrically connecting the pads 111 of the front surface 11a, the conductive blocks 1411 of the first conductive metal layer 141 of the DBC plate 14 corresponding to the pads 111 of the chip 11, and the conductive pillars 13 corresponding to the chip 11 to the rewiring structure 20 in sequence. The electrical leading-out of the driven element 12 is realized by electrically connecting the solder leg 121 of the driven element 12, the conductive block corresponding to the driven element 12 and the first conductive metal layer 141 of the DBC board 14, and the conductive pillar (not shown) corresponding to the driven element 12 with the rewiring structure 20 in sequence.
In step 400, in particular, it comprises:
step 410: sequentially forming a first redistribution layer 21 and conductive pillars 22 on the first surface 10a of the encapsulation structure 10, wherein the back surface 11b of the chip 11 and one end of the plurality of conductive pillars 13 away from the DBC board 14 are electrically connected to the first redistribution layer 21;
step 420: a first dielectric layer 23 is formed on the first redistribution layer 21 and the exposed first surface 10a of the encapsulation structure 10, and an end of the conductive pillar 22 away from the first redistribution layer 21 is exposed on a surface of the first dielectric layer 23 away from the encapsulation structure 10.
The first redistribution layer 21 includes a first metal layer 211 and a second metal layer 212, and includes:
step 411: as shown in fig. 3(g), a plurality of openings 17 are formed on the first surface 10a of the encapsulation structure 10, and the openings 17 are located right above the chip 11 to expose the metal layer on the back surface 11b of the chip 11;
step 412: as shown in fig. 3(h), a first metal layer 211 is sputtered on the first surface 10a of the encapsulation structure 10 and inside the opening 17, and the first metal layer 211 is electrically connected to the conductive pillars 13 exposed on the first surface 10a of the encapsulation structure 10 and the metal layer of the back surface 11b of the chip 11 in the opening 17;
step 413: as shown in fig. 3(i) and 3(j), a first photosensitive film 41 is formed on the first metal layer 211, and a plurality of first photosensitive film openings 411 are formed on the first photosensitive film 41;
step 414: as shown in fig. 3(k), a second metal layer 212 is formed by filling a conductive medium in the first photosensitive film opening 411;
step 415: as shown in fig. 3(l) and 3(m), a second photosensitive film 42 is formed on the first photosensitive film 41 and the second metal layer 212, and a plurality of second photosensitive film openings 421 are formed on the second photosensitive film 42;
step 416: as shown in fig. 3(n), the conductive pillar 22 is formed by filling a conductive medium in the second photosensitive film opening 421;
step 417: as shown in fig. 3(o), the second photosensitive film 42 and the first photosensitive film 41 on both sides of the conductive pillar 22 are removed; and the first metal layers 211 located under the first photosensitive films 41 are all removed as shown in fig. 3 (p).
Step 420 includes:
step 421: as shown in fig. 3(q), a first dielectric layer 23 is formed on the first redistribution layer 21, the conductive stud 22, and the exposed first surface 10a of the encapsulation structure 10;
step 422: as shown in fig. 3(r), a surface of the first dielectric layer 23 away from the encapsulation structure 10 is polished, such that an end of the conductive pillar 22 away from the first redistribution layer 21 is exposed at a surface of the first dielectric layer 23 away from the encapsulation structure 10.
After the above-described step of forming the re-wiring structure 20 is completed, the package has been completed, and the semiconductor module 1 that can be used is manufactured.
In the above step, the first dielectric layer 23 may be formed by Molding film. The first metal layer 211 is made of titanium, and the second metal layer 212 and the conductive stud 22 are made of copper.
As is clear from the above, the rewiring structure 20 realizes the electrical lead-out of the front surface 11a and the back surface 11b of the chip 11, the electrical lead-out of the passive component 12, and the electrical connection of the electronic components (the chip 11 and the passive component 12) inside the package of the semiconductor module 1, and the rewiring structure 20 requires a smaller space, particularly a space in the thickness direction, than the electrical connection by the lead wire in the related art; furthermore, since the electrical connections are no longer concentrated on the lead frame pins, the rewiring structure 20 is more flexible and free to layout.
Specifically, the electrical lead-out of the front surface 11a of the chip 11 is implemented by electrically connecting the pad 111 of the front surface 11a of the chip 11, the conductive block 1141 of the first conductive metal layer 141 of the DBC board 14 corresponding to the pad 111 of the chip 11, the conductive pillar 13 corresponding to the chip 11, and the rewiring structure 20 in sequence; the electrical extraction of the back 11b of the chip 11 is achieved by direct electrical connection with the rewiring structure 20; the electrical leading-out of the driven element 12 is realized by electrically connecting the solder leg 121 of the driven element 12, the conductive block 1141 of the first conductive metal layer 141 of the DBC board 14 and the driven element 12, and the conductive pillar (not shown) corresponding to the driven element 12 and the rewiring structure 20 in sequence.
Before entering step 500, as shown in fig. 3(s), peeling off the carrier plate 2 is further included to expose the second surface 10b of the encapsulated structure 10.
Because the adhesive layer between the carrier plate 2 and the DBC plate 14 is a thermal separation film, the adhesive layer can be reduced in viscosity after being heated by a heating method, and the carrier plate 2 is peeled. By peeling the carrier sheet 2 by heating the adhesive layer, damage to the DBC sheet 14 during peeling can be minimized. In other embodiments, the carrier plate 2 can also be peeled off directly mechanically.
The step of peeling the carrier 2 may be performed after the step 500, and particularly in the case of packaging a plurality of semiconductor modules 1 together, the process can be simplified by forming the metal connection layers in a batch. In the case where a plurality of semiconductor modules 1 are packaged together, after the formation of the metal connection layer is completed, the entire package structure is cut into a plurality of semiconductor modules 1 by laser or mechanical cutting.
After the carrier plate 2 is peeled off, the DBC plate 14 is exposed on the second surface 10b of the encapsulation structure 10, that is, the DBC plate 14 is exposed on one surface of the semiconductor module 1, and the DBC plate 14 has high thermal conductivity, so that the semiconductor module 1 can dissipate heat at the surface through the DBC plate 14; on the other side of the semiconductor module 1 opposite to the first dielectric layer 23, the conductive pillar 22 of the redistribution structure 20 is exposed to dissipate heat, so that a double-sided heat dissipation effect is achieved. That is, the semiconductor module 1 is heat-dissipated on both sides by the double-sided copper-clad board, which is the DBC board 14 on one side to help dissipate heat from the front surface 11a of the chip 11 and the rewiring structure 20 (copper wiring) on one side to help dissipate heat from the back surface 11b of the chip 11.
In step 500, as shown in fig. 3(t), the metal connection layer 60 is brushed on a predetermined position of the rewiring structure 20 to form the final semiconductor module 1. The metal connection layer 60 functions similarly to the lead of the lead frame in the related art, and the semiconductor module 1 is electrically connected to the outside through the metal connection layer 60 and is mounted in the next step through the metal connection layer 60.
Specifically, the metal connection layer 60 is located on a side of the conductive pillar 22 away from the first redistribution layer 21, and is directly connected to the conductive pillar 22. The material of the metal connection layer 60 is tin, but is not limited to tin, and may also be nickel-gold alloy or other metals.
In other embodiments, step 500 may not be included, and the semiconductor module 1 is mounted by forming the metal connection layer 60 on the surface of another module (such as a PCB) to which the semiconductor module 1 is to be mounted and by aligning. In this case, if a plurality of semiconductor modules 1 are packaged together, after the packaging of the rewiring structure 20 is completed, the entire package structure is cut into a plurality of semiconductor modules 1 by laser or mechanical cutting.
Fig. 4 is a schematic structural diagram of a semiconductor module 1 obtained by the semiconductor module packaging method according to an embodiment of the present application. The semiconductor module 1 includes: encapsulating the structural member 10, the rewiring structure 20 and the metal connection layer 60.
The encapsulation structure 10 includes a first surface 10a and a second surface 10b opposite to each other, and is provided with a recessed cavity, the DBC board, the chip 11, the passive component 12, and a plurality of conductive pillars 13 (only 1 conductive pillar 13 is shown in the figure) are all located in the cavity, and the plurality of conductive pillars 13 are respectively disposed corresponding to the chip 11 and the passive component 12.
The DBC plate includes a first conductive metal layer 141 and a second conductive metal layer 142 that are oppositely disposed, and particularly, the DBC plate includes the first conductive metal layer 141, an insulating layer 143, and the second conductive metal layer 142 that are sequentially stacked. The first conductive metal layer 141 is a patterned metal layer, and the first conductive metal layer 141 is composed of a plurality of conductive blocks isolated from each other. The specific pattern of the first conductive metal layer 141 corresponds to the design of the electrical leads of the electronic component mounted thereon. The first conductive metal layer 141 and the second conductive metal layer 142 may be made of the same material, such as a metal material like copper; the material of the insulating layer 143 may be a ceramic material.
The chip 11, the passive component 12, and the conductive pillars 13 are fixed to the first conductive metal layer 141 of the DBC board 14, specifically, the passive component 12 and the chip 11 are respectively located on different and isolated conductive blocks, the conductive pillars 13 corresponding to the chip 11 are fixed to the conductive blocks corresponding to the chip 11, and the conductive pillars 13 corresponding to the passive component 12 are fixed to the conductive blocks corresponding to the passive component 12.
The second conductive metal layer 142 of the DBC board 14 is exposed on the second surface 10b of the encapsulation structure 10, the chip 11 includes a front surface 11a and a back surface 11b that are opposite to each other, the back surface 11b of the chip 11 faces the bottom of the cavity, and the front surface 11a of the chip 11 is electrically connected to the passive component 12 through the first conductive metal layer 141 of the DBC board and the corresponding conductive pillar 13, and is electrically connected to the corresponding conductive pillar (not shown in the figure) through the first conductive metal layer 141 of the DBC board.
The thickness of the conductive column 13 is not less than the thickness of the chip 11 and not less than the thickness of the driven member 12 along the thickness direction T of the semiconductor module 1; an end of the conductive pillar 13 away from the DBC board 14 is exposed at the first surface 10a of the encapsulation structure 10. To the effect of minimizing the thickness of the encapsulating structure 10 and thus reducing the overall thickness of the semiconductor module 1.
The redistribution structure 20 is formed on the first surface 10a of the encapsulation structure 10 corresponding to the back surface 11b of the chip 11, the back surface 11b of the chip 11 is directly electrically connected to the redistribution structure 20, and the passive component 12 and the front surface 11a of the chip 11 are electrically connected to the redistribution structure 20 through different conductive pillars 13. One end of each conductive column 13 is electrically connected to the DBC board 14, and the other end of each conductive column is electrically connected to the redistribution structure 20, and the passive component 12 and the front surface 11a of the chip 11 are both electrically connected to the redistribution structure 20 through the DBC board 14 and the corresponding conductive column 13 in sequence.
The electrical lead-out of the front surface 11a of the chip 11 is realized by electrically connecting the pads 111 of the front surface 11a, the conductive blocks of the first conductive metal layer 141 of the DBC board 14 corresponding to the pads 111 of the chip 11, the conductive columns 13 corresponding to the chip 11, and the re-wiring structure 20 in sequence; the electrical lead-out of the back surface 11b of the chip 11 is realized by a direct electrical connection of the metal layer of the back surface 11b of the chip 11 with the re-wiring structure 20. The electrical leading-out of the driven part 12 is realized by electrically connecting the first conductive metal layer 141 of the DBC board 14 with the conductive block corresponding to the driven part 12, the conductive pillar (not labeled in the figure) corresponding to the driven part 12 and the rewiring structure 20 in sequence.
The rewiring structure 20 includes: a first redistribution layer 21 formed on the first surface 10a of the encapsulation structure 10, wherein the back surface 11b of the chip 11 and one end of the conductive pillar 13 far away from the DBC board 14 are electrically connected to the first redistribution layer 21; a conductive pillar 22 formed on a side of the first redistribution layer 21 away from the encapsulation structure 10; the first dielectric layer 23 is formed on the first redistribution layer 21, the conductive pillar 22 and the exposed first surface 10a of the encapsulation structure 10, and one end of the conductive pillar 22 away from the encapsulation structure 10 is exposed on a surface of the first dielectric layer 23 away from the encapsulation structure 10.
In this way, the rewiring structure 20 is used to electrically lead out the front surface 11a and the back surface 11b of the chip 11, the passive component 12, and the electronic components (the chip 11 and the passive component 12) inside the package of the semiconductor module 1, and thus, compared with the case where the electrical connection is performed by a lead wire in the prior art, the rewiring structure 20 requires a smaller space, particularly a space in the thickness direction; furthermore, since the electrical connections are no longer concentrated on the lead frame pins, the rewiring structure 20 is more flexible and free to layout.
Specifically, the electrical lead-out of the front surface 11a of the chip 11 is realized by electrically connecting the pad 111, the DBC board 14, and the conductive pillar 13 of the front surface 11a of the chip 11 with the redistribution structure 20 in sequence; the electrical extraction of the rear face 11b of the chip 11 is achieved by direct electrical connection to the rewiring structure 20; the passive element 12 is electrically led out by electrically connecting the solder leg 121 of the passive element 12, the DBC board 14, and the conductive pillar 13 to the rewiring structure 20 in this order.
The first redistribution layer 21 includes a first metal layer and a second metal layer stacked in sequence from near to the encapsulation structure 10 to far from the encapsulation structure 10.
The first metal layer is made of titanium, and the second metal layer and the conductive convex column 22 are made of copper.
The metal connection layer 60 is located on a surface of the redistribution structure 20 away from the encapsulation structure 10, and is directly connected to the redistribution structure 20. Specifically, the metal connection layer 60 is located on a side of the conductive pillar 22 away from the first redistribution layer 21, and the metal connection layer 60 is directly connected to the conductive pillar 22.
Along the thickness direction T of the semiconductor module 1, the orthographic projection of the rewiring structure 20 coincides with the orthographic projection of the encapsulation structure 10, and the orthographic projection of the metal connection layer 60 is located within the orthographic projection of the rewiring structure 20, so that compared with the IPM module in the prior art, the semiconductor module of the present embodiment has a more compact structure in the horizontal direction, and there are no leads of the lead frame arranged in the horizontal direction.
Compared with the prior art, the semiconductor module of the embodiment does not need a lead frame in the semiconductor module 1, so that the overall volume and the product cost of the semiconductor module 1 are greatly reduced, and the semiconductor module 1 has the advantages of small volume and compact structure and is suitable for small-sized light-weight electronic equipment; double-sided heat dissipation is realized through the DBC board and the rewiring structure; moreover, due to the leadless interconnection, the impedance can be reduced, the current capacity can be increased, and the layout is more free and flexible; meanwhile, the thickness of the product is freely controllable, an independent plastic package mold is not needed, and the size of the product is freely switched.
The present embodiment is applied to the semiconductor module 1 in which signals are present on both sides (front and back sides) of the chip, and the electrical lead-out on the front side of the chip is realized by leading out the corresponding conductive column to the rewiring structure, and the electrical lead-out on the back side of the chip is realized by directly electrically connecting the rewiring structure. Meanwhile, the back surface of the chip is much smaller than the number of I/O (Input/Output, full name) on the front surface (active surface), specifically, the front surface of the chip is generally provided with a plurality of I/O (such as a plurality of sources and a plurality of gates), while the back surface is generally provided with only one I/O (such as a drain), and different I/O require different lines to be led out, so that the wiring patterns on the front surface of the chip are more dispersed, and the wiring patterns on the back surface of the chip are not very dispersed, so that a larger-area heat dissipation area can be formed on the back surface of the chip, and a better heat dissipation effect is achieved.
Example 2
The contents of the semiconductor module packaging method of this embodiment are basically the same as the semiconductor module packaging method of embodiment 1, except that the step of forming the rewiring structure in the semiconductor module packaging method of this embodiment further includes forming a second rewiring layer and a second dielectric layer.
Specifically, as shown in fig. 5(a) -5 (j), the method for packaging a semiconductor module of the present embodiment further includes, after step 420:
step 430: forming a second rewiring layer on the first dielectric layer and the conductive posts;
step 440: and forming a second dielectric layer on the first dielectric layer, and exposing one end of the second rewiring layer, which is far away from the conductive convex column, on one surface of the second dielectric layer, which is far away from the first dielectric layer.
The second re-routing layer 24 includes a third metal layer 241 and a fourth metal layer 242, and includes in step 430:
step 431: as shown in fig. 5(a), a third metal layer 241 is sputtered on the first dielectric layer 23 and the conductive posts 22;
step 432: as shown in fig. 5(b) and 5(c), a third photosensitive film 43 is formed on the third metal layer 241, and a plurality of third photosensitive film openings 431 are formed on the third photosensitive film 43;
step 433: as shown in fig. 5(d), a fourth metal layer 242 is formed by filling a conductive medium in the third photosensitive film opening 431;
step 434: as shown in fig. 5(e), the third photosensitive films 43 on both sides of the fourth metal layer 242 are removed; and the third metal layers 241 all located under the third photosensitive film 43 are removed as shown in fig. 5 (f).
Step 440 includes:
step 441: as shown in fig. 5(g), a second dielectric layer 25 is formed on the second re-wiring layer 24 and the exposed first dielectric layer 23;
step 442: as shown in fig. 5(h), a surface of the second dielectric layer 25 away from the encapsulation structure 10 is polished, such that an end of the second redistribution layer 24 away from the first redistribution layer 21 is exposed at a surface of the second dielectric layer 25 away from the encapsulation structure 10.
In the above step, the second dielectric layer 25 may be formed by Molding film. The third metal layer 241 is made of titanium, and the fourth metal layer 242 is made of copper.
In other embodiments, the step of forming the re-wiring structure 20 may further include forming a third re-wiring layer or more layers in the wiring structure layer, and more dielectric layers, which may be adjusted according to design requirements.
As in the step of peeling the carrier plate 2 in embodiment 1, before entering step 500, as shown in fig. 5(i), peeling the carrier plate 2 is further included, and the second surface 10b of the encapsulated structure 10 is exposed.
After the carrier plate 2 is peeled off, the second conductive metal layer 142 of the DBC plate is exposed on the second surface 10b of the encapsulation structure 10, that is, the DBC plate is exposed on one surface of the semiconductor module 1, and the DBC plate has a high thermal conductivity property, so that the semiconductor module 1 can dissipate heat on the surface through the DBC plate; on the other side of the semiconductor module 1 opposite to the other side, heat can be dissipated through the second redistribution layer 24 in the formed redistribution structure 20, exposing the second dielectric layer 25, thereby achieving a double-sided heat dissipation effect. It should be noted that, since the second redistribution layer 24 includes not only the first portion 243 located above the conductive stud 22, but also the second portion 244 located above the first dielectric layer 23, heat can be simultaneously dissipated through the first portion 243 and the second portion 244, so that the heat dissipation area is larger, and the heat dissipation effect is better.
Likewise, the step of peeling off the carrier plate 2 can also be placed after step 500.
In the present embodiment, in step 500, as shown in fig. 5(j), the metal connection layer 60 is brushed on a predetermined position of the rewiring structure 20 to form the final semiconductor module 1. The metal connection layer 60 functions similarly to the lead of the lead frame in the related art, and the semiconductor module 1 is electrically connected to the outside through the metal connection layer 60 and is mounted in the next step through the metal connection layer 60.
Specifically, the metal connection layer 60 is located on a side of the second redistribution layer 24 away from the conductive stud 22, and is directly connected to the second redistribution layer 24. The material of the metal connection layer 60 is tin, but is not limited to tin, and may also be nickel-gold alloy or other metals.
In other embodiments, step 500 may not be included, and the semiconductor module 1 is mounted by forming the metal connection layer 60 on the surface of another module (such as a PCB) to which the semiconductor module 1 is to be mounted and by aligning.
Fig. 6 is a schematic structural diagram of a semiconductor module 1 obtained by the semiconductor module packaging method according to an embodiment of the present application. The semiconductor module 1 includes: encapsulating the structural member 10, the rewiring structure 20 and the metal connection layer 60. The structure of the semiconductor module 1 in this embodiment is basically the same as that in embodiment 1, except that the rewiring structure 20 of the semiconductor module 1 in this embodiment further includes a second rewiring layer 24 and a second dielectric layer 25.
A second redistribution layer 24 is formed on the first dielectric layer 23, and the second redistribution layer 24 is electrically connected to the conductive stud 22.
The second dielectric layer 25 is formed on the first dielectric layer 23, and one end of the second rewiring layer 24 away from the conductive post 22 is exposed out of one surface of the second dielectric layer 25 away from the first dielectric layer 23.
The second redistribution layer 24 includes a third metal layer and a fourth metal layer stacked in sequence from near the encapsulation structure 10 to far from the encapsulation structure 10.
The third metal layer is made of titanium, and the fourth metal layer is made of copper.
The metal connection layer 60 is located on a surface of the redistribution structure 20 away from the encapsulation structure 10, and is directly connected to the redistribution structure 20. Specifically, the metal connection layer 60 is located on a side of the second redistribution layer 24 away from the conductive stud 22, and the metal connection layer 60 is directly connected to the second redistribution layer 24.
In other embodiments, the redistribution structure 20 may further include a third redistribution layer or more in-line structure layers, and more dielectric layers, which may be adjusted according to design requirements.
In the present application, the structural embodiments and the method embodiments may be complementary to each other without conflict.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Claims (13)
1. A semiconductor module packaging method, comprising:
s1: attaching a chip, a passive component and a plurality of conductive columns to a first conductive metal layer of a DBC board, wherein the plurality of conductive columns are respectively arranged corresponding to the chip and the passive component, the front surface of the chip faces the first conductive metal layer of the DBC board, the front surface of the chip is electrically connected with the corresponding conductive columns through the first conductive metal layer of the DBC board, and the passive component is electrically connected with the corresponding conductive columns through the first conductive metal layer of the DBC board;
s2: attaching the DBC board to a carrier board, wherein a second conductive metal layer arranged opposite to the first conductive metal layer in the DBC board faces the carrier board;
s3: covering the whole carrier plate by an encapsulating layer, and plastically packaging the chip, the driven piece, the conductive column and the DBC plate to form an encapsulating structural member;
s4: and forming a rewiring structure on the first surface of the encapsulation structure, wherein the back surface of the chip is directly and electrically connected with the rewiring structure, and the driven piece and the front surface of the chip are respectively and electrically connected with the rewiring structure through different conductive columns.
2. The method for packaging a semiconductor module according to claim 1, wherein the encapsulating structure comprises the first surface and a second surface oppositely disposed, and the second surface faces the carrier plate, in step S3, the method comprises:
and grinding the first surface of the encapsulating structure member to expose one end, far away from the DBC plate, of the conductive column to the first surface of the encapsulating structure member.
3. The semiconductor module packaging method according to claim 1, wherein in step S4, the method includes:
s41: sequentially forming a first redistribution layer and a conductive convex column on the first surface of the encapsulation structure, wherein the back surface of the chip and one end, far away from the DBC plate, of the conductive column are electrically connected with the first redistribution layer;
s42: and forming a first dielectric layer on the first redistribution layer and the exposed first surface of the encapsulation structure, and exposing one end of the conductive pillar, which is far away from the first redistribution layer, on one surface of the first dielectric layer, which is far away from the encapsulation structure.
4. The semiconductor module packaging method according to claim 3, wherein step S42 includes:
forming a first dielectric layer on the first redistribution layer, the conductive posts, and the exposed first surface of the encapsulation structure;
and grinding a surface of the first dielectric layer far away from the encapsulation structure, so that one end of the conductive convex column far away from the first rewiring layer is exposed out of a surface of the first dielectric layer far away from the encapsulation structure.
5. The semiconductor module packaging method according to claim 3, further comprising, after step S42:
s43: forming a second rewiring layer on the first dielectric layer and the conductive posts;
s44: and forming a second dielectric layer on the first dielectric layer, and exposing one end of the second rewiring layer, which is far away from the conductive convex column, on one surface of the second dielectric layer, which is far away from the first dielectric layer.
6. The semiconductor module packaging method according to claim 5, wherein step S44 includes:
forming a second dielectric layer on the second rewiring layer and the exposed first dielectric layer;
and grinding one surface of the second dielectric layer far away from the encapsulation structure, so that one end of the second rewiring layer far away from the first rewiring layer is exposed out of one surface of the second dielectric layer far away from the encapsulation structure.
7. The semiconductor module packaging method according to claim 1, further comprising, after step S4:
s5: and forming a metal connecting layer on one side of the rewiring structure far away from the encapsulation structure, wherein the metal connecting layer is directly connected with the rewiring structure.
8. The semiconductor module packaging method according to claim 7, further comprising, before step S5: stripping the carrier plate; alternatively, the first and second electrodes may be,
after step S5, the method further includes: and stripping the carrier plate.
9. A semiconductor module, comprising:
the encapsulation structure comprises a first surface and a second surface which are opposite, and a concave cavity is arranged, a DBC plate, a chip, a driven piece and a conductive post are all positioned in the cavity, the DBC plate comprises a first conductive metal layer and a second conductive metal layer which are opposite, the chip, the driven piece and the conductive post are fixed on the first conductive metal layer of the DBC plate, the second conductive metal layer of the DBC plate is exposed out of the second surface of the encapsulation structure, the chip comprises a front surface and a back surface which are opposite, the back surface of the chip faces to the bottom of the cavity, the front surface of the chip is electrically connected with the corresponding conductive post through the first conductive metal layer of the DBC plate, and the driven piece is electrically connected with the corresponding conductive post through the first conductive metal layer of the DBC plate;
and the rewiring structure is formed on the first surface of the encapsulation structure part corresponding to the back surface of the chip, the back surface of the chip is directly and electrically connected with the rewiring structure, and the driven part and the front surface of the chip are respectively and electrically connected with the rewiring structure through different conductive columns.
10. The semiconductor module of claim 9, further comprising a metal connection layer on a surface of the rewiring structure remote from the encapsulation structure and directly connected to the rewiring structure.
11. The semiconductor module according to claim 9, wherein in a thickness direction of the semiconductor module, a thickness of the conductive pillar is not less than a thickness of the chip and not less than a thickness of the driven member; one end of the conductive column, which is far away from the DBC plate, is exposed out of the first surface of the encapsulation structure.
12. The semiconductor module according to claim 9, wherein the rewiring structure comprises:
the first redistribution layer is formed on the first surface of the encapsulation structure, and the back surface of the chip and one end, far away from the DBC board, of the conductive column are electrically connected with the first redistribution layer;
the conductive convex column is formed on one side, away from the encapsulation structure, of the first rewiring layer;
the first dielectric layer is formed on the first rewiring layer, the conductive convex column and the exposed first surface of the encapsulation structure, and one end, far away from the encapsulation structure, of the conductive convex column is exposed on one surface, far away from the encapsulation structure, of the first dielectric layer.
13. The semiconductor module of claim 12, wherein the rewiring structure further comprises:
a second rewiring layer formed on the first dielectric layer, the second rewiring layer being electrically connected to the conductive posts;
and the second dielectric layer is formed on the first dielectric layer, and one end of the second rewiring layer, which is far away from the conductive convex column, is exposed out of one surface of the second dielectric layer, which is far away from the first dielectric layer.
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| WO2024022174A1 (en) * | 2022-07-26 | 2024-02-01 | 矽磐微电子(重庆)有限公司 | Chip packaging structure and preparation method therefor |
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Application publication date: 20200828 |