WO2024022174A1 - Chip packaging structure and preparation method therefor - Google Patents

Chip packaging structure and preparation method therefor Download PDF

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Publication number
WO2024022174A1
WO2024022174A1 PCT/CN2023/107955 CN2023107955W WO2024022174A1 WO 2024022174 A1 WO2024022174 A1 WO 2024022174A1 CN 2023107955 W CN2023107955 W CN 2023107955W WO 2024022174 A1 WO2024022174 A1 WO 2024022174A1
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WO
WIPO (PCT)
Prior art keywords
chip
auxiliary
semiconductor chip
conductive
layer
Prior art date
Application number
PCT/CN2023/107955
Other languages
French (fr)
Chinese (zh)
Inventor
杨磊
霍炎
Original Assignee
矽磐微电子(重庆)有限公司
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Publication of WO2024022174A1 publication Critical patent/WO2024022174A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to a chip packaging structure and a preparation method thereof.
  • the rewiring structure of the existing chip packaging structure is directly in contact with the substrate on the back side of the gallium nitride chip, and the existing process generally
  • the substrate is connected to the front source by mounting a low-resistance auxiliary chip, grinding to expose the silicon, and rewiring.
  • the stress during grinding to expose the silicon will cause cracks in the gallium nitride chip and low-resistance auxiliary chip and delamination of the packaging structure, which will lead to the scrapping of a large number of products.
  • This application provides a chip packaging structure, including:
  • a semiconductor chip and an auxiliary chip juxtaposed with the semiconductor chip the front side of the semiconductor chip is provided with a plurality of metal bonding pads, and the front side of the auxiliary chip is flush with the front side of the semiconductor chip;
  • a plastic sealing layer covers the back and side surfaces of the semiconductor chip and extends to cover the back and side surfaces of the auxiliary chip.
  • the plastic sealing layer is provided with a plurality of third holes respectively exposing the back surface of the semiconductor chip and the back surface of the auxiliary chip. an opening;
  • the first rewiring structure covers the metal bonding pad and extends to cover the front surface of the auxiliary chip to achieve electrical connection between the front surface of the auxiliary chip and the metal bonding pad;
  • the second rewiring structure covers part of the surface of the plastic layer away from the front side of the semiconductor chip and fills the first opening to achieve electrical connection between the back side of the auxiliary chip and the back side of the semiconductor chip.
  • the thickness of the plastic sealing layer on the back side of the semiconductor chip is a set value, and the set value ranges from 5 ⁇ m to 50 ⁇ m.
  • the auxiliary chip includes an auxiliary substrate, and the auxiliary substrate is a substrate made of silicon, a substrate made of germanium, a substrate made of germanium silicon and One of the substrates made of silicon carbide;
  • the doping ions in the auxiliary substrate are selected from one of phosphorus, boron and arsenic, and the doping concentration of the auxiliary substrate is 10 16 cm -3 to 10 22 cm -3 .
  • the auxiliary chip is a low-resistance auxiliary chip with a resistance value ⁇ 0.1m ⁇ .
  • the chip packaging structure includes one or more auxiliary chips.
  • a protective layer is further provided on the front side of the semiconductor chip, and a plurality of third openings exposing the metal pads are provided on the protective layer.
  • the chip packaging structure further includes a first dielectric layer, and the first rewiring structure includes a first conductive layer and a second conductive layer, wherein,
  • the first conductive layer includes a plurality of first conductive traces arranged at intervals on the front surface of the semiconductor chip and the front surface of the auxiliary chip and a first conductive plug disposed in the third opening, so The front side of the auxiliary chip is electrically connected to the metal pad through the first conductive trace and the first conductive plug;
  • the first dielectric layer covers the first conductive traces, and the first dielectric layer is provided with a plurality of second openings exposing the first conductive traces;
  • the second conductive layer includes a plurality of conductive bumps arranged at intervals on the first dielectric layer and a second conductive plug disposed in the second opening.
  • the conductive bumps pass through the first dielectric layer.
  • Two conductive plugs are electrically connected to the first conductive trace.
  • the chip packaging structure further includes a metal tin layer covering the sides of the conductive bumps and the surface on the side away from the semiconductor chip.
  • the second rewiring structure includes a third conductive trace located on a side of the plastic encapsulation layer away from the front surface of the semiconductor chip and a third conductive trace disposed in the first opening.
  • the back side of the auxiliary chip is electrically connected to the back side of the semiconductor chip through the third conductive trace and the third conductive plug.
  • the chip packaging structure further includes a second dielectric layer covering the side of the third conductive trace and the surface on the side away from the semiconductor chip.
  • the semiconductor chip is a gallium nitride chip.
  • This application also provides a method for preparing a chip packaging structure, including:
  • a semiconductor chip, an auxiliary chip and a carrier board and mount the semiconductor chip and the auxiliary chip on the carrier board, with the front surface of the semiconductor chip and the front surface of the auxiliary chip facing the carrier board, and the semiconductor chip and the auxiliary chip are mounted on the carrier board.
  • the plastic sealing layer covers the side and back of the semiconductor chip, and extends to cover the side and back of the auxiliary chip;
  • first rewiring structure Forming a first rewiring structure on the front surface of the semiconductor chip and the front surface of the auxiliary chip, and the first rewiring structure is electrically connected to the metal pad;
  • a second rewiring structure is formed on a side of the plastic encapsulation layer away from the front surface of the semiconductor chip, and the second rewiring structure also fills the first opening.
  • Figures 1 to 4 are structural schematic diagrams corresponding to each step in a method for preparing a gallium nitride chip board-level packaging structure
  • Figure 5 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application.
  • 6 to 10 are structural schematic diagrams corresponding to each step in the method for preparing a chip packaging structure according to an embodiment of the present application
  • 01-GaN chip 011-metal pad, 012-protective layer, 02-low resistance auxiliary chip, 03-plastic sealing layer, 04-first rewiring structure, 041-first conductive plug, 042-first Conductive traces, 043-second conductive plug, 044-conductive bump, 05-first dielectric layer, 06-metal tin layer, 07-second rewiring structure, 08-second dielectric layer;
  • 10-semiconductor chip 10a-front side of semiconductor chip, 101-metal pad, 102-protective layer, 20-auxiliary chip, 20a-front side of auxiliary chip, 30-plastic sealing material layer, 301-plastic sealing layer, 3011-first Opening, 40-first redistribution structure, 401-first conductive plug, 402-first conductive trace, 403-second conductive plug, 404-conductive bump, 50-first dielectric layer, 60- Metal tin layer, 70-second rewiring structure, 701-third conductive plug, 702-third conductive trace, 80-second dielectric layer.
  • a method for preparing a gallium nitride chip board-level packaging structure realizes the connection between the substrate and the front source by mounting a low-resistance auxiliary chip, grinding to expose the silicon, and rewiring. Please refer to Figures 1 to 4 for details.
  • the preparation method of the gallium nitride chip board-level packaging structure includes:
  • the gallium nitride chip 01 and the low-resistance auxiliary chip 02 are mounted on a carrier board (not shown in the figure).
  • the front side of the gallium nitride chip 01 is provided with a protective layer 012 and a plurality of metal pads 011.
  • the protective layer 012 is provided with a plurality of first openings that expose portions of the metal pads 011;
  • a first rewiring structure 04, a first dielectric layer 05, and a metal tin layer 06 are formed.
  • the first rewiring structure 04 includes a plurality of first conductive plugs 041, first conductive traces 042, and second conductive plugs.
  • the first conductive plug 041 is located in the first opening;
  • the first conductive trace 042 is located on the front surface of the gallium nitride chip 01 and the front surface of the auxiliary chip 02, so The front side of the auxiliary chip 02 is electrically connected to the metal pad 011 through the first conductive trace 042 and the first conductive plug 041;
  • the first dielectric layer 05 covers the first conductive trace 042,
  • the first dielectric layer 05 is provided with a plurality of second openings exposing portions of the first conductive traces 042;
  • the second conductive plugs 043 are located in the second openings;
  • the conductive bumps 044 is located on the side of the first dielectric layer 05 away from the gallium nitride chip 01 and is electrically connected to the first conductive trace 042 through the second conductive plug 043;
  • the metal tin layer 06 Cover the conductive bumps 044;
  • a second rewiring structure 07 and a second dielectric layer 08 are formed.
  • the second rewiring structure 07 is located on the back side of the gallium nitride chip 01 and the auxiliary chip 02.
  • the second dielectric layer 08 covers the second dielectric layer 08.
  • the stress generated by grinding will directly act on the auxiliary chip 02 and the gallium nitride chip 01, which may easily lead to cracking of the gallium nitride chip 01 and the auxiliary chip 02 and delamination of the chip packaging structure. , which in turn leads to a large number of products being scrapped, and the final product defect rate is approximately 30%.
  • this application provides a new type of chip packaging structure, which is on the back side of the semiconductor chip and auxiliary There is a certain thickness of the plastic sealing layer on the back of the chip, which does not need to be ground to the back of the semiconductor chip and auxiliary chip, and there will be no stress acting directly on the semiconductor chip and auxiliary chip, which can avoid cracking and cracking of the semiconductor chip and auxiliary chip.
  • the delamination problem of the chip packaging structure can avoid a large number of product scraps, thereby improving product yield and productivity.
  • the chip packaging structure includes:
  • the semiconductor chip 10 and the auxiliary chip 20 juxtaposed with the semiconductor chip 10 are provided with a plurality of metal bonding pads 101 on the front side of the semiconductor chip 10, and the front side of the auxiliary chip 20 is flush with the front side of the semiconductor chip 10. flat;
  • the plastic sealing layer 301 covers the back and side surfaces of the semiconductor chip 10 and extends to cover the back and side surfaces of the auxiliary chip 20 .
  • the plastic sealing layer 301 is provided with a plurality of exposed back surfaces and auxiliary chips of the semiconductor chip 10 . the first opening on the back of 20;
  • the first rewiring structure 40 covers the metal bonding pad 101 and extends to cover the front surface of the auxiliary chip 20 to achieve electrical connection between the front surface of the auxiliary chip 20 and the metal bonding pad 101;
  • the second rewiring structure 70 covers part of the surface of the plastic encapsulation layer 301 away from the front side of the semiconductor chip 10 and fills the first opening to realize the connection between the back side of the auxiliary chip 20 and the semiconductor chip 10 electrical connections on the back.
  • the semiconductor chip 10 is preferably a gallium nitride (GaN) chip, but is not limited thereto.
  • the semiconductor chip 10 can be obtained by cutting a wafer.
  • the wafer has an active surface, and the active surface of the wafer is provided with a metal bonding pad 101 .
  • the wafer can be cut by mechanical cutting or laser cutting.
  • the metal pad 101 of the semiconductor chip 10 serves as a source, which is composed of a conductive electrode led from the internal circuit of the chip to the surface of the chip.
  • a plurality of metal bonding pads 101 may be provided on the front surface of the semiconductor chip 10 .
  • the metal pad 101 is used to lead out the conductive electrode of the semiconductor chip 10 .
  • the back side of the semiconductor chip 10 is the substrate of the semiconductor chip 10 , that is, the semiconductor substrate.
  • a protective layer 102 is also provided on the front side of the semiconductor chip 10.
  • the protective layer 102 will cover part of the metal bonding pad 101. That is, a plurality of holes are formed on the protective layer 102 to expose part of the surface of the metal bonding pad. The third opening.
  • the material of the protective layer 102 may be a plastic film, PI (Polyimide, polyimide), PBO (Polybenzoxazole, polybenzoxazole), organic polymer film, organic polymer composite material or other materials with similar characteristics. .
  • organic or inorganic fillers may be added to the protective layer 102 .
  • the chip packaging structure may further include an auxiliary chip 20 juxtaposed with the semiconductor chip 10 .
  • the auxiliary The chip 20 is mainly used for conduction, and can form a loop with the semiconductor chip 10 after forming the first rewiring structure and the second rewiring structure.
  • the semiconductor chip is preferably a Gallium Nitride (GaN) chip
  • the electrons in the GaN chip may fall into the substrate due to the poor insulation effect of the insulating layer above the substrate during operation, thus causing leakage.
  • the additional auxiliary chip 20 can form a loop with the semiconductor chip 10 to allow the electrons of the substrate to return to the source, thereby avoiding leakage.
  • the number of the auxiliary chip 20 is one, thereby forming a current-carrying channel. Alternatively, in other embodiments, the number of the auxiliary chips 20 may also be multiple, thereby forming multiple current-carrying channels.
  • a plurality of the auxiliary chips 20 are laterally spaced apart and are juxtaposed with the semiconductor chip 10 , wherein the gap between the semiconductor chip 10 and the auxiliary chip 20 and the plurality of auxiliary chips 20 are laterally spaced apart. The resulting gap may be filled with non-conductive material.
  • the plurality of auxiliary chips 20 may be located on the same side of the semiconductor chip 10 , or may be located on different sides of the semiconductor chip 10 .
  • the auxiliary chip 20 is preferably a low-resistance auxiliary chip, but is not limited thereto. Further, the resistance value of the low-resistance auxiliary chip is ⁇ 0.1m ⁇ .
  • the auxiliary chip 20 may only include an auxiliary substrate, that is, only include a layer of semiconductor material.
  • the impedance of the auxiliary substrate is smaller than the impedance of the semiconductor substrate.
  • the materials of the auxiliary substrate and the semiconductor substrate can be selected and/or doped so that the impedance of the auxiliary substrate is smaller than the impedance of the semiconductor substrate.
  • the materials of the auxiliary substrate and the semiconductor substrate may be the same or different.
  • the auxiliary substrate and the semiconductor substrate are made of the same material and are both silicon.
  • the auxiliary substrate and the semiconductor substrate may be made of different materials, and the materials of the auxiliary substrate and the semiconductor substrate may be selected from one of silicon, germanium, silicon germanium and silicon carbide.
  • the material of the auxiliary substrate is silicon, and the material of the semiconductor substrate is silicon carbide; or the material of the auxiliary substrate is germanium, and the material of the semiconductor substrate is silicon germanium, etc.
  • both the auxiliary substrate and the semiconductor substrate are doped with ions.
  • the doping ions in the auxiliary substrate and the doping ions in the semiconductor substrate are the same.
  • the doping ions in the auxiliary substrate and the doping ions in the semiconductor substrate are both P-type ions or both are N-type ions.
  • the doping ions in the auxiliary substrate and the doping ions in the semiconductor substrate are selected from one of phosphorus, boron and arsenic.
  • the auxiliary chip 20 is preferably a P-type highly doped chip, that is, the doping ions of the auxiliary substrate are preferably P-type ions.
  • the doping concentration of the auxiliary substrate is higher than the doping concentration of the semiconductor substrate.
  • the doping concentration of the auxiliary substrate is 10 16 cm -3 ⁇ 10 22 cm -3 and the doping concentration of the semiconductor substrate is 10 15 cm -3 ⁇ 10 19 cm -3 .
  • the doping concentration of the auxiliary substrate is 10 21 cm -3 and the doping concentration of the semiconductor substrate is 10 19 cm -3 ;
  • the doping concentration of the auxiliary substrate is 10 19 cm -3 and the doping concentration of the semiconductor substrate is 10 18 cm -3 .
  • the doping ions in the auxiliary substrate and the doping ions in the semiconductor substrate may also be different.
  • the auxiliary substrate can be used as a current-carrying channel for electrons in the semiconductor substrate.
  • the auxiliary chip 20 may include an auxiliary substrate and a semiconductor material layer located on the auxiliary substrate, that is, include multiple semiconductor material layers.
  • the arrangement of the auxiliary chip 20 only needs to satisfy that the impedance of the auxiliary chip 20 is smaller than the impedance of the semiconductor chip 10 , which will not be described in detail here.
  • the front side of the auxiliary chip 20 is preferably flush with the front side of the semiconductor chip 10
  • the back side of the auxiliary chip 20 is preferably flush with the back side of the semiconductor chip 10
  • the front side is opposite to the back side. Since the auxiliary chip 20 is used for electronic conduction, there are no special requirements for the arrangement of the front and back of the auxiliary chip 20 .
  • the back of the auxiliary chip 20 is an auxiliary substrate.
  • the front side of the auxiliary chip 20 is an auxiliary substrate.
  • the plastic encapsulation layer 301 covers the side and back of the semiconductor chip 10 and also covers the back and side of the auxiliary chip 10 .
  • the thickness of the plastic sealing layer 301 on the back surface of the semiconductor chip 10 is a set value, that is, the distance between the surface of the plastic sealing layer 301 away from the front side of the semiconductor chip 10 and the back surface of the semiconductor chip 10 is a set value.
  • the set value can range from 5 ⁇ m to 50 ⁇ m.
  • the thickness of the plastic sealing layer 301 on the back side of the auxiliary chip 20 is also a set value.
  • the plastic sealing layer 301 is provided with a plurality of first openings that expose part of the back surface of the semiconductor chip 10 and the back surface of the auxiliary chip 20 .
  • the first openings are separated from the front surface of the semiconductor chip 10 from the plastic sealing layer 301 .
  • the surface of the side extends to the back side of the semiconductor chip or the back side of the auxiliary chip 20 .
  • the first rewiring structure 40 includes a first conductive layer and a second conductive layer, and the chip packaging structure further includes a first dielectric layer 50 .
  • the first conductive layer includes a plurality of first conductive traces 402 spaced apart on the front surface of the semiconductor chip 10 and the front surface of the auxiliary chip 20 and a first conductive plug 401 disposed in the third opening. , the front side of the auxiliary chip 20 is electrically connected to the metal pad 101 through the first conductive trace 402 and the first conductive plug 401 catch.
  • the first dielectric layer 50 covers the first conductive traces 402 , and the first dielectric layer 50 is provided with a plurality of second openings exposing the first conductive traces 402 .
  • the first dielectric layer 50 may be made of plastic film, PI, PBO, organic polymer film, organic polymer composite material or other materials with similar properties. In some embodiments, organic or inorganic fillers may be added to the first dielectric layer 50 .
  • the second conductive layer includes a plurality of conductive bumps 404 spaced apart on a side of the first dielectric layer 50 away from the semiconductor chip 10 and a second conductive plug 403 disposed in the second opening, Each of the conductive bumps 404 is electrically connected to the first conductive trace 402 through at least one of the second conductive plugs 403 .
  • the chip packaging structure also includes a metal tin layer 60 for external connection to other circuits.
  • the metal tin layer 60 covers the side surface of the conductive bump 404 and the surface away from the semiconductor chip 10 .
  • the material of the metal tin layer is preferably metal tin, but is not limited thereto.
  • the second rewiring structure 70 includes a third conductive trace 702 located on a side of the plastic encapsulation layer 301 away from the front surface of the semiconductor chip 10 and a third conductive plug 701 disposed in the first opening, so The backside of the auxiliary chip 20 is electrically connected to the backside of the semiconductor chip 10 through the third conductive trace 702 and the third conductive plug 701 .
  • the chip packaging structure also includes a second dielectric layer 80 covering the second rewiring structure 70.
  • the material of the second dielectric layer 80 can be plastic film, PI, PBO, organic polymer film, organic polymer composite materials or other materials with similar properties.
  • organic or inorganic fillers may be added to the second dielectric layer 80 .
  • the method for preparing the chip packaging structure includes:
  • Step S1 Provide a semiconductor chip 10, an auxiliary chip 20 and a carrier board (not shown in the figure), and mount the semiconductor chip 10 and the auxiliary chip 20 on the carrier board.
  • the front side 10a of the semiconductor chip And the front surface 20a of the auxiliary chip faces the carrier board, and the front surface 10a of the semiconductor chip 10 is provided with a plurality of metal bonding pads 101;
  • Step S2 Form a plastic sealing layer 301 that covers the side and back of the semiconductor chip 10 and extends to cover the back and side of the auxiliary chip 20;
  • Step S3 Form a first rewiring structure 40 on the front side 10a of the semiconductor chip and the front side 20a of the auxiliary chip, and the first rewiring structure 40 is electrically connected to the metal pad 101;
  • Step S4 Form a plurality of first openings respectively exposing the back surface of the semiconductor chip and the back surface of the auxiliary chip.
  • the opening 3011 is on the plastic sealing layer 301;
  • Step S5 Form a second rewiring structure 70 on the side of the plastic encapsulation layer 301 away from the front surface 10a of the semiconductor chip, and the second rewiring structure 70 also fills the first opening 3011.
  • step S1 is performed to provide a semiconductor chip 10 .
  • a plurality of metal bonding pads 101 are provided on the front surface 10 a of the semiconductor chip 10 .
  • the front surface 10a of the semiconductor chip is also provided with a protective layer 102.
  • the protective layer 102 will cover part of the metal pads 101. That is, the protective layer 102 is formed with a plurality of partial surfaces exposing the metal pads 101.
  • the third opening (not marked in the figure).
  • the formation method of the third opening is preferably a laser method or a development method, but is not limited thereto.
  • the protective layer 102 may be made of a plastic film, PI (polyimide), PBO (polybenzoxazole), organic polymer film, organic polymer composite material, or other materials with similar properties. In some embodiments, organic or inorganic fillers may be added to the protective layer 102 .
  • the protective layer 102 is used to protect the internal circuits of the chip, and the protective layer 102 can be used to determine the size of the third opening, that is, the surface size of the exposed metal pad 101 .
  • This embodiment may also provide an auxiliary chip 20 .
  • the semiconductor chip 10 and the auxiliary chip 20 are mounted on the carrier board.
  • One semiconductor chip 10 and one auxiliary chip 20 can be mounted on the carrier board.
  • the number of semiconductor chips 10 and auxiliary chips 20 that can be mounted on the carrier board may be multiple.
  • the shape of the carrier plate may be circular, rectangular or other shapes.
  • the material of the carrier plate may include iron-nickel fixed expansion alloy, or the material of the carrier plate may also include stainless steel or polymer.
  • step S2 is performed to form the plastic sealing layer 301 .
  • the plastic encapsulation layer 301 covers the back and side surfaces of the semiconductor chip 10 and extends to cover the side and back surfaces of the auxiliary chip 20 .
  • the specific process of forming the plastic sealing layer 301 includes:
  • Step S21 Form a molding material layer 30 covering the semiconductor chip 10 and the auxiliary chip 20;
  • Step S22 Grind part of the thickness of the plastic sealing material layer 30 to form a plastic sealing layer 301.
  • step S21 is performed to form a molding material layer 30 , and the thickness of the molding material layer 30 is greater than that of the semiconductor chip 10 , and also needs to be greater than the thickness of the auxiliary chip 20 so that the molding material layer 30 will be
  • the semiconductor chip 10 and the auxiliary chip 20 are completely covered. Furthermore, the distance between the surface of the plastic sealing material layer 30 away from the front surface 10a of the semiconductor chip and the back surface of the semiconductor chip is greater than the set value, that is, the distance between the plastic sealing material layer 30 and the back surface of the semiconductor chip is greater than the set value.
  • the thickness of layer 30 is greater than the set value.
  • the range of the set value is 5 ⁇ m to 50 ⁇ m.
  • the plastic sealing material layer 30 preferably has a small shrinkage and CTE (Coefficient of Thermal Expansion, thermal expansion). coefficient), and the material needs to be able to undergo subsequent RDL (Re-Distribution Layer, rewiring layer) processing, and it also needs to have a certain acid and alkali resistance.
  • the molding material layer 30 may be polymer, resin, resin composite material or polymer composite material, etc.
  • the molding material layer 30 may be resin with fillers, where the fillers are inorganic particles.
  • the plastic sealing material layer can be formed by lamination molding, injection molding, compression molding or transfer molding.
  • step S22 is performed to grind away part of the thickness of the plastic sealing material layer 30 to form a plastic sealing layer 301 .
  • the distance between the surface of the plastic sealing layer 301 away from the front surface 10a of the semiconductor chip and the back surface of the semiconductor chip is a set value. That is, the overall thickness of the plastic sealing layer 301 is still larger than the semiconductor chip 10 .
  • the overall thickness of the plastic sealing layer 301 needs to be larger than the auxiliary chip 20 .
  • the backside of the polished semiconductor chip 10 in this embodiment is also provided with a plastic sealing layer of a certain thickness and is not directly ground to the backside of the semiconductor chip 10 , the stress generated during the polishing process will not directly act on the semiconductor chip 10 , can avoid cracking of the semiconductor chip 10 and delamination of the chip packaging structure, and improve product yield and productivity.
  • the auxiliary chip 20 is provided, it is not ground directly onto the auxiliary chip 20 . Therefore, the stress generated during the grinding process will not directly act on the auxiliary chip 20 , which can avoid cracking of the auxiliary chip 20 and the chip packaging structure. of layering.
  • the molding layer 301 is formed, the molded structure is turned over, and the carrier board is removed.
  • step S3 is performed to form a first rewiring structure 40 on the front surface 10 a of the semiconductor chip and the front surface 20 a of the auxiliary chip.
  • the first redistribution structure 40 includes a first conductive layer and a second conductive layer, wherein the first conductive layer includes a plurality of first conductive traces 402 and a plurality of first conductive plugs 401 , and the second conductive layer
  • the conductive layer includes a plurality of conductive bumps 404 and a plurality of second conductive plugs 403 .
  • the method of forming the first rewiring structure 40 includes:
  • Step S31 Form a plurality of spaced-apart first conductive traces 402 on the front surface 10a of the semiconductor chip and the front surface 20a of the auxiliary chip, and form first conductive plugs 401 in the third opening,
  • the front side 20a of the auxiliary chip is electrically connected to the metal pad 101 through the first conductive trace 402 and the first conductive plug 401;
  • Step S32 Form a first dielectric layer 50 on the first conductive traces 402, and form a plurality of second openings (not shown in the figure) exposing the first conductive traces 402 on the first conductive traces 402. on the dielectric layer 50;
  • Step S33 Form a plurality of conductive bumps 404 arranged at intervals on a side of the first dielectric layer 50 away from the semiconductor chip 10, and form a second conductive plug 403 in the second opening.
  • the conductive bumps 404 pass At least one of the second conductive plugs 403 is electrically connected to the first conductive trace 402 .
  • Step S31 is executed to form the first conductive trace 402 and the first conductive plug 401 .
  • a first conductive plug 401 is formed in the third opening of the protective layer 102.
  • the first conductive plug 401 is in direct contact with the metal pad 101 and the first conductive trace 402 respectively.
  • a conductive trace 402 is electrically connected to the metal pad 101 through the first conductive plug 401 .
  • the first conductive trace 402 is also in direct contact with the front surface of the auxiliary chip 20 , and the front surface of the auxiliary chip 20 can be connected to at least one through the first conductive trace 402
  • One of the metal pads 101 is electrically connected.
  • the first conductive plug 401 and the first conductive trace 402 can be formed by electrolytic plating, electrodeless plating, or other methods. Furthermore, the first conductive plug 401 and the first conductive trace 402 can be formed in the same process step, which helps to simplify the packaging process.
  • the first conductive plug 401 and the first conductive trace 402 may be made of metal material, such as metal copper.
  • Step S32 is performed to form a first dielectric layer 50 and form a plurality of second openings on the first dielectric layer 50 .
  • the first dielectric layer 50 covers the surface of the first conductive trace 402 away from the semiconductor chip 10 .
  • the first dielectric layer 50 also covers the exposed plastic encapsulation layer 301 .
  • the material of the first dielectric layer 50 is preferably at least one of ABF (Ajinomoto Buildup Film), PID (Photosensitive Insulation Material) or other insulating films, but is not limited thereto.
  • the formation method of the second opening is preferably a laser method or a development method, but is not limited thereto.
  • Step S33 is executed to form conductive bumps 404 and second conductive plugs 403 .
  • the second conductive plug 403 is formed in the second opening of the first dielectric layer 50 , and the second conductive plug 403 is connected to the conductive bump 404 and the first conductive bump respectively.
  • the traces 402 are in direct contact, and the conductive bumps 404 are electrically connected to the first conductive traces 402 through the second conductive plugs 403 .
  • the conductive bumps 404 and the second conductive plugs 403 can be formed by electrolytic plating, electrodeless plating, or other methods. Furthermore, the second conductive plug 403 and the conductive bump 404 can be formed in the same process step, which helps to simplify the packaging process.
  • the conductive bump 404 and the second conductive plug 403 may be made of metal material, such as metal copper.
  • the method for preparing the chip packaging structure further includes forming a metal tin layer 60 that covers the side of the conductive bump 404 and the surface on the side away from the semiconductor chip 10 .
  • the material of the metal tin layer 60 is preferably metal tin, but is not limited thereto.
  • step S4 is performed to form a plurality of first openings 3011 on the plastic sealing layer 301 .
  • the first opening The opening 3011 extends from the surface of the plastic sealing layer 301 away from the front surface 10 a of the semiconductor chip to the back surface of the semiconductor chip 10 or the back surface of the auxiliary chip 10 .
  • the back side of the semiconductor chip is a substrate, so the first opening 3011 can expose the substrate of the semiconductor chip.
  • the formation method of the first opening 3011 is preferably a laser method or a development method, but is not limited thereto.
  • step S5 is performed to form a second rewiring structure 70 on the side of the plastic encapsulation layer 301 away from the front surface 10 a of the semiconductor chip, and the second rewiring structure 70 also fills the first opening.
  • the second redistribution structure 70 includes a third conductive trace 702 located on a side of the plastic encapsulation layer 301 away from the front surface 10 a of the semiconductor chip and a third conductive plug 701 disposed in the first opening.
  • the third conductive plug 701 is formed in the first opening 3011 of the plastic sealing layer 301, and the third conductive plug 701 is connected to the third conductive trace 702 and the semiconductor chip respectively.
  • the back surface is in direct contact, and the third conductive trace 702 is electrically connected to the back surface of the semiconductor chip through the third conductive plug 701 .
  • the third conductive trace 702 and the third conductive plug 701 can be formed by electrolytic plating, electrodeless plating, or other methods. Furthermore, the third conductive plug 701 and the third conductive trace 702 can be formed in the same process step, which helps to simplify the packaging process.
  • the material of the third conductive trace 702 and the third conductive plug 701 may be a metal material, such as metal copper.
  • step S5 further includes forming a second dielectric layer 80 covering the second redistribution structure 70 .
  • the material of the second dielectric layer 80 may be a plastic film, PI, PBO, organic polymer film, organic polymer composite material or other materials with similar properties.
  • organic or inorganic fillers may be added to the second dielectric layer 80 .
  • the substrate and the substrate are connected by drilling, filling, and rewiring.
  • the source electrode replaces the existing methods of grinding exposed silicon and direct rewiring. That is to say, this application cancels the grinding and exposing silicon process, and subsequently uses the method of drilling, filling holes and wiring to realize the connection between the substrate and the source. This can avoid cracking of the semiconductor chip and auxiliary chip caused by excessive stress during the grinding operation, and can also avoid The chip packaging structure is delaminated. Therefore, the chip packaging structure obtained by the method for preparing the chip packaging structure provided in this embodiment has no problems with delamination and cracking.

Abstract

The present application provides a chip packaging structure. The chip packaging structure comprises a semiconductor chip, an auxiliary chip, a plastic packaging layer, a first rewiring structure and a second rewiring structure; the plastic packaging layer covers the side surfaces and back surfaces of the semiconductor chip and the auxiliary chip. That is, in the present application, the back surface of the semiconductor chip and the back surface of the auxiliary chip are covered with the plastic packaging layer; thus, cracking of the semiconductor chip and the auxiliary chip can be avoided, layering of the chip packaging structure can also be avoided, and the product yield is improved.

Description

芯片封装结构及其制备方法Chip packaging structure and preparation method thereof 技术领域Technical field
本申请涉及半导体技术领域，特别涉及一种芯片封装结构及其制备方法。The present application relates to the field of semiconductor technology, and in particular to a chip packaging structure and a preparation method thereof.
背景技术Background technique
为了解决氮化镓芯片板级封装结构的衬底与正面源极相连问题，现有的芯片封装结构的再布线结构是直接与氮化镓芯片的背面的衬底接触的，而现有工艺一般通过贴装低阻辅芯片、研磨露硅以及再布线来实现衬底与正面源极相连的。在实际工艺过程中，研磨露硅作业时的应力会导致氮化镓芯片和低阻辅芯片开裂以及封装结构分层，进而导致大量产品报废。In order to solve the problem of connecting the substrate of the gallium nitride chip board-level packaging structure to the front source, the rewiring structure of the existing chip packaging structure is directly in contact with the substrate on the back side of the gallium nitride chip, and the existing process generally The substrate is connected to the front source by mounting a low-resistance auxiliary chip, grinding to expose the silicon, and rewiring. In the actual process, the stress during grinding to expose the silicon will cause cracks in the gallium nitride chip and low-resistance auxiliary chip and delamination of the packaging structure, which will lead to the scrapping of a large number of products.
因此，有必要提供一种能够解决芯片开裂和分层问题的芯片封装结构。Therefore, it is necessary to provide a chip packaging structure that can solve the problems of chip cracking and delamination.
发明内容Contents of the invention
本申请提供了一种芯片封装结构，包括：This application provides a chip packaging structure, including:
半导体芯片以及与所述半导体芯片并置的辅助芯片，所述半导体芯片的正面设有多个金属焊垫，且所述辅助芯片的正面与所述半导体芯片的正面齐平；A semiconductor chip and an auxiliary chip juxtaposed with the semiconductor chip, the front side of the semiconductor chip is provided with a plurality of metal bonding pads, and the front side of the auxiliary chip is flush with the front side of the semiconductor chip;
塑封层，覆盖所述半导体芯片的背面和侧面，并延伸覆盖所述辅助芯片的背面和侧面，且所述塑封层上设有多个分别露出所述半导体芯片的背面和辅助芯片的背面的第一开口；A plastic sealing layer covers the back and side surfaces of the semiconductor chip and extends to cover the back and side surfaces of the auxiliary chip. The plastic sealing layer is provided with a plurality of third holes respectively exposing the back surface of the semiconductor chip and the back surface of the auxiliary chip. an opening;
第一再布线结构，覆盖所述金属焊垫，并延伸覆盖所述辅助芯片的正面，以实现所述辅助芯片的正面与所述金属焊垫电连接；The first rewiring structure covers the metal bonding pad and extends to cover the front surface of the auxiliary chip to achieve electrical connection between the front surface of the auxiliary chip and the metal bonding pad;
第二再布线结构，覆盖部分所述塑封层远离所述半导体芯片的正面一侧的表面，并填充所述第一开口，以实现所述辅助芯片的背面与所述半导体芯片的背面电连接。The second rewiring structure covers part of the surface of the plastic layer away from the front side of the semiconductor chip and fills the first opening to achieve electrical connection between the back side of the auxiliary chip and the back side of the semiconductor chip.
可选的，在所述的芯片封装结构中，所述半导体芯片的背面上的塑封层厚度为设定值，所述设定值的范围为5μm～50μm。Optionally, in the chip packaging structure, the thickness of the plastic sealing layer on the back side of the semiconductor chip is a set value, and the set value ranges from 5 μm to 50 μm.
可选的，在所述的芯片封装结构中，所述辅助芯片包括辅助衬底，所述辅助衬底为材质为硅的衬底、材质为锗的衬底、材质为锗硅的衬底和材质为碳化硅的衬底中的一种； 所述辅助衬底中的掺杂离子选自于磷、硼和砷中的一种，且所述辅助衬底的掺杂浓度为1016cm-3～1022cm-3。Optionally, in the chip packaging structure, the auxiliary chip includes an auxiliary substrate, and the auxiliary substrate is a substrate made of silicon, a substrate made of germanium, a substrate made of germanium silicon and One of the substrates made of silicon carbide; The doping ions in the auxiliary substrate are selected from one of phosphorus, boron and arsenic, and the doping concentration of the auxiliary substrate is 10 16 cm -3 to 10 22 cm -3 .
可选的，在所述的芯片封装结构中，所述辅助芯片为低电阻辅助芯片，其电阻值<0.1mΩ。Optionally, in the chip packaging structure, the auxiliary chip is a low-resistance auxiliary chip with a resistance value <0.1mΩ.
可选的，在所述的芯片封装结构中，所述芯片封装结构包括一个或者多个所述辅助芯片。Optionally, in the chip packaging structure, the chip packaging structure includes one or more auxiliary chips.
可选的，在所述的芯片封装结构中，所述半导体芯片的正面还设有保护层，且所述保护层上设有多个露出所述金属焊垫的第三开口。Optionally, in the chip packaging structure, a protective layer is further provided on the front side of the semiconductor chip, and a plurality of third openings exposing the metal pads are provided on the protective layer.
可选的，在所述的芯片封装结构中，所述芯片封装结构还包括第一介电层，所述第一再布线结构包括第一导电层和第二导电层，其中，Optionally, in the chip packaging structure, the chip packaging structure further includes a first dielectric layer, and the first rewiring structure includes a first conductive layer and a second conductive layer, wherein,
所述第一导电层包括多个间隔排布在所述半导体芯片的正面和所述辅助芯片的正面上的第一导电迹线和设置在所述第三开口内的第一导电插塞，所述辅助芯片的正面通过所述第一导电迹线和第一导电插塞与所述金属焊垫电连接；The first conductive layer includes a plurality of first conductive traces arranged at intervals on the front surface of the semiconductor chip and the front surface of the auxiliary chip and a first conductive plug disposed in the third opening, so The front side of the auxiliary chip is electrically connected to the metal pad through the first conductive trace and the first conductive plug;
所述第一介电层覆盖所述第一导电迹线，且所述第一介电层上设有多个露出所述第一导电迹线的第二开口；The first dielectric layer covers the first conductive traces, and the first dielectric layer is provided with a plurality of second openings exposing the first conductive traces;
所述第二导电层包括多个间隔排布在所述第一介电层上的导电凸块和设置在所述第二开口内的第二导电插塞，所述导电凸块通过所述第二导电插塞与所述第一导电迹线电连接。The second conductive layer includes a plurality of conductive bumps arranged at intervals on the first dielectric layer and a second conductive plug disposed in the second opening. The conductive bumps pass through the first dielectric layer. Two conductive plugs are electrically connected to the first conductive trace.
可选的，在所述的芯片封装结构中，所述芯片封装结构还包括金属锡层，其覆盖所述导电凸块的侧面和远离所述半导体芯片一侧的表面。Optionally, in the chip packaging structure, the chip packaging structure further includes a metal tin layer covering the sides of the conductive bumps and the surface on the side away from the semiconductor chip.
可选的，在所述的芯片封装结构中，所述第二再布线结构包括位于所述塑封层远离所述半导体芯片的正面的一侧的第三导电迹线和设置在所述第一开口内第三导电插塞，所述辅助芯片的背面通过所述第三导电迹线和第三导电插塞与所述半导体芯片的背面电连接。Optionally, in the chip packaging structure, the second rewiring structure includes a third conductive trace located on a side of the plastic encapsulation layer away from the front surface of the semiconductor chip and a third conductive trace disposed in the first opening. Inside the third conductive plug, the back side of the auxiliary chip is electrically connected to the back side of the semiconductor chip through the third conductive trace and the third conductive plug.
可选的，在所述的芯片封装结构中，所述芯片封装结构还包括第二介电层，其覆盖所述第三导电迹线的侧面和远离所述半导体芯片一侧的表面。Optionally, in the chip packaging structure, the chip packaging structure further includes a second dielectric layer covering the side of the third conductive trace and the surface on the side away from the semiconductor chip.
可选的，在所述的芯片封装结构中，所述半导体芯片为氮化镓芯片。Optionally, in the chip packaging structure, the semiconductor chip is a gallium nitride chip.
本申请还提供了一种芯片封装结构的制备方法，包括： This application also provides a method for preparing a chip packaging structure, including:
提供半导体芯片、辅助芯片和载板，并将所述半导体芯片和辅助芯片贴装至所述载板上，所述半导体芯片的正面和所述辅助芯片的正面朝向所述载板，所述半导体芯片的正面设有多个金属焊垫；Provide a semiconductor chip, an auxiliary chip and a carrier board, and mount the semiconductor chip and the auxiliary chip on the carrier board, with the front surface of the semiconductor chip and the front surface of the auxiliary chip facing the carrier board, and the semiconductor chip and the auxiliary chip are mounted on the carrier board. There are multiple metal pads on the front side of the chip;
形成塑封层，所述塑封层覆盖所述半导体芯片的侧面和背面，并延伸覆盖所述辅助芯片的侧面和背面；Forming a plastic sealing layer, the plastic sealing layer covers the side and back of the semiconductor chip, and extends to cover the side and back of the auxiliary chip;
形成第一再布线结构于所述半导体芯片的正面和所述辅助芯片的正面，且所述第一再布线结构与所述金属焊垫电连接；Forming a first rewiring structure on the front surface of the semiconductor chip and the front surface of the auxiliary chip, and the first rewiring structure is electrically connected to the metal pad;
形成多个分别露出所述半导体芯片的背面和所述辅助芯片的背面的第一开口于所述塑封层上；Forming a plurality of first openings on the plastic sealing layer respectively exposing the back surface of the semiconductor chip and the back surface of the auxiliary chip;
形成第二再布线结构于所述塑封层远离所述半导体芯片的正面的一侧，且所述第二再布线结构还填满所述第一开口。A second rewiring structure is formed on a side of the plastic encapsulation layer away from the front surface of the semiconductor chip, and the second rewiring structure also fills the first opening.
附图说明Description of drawings
图1～4是一种氮化镓芯片板级封装结构的制备方法中各步骤对应的结构示意图；Figures 1 to 4 are structural schematic diagrams corresponding to each step in a method for preparing a gallium nitride chip board-level packaging structure;
图5是本申请一实施例的芯片封装结构的结构示意图；Figure 5 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application;
图6～图10是本申请一实施例的芯片封装结构的制备方法中各步骤对应的结构示意图；6 to 10 are structural schematic diagrams corresponding to each step in the method for preparing a chip packaging structure according to an embodiment of the present application;
图1～图4中附图标记：Reference signs in Figures 1 to 4:
01-氮化镓芯片，011-金属焊垫，012-保护层，02-低电阻辅助芯片，03-塑封层，04-第一再布线结构，041-第一导电插塞，042-第一导电迹线，043-第二导电插塞，044-导电凸块，05-第一介电层，06-金属锡层，07-第二再布线结构，08-第二介电层；01-GaN chip, 011-metal pad, 012-protective layer, 02-low resistance auxiliary chip, 03-plastic sealing layer, 04-first rewiring structure, 041-first conductive plug, 042-first Conductive traces, 043-second conductive plug, 044-conductive bump, 05-first dielectric layer, 06-metal tin layer, 07-second rewiring structure, 08-second dielectric layer;
图5～图10中附图标记：Reference signs in Figures 5 to 10:
10-半导体芯片，10a-半导体芯片的正面，101-金属焊垫，102-保护层，20-辅助芯片，20a-辅助芯片的正面，30-塑封材料层，301-塑封层，3011-第一开口，40-第一再布线结构，401-第一导电插塞，402-第一导电迹线，403-第二导电插塞，404-导电凸块，50-第一介电层，60-金属锡层，70-第二再布线结构，701-第三导电插塞，702-第三导电迹线，80-第二介电层。 10-semiconductor chip, 10a-front side of semiconductor chip, 101-metal pad, 102-protective layer, 20-auxiliary chip, 20a-front side of auxiliary chip, 30-plastic sealing material layer, 301-plastic sealing layer, 3011-first Opening, 40-first redistribution structure, 401-first conductive plug, 402-first conductive trace, 403-second conductive plug, 404-conductive bump, 50-first dielectric layer, 60- Metal tin layer, 70-second rewiring structure, 701-third conductive plug, 702-third conductive trace, 80-second dielectric layer.
具体实施方式Detailed ways
以下结合附图和具体实施例对本申请提出的芯片封装结构作进一步详细说明。根据下面说明书，本申请的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本申请实施例的目的。The chip packaging structure proposed in this application will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present application will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use imprecise proportions, and are only used to conveniently and clearly assist in explaining the embodiments of the present application.
一种氮化镓芯片板级封装结构的制备方法通过贴装低阻辅芯片、研磨露硅以及再布线来实现衬底与正面源极相连，具体请参阅图1～图4。A method for preparing a gallium nitride chip board-level packaging structure realizes the connection between the substrate and the front source by mounting a low-resistance auxiliary chip, grinding to expose the silicon, and rewiring. Please refer to Figures 1 to 4 for details.
所述氮化镓芯片板级封装结构的制备方法包括：The preparation method of the gallium nitride chip board-level packaging structure includes:
贴装氮化镓芯片01和低电阻辅助芯片02至一载板(图中未示出)上，所述氮化镓芯片01的正面设有保护层012和多个金属焊垫011，所述保护层012上设有多个露出部分所述金属焊垫011的第一开口；The gallium nitride chip 01 and the low-resistance auxiliary chip 02 are mounted on a carrier board (not shown in the figure). The front side of the gallium nitride chip 01 is provided with a protective layer 012 and a plurality of metal pads 011. The protective layer 012 is provided with a plurality of first openings that expose portions of the metal pads 011;
形成塑封层03，所述塑封层03覆盖所述氮化镓芯片01和低电阻辅助芯片02的侧面和背面；Form a plastic encapsulation layer 03 that covers the side and back sides of the gallium nitride chip 01 and the low-resistance auxiliary chip 02;
研磨所述塑封层03，直至露出所述氮化镓芯片01的背面；Grind the plastic encapsulation layer 03 until the back side of the gallium nitride chip 01 is exposed;
形成第一再布线结构04、第一介电层05和金属锡层06，所述第一再布线结构04包括多个第一导电插塞041、第一导电迹线042、第二导电插塞043和导电凸块044，所述第一导电插塞041位于所述第一开口内；所述第一导电迹线042位于所述氮化镓芯片01的正面和辅助芯片02的正面上，所述辅助芯片02的正面通过所述第一导电迹线042和第一导电插塞041与所述金属焊垫011电连接；所述第一介电层05覆盖所述第一导电迹线042，且所述第一介电层05上设有多个露出部分所述第一导电迹线042的第二开口；所述第二导电插塞043位于所述第二开口内；所述导电凸块044位于所述第一介电层05远离所述氮化镓芯片01的一侧，且通过所述第二导电插塞043与所述第一导电迹线042电连接；所述金属锡层06覆盖所述导电凸块044；A first rewiring structure 04, a first dielectric layer 05, and a metal tin layer 06 are formed. The first rewiring structure 04 includes a plurality of first conductive plugs 041, first conductive traces 042, and second conductive plugs. 043 and conductive bumps 044, the first conductive plug 041 is located in the first opening; the first conductive trace 042 is located on the front surface of the gallium nitride chip 01 and the front surface of the auxiliary chip 02, so The front side of the auxiliary chip 02 is electrically connected to the metal pad 011 through the first conductive trace 042 and the first conductive plug 041; the first dielectric layer 05 covers the first conductive trace 042, And the first dielectric layer 05 is provided with a plurality of second openings exposing portions of the first conductive traces 042; the second conductive plugs 043 are located in the second openings; the conductive bumps 044 is located on the side of the first dielectric layer 05 away from the gallium nitride chip 01 and is electrically connected to the first conductive trace 042 through the second conductive plug 043; the metal tin layer 06 Cover the conductive bumps 044;
形成第二再布线结构07和第二介电层08，所述第二再布线结构07位于所述氮化镓芯片01和辅助芯片02的背面，所述第二介电层08覆盖所述第二再布线结构07。A second rewiring structure 07 and a second dielectric layer 08 are formed. The second rewiring structure 07 is located on the back side of the gallium nitride chip 01 and the auxiliary chip 02. The second dielectric layer 08 covers the second dielectric layer 08. Second rewiring structure 07.
由于在研磨塑封层03的步骤中，研磨产生的应力将直接作用于辅助芯片02和氮化镓芯片01上，容易导致氮化镓芯片01和辅助芯片02的开裂以及芯片封装结构的分层问题，进而导致大量产品报废，最终获得的产品不良率大约为30％。During the step of grinding the plastic encapsulation layer 03, the stress generated by grinding will directly act on the auxiliary chip 02 and the gallium nitride chip 01, which may easily lead to cracking of the gallium nitride chip 01 and the auxiliary chip 02 and delamination of the chip packaging structure. , which in turn leads to a large number of products being scrapped, and the final product defect rate is approximately 30%.
因此，本申请提供了一种新型的芯片封装结构，其在所述半导体芯片的背面和辅助 芯片的背面上保留了一定厚度的塑封层，并不需要研磨至半导体芯片和辅助芯片的背面，也不会出现应力直接作用在半导体芯片和辅助芯片上，能够避免半导体芯片和辅助芯片的开裂以及芯片封装结构的分层问题，进而避免出现大量产品报废，进而可以提高产品良率和产率。Therefore, this application provides a new type of chip packaging structure, which is on the back side of the semiconductor chip and auxiliary There is a certain thickness of the plastic sealing layer on the back of the chip, which does not need to be ground to the back of the semiconductor chip and auxiliary chip, and there will be no stress acting directly on the semiconductor chip and auxiliary chip, which can avoid cracking and cracking of the semiconductor chip and auxiliary chip. The delamination problem of the chip packaging structure can avoid a large number of product scraps, thereby improving product yield and productivity.
参见图5，所述芯片封装结构包括：Referring to Figure 5, the chip packaging structure includes:
半导体芯片10以及与所述半导体芯片10并置的辅助芯片20，所述半导体芯片10的正面设有多个金属焊垫101，且所述辅助芯片20的正面与所述半导体芯片10的正面齐平；The semiconductor chip 10 and the auxiliary chip 20 juxtaposed with the semiconductor chip 10 are provided with a plurality of metal bonding pads 101 on the front side of the semiconductor chip 10, and the front side of the auxiliary chip 20 is flush with the front side of the semiconductor chip 10. flat;
塑封层301，覆盖所述半导体芯片10的背面和侧面，并延伸覆盖所述辅助芯片20的背面和侧面，且所述塑封层301上设有多个露出所述半导体芯片10的背面和辅助芯片20的背面的第一开口；The plastic sealing layer 301 covers the back and side surfaces of the semiconductor chip 10 and extends to cover the back and side surfaces of the auxiliary chip 20 . The plastic sealing layer 301 is provided with a plurality of exposed back surfaces and auxiliary chips of the semiconductor chip 10 . the first opening on the back of 20;
第一再布线结构40，覆盖所述金属焊垫101，并延伸覆盖所述辅助芯片20的正面，以实现所述辅助芯片20的正面与所述金属焊垫101电连接；The first rewiring structure 40 covers the metal bonding pad 101 and extends to cover the front surface of the auxiliary chip 20 to achieve electrical connection between the front surface of the auxiliary chip 20 and the metal bonding pad 101;
第二再布线结构70，覆盖部分所述塑封层301远离所述半导体芯片10的正面一侧的表面，并填充所述第一开口，以实现所述辅助芯片20的背面与所述半导体芯片10的背面电连接。The second rewiring structure 70 covers part of the surface of the plastic encapsulation layer 301 away from the front side of the semiconductor chip 10 and fills the first opening to realize the connection between the back side of the auxiliary chip 20 and the semiconductor chip 10 electrical connections on the back.
所述半导体芯片10优选为氮化镓(GaN)芯片，但不限于此。在一个实施例中，所述半导体芯片10可通过对晶圆进行切割得到。晶圆具有活性面，晶圆的活性面设有金属焊垫101。可采用机械切割的方式或者激光切割的方式切割晶圆。The semiconductor chip 10 is preferably a gallium nitride (GaN) chip, but is not limited thereto. In one embodiment, the semiconductor chip 10 can be obtained by cutting a wafer. The wafer has an active surface, and the active surface of the wafer is provided with a metal bonding pad 101 . The wafer can be cut by mechanical cutting or laser cutting.
所述半导体芯片10的金属焊垫101作为源极，是由芯片内部电路引出至芯片表面的导电电极构成。所述半导体芯片10的正面可设有多个金属焊垫101。所述金属焊垫101用于将半导体芯片10的导电电极引出。所述半导体芯片10的背面为所述半导体芯片10的衬底，即半导体衬底。The metal pad 101 of the semiconductor chip 10 serves as a source, which is composed of a conductive electrode led from the internal circuit of the chip to the surface of the chip. A plurality of metal bonding pads 101 may be provided on the front surface of the semiconductor chip 10 . The metal pad 101 is used to lead out the conductive electrode of the semiconductor chip 10 . The back side of the semiconductor chip 10 is the substrate of the semiconductor chip 10 , that is, the semiconductor substrate.
所述半导体芯片10的正面还设有保护层102，所述保护层102会覆盖部分所述金属焊垫101，即所述保护层102上形成有多个露出所述金属焊垫的部分表面的第三开口。所述保护层102的材料可以是塑封膜、PI(Polyimide，聚酰亚胺)、PBO(Polybenzoxazole，聚苯并恶唑)、有机聚合物膜、有机聚合物复合材料或者其他具有类似特性的材料。在一些实施例中，所述保护层102中还可以加入有机或无机的填料。A protective layer 102 is also provided on the front side of the semiconductor chip 10. The protective layer 102 will cover part of the metal bonding pad 101. That is, a plurality of holes are formed on the protective layer 102 to expose part of the surface of the metal bonding pad. The third opening. The material of the protective layer 102 may be a plastic film, PI (Polyimide, polyimide), PBO (Polybenzoxazole, polybenzoxazole), organic polymer film, organic polymer composite material or other materials with similar characteristics. . In some embodiments, organic or inorganic fillers may be added to the protective layer 102 .
所述芯片封装结构还可以包括与所述半导体芯片10并置的辅助芯片20。所述辅助 芯片20主要用于导通，在形成第一再布线结构和第二再布线结构之后可以与所述半导体芯片10形成回路。由于所述半导体芯片优选为氮化镓(GaN)芯片，而氮化镓芯片的电子在工作时可能会因为衬底上方的绝缘层的绝缘效果不太好而掉入衬底中，从而产生漏电的情况，在持续工作的过程中，电子无法回到氮化镓芯片的源极，逐渐积累会导致器件静态工作点漂移。因此，本实施例可以通过增设的辅助芯片20与所述半导体芯片10形成一个回路让衬底的电子回到源极，来避免产生漏电的情况。The chip packaging structure may further include an auxiliary chip 20 juxtaposed with the semiconductor chip 10 . The auxiliary The chip 20 is mainly used for conduction, and can form a loop with the semiconductor chip 10 after forming the first rewiring structure and the second rewiring structure. Since the semiconductor chip is preferably a Gallium Nitride (GaN) chip, the electrons in the GaN chip may fall into the substrate due to the poor insulation effect of the insulating layer above the substrate during operation, thus causing leakage. In this case, during continuous operation, electrons cannot return to the source of the gallium nitride chip, and the gradual accumulation will cause the static operating point of the device to drift. Therefore, in this embodiment, the additional auxiliary chip 20 can form a loop with the semiconductor chip 10 to allow the electrons of the substrate to return to the source, thereby avoiding leakage.
所述辅助芯片20的数量为一个，从而形成一条载流通道。或者，在其他实施例中，所述辅助芯片20的数量也可以为多个，从而形成多条载流通道。多个所述辅助芯片20横向间隔布置，并且均与所述半导体芯片10并置，其中，所述半导体芯片10和所述辅助芯片20之间的间隙以及多个所述辅助芯片20横向间隔布置所形成的间隙可以由非导电材料填充。进一步的，多个所述辅助芯片20可以位于所述半导体芯片10的同一侧，也可以位于所述半导体芯片10的不同侧。The number of the auxiliary chip 20 is one, thereby forming a current-carrying channel. Alternatively, in other embodiments, the number of the auxiliary chips 20 may also be multiple, thereby forming multiple current-carrying channels. A plurality of the auxiliary chips 20 are laterally spaced apart and are juxtaposed with the semiconductor chip 10 , wherein the gap between the semiconductor chip 10 and the auxiliary chip 20 and the plurality of auxiliary chips 20 are laterally spaced apart. The resulting gap may be filled with non-conductive material. Furthermore, the plurality of auxiliary chips 20 may be located on the same side of the semiconductor chip 10 , or may be located on different sides of the semiconductor chip 10 .
在本实施例中，所述辅助芯片20优选为低电阻辅助芯片，但不限于此。进一步的，所述低电阻辅助芯片的电阻值<0.1mΩ。在本实施例中，所述辅助芯片20可以仅包括辅助衬底，即仅包括一层半导体材料层。在此，所述辅助衬底的阻抗小于所述半导体衬底的阻抗。具体的，可以通过对所述辅助衬底和所述半导体衬底的材质的选择和/或掺杂以使得所述辅助衬底的阻抗小于所述半导体衬底的阻抗。In this embodiment, the auxiliary chip 20 is preferably a low-resistance auxiliary chip, but is not limited thereto. Further, the resistance value of the low-resistance auxiliary chip is <0.1mΩ. In this embodiment, the auxiliary chip 20 may only include an auxiliary substrate, that is, only include a layer of semiconductor material. Here, the impedance of the auxiliary substrate is smaller than the impedance of the semiconductor substrate. Specifically, the materials of the auxiliary substrate and the semiconductor substrate can be selected and/or doped so that the impedance of the auxiliary substrate is smaller than the impedance of the semiconductor substrate.
其中，所述辅助衬底和所述半导体衬底的材质可以相同，也可以不相同。例如，所述辅助衬底和所述半导体衬底的材质相同并且均为硅。或者，所述辅助衬底和所述半导体衬底的材质不同，所述辅助衬底和所述半导体衬底的材质可以选自于硅、锗、锗硅和碳化硅中的一种。例如，所述辅助衬底的材质为硅，所述半导体衬底的材质为碳化硅；或者所述辅助衬底的材质为锗，所述半导体衬底的材质为锗硅等。The materials of the auxiliary substrate and the semiconductor substrate may be the same or different. For example, the auxiliary substrate and the semiconductor substrate are made of the same material and are both silicon. Alternatively, the auxiliary substrate and the semiconductor substrate may be made of different materials, and the materials of the auxiliary substrate and the semiconductor substrate may be selected from one of silicon, germanium, silicon germanium and silicon carbide. For example, the material of the auxiliary substrate is silicon, and the material of the semiconductor substrate is silicon carbide; or the material of the auxiliary substrate is germanium, and the material of the semiconductor substrate is silicon germanium, etc.
进一步的，所述辅助衬底和所述半导体衬底均有掺杂离子。优选的，所述辅助衬底中的掺杂离子和所述半导体衬底中的掺杂离子相同。具体的，所述辅助衬底中的掺杂离子和所述半导体衬底中的掺杂离子均为P型离子或者均为N型离子。例如，所述辅助衬底中的掺杂离子和所述半导体衬底中的掺杂离子均选自于磷、硼和砷中的一种。所述辅助芯片20优选为P型高掺杂的芯片，即辅助衬底的掺杂离子优选为P型离子。Further, both the auxiliary substrate and the semiconductor substrate are doped with ions. Preferably, the doping ions in the auxiliary substrate and the doping ions in the semiconductor substrate are the same. Specifically, the doping ions in the auxiliary substrate and the doping ions in the semiconductor substrate are both P-type ions or both are N-type ions. For example, the doping ions in the auxiliary substrate and the doping ions in the semiconductor substrate are selected from one of phosphorus, boron and arsenic. The auxiliary chip 20 is preferably a P-type highly doped chip, that is, the doping ions of the auxiliary substrate are preferably P-type ions.
其中，所述辅助衬底的掺杂浓度较所述半导体衬底的掺杂浓度高。优选的，所述辅助衬底的掺杂浓度为1016cm-3～1022cm-3，所述半导体衬底的掺杂浓度为1015cm-3～1019cm-3。例如，所述辅助衬底的掺杂浓度为1021cm-3，所述半导体衬底的掺杂浓度为1019cm-3； 又如，所述辅助衬底的掺杂浓度为1019cm-3，所述半导体衬底的掺杂浓度为1018cm-3。Wherein, the doping concentration of the auxiliary substrate is higher than the doping concentration of the semiconductor substrate. Preferably, the doping concentration of the auxiliary substrate is 10 16 cm -3 ~ 10 22 cm -3 and the doping concentration of the semiconductor substrate is 10 15 cm -3 ~ 10 19 cm -3 . For example, the doping concentration of the auxiliary substrate is 10 21 cm -3 and the doping concentration of the semiconductor substrate is 10 19 cm -3 ; For another example, the doping concentration of the auxiliary substrate is 10 19 cm -3 and the doping concentration of the semiconductor substrate is 10 18 cm -3 .
在本申请的其他实施例中，所述辅助衬底中的掺杂离子和所述半导体衬底中的掺杂离子也可以不相同。在此，只要实现所述辅助衬底的阻抗小于所述半导体衬底的阻抗即可，从而可以通过所述辅助衬底作为所述半导体衬底中电子的载流通道。In other embodiments of the present application, the doping ions in the auxiliary substrate and the doping ions in the semiconductor substrate may also be different. Here, as long as the impedance of the auxiliary substrate is smaller than the impedance of the semiconductor substrate, the auxiliary substrate can be used as a current-carrying channel for electrons in the semiconductor substrate.
在其他本实施例，所述辅助芯片20可以包括辅助衬底和位于所述辅助衬底上的半导体材料层，即包括多层半导体材料层。所述辅助芯片20的设置只要满足所述辅助芯片20的阻抗小于所述半导体芯片10的阻抗即可，在此不做赘述。In other embodiments, the auxiliary chip 20 may include an auxiliary substrate and a semiconductor material layer located on the auxiliary substrate, that is, include multiple semiconductor material layers. The arrangement of the auxiliary chip 20 only needs to satisfy that the impedance of the auxiliary chip 20 is smaller than the impedance of the semiconductor chip 10 , which will not be described in detail here.
在本申请实施例中，所述辅助芯片20的正面优选与所述半导体芯片10的正面齐平，所述辅助芯片20的背面优选与所述半导体芯片10的背面齐平。所述正面与所述背面相对。由于所述辅助芯片20是用于电子导通的，因此，所述辅助芯片20的正背面设置并不做特殊要求，例如，在本实施例中所述辅助芯片20的背面为辅助衬底。在其他实施例中，所述辅助芯片20的正面为辅助衬底。In the embodiment of the present application, the front side of the auxiliary chip 20 is preferably flush with the front side of the semiconductor chip 10 , and the back side of the auxiliary chip 20 is preferably flush with the back side of the semiconductor chip 10 . The front side is opposite to the back side. Since the auxiliary chip 20 is used for electronic conduction, there are no special requirements for the arrangement of the front and back of the auxiliary chip 20 . For example, in this embodiment, the back of the auxiliary chip 20 is an auxiliary substrate. In other embodiments, the front side of the auxiliary chip 20 is an auxiliary substrate.
所述塑封层301覆盖所述半导体芯片10的侧面和背面，同时也覆盖所述辅助芯片10的背面和侧面。所述半导体芯片10的背面上的塑封层301厚度为设定值，即所述塑封层301远离所述半导体芯片10的正面一侧的表面与所述半导体芯片10的背面之间的距离为设定值，所述设定值的范围可以为5μm～50μm。所述辅助芯片20的背面上的塑封层301厚度也为设定值。由于所述半导体芯片10的背面和辅助芯片20的背面上还保留一定厚度的塑封层，因此，在制备所述芯片封装结构的过程中并不需要将塑封层301研磨至露出所述半导体芯片10的背面和所述辅助芯片20的背面，研磨产生的应力也不会直接作用在半导体芯片10和辅助芯片上，能够避免半导体芯片10和辅助芯片20的开裂，同时也可以避免芯片封装结构的分层，进而可以提高产品良率和产率。The plastic encapsulation layer 301 covers the side and back of the semiconductor chip 10 and also covers the back and side of the auxiliary chip 10 . The thickness of the plastic sealing layer 301 on the back surface of the semiconductor chip 10 is a set value, that is, the distance between the surface of the plastic sealing layer 301 away from the front side of the semiconductor chip 10 and the back surface of the semiconductor chip 10 is a set value. The set value can range from 5 μm to 50 μm. The thickness of the plastic sealing layer 301 on the back side of the auxiliary chip 20 is also a set value. Since a certain thickness of the plastic sealing layer remains on the back surface of the semiconductor chip 10 and the back surface of the auxiliary chip 20 , there is no need to grind the plastic sealing layer 301 to expose the semiconductor chip 10 during the process of preparing the chip packaging structure. The stress generated by grinding will not directly act on the semiconductor chip 10 and the auxiliary chip 20, which can avoid cracking of the semiconductor chip 10 and the auxiliary chip 20, and also avoid the decomposition of the chip packaging structure. layer, thereby improving product yield and productivity.
所述塑封层301上设有多个露出部分所述半导体芯片10的背面和辅助芯片20的背面的第一开口，所述第一开口从所述塑封层301远离所述半导体芯片10的正面一侧的表面延伸至所述半导体芯片的背面或者辅助芯片20的背面。The plastic sealing layer 301 is provided with a plurality of first openings that expose part of the back surface of the semiconductor chip 10 and the back surface of the auxiliary chip 20 . The first openings are separated from the front surface of the semiconductor chip 10 from the plastic sealing layer 301 . The surface of the side extends to the back side of the semiconductor chip or the back side of the auxiliary chip 20 .
所述第一再布线结构40包括第一导电层和第二导电层，所述芯片封装结构还包括第一介电层50。The first rewiring structure 40 includes a first conductive layer and a second conductive layer, and the chip packaging structure further includes a first dielectric layer 50 .
所述第一导电层包括多个间隔排布在所述半导体芯片10的正面和辅助芯片20的正面上的第一导电迹线402和设置在所述第三开口内的第一导电插塞401，所述辅助芯片20的正面通过所述第一导电迹线402和所述第一导电插塞401与所述金属焊垫101电连 接。The first conductive layer includes a plurality of first conductive traces 402 spaced apart on the front surface of the semiconductor chip 10 and the front surface of the auxiliary chip 20 and a first conductive plug 401 disposed in the third opening. , the front side of the auxiliary chip 20 is electrically connected to the metal pad 101 through the first conductive trace 402 and the first conductive plug 401 catch.
所述第一介电层50覆盖所述第一导电迹线402，且所述第一介电层50上设有多个露出所述第一导电迹线402的第二开口。所述第一介电层50的材料可以是塑封膜、PI、PBO、有机聚合物膜、有机聚合物复合材料或者其他具有类似特性的材料。在一些实施例中，所述第一介电层50中还可以加入有机或无机的填料。The first dielectric layer 50 covers the first conductive traces 402 , and the first dielectric layer 50 is provided with a plurality of second openings exposing the first conductive traces 402 . The first dielectric layer 50 may be made of plastic film, PI, PBO, organic polymer film, organic polymer composite material or other materials with similar properties. In some embodiments, organic or inorganic fillers may be added to the first dielectric layer 50 .
所述第二导电层包括多个间隔排布在所述第一介电层50远离所述半导体芯片10的一侧的导电凸块404和设置在第二开口内的第二导电插塞403，每个所述导电凸块404通过至少一个所述第二导电插塞403与所述第一导电迹线402电连接。The second conductive layer includes a plurality of conductive bumps 404 spaced apart on a side of the first dielectric layer 50 away from the semiconductor chip 10 and a second conductive plug 403 disposed in the second opening, Each of the conductive bumps 404 is electrically connected to the first conductive trace 402 through at least one of the second conductive plugs 403 .
所述芯片封装结构还包括金属锡层60，其用于外接其他电路。所述金属锡层60覆盖所述导电凸块404侧面和远离所述半导体芯片10一侧的表面。所述金属锡层的材料优选为金属锡，但不限于此。The chip packaging structure also includes a metal tin layer 60 for external connection to other circuits. The metal tin layer 60 covers the side surface of the conductive bump 404 and the surface away from the semiconductor chip 10 . The material of the metal tin layer is preferably metal tin, but is not limited thereto.
所述第二再布线结构70包括位于所述塑封层301远离所述半导体芯片10的正面的一侧的第三导电迹线702和设置在所述第一开口内第三导电插塞701，所述辅助芯片20的背面通过所述第三导电迹线702和第三导电插塞701与所述半导体芯片10的背面电连接。The second rewiring structure 70 includes a third conductive trace 702 located on a side of the plastic encapsulation layer 301 away from the front surface of the semiconductor chip 10 and a third conductive plug 701 disposed in the first opening, so The backside of the auxiliary chip 20 is electrically connected to the backside of the semiconductor chip 10 through the third conductive trace 702 and the third conductive plug 701 .
所述芯片封装结构还包括覆盖所述第二再布线结构70的第二介电层80，所述第二介电层80的材料可以是塑封膜、PI、PBO、有机聚合物膜、有机聚合物复合材料或者其他具有类似特性的材料。在一些实施例中，所述第二介电层80中还可以加入有机或无机的填料。The chip packaging structure also includes a second dielectric layer 80 covering the second rewiring structure 70. The material of the second dielectric layer 80 can be plastic film, PI, PBO, organic polymer film, organic polymer composite materials or other materials with similar properties. In some embodiments, organic or inorganic fillers may be added to the second dielectric layer 80 .
参阅图6～图10，所述芯片封装结构的制备方法包括：Referring to Figures 6 to 10, the method for preparing the chip packaging structure includes:
步骤S1：提供一半导体芯片10、辅助芯片20和载板(图中未示出)，并将所述半导体芯片10和辅助芯片20贴装至所述载板上，所述半导体芯片的正面10a和所述辅助芯片的正面20a朝向所述载板，所述半导体芯片10的正面10a设有多个金属焊垫101；Step S1: Provide a semiconductor chip 10, an auxiliary chip 20 and a carrier board (not shown in the figure), and mount the semiconductor chip 10 and the auxiliary chip 20 on the carrier board. The front side 10a of the semiconductor chip And the front surface 20a of the auxiliary chip faces the carrier board, and the front surface 10a of the semiconductor chip 10 is provided with a plurality of metal bonding pads 101;
步骤S2：形成塑封层301，所述塑封层301覆盖所述半导体芯片10的侧面和背面，并延伸覆盖所述辅助芯片20的背面和侧面；Step S2: Form a plastic sealing layer 301 that covers the side and back of the semiconductor chip 10 and extends to cover the back and side of the auxiliary chip 20;
步骤S3：形成第一再布线结构40于所述半导体芯片的正面10a和所述辅助芯片的正面20a，且所述第一再布线结构40与所述金属焊垫101电连接；Step S3: Form a first rewiring structure 40 on the front side 10a of the semiconductor chip and the front side 20a of the auxiliary chip, and the first rewiring structure 40 is electrically connected to the metal pad 101;
步骤S4：形成多个分别露出所述半导体芯片的背面和所述辅助芯片的背面的第一开 口3011于所述塑封层301上；Step S4: Form a plurality of first openings respectively exposing the back surface of the semiconductor chip and the back surface of the auxiliary chip. The opening 3011 is on the plastic sealing layer 301;
步骤S5：形成第二再布线结构70于所述塑封层301远离所述半导体芯片的正面10a的一侧，且所述第二再布线结构70还填满所述第一开口3011。Step S5: Form a second rewiring structure 70 on the side of the plastic encapsulation layer 301 away from the front surface 10a of the semiconductor chip, and the second rewiring structure 70 also fills the first opening 3011.
参阅图6，执行步骤S1，提供半导体芯片10，所述半导体芯片10的正面10a设有多个金属焊垫101。所述半导体芯片的正面10a还设有保护层102，所述保护层102会覆盖部分所述金属焊垫101，即所述保护层102上形成有多个露出所述金属焊垫101的部分表面的第三开口(图中未标出)。所述第三开口的形成方法优选为镭射方法或者显影方法，但不限于此。所述保护层102的材料可以为塑封膜、PI(聚酰亚胺)、PBO(聚苯并恶唑)、有机聚合物膜、有机聚合物复合材料或者其他具有类似特性的材料。在一些实施例中，所述保护层102中还可以加入有机或无机的填料。所述保护层102用来保护芯片内部线路，且所述保护层102可以用来决定第三开口的大小，即露出的金属焊垫101的表面大小。Referring to FIG. 6 , step S1 is performed to provide a semiconductor chip 10 . A plurality of metal bonding pads 101 are provided on the front surface 10 a of the semiconductor chip 10 . The front surface 10a of the semiconductor chip is also provided with a protective layer 102. The protective layer 102 will cover part of the metal pads 101. That is, the protective layer 102 is formed with a plurality of partial surfaces exposing the metal pads 101. The third opening (not marked in the figure). The formation method of the third opening is preferably a laser method or a development method, but is not limited thereto. The protective layer 102 may be made of a plastic film, PI (polyimide), PBO (polybenzoxazole), organic polymer film, organic polymer composite material, or other materials with similar properties. In some embodiments, organic or inorganic fillers may be added to the protective layer 102 . The protective layer 102 is used to protect the internal circuits of the chip, and the protective layer 102 can be used to determine the size of the third opening, that is, the surface size of the exposed metal pad 101 .
本实施例还可以提供辅助芯片20。在步骤S1中，将所述半导体芯片10和辅助芯片20贴装到所述载板上，所述载板上可以贴装有一个半导体芯片10和一个辅助芯片20。在其他实施例中，所述载板上可以贴装的半导体芯片10和辅助芯片20的数量均可为多个。所述载板的形状可为圆形、矩形或其他形状。所述载板的材料可以包括铁镍定膨胀合金，或者载板的材料也可以包括不锈钢或者聚合物等。This embodiment may also provide an auxiliary chip 20 . In step S1, the semiconductor chip 10 and the auxiliary chip 20 are mounted on the carrier board. One semiconductor chip 10 and one auxiliary chip 20 can be mounted on the carrier board. In other embodiments, the number of semiconductor chips 10 and auxiliary chips 20 that can be mounted on the carrier board may be multiple. The shape of the carrier plate may be circular, rectangular or other shapes. The material of the carrier plate may include iron-nickel fixed expansion alloy, or the material of the carrier plate may also include stainless steel or polymer.
参阅图6和图7，执行步骤S2，形成塑封层301。所述塑封层301覆盖所述半导体芯片10的背面和侧面，并延伸覆盖所述辅助芯片20的侧面和背面。Referring to FIG. 6 and FIG. 7 , step S2 is performed to form the plastic sealing layer 301 . The plastic encapsulation layer 301 covers the back and side surfaces of the semiconductor chip 10 and extends to cover the side and back surfaces of the auxiliary chip 20 .
形成所述塑封层301的具体过程包括：The specific process of forming the plastic sealing layer 301 includes:
步骤S21：形成覆盖所述半导体芯片10和辅助芯片20的塑封材料层30；Step S21: Form a molding material layer 30 covering the semiconductor chip 10 and the auxiliary chip 20;
步骤S22：对所述塑封材料层30的部分厚度进行研磨，以形成塑封层301。Step S22: Grind part of the thickness of the plastic sealing material layer 30 to form a plastic sealing layer 301.
参阅图6，执行步骤S21，形成塑封材料层30，且所述塑封材料层30的厚度大于所述半导体芯片10，同时也需要大于所述辅助芯片20的厚度，以便所述塑封材料层30将所述半导体芯片10和辅助芯片20完全覆盖住。更进一步，所述塑封材料层30远离所述半导体芯片的正面10a一侧的表面与所述半导体芯片的背面之间的距离大于所述设定值，即所述半导体芯片的背面上的塑封材料层30的厚度大于设定值。所述设定值的范围是5μm～50μm。Referring to FIG. 6 , step S21 is performed to form a molding material layer 30 , and the thickness of the molding material layer 30 is greater than that of the semiconductor chip 10 , and also needs to be greater than the thickness of the auxiliary chip 20 so that the molding material layer 30 will be The semiconductor chip 10 and the auxiliary chip 20 are completely covered. Furthermore, the distance between the surface of the plastic sealing material layer 30 away from the front surface 10a of the semiconductor chip and the back surface of the semiconductor chip is greater than the set value, that is, the distance between the plastic sealing material layer 30 and the back surface of the semiconductor chip is greater than the set value. The thickness of layer 30 is greater than the set value. The range of the set value is 5 μm to 50 μm.
所述塑封材料层30优选收缩率小且CTE(Coefficient of Thermal Expansion，热膨胀 系数)小的材料，并且材料需要能够进行后续的RDL(Re-Distribution Layer，重布线层)加工，还需要具有一定的耐酸碱能力。进一步的，所述塑封材料层30可以为聚合物、树脂、树脂复合材料或者聚合物复合材料等。例如所述塑封材料层30可以为具有填充物的树脂，其中，填充物为无机颗粒。所述塑封材料层可采用层压成型、注塑成型、压模成型或传递成型等方式形成。The plastic sealing material layer 30 preferably has a small shrinkage and CTE (Coefficient of Thermal Expansion, thermal expansion). coefficient), and the material needs to be able to undergo subsequent RDL (Re-Distribution Layer, rewiring layer) processing, and it also needs to have a certain acid and alkali resistance. Further, the molding material layer 30 may be polymer, resin, resin composite material or polymer composite material, etc. For example, the molding material layer 30 may be resin with fillers, where the fillers are inorganic particles. The plastic sealing material layer can be formed by lamination molding, injection molding, compression molding or transfer molding.
参阅图7，执行步骤S22，研磨掉所述塑封材料层30的部分厚度，形成塑封层301。所述塑封层301远离所述半导体芯片的正面10a一侧的表面与所述半导体芯片的背面之间的距离为设定值。即所述塑封层301的整体厚度仍然大于所述半导体芯片10，在本实施例设有辅助芯片20的情况下，所述塑封层301的整体厚度还需要大于所述辅助芯片20。由于该实施例的研磨后半导体芯片10的背面还设有一定厚度的塑封层，并不是直接研磨至所述半导体芯片10的背面，因此研磨过程产生的应力并不会直接作用在半导体芯片10上，能够避免半导体芯片10的开裂和芯片封装结构的分层，提高产品良率和产率。在设有辅助芯片20的情况下，也不是直接研磨至所述辅助芯片20上，因此研磨过程产生的应力也不会直接作用在辅助芯片20上，能够避免辅助芯片20的开裂和芯片封装结构的分层。Referring to FIG. 7 , step S22 is performed to grind away part of the thickness of the plastic sealing material layer 30 to form a plastic sealing layer 301 . The distance between the surface of the plastic sealing layer 301 away from the front surface 10a of the semiconductor chip and the back surface of the semiconductor chip is a set value. That is, the overall thickness of the plastic sealing layer 301 is still larger than the semiconductor chip 10 . In the case where an auxiliary chip 20 is provided in this embodiment, the overall thickness of the plastic sealing layer 301 needs to be larger than the auxiliary chip 20 . Since the backside of the polished semiconductor chip 10 in this embodiment is also provided with a plastic sealing layer of a certain thickness and is not directly ground to the backside of the semiconductor chip 10 , the stress generated during the polishing process will not directly act on the semiconductor chip 10 , can avoid cracking of the semiconductor chip 10 and delamination of the chip packaging structure, and improve product yield and productivity. In the case where the auxiliary chip 20 is provided, it is not ground directly onto the auxiliary chip 20 . Therefore, the stress generated during the grinding process will not directly act on the auxiliary chip 20 , which can avoid cracking of the auxiliary chip 20 and the chip packaging structure. of layering.
在形成塑封层301之后，将塑封后的结构翻转，并去除所述载板。After the molding layer 301 is formed, the molded structure is turned over, and the carrier board is removed.
参阅图8，执行步骤S3，形成第一再布线结构40于所述半导体芯片的正面10a和所述辅助芯片的正面20a。所述第一再布线结构40包括第一导电层和第二导电层，其中，所述第一导电层包括多个第一导电迹线402和多个第一导电插塞401，所述第二导电层包括多个导电凸块404和多个第二导电插塞403。Referring to FIG. 8 , step S3 is performed to form a first rewiring structure 40 on the front surface 10 a of the semiconductor chip and the front surface 20 a of the auxiliary chip. The first redistribution structure 40 includes a first conductive layer and a second conductive layer, wherein the first conductive layer includes a plurality of first conductive traces 402 and a plurality of first conductive plugs 401 , and the second conductive layer The conductive layer includes a plurality of conductive bumps 404 and a plurality of second conductive plugs 403 .
所述第一再布线结构40的形成方法包括：The method of forming the first rewiring structure 40 includes:
步骤S31：形成多个间隔排布的第一导电迹线402于所述半导体芯片的正面10a和所述辅助芯片的正面20a上，并形成第一导电插塞401于所述第三开口内，所述辅助芯片的正面20a通过所述第一导电迹线402和所述第一导电插塞401与所述金属焊垫101电连接；Step S31: Form a plurality of spaced-apart first conductive traces 402 on the front surface 10a of the semiconductor chip and the front surface 20a of the auxiliary chip, and form first conductive plugs 401 in the third opening, The front side 20a of the auxiliary chip is electrically connected to the metal pad 101 through the first conductive trace 402 and the first conductive plug 401;
步骤S32：形成第一介电层50于所述第一导电迹线402上，并形成多个露出所述第一导电迹线402的第二开口(图中未标出)于所述第一介电层50上；Step S32: Form a first dielectric layer 50 on the first conductive traces 402, and form a plurality of second openings (not shown in the figure) exposing the first conductive traces 402 on the first conductive traces 402. on the dielectric layer 50;
步骤S33：形成多个间隔排布的导电凸块404于所述第一介电层50远离所述半导体芯片10的一侧，并形成第二导电插塞403于第二开口内，每个所述导电凸块404通过 至少一个所述第二导电插塞403与所述第一导电迹线402电连接。Step S33: Form a plurality of conductive bumps 404 arranged at intervals on a side of the first dielectric layer 50 away from the semiconductor chip 10, and form a second conductive plug 403 in the second opening. The conductive bumps 404 pass At least one of the second conductive plugs 403 is electrically connected to the first conductive trace 402 .
执行步骤S31，形成第一导电迹线402和第一导电插塞401。在本实施例中，所述保护层102的第三开口中形成有第一导电插塞401，第一导电插塞401分别与金属焊垫101和第一导电迹线402直接接触，所述第一导电迹线402通过第一导电插塞401与金属焊垫101电连接。在设有辅助芯片20的情况下，所述第一导电迹线402还直接与所述辅助芯片20的正面接触，且所述辅助芯片20的正面通过所述第一导电迹线402可以与至少一个所述金属焊垫101电连接。Step S31 is executed to form the first conductive trace 402 and the first conductive plug 401 . In this embodiment, a first conductive plug 401 is formed in the third opening of the protective layer 102. The first conductive plug 401 is in direct contact with the metal pad 101 and the first conductive trace 402 respectively. A conductive trace 402 is electrically connected to the metal pad 101 through the first conductive plug 401 . In the case where the auxiliary chip 20 is provided, the first conductive trace 402 is also in direct contact with the front surface of the auxiliary chip 20 , and the front surface of the auxiliary chip 20 can be connected to at least one through the first conductive trace 402 One of the metal pads 101 is electrically connected.
所述第一导电插塞401和第一导电迹线402可采用电解电镀、无电极电镀等方式形成。进一步的，所述第一导电插塞401与所述第一导电迹线402可在同一工艺步骤中形成，如此有助于简化封装工艺。所述第一导电插塞401和第一导电迹线402的材料可以是金属材料，例如金属铜。The first conductive plug 401 and the first conductive trace 402 can be formed by electrolytic plating, electrodeless plating, or other methods. Furthermore, the first conductive plug 401 and the first conductive trace 402 can be formed in the same process step, which helps to simplify the packaging process. The first conductive plug 401 and the first conductive trace 402 may be made of metal material, such as metal copper.
执行步骤S32，形成第一介电层50，并在所述第一介电层50上形成多个第二开口。所述第一介电层50覆盖所述第一导电迹线402远离所述半导体芯片10一侧的表面，除此之外，所述第一介电层50还会覆盖露出的塑封层301。所述第一介电层50的材料优选为ABF(Ajinomoto Buildup Film，味之素堆积膜)、PID(Photosensitive Insulation Material，光敏绝缘材料)或其他绝缘膜中的至少一种，但不限于此。所述第二开口的形成方法优选为镭射方法或者显影方法，但不限于此。Step S32 is performed to form a first dielectric layer 50 and form a plurality of second openings on the first dielectric layer 50 . The first dielectric layer 50 covers the surface of the first conductive trace 402 away from the semiconductor chip 10 . In addition, the first dielectric layer 50 also covers the exposed plastic encapsulation layer 301 . The material of the first dielectric layer 50 is preferably at least one of ABF (Ajinomoto Buildup Film), PID (Photosensitive Insulation Material) or other insulating films, but is not limited thereto. The formation method of the second opening is preferably a laser method or a development method, but is not limited thereto.
执行步骤S33，形成导电凸块404和第二导电插塞403。在本实施例中，所述第一介电层50的第二开口中形成有所述第二导电插塞403，所述第二导电插塞403分别与所述导电凸块404和第一导电迹线402直接接触，所述导电凸块404通过所述第二导电插塞403与第一导电迹线402电连接。Step S33 is executed to form conductive bumps 404 and second conductive plugs 403 . In this embodiment, the second conductive plug 403 is formed in the second opening of the first dielectric layer 50 , and the second conductive plug 403 is connected to the conductive bump 404 and the first conductive bump respectively. The traces 402 are in direct contact, and the conductive bumps 404 are electrically connected to the first conductive traces 402 through the second conductive plugs 403 .
所述导电凸块404和第二导电插塞403可采用电解电镀、无电极电镀等方式形成。进一步的，所述第二导电插塞403与所述导电凸块404可在同一工艺步骤中形成，如此有助于简化封装工艺。所述导电凸块404和第二导电插塞403的材料可以是金属材料，例如金属铜。The conductive bumps 404 and the second conductive plugs 403 can be formed by electrolytic plating, electrodeless plating, or other methods. Furthermore, the second conductive plug 403 and the conductive bump 404 can be formed in the same process step, which helps to simplify the packaging process. The conductive bump 404 and the second conductive plug 403 may be made of metal material, such as metal copper.
在执行步骤S3之后，所述芯片封装结构的制备方法还包括形成金属锡层60，所述金属锡层60覆盖所述导电凸块404侧面和远离所述半导体芯片10一侧的表面。所述金属锡层60的材料优选为金属锡，但不限于此。After step S3 is performed, the method for preparing the chip packaging structure further includes forming a metal tin layer 60 that covers the side of the conductive bump 404 and the surface on the side away from the semiconductor chip 10 . The material of the metal tin layer 60 is preferably metal tin, but is not limited thereto.
参阅图9，执行步骤S4，在所述塑封层301上形成多个第一开口3011。所述第一开 口3011从所述塑封层301远离所述半导体芯片的正面10a一侧的表面延伸至所述半导体芯片10的背面或者所述辅助芯片10的背面。所述半导体芯片的背面为衬底，因此所述第一开口3011可以露出所述半导体芯片的衬底。所述第一开口3011的形成方法优选为镭射方法或者显影方法，但不限于此。Referring to FIG. 9 , step S4 is performed to form a plurality of first openings 3011 on the plastic sealing layer 301 . The first opening The opening 3011 extends from the surface of the plastic sealing layer 301 away from the front surface 10 a of the semiconductor chip to the back surface of the semiconductor chip 10 or the back surface of the auxiliary chip 10 . The back side of the semiconductor chip is a substrate, so the first opening 3011 can expose the substrate of the semiconductor chip. The formation method of the first opening 3011 is preferably a laser method or a development method, but is not limited thereto.
参阅图10，执行步骤S5，形成第二再布线结构70于所述塑封层301远离所述半导体芯片的正面10a的一侧，且所述第二再布线结构70还填满所述第一开口。所述第二再布线结构70包括位于所述塑封层301远离所述半导体芯片的正面10a的一侧的第三导电迹线702和设置在所述第一开口内第三导电插塞701。Referring to FIG. 10 , step S5 is performed to form a second rewiring structure 70 on the side of the plastic encapsulation layer 301 away from the front surface 10 a of the semiconductor chip, and the second rewiring structure 70 also fills the first opening. . The second redistribution structure 70 includes a third conductive trace 702 located on a side of the plastic encapsulation layer 301 away from the front surface 10 a of the semiconductor chip and a third conductive plug 701 disposed in the first opening.
在本实施例中，所述塑封层301的第一开口3011中形成有所述第三导电插塞701，所述第三导电插塞701分别与所述第三导电迹线702和半导体芯片的背面直接接触，所述第三导电迹线702通过所述第三导电插塞701与半导体芯片的背面电连接。In this embodiment, the third conductive plug 701 is formed in the first opening 3011 of the plastic sealing layer 301, and the third conductive plug 701 is connected to the third conductive trace 702 and the semiconductor chip respectively. The back surface is in direct contact, and the third conductive trace 702 is electrically connected to the back surface of the semiconductor chip through the third conductive plug 701 .
所述第三导电迹线702和第三导电插塞701可采用电解电镀、无电极电镀等方式形成。进一步的，所述第三导电插塞701与所述第三导电迹线702可在同一工艺步骤中形成，如此有助于简化封装工艺。所述第三导电迹线702和第三导电插塞701的材料可以是金属材料，例如金属铜。The third conductive trace 702 and the third conductive plug 701 can be formed by electrolytic plating, electrodeless plating, or other methods. Furthermore, the third conductive plug 701 and the third conductive trace 702 can be formed in the same process step, which helps to simplify the packaging process. The material of the third conductive trace 702 and the third conductive plug 701 may be a metal material, such as metal copper.
所述形成第二再布线结构70之后，所述步骤S5还包括：形成覆盖所述第二再布线结构70的第二介电层80。所述第二介电层80的材料可以是塑封膜、PI、PBO、有机聚合物膜、有机聚合物复合材料或者其他具有类似特性的材料。在一些实施例中，所述第二介电层80中还可以加入有机或无机的填料。After forming the second redistribution structure 70 , step S5 further includes forming a second dielectric layer 80 covering the second redistribution structure 70 . The material of the second dielectric layer 80 may be a plastic film, PI, PBO, organic polymer film, organic polymer composite material or other materials with similar properties. In some embodiments, organic or inorganic fillers may be added to the second dielectric layer 80 .
本实施例提供的芯片封装结构的制备方法，在研磨作业时，半导体芯片的背面和辅助芯片的背面上保留一定厚度的塑封层，后续通过打孔、填孔、再布线的方式连接衬底与源极，代替现有的研磨露硅和直接再布线的方法。即本申请取消了研磨露硅工艺，后续使用打孔、填孔再布线的方式实现衬底与源极连接，可以避免研磨作业时应力过大导致的半导体芯片和辅助芯片的开裂，还可以避免芯片封装结构的分层，因此通过本实施例提供的芯片封装结构的制备方法获得的芯片封装结构无分层和开裂问题。In the preparation method of the chip packaging structure provided by this embodiment, during the grinding operation, a certain thickness of the plastic sealing layer is retained on the back side of the semiconductor chip and the back side of the auxiliary chip. Subsequently, the substrate and the substrate are connected by drilling, filling, and rewiring. The source electrode replaces the existing methods of grinding exposed silicon and direct rewiring. That is to say, this application cancels the grinding and exposing silicon process, and subsequently uses the method of drilling, filling holes and wiring to realize the connection between the substrate and the source. This can avoid cracking of the semiconductor chip and auxiliary chip caused by excessive stress during the grinding operation, and can also avoid The chip packaging structure is delaminated. Therefore, the chip packaging structure obtained by the method for preparing the chip packaging structure provided in this embodiment has no problems with delamination and cracking.
此外，可以理解的是，虽然本申请已以较佳实施例披露如上，然而上述实施例并非用以限定本申请。对于任何熟悉本领域的技术人员而言，在不脱离本申请技术方案范围情况下，都可利用上述揭示的技术内容对本申请技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本申请技术方案的内容，依据本申 请的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本申请技术方案保护的范围内。In addition, it can be understood that although the present application has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present application. For any person familiar with the art, without departing from the scope of the technical solution of the present application, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present application, or modify it into equivalent changes. Example. Therefore, any content that does not deviate from the technical solution of this application shall be Any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the application still fall within the protection scope of the technical solution of the present application.
而且还应该理解的是，本申请并不限于此处描述的特定的方法、化合物、材料、制造技术、用法和应用，它们可以变化。还应该理解的是，此处描述的术语仅仅用来描述特定实施例，而不是用来限制本申请的范围。必须注意的是，此处的以及所附权利要求中使用的单数形式“一个”、“一种”以及“该”包括复数基准，除非上下文明确表示相反意思。因此，例如，对“一个步骤”引述意味着对一个或多个步骤的引述，并且可能包括次级步骤。应该以最广义的含义来理解使用的所有连词。因此，词语“或”应该被理解为具有逻辑“或”的定义，而不是逻辑“异或”的定义，除非上下文明确表示相反意思。此处描述的结构将被理解为还引述该结构的功能等效物。可被解释为近似的语言应该被那样理解，除非上下文明确表示相反意思。 Furthermore, it is to be understood that this application is not limited to the particular methods, compounds, materials, manufacturing techniques, uses and applications described herein, as they may vary. It should also be understood that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of the application. It must be noted that, as used herein and in the appended claims, the singular forms "a,""an," and "the" include plural referents unless the context clearly dictates a contrary meaning. Thus, for example, a reference to "a step" means a reference to one or more steps, and may include secondary steps. All conjunctions used should be understood in their broadest sense. Accordingly, the word "or" should be understood to have the definition of a logical "or" and not a logical "exclusive-or" unless the context clearly indicates the contrary. Structures described herein will be understood to also recite functional equivalents of that structure. Language that may be construed as approximate should be construed as such unless the context clearly indicates a contrary meaning.

Claims (13)

  1. 一种芯片封装结构，其特征在于，包括：A chip packaging structure, which is characterized by including:
    半导体芯片以及与所述半导体芯片并置的辅助芯片，所述半导体芯片的正面设有多个金属焊垫，且所述辅助芯片的正面与所述半导体芯片的正面齐平；A semiconductor chip and an auxiliary chip juxtaposed with the semiconductor chip, the front side of the semiconductor chip is provided with a plurality of metal bonding pads, and the front side of the auxiliary chip is flush with the front side of the semiconductor chip;
    塑封层，覆盖所述半导体芯片的背面和侧面，并延伸覆盖所述辅助芯片的背面和侧面，所述塑封层上设有多个分别露出所述半导体芯片的背面和辅助芯片的背面的第一开口；A plastic sealing layer covers the back and side surfaces of the semiconductor chip and extends to cover the back and side surfaces of the auxiliary chip. The plastic seal layer is provided with a plurality of first holes respectively exposing the back surface of the semiconductor chip and the back surface of the auxiliary chip. to open one's mouth;
    第一再布线结构，覆盖所述金属焊垫，并延伸覆盖所述辅助芯片的正面，以实现所述辅助芯片的正面与所述金属焊垫电连接；The first rewiring structure covers the metal bonding pad and extends to cover the front surface of the auxiliary chip to achieve electrical connection between the front surface of the auxiliary chip and the metal bonding pad;
    第二再布线结构，覆盖部分所述塑封层远离所述半导体芯片的正面一侧的表面，并填充所述第一开口，以实现所述辅助芯片的背面与所述半导体芯片的背面电连接。The second rewiring structure covers part of the surface of the plastic layer away from the front side of the semiconductor chip and fills the first opening to achieve electrical connection between the back side of the auxiliary chip and the back side of the semiconductor chip.
  2. 如权利要求1所述的芯片封装结构，其特征在于，所述半导体芯片的背面上的塑封层厚度为设定值，所述设定值的范围为5μm～50μm。The chip packaging structure of claim 1, wherein the thickness of the plastic sealing layer on the back side of the semiconductor chip is a set value, and the set value ranges from 5 μm to 50 μm.
  3. 如权利要求1所述的芯片封装结构，其特征在于，所述辅助芯片包括辅助衬底，所述辅助衬底为材质为硅的衬底、材质为锗的衬底、材质为锗硅的衬底和材质为碳化硅的衬底中的一种。The chip packaging structure of claim 1, wherein the auxiliary chip includes an auxiliary substrate, and the auxiliary substrate is a substrate made of silicon, a substrate made of germanium, or a substrate made of silicon germanium. The base and material are one of the substrates made of silicon carbide.
  4. 如权利要求3所述的芯片封装结构，其特征在于，所述辅助衬底中的掺杂离子选自于磷、硼和砷中的一种，且所述辅助衬底的掺杂浓度为1016cm-3～1022cm-3。The chip packaging structure of claim 3, wherein the doping ions in the auxiliary substrate are selected from one of phosphorus, boron and arsenic, and the doping concentration of the auxiliary substrate is 10 16 cm -3 ~ 10 22 cm -3 .
  5. 如权利要求1所述的芯片封装结构，其特征在于，所述辅助芯片为低电阻辅助芯片，其电阻值<0.1mΩ。The chip packaging structure of claim 1, wherein the auxiliary chip is a low-resistance auxiliary chip with a resistance value <0.1mΩ.
  6. 如权利要求1所述的芯片封装结构，其特征在于，所述芯片封装结构包括一个或者多个所述辅助芯片。The chip packaging structure of claim 1, wherein the chip packaging structure includes one or more auxiliary chips.
  7. 如权利要求1所述的芯片封装结构，其特征在于，所述半导体芯片的正面还设有保护层，且所述保护层上设有多个露出所述金属焊垫的第三开口。The chip packaging structure of claim 1, wherein a protective layer is provided on the front side of the semiconductor chip, and a plurality of third openings are provided on the protective layer to expose the metal pads.
  8. 如权利要求7所述的芯片封装结构，其特征在于，所述芯片封装结构还包括第一介电层，所述第一再布线结构包括第一导电层和第二导电层，其中，The chip packaging structure of claim 7, wherein the chip packaging structure further includes a first dielectric layer, and the first rewiring structure includes a first conductive layer and a second conductive layer, wherein,
    所述第一导电层包括多个间隔排布在所述半导体芯片的正面和所述辅助芯片的正面上的第一导电迹线和设置在所述第三开口内的第一导电插塞，所述辅助芯片的正面通过所述第一导电迹线和所述第一导电插塞与所述金属焊垫电连接；The first conductive layer includes a plurality of first conductive traces arranged at intervals on the front surface of the semiconductor chip and the front surface of the auxiliary chip and first conductive plugs disposed in the third opening, so The front side of the auxiliary chip is electrically connected to the metal pad through the first conductive trace and the first conductive plug;
    所述第一介电层覆盖所述第一导电迹线，且所述第一介电层上设有多个露出所述第一导电迹线的第二开口； The first dielectric layer covers the first conductive traces, and the first dielectric layer is provided with a plurality of second openings exposing the first conductive traces;
    所述第二导电层包括多个间隔排布在所述第一介电层上的导电凸块和设置在所述第二开口内的第二导电插塞，所述导电凸块通过所述第二导电插塞与所述第一导电迹线电连接。The second conductive layer includes a plurality of conductive bumps arranged at intervals on the first dielectric layer and a second conductive plug disposed in the second opening. The conductive bumps pass through the first dielectric layer. Two conductive plugs are electrically connected to the first conductive trace.
  9. 如权利要求8所述的芯片封装结构，其特征在于，所述芯片封装结构还包括金属锡层，其覆盖所述导电凸块的侧面和远离所述半导体芯片一侧的表面。The chip packaging structure of claim 8, further comprising a metal tin layer covering the side of the conductive bump and the surface on the side away from the semiconductor chip.
  10. 如权利要求1所述的芯片封装结构，其特征在于，所述第二再布线结构包括位于所述塑封层远离所述半导体芯片的正面的一侧的第三导电迹线和设置在所述第一开口内第三导电插塞，所述辅助芯片的背面通过所述第三导电迹线和所述第三导电插塞与所述半导体芯片的背面电连接。The chip packaging structure of claim 1, wherein the second rewiring structure includes a third conductive trace located on a side of the plastic encapsulation layer away from the front surface of the semiconductor chip and a third conductive trace disposed on the first side of the plastic packaging layer. There is a third conductive plug in an opening, and the back side of the auxiliary chip is electrically connected to the back side of the semiconductor chip through the third conductive trace and the third conductive plug.
  11. 如权利要求10所述的芯片封装结构，其特征在于，所述芯片封装结构还包括第二介电层，其覆盖所述第三导电迹线的侧面和远离所述半导体芯片一侧的表面。The chip packaging structure of claim 10, further comprising a second dielectric layer covering the side of the third conductive trace and the surface away from the side of the semiconductor chip.
  12. 如权利要求1所述的芯片封装结构，其特征在于，所述半导体芯片为氮化镓芯片。The chip packaging structure of claim 1, wherein the semiconductor chip is a gallium nitride chip.
  13. 一种芯片封装结构的制备方法，其特征在于，包括：A method for preparing a chip packaging structure, which is characterized by including:
    提供半导体芯片、辅助芯片和载板，并将所述半导体芯片和辅助芯片贴装至所述载板上，所述半导体芯片的正面和所述辅助芯片的正面朝向所述载板，所述半导体芯片的正面设有多个金属焊垫；Provide a semiconductor chip, an auxiliary chip and a carrier board, and mount the semiconductor chip and the auxiliary chip on the carrier board, with the front surface of the semiconductor chip and the front surface of the auxiliary chip facing the carrier board, and the semiconductor chip and the auxiliary chip are mounted on the carrier board. There are multiple metal pads on the front side of the chip;
    形成塑封层，所述塑封层覆盖所述半导体芯片的侧面和背面，并延伸覆盖所述辅助芯片的侧面和背面；Forming a plastic sealing layer, the plastic sealing layer covers the side and back of the semiconductor chip, and extends to cover the side and back of the auxiliary chip;
    形成第一再布线结构于所述半导体芯片的正面和所述辅助芯片的正面，且所述第一再布线结构与所述金属焊垫电连接；Forming a first rewiring structure on the front surface of the semiconductor chip and the front surface of the auxiliary chip, and the first rewiring structure is electrically connected to the metal pad;
    形成多个分别露出所述半导体芯片的背面和所述辅助芯片的背面的第一开口于所述塑封层上；Forming a plurality of first openings on the plastic sealing layer respectively exposing the back surface of the semiconductor chip and the back surface of the auxiliary chip;
    形成第二再布线结构于所述塑封层远离所述半导体芯片的正面的一侧，且所述第二再布线结构还填满所述第一开口。 A second rewiring structure is formed on a side of the plastic encapsulation layer away from the front surface of the semiconductor chip, and the second rewiring structure also fills the first opening.
PCT/CN2023/107955 2022-07-26 2023-07-18 Chip packaging structure and preparation method therefor WO2024022174A1 (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018006654A (en) * 2016-07-06 2018-01-11 株式会社デンソー Electronic device
CN111341681A (en) * 2020-04-02 2020-06-26 广东佛智芯微电子技术研究有限公司 Low-thickness 3D stacked packaging structure and preparation method thereof
CN111599696A (en) * 2020-05-28 2020-08-28 矽磐微电子(重庆)有限公司 Semiconductor module packaging method and semiconductor module
CN111739867A (en) * 2020-07-31 2020-10-02 矽磐微电子(重庆)有限公司 Semiconductor packaging method and semiconductor packaging structure
CN113611615A (en) * 2021-07-29 2021-11-05 矽磐微电子(重庆)有限公司 Manufacturing method of chip packaging structure
CN218548408U (en) * 2022-07-26 2023-02-28 矽磐微电子(重庆)有限公司 Chip packaging structure

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018006654A (en) * 2016-07-06 2018-01-11 株式会社デンソー Electronic device
CN111341681A (en) * 2020-04-02 2020-06-26 广东佛智芯微电子技术研究有限公司 Low-thickness 3D stacked packaging structure and preparation method thereof
CN111599696A (en) * 2020-05-28 2020-08-28 矽磐微电子(重庆)有限公司 Semiconductor module packaging method and semiconductor module
CN111739867A (en) * 2020-07-31 2020-10-02 矽磐微电子(重庆)有限公司 Semiconductor packaging method and semiconductor packaging structure
CN113611615A (en) * 2021-07-29 2021-11-05 矽磐微电子(重庆)有限公司 Manufacturing method of chip packaging structure
CN218548408U (en) * 2022-07-26 2023-02-28 矽磐微电子(重庆)有限公司 Chip packaging structure

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