WO2024022174A1 - Structure d'encapsulation de puce et son procédé de préparation - Google Patents

Structure d'encapsulation de puce et son procédé de préparation Download PDF

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Publication number
WO2024022174A1
WO2024022174A1 PCT/CN2023/107955 CN2023107955W WO2024022174A1 WO 2024022174 A1 WO2024022174 A1 WO 2024022174A1 CN 2023107955 W CN2023107955 W CN 2023107955W WO 2024022174 A1 WO2024022174 A1 WO 2024022174A1
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WIPO (PCT)
Prior art keywords
chip
auxiliary
semiconductor chip
conductive
layer
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Application number
PCT/CN2023/107955
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English (en)
Chinese (zh)
Inventor
杨磊
霍炎
Original Assignee
矽磐微电子(重庆)有限公司
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Publication of WO2024022174A1 publication Critical patent/WO2024022174A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to a chip packaging structure and a preparation method thereof.
  • the rewiring structure of the existing chip packaging structure is directly in contact with the substrate on the back side of the gallium nitride chip, and the existing process generally
  • the substrate is connected to the front source by mounting a low-resistance auxiliary chip, grinding to expose the silicon, and rewiring.
  • the stress during grinding to expose the silicon will cause cracks in the gallium nitride chip and low-resistance auxiliary chip and delamination of the packaging structure, which will lead to the scrapping of a large number of products.
  • This application provides a chip packaging structure, including:
  • a semiconductor chip and an auxiliary chip juxtaposed with the semiconductor chip the front side of the semiconductor chip is provided with a plurality of metal bonding pads, and the front side of the auxiliary chip is flush with the front side of the semiconductor chip;
  • a plastic sealing layer covers the back and side surfaces of the semiconductor chip and extends to cover the back and side surfaces of the auxiliary chip.
  • the plastic sealing layer is provided with a plurality of third holes respectively exposing the back surface of the semiconductor chip and the back surface of the auxiliary chip. an opening;
  • the first rewiring structure covers the metal bonding pad and extends to cover the front surface of the auxiliary chip to achieve electrical connection between the front surface of the auxiliary chip and the metal bonding pad;
  • the second rewiring structure covers part of the surface of the plastic layer away from the front side of the semiconductor chip and fills the first opening to achieve electrical connection between the back side of the auxiliary chip and the back side of the semiconductor chip.
  • the thickness of the plastic sealing layer on the back side of the semiconductor chip is a set value, and the set value ranges from 5 ⁇ m to 50 ⁇ m.
  • the auxiliary chip includes an auxiliary substrate, and the auxiliary substrate is a substrate made of silicon, a substrate made of germanium, a substrate made of germanium silicon and One of the substrates made of silicon carbide;
  • the doping ions in the auxiliary substrate are selected from one of phosphorus, boron and arsenic, and the doping concentration of the auxiliary substrate is 10 16 cm -3 to 10 22 cm -3 .
  • the auxiliary chip is a low-resistance auxiliary chip with a resistance value ⁇ 0.1m ⁇ .
  • the chip packaging structure includes one or more auxiliary chips.
  • a protective layer is further provided on the front side of the semiconductor chip, and a plurality of third openings exposing the metal pads are provided on the protective layer.
  • the chip packaging structure further includes a first dielectric layer, and the first rewiring structure includes a first conductive layer and a second conductive layer, wherein,
  • the first conductive layer includes a plurality of first conductive traces arranged at intervals on the front surface of the semiconductor chip and the front surface of the auxiliary chip and a first conductive plug disposed in the third opening, so The front side of the auxiliary chip is electrically connected to the metal pad through the first conductive trace and the first conductive plug;
  • the first dielectric layer covers the first conductive traces, and the first dielectric layer is provided with a plurality of second openings exposing the first conductive traces;
  • the second conductive layer includes a plurality of conductive bumps arranged at intervals on the first dielectric layer and a second conductive plug disposed in the second opening.
  • the conductive bumps pass through the first dielectric layer.
  • Two conductive plugs are electrically connected to the first conductive trace.
  • the chip packaging structure further includes a metal tin layer covering the sides of the conductive bumps and the surface on the side away from the semiconductor chip.
  • the second rewiring structure includes a third conductive trace located on a side of the plastic encapsulation layer away from the front surface of the semiconductor chip and a third conductive trace disposed in the first opening.
  • the back side of the auxiliary chip is electrically connected to the back side of the semiconductor chip through the third conductive trace and the third conductive plug.
  • the chip packaging structure further includes a second dielectric layer covering the side of the third conductive trace and the surface on the side away from the semiconductor chip.
  • the semiconductor chip is a gallium nitride chip.
  • This application also provides a method for preparing a chip packaging structure, including:
  • a semiconductor chip, an auxiliary chip and a carrier board and mount the semiconductor chip and the auxiliary chip on the carrier board, with the front surface of the semiconductor chip and the front surface of the auxiliary chip facing the carrier board, and the semiconductor chip and the auxiliary chip are mounted on the carrier board.
  • the plastic sealing layer covers the side and back of the semiconductor chip, and extends to cover the side and back of the auxiliary chip;
  • first rewiring structure Forming a first rewiring structure on the front surface of the semiconductor chip and the front surface of the auxiliary chip, and the first rewiring structure is electrically connected to the metal pad;
  • a second rewiring structure is formed on a side of the plastic encapsulation layer away from the front surface of the semiconductor chip, and the second rewiring structure also fills the first opening.
  • Figures 1 to 4 are structural schematic diagrams corresponding to each step in a method for preparing a gallium nitride chip board-level packaging structure
  • Figure 5 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application.
  • 6 to 10 are structural schematic diagrams corresponding to each step in the method for preparing a chip packaging structure according to an embodiment of the present application
  • 01-GaN chip 011-metal pad, 012-protective layer, 02-low resistance auxiliary chip, 03-plastic sealing layer, 04-first rewiring structure, 041-first conductive plug, 042-first Conductive traces, 043-second conductive plug, 044-conductive bump, 05-first dielectric layer, 06-metal tin layer, 07-second rewiring structure, 08-second dielectric layer;
  • 10-semiconductor chip 10a-front side of semiconductor chip, 101-metal pad, 102-protective layer, 20-auxiliary chip, 20a-front side of auxiliary chip, 30-plastic sealing material layer, 301-plastic sealing layer, 3011-first Opening, 40-first redistribution structure, 401-first conductive plug, 402-first conductive trace, 403-second conductive plug, 404-conductive bump, 50-first dielectric layer, 60- Metal tin layer, 70-second rewiring structure, 701-third conductive plug, 702-third conductive trace, 80-second dielectric layer.
  • a method for preparing a gallium nitride chip board-level packaging structure realizes the connection between the substrate and the front source by mounting a low-resistance auxiliary chip, grinding to expose the silicon, and rewiring. Please refer to Figures 1 to 4 for details.
  • the preparation method of the gallium nitride chip board-level packaging structure includes:
  • the gallium nitride chip 01 and the low-resistance auxiliary chip 02 are mounted on a carrier board (not shown in the figure).
  • the front side of the gallium nitride chip 01 is provided with a protective layer 012 and a plurality of metal pads 011.
  • the protective layer 012 is provided with a plurality of first openings that expose portions of the metal pads 011;
  • a first rewiring structure 04, a first dielectric layer 05, and a metal tin layer 06 are formed.
  • the first rewiring structure 04 includes a plurality of first conductive plugs 041, first conductive traces 042, and second conductive plugs.
  • the first conductive plug 041 is located in the first opening;
  • the first conductive trace 042 is located on the front surface of the gallium nitride chip 01 and the front surface of the auxiliary chip 02, so The front side of the auxiliary chip 02 is electrically connected to the metal pad 011 through the first conductive trace 042 and the first conductive plug 041;
  • the first dielectric layer 05 covers the first conductive trace 042,
  • the first dielectric layer 05 is provided with a plurality of second openings exposing portions of the first conductive traces 042;
  • the second conductive plugs 043 are located in the second openings;
  • the conductive bumps 044 is located on the side of the first dielectric layer 05 away from the gallium nitride chip 01 and is electrically connected to the first conductive trace 042 through the second conductive plug 043;
  • the metal tin layer 06 Cover the conductive bumps 044;
  • a second rewiring structure 07 and a second dielectric layer 08 are formed.
  • the second rewiring structure 07 is located on the back side of the gallium nitride chip 01 and the auxiliary chip 02.
  • the second dielectric layer 08 covers the second dielectric layer 08.
  • the stress generated by grinding will directly act on the auxiliary chip 02 and the gallium nitride chip 01, which may easily lead to cracking of the gallium nitride chip 01 and the auxiliary chip 02 and delamination of the chip packaging structure. , which in turn leads to a large number of products being scrapped, and the final product defect rate is approximately 30%.
  • this application provides a new type of chip packaging structure, which is on the back side of the semiconductor chip and auxiliary There is a certain thickness of the plastic sealing layer on the back of the chip, which does not need to be ground to the back of the semiconductor chip and auxiliary chip, and there will be no stress acting directly on the semiconductor chip and auxiliary chip, which can avoid cracking and cracking of the semiconductor chip and auxiliary chip.
  • the delamination problem of the chip packaging structure can avoid a large number of product scraps, thereby improving product yield and productivity.
  • the chip packaging structure includes:
  • the semiconductor chip 10 and the auxiliary chip 20 juxtaposed with the semiconductor chip 10 are provided with a plurality of metal bonding pads 101 on the front side of the semiconductor chip 10, and the front side of the auxiliary chip 20 is flush with the front side of the semiconductor chip 10. flat;
  • the plastic sealing layer 301 covers the back and side surfaces of the semiconductor chip 10 and extends to cover the back and side surfaces of the auxiliary chip 20 .
  • the plastic sealing layer 301 is provided with a plurality of exposed back surfaces and auxiliary chips of the semiconductor chip 10 . the first opening on the back of 20;
  • the first rewiring structure 40 covers the metal bonding pad 101 and extends to cover the front surface of the auxiliary chip 20 to achieve electrical connection between the front surface of the auxiliary chip 20 and the metal bonding pad 101;
  • the second rewiring structure 70 covers part of the surface of the plastic encapsulation layer 301 away from the front side of the semiconductor chip 10 and fills the first opening to realize the connection between the back side of the auxiliary chip 20 and the semiconductor chip 10 electrical connections on the back.
  • the semiconductor chip 10 is preferably a gallium nitride (GaN) chip, but is not limited thereto.
  • the semiconductor chip 10 can be obtained by cutting a wafer.
  • the wafer has an active surface, and the active surface of the wafer is provided with a metal bonding pad 101 .
  • the wafer can be cut by mechanical cutting or laser cutting.
  • the metal pad 101 of the semiconductor chip 10 serves as a source, which is composed of a conductive electrode led from the internal circuit of the chip to the surface of the chip.
  • a plurality of metal bonding pads 101 may be provided on the front surface of the semiconductor chip 10 .
  • the metal pad 101 is used to lead out the conductive electrode of the semiconductor chip 10 .
  • the back side of the semiconductor chip 10 is the substrate of the semiconductor chip 10 , that is, the semiconductor substrate.
  • a protective layer 102 is also provided on the front side of the semiconductor chip 10.
  • the protective layer 102 will cover part of the metal bonding pad 101. That is, a plurality of holes are formed on the protective layer 102 to expose part of the surface of the metal bonding pad. The third opening.
  • the material of the protective layer 102 may be a plastic film, PI (Polyimide, polyimide), PBO (Polybenzoxazole, polybenzoxazole), organic polymer film, organic polymer composite material or other materials with similar characteristics. .
  • organic or inorganic fillers may be added to the protective layer 102 .
  • the chip packaging structure may further include an auxiliary chip 20 juxtaposed with the semiconductor chip 10 .
  • the auxiliary The chip 20 is mainly used for conduction, and can form a loop with the semiconductor chip 10 after forming the first rewiring structure and the second rewiring structure.
  • the semiconductor chip is preferably a Gallium Nitride (GaN) chip
  • the electrons in the GaN chip may fall into the substrate due to the poor insulation effect of the insulating layer above the substrate during operation, thus causing leakage.
  • the additional auxiliary chip 20 can form a loop with the semiconductor chip 10 to allow the electrons of the substrate to return to the source, thereby avoiding leakage.
  • the number of the auxiliary chip 20 is one, thereby forming a current-carrying channel. Alternatively, in other embodiments, the number of the auxiliary chips 20 may also be multiple, thereby forming multiple current-carrying channels.
  • a plurality of the auxiliary chips 20 are laterally spaced apart and are juxtaposed with the semiconductor chip 10 , wherein the gap between the semiconductor chip 10 and the auxiliary chip 20 and the plurality of auxiliary chips 20 are laterally spaced apart. The resulting gap may be filled with non-conductive material.
  • the plurality of auxiliary chips 20 may be located on the same side of the semiconductor chip 10 , or may be located on different sides of the semiconductor chip 10 .
  • the auxiliary chip 20 is preferably a low-resistance auxiliary chip, but is not limited thereto. Further, the resistance value of the low-resistance auxiliary chip is ⁇ 0.1m ⁇ .
  • the auxiliary chip 20 may only include an auxiliary substrate, that is, only include a layer of semiconductor material.
  • the impedance of the auxiliary substrate is smaller than the impedance of the semiconductor substrate.
  • the materials of the auxiliary substrate and the semiconductor substrate can be selected and/or doped so that the impedance of the auxiliary substrate is smaller than the impedance of the semiconductor substrate.
  • the materials of the auxiliary substrate and the semiconductor substrate may be the same or different.
  • the auxiliary substrate and the semiconductor substrate are made of the same material and are both silicon.
  • the auxiliary substrate and the semiconductor substrate may be made of different materials, and the materials of the auxiliary substrate and the semiconductor substrate may be selected from one of silicon, germanium, silicon germanium and silicon carbide.
  • the material of the auxiliary substrate is silicon, and the material of the semiconductor substrate is silicon carbide; or the material of the auxiliary substrate is germanium, and the material of the semiconductor substrate is silicon germanium, etc.
  • both the auxiliary substrate and the semiconductor substrate are doped with ions.
  • the doping ions in the auxiliary substrate and the doping ions in the semiconductor substrate are the same.
  • the doping ions in the auxiliary substrate and the doping ions in the semiconductor substrate are both P-type ions or both are N-type ions.
  • the doping ions in the auxiliary substrate and the doping ions in the semiconductor substrate are selected from one of phosphorus, boron and arsenic.
  • the auxiliary chip 20 is preferably a P-type highly doped chip, that is, the doping ions of the auxiliary substrate are preferably P-type ions.
  • the doping concentration of the auxiliary substrate is higher than the doping concentration of the semiconductor substrate.
  • the doping concentration of the auxiliary substrate is 10 16 cm -3 ⁇ 10 22 cm -3 and the doping concentration of the semiconductor substrate is 10 15 cm -3 ⁇ 10 19 cm -3 .
  • the doping concentration of the auxiliary substrate is 10 21 cm -3 and the doping concentration of the semiconductor substrate is 10 19 cm -3 ;
  • the doping concentration of the auxiliary substrate is 10 19 cm -3 and the doping concentration of the semiconductor substrate is 10 18 cm -3 .
  • the doping ions in the auxiliary substrate and the doping ions in the semiconductor substrate may also be different.
  • the auxiliary substrate can be used as a current-carrying channel for electrons in the semiconductor substrate.
  • the auxiliary chip 20 may include an auxiliary substrate and a semiconductor material layer located on the auxiliary substrate, that is, include multiple semiconductor material layers.
  • the arrangement of the auxiliary chip 20 only needs to satisfy that the impedance of the auxiliary chip 20 is smaller than the impedance of the semiconductor chip 10 , which will not be described in detail here.
  • the front side of the auxiliary chip 20 is preferably flush with the front side of the semiconductor chip 10
  • the back side of the auxiliary chip 20 is preferably flush with the back side of the semiconductor chip 10
  • the front side is opposite to the back side. Since the auxiliary chip 20 is used for electronic conduction, there are no special requirements for the arrangement of the front and back of the auxiliary chip 20 .
  • the back of the auxiliary chip 20 is an auxiliary substrate.
  • the front side of the auxiliary chip 20 is an auxiliary substrate.
  • the plastic encapsulation layer 301 covers the side and back of the semiconductor chip 10 and also covers the back and side of the auxiliary chip 10 .
  • the thickness of the plastic sealing layer 301 on the back surface of the semiconductor chip 10 is a set value, that is, the distance between the surface of the plastic sealing layer 301 away from the front side of the semiconductor chip 10 and the back surface of the semiconductor chip 10 is a set value.
  • the set value can range from 5 ⁇ m to 50 ⁇ m.
  • the thickness of the plastic sealing layer 301 on the back side of the auxiliary chip 20 is also a set value.
  • the plastic sealing layer 301 is provided with a plurality of first openings that expose part of the back surface of the semiconductor chip 10 and the back surface of the auxiliary chip 20 .
  • the first openings are separated from the front surface of the semiconductor chip 10 from the plastic sealing layer 301 .
  • the surface of the side extends to the back side of the semiconductor chip or the back side of the auxiliary chip 20 .
  • the first rewiring structure 40 includes a first conductive layer and a second conductive layer, and the chip packaging structure further includes a first dielectric layer 50 .
  • the first conductive layer includes a plurality of first conductive traces 402 spaced apart on the front surface of the semiconductor chip 10 and the front surface of the auxiliary chip 20 and a first conductive plug 401 disposed in the third opening. , the front side of the auxiliary chip 20 is electrically connected to the metal pad 101 through the first conductive trace 402 and the first conductive plug 401 catch.
  • the first dielectric layer 50 covers the first conductive traces 402 , and the first dielectric layer 50 is provided with a plurality of second openings exposing the first conductive traces 402 .
  • the first dielectric layer 50 may be made of plastic film, PI, PBO, organic polymer film, organic polymer composite material or other materials with similar properties. In some embodiments, organic or inorganic fillers may be added to the first dielectric layer 50 .
  • the second conductive layer includes a plurality of conductive bumps 404 spaced apart on a side of the first dielectric layer 50 away from the semiconductor chip 10 and a second conductive plug 403 disposed in the second opening, Each of the conductive bumps 404 is electrically connected to the first conductive trace 402 through at least one of the second conductive plugs 403 .
  • the chip packaging structure also includes a metal tin layer 60 for external connection to other circuits.
  • the metal tin layer 60 covers the side surface of the conductive bump 404 and the surface away from the semiconductor chip 10 .
  • the material of the metal tin layer is preferably metal tin, but is not limited thereto.
  • the second rewiring structure 70 includes a third conductive trace 702 located on a side of the plastic encapsulation layer 301 away from the front surface of the semiconductor chip 10 and a third conductive plug 701 disposed in the first opening, so The backside of the auxiliary chip 20 is electrically connected to the backside of the semiconductor chip 10 through the third conductive trace 702 and the third conductive plug 701 .
  • the chip packaging structure also includes a second dielectric layer 80 covering the second rewiring structure 70.
  • the material of the second dielectric layer 80 can be plastic film, PI, PBO, organic polymer film, organic polymer composite materials or other materials with similar properties.
  • organic or inorganic fillers may be added to the second dielectric layer 80 .
  • the method for preparing the chip packaging structure includes:
  • Step S1 Provide a semiconductor chip 10, an auxiliary chip 20 and a carrier board (not shown in the figure), and mount the semiconductor chip 10 and the auxiliary chip 20 on the carrier board.
  • the front side 10a of the semiconductor chip And the front surface 20a of the auxiliary chip faces the carrier board, and the front surface 10a of the semiconductor chip 10 is provided with a plurality of metal bonding pads 101;
  • Step S2 Form a plastic sealing layer 301 that covers the side and back of the semiconductor chip 10 and extends to cover the back and side of the auxiliary chip 20;
  • Step S3 Form a first rewiring structure 40 on the front side 10a of the semiconductor chip and the front side 20a of the auxiliary chip, and the first rewiring structure 40 is electrically connected to the metal pad 101;
  • Step S4 Form a plurality of first openings respectively exposing the back surface of the semiconductor chip and the back surface of the auxiliary chip.
  • the opening 3011 is on the plastic sealing layer 301;
  • Step S5 Form a second rewiring structure 70 on the side of the plastic encapsulation layer 301 away from the front surface 10a of the semiconductor chip, and the second rewiring structure 70 also fills the first opening 3011.
  • step S1 is performed to provide a semiconductor chip 10 .
  • a plurality of metal bonding pads 101 are provided on the front surface 10 a of the semiconductor chip 10 .
  • the front surface 10a of the semiconductor chip is also provided with a protective layer 102.
  • the protective layer 102 will cover part of the metal pads 101. That is, the protective layer 102 is formed with a plurality of partial surfaces exposing the metal pads 101.
  • the third opening (not marked in the figure).
  • the formation method of the third opening is preferably a laser method or a development method, but is not limited thereto.
  • the protective layer 102 may be made of a plastic film, PI (polyimide), PBO (polybenzoxazole), organic polymer film, organic polymer composite material, or other materials with similar properties. In some embodiments, organic or inorganic fillers may be added to the protective layer 102 .
  • the protective layer 102 is used to protect the internal circuits of the chip, and the protective layer 102 can be used to determine the size of the third opening, that is, the surface size of the exposed metal pad 101 .
  • This embodiment may also provide an auxiliary chip 20 .
  • the semiconductor chip 10 and the auxiliary chip 20 are mounted on the carrier board.
  • One semiconductor chip 10 and one auxiliary chip 20 can be mounted on the carrier board.
  • the number of semiconductor chips 10 and auxiliary chips 20 that can be mounted on the carrier board may be multiple.
  • the shape of the carrier plate may be circular, rectangular or other shapes.
  • the material of the carrier plate may include iron-nickel fixed expansion alloy, or the material of the carrier plate may also include stainless steel or polymer.
  • step S2 is performed to form the plastic sealing layer 301 .
  • the plastic encapsulation layer 301 covers the back and side surfaces of the semiconductor chip 10 and extends to cover the side and back surfaces of the auxiliary chip 20 .
  • the specific process of forming the plastic sealing layer 301 includes:
  • Step S21 Form a molding material layer 30 covering the semiconductor chip 10 and the auxiliary chip 20;
  • Step S22 Grind part of the thickness of the plastic sealing material layer 30 to form a plastic sealing layer 301.
  • step S21 is performed to form a molding material layer 30 , and the thickness of the molding material layer 30 is greater than that of the semiconductor chip 10 , and also needs to be greater than the thickness of the auxiliary chip 20 so that the molding material layer 30 will be
  • the semiconductor chip 10 and the auxiliary chip 20 are completely covered. Furthermore, the distance between the surface of the plastic sealing material layer 30 away from the front surface 10a of the semiconductor chip and the back surface of the semiconductor chip is greater than the set value, that is, the distance between the plastic sealing material layer 30 and the back surface of the semiconductor chip is greater than the set value.
  • the thickness of layer 30 is greater than the set value.
  • the range of the set value is 5 ⁇ m to 50 ⁇ m.
  • the plastic sealing material layer 30 preferably has a small shrinkage and CTE (Coefficient of Thermal Expansion, thermal expansion). coefficient), and the material needs to be able to undergo subsequent RDL (Re-Distribution Layer, rewiring layer) processing, and it also needs to have a certain acid and alkali resistance.
  • the molding material layer 30 may be polymer, resin, resin composite material or polymer composite material, etc.
  • the molding material layer 30 may be resin with fillers, where the fillers are inorganic particles.
  • the plastic sealing material layer can be formed by lamination molding, injection molding, compression molding or transfer molding.
  • step S22 is performed to grind away part of the thickness of the plastic sealing material layer 30 to form a plastic sealing layer 301 .
  • the distance between the surface of the plastic sealing layer 301 away from the front surface 10a of the semiconductor chip and the back surface of the semiconductor chip is a set value. That is, the overall thickness of the plastic sealing layer 301 is still larger than the semiconductor chip 10 .
  • the overall thickness of the plastic sealing layer 301 needs to be larger than the auxiliary chip 20 .
  • the backside of the polished semiconductor chip 10 in this embodiment is also provided with a plastic sealing layer of a certain thickness and is not directly ground to the backside of the semiconductor chip 10 , the stress generated during the polishing process will not directly act on the semiconductor chip 10 , can avoid cracking of the semiconductor chip 10 and delamination of the chip packaging structure, and improve product yield and productivity.
  • the auxiliary chip 20 is provided, it is not ground directly onto the auxiliary chip 20 . Therefore, the stress generated during the grinding process will not directly act on the auxiliary chip 20 , which can avoid cracking of the auxiliary chip 20 and the chip packaging structure. of layering.
  • the molding layer 301 is formed, the molded structure is turned over, and the carrier board is removed.
  • step S3 is performed to form a first rewiring structure 40 on the front surface 10 a of the semiconductor chip and the front surface 20 a of the auxiliary chip.
  • the first redistribution structure 40 includes a first conductive layer and a second conductive layer, wherein the first conductive layer includes a plurality of first conductive traces 402 and a plurality of first conductive plugs 401 , and the second conductive layer
  • the conductive layer includes a plurality of conductive bumps 404 and a plurality of second conductive plugs 403 .
  • the method of forming the first rewiring structure 40 includes:
  • Step S31 Form a plurality of spaced-apart first conductive traces 402 on the front surface 10a of the semiconductor chip and the front surface 20a of the auxiliary chip, and form first conductive plugs 401 in the third opening,
  • the front side 20a of the auxiliary chip is electrically connected to the metal pad 101 through the first conductive trace 402 and the first conductive plug 401;
  • Step S32 Form a first dielectric layer 50 on the first conductive traces 402, and form a plurality of second openings (not shown in the figure) exposing the first conductive traces 402 on the first conductive traces 402. on the dielectric layer 50;
  • Step S33 Form a plurality of conductive bumps 404 arranged at intervals on a side of the first dielectric layer 50 away from the semiconductor chip 10, and form a second conductive plug 403 in the second opening.
  • the conductive bumps 404 pass At least one of the second conductive plugs 403 is electrically connected to the first conductive trace 402 .
  • Step S31 is executed to form the first conductive trace 402 and the first conductive plug 401 .
  • a first conductive plug 401 is formed in the third opening of the protective layer 102.
  • the first conductive plug 401 is in direct contact with the metal pad 101 and the first conductive trace 402 respectively.
  • a conductive trace 402 is electrically connected to the metal pad 101 through the first conductive plug 401 .
  • the first conductive trace 402 is also in direct contact with the front surface of the auxiliary chip 20 , and the front surface of the auxiliary chip 20 can be connected to at least one through the first conductive trace 402
  • One of the metal pads 101 is electrically connected.
  • the first conductive plug 401 and the first conductive trace 402 can be formed by electrolytic plating, electrodeless plating, or other methods. Furthermore, the first conductive plug 401 and the first conductive trace 402 can be formed in the same process step, which helps to simplify the packaging process.
  • the first conductive plug 401 and the first conductive trace 402 may be made of metal material, such as metal copper.
  • Step S32 is performed to form a first dielectric layer 50 and form a plurality of second openings on the first dielectric layer 50 .
  • the first dielectric layer 50 covers the surface of the first conductive trace 402 away from the semiconductor chip 10 .
  • the first dielectric layer 50 also covers the exposed plastic encapsulation layer 301 .
  • the material of the first dielectric layer 50 is preferably at least one of ABF (Ajinomoto Buildup Film), PID (Photosensitive Insulation Material) or other insulating films, but is not limited thereto.
  • the formation method of the second opening is preferably a laser method or a development method, but is not limited thereto.
  • Step S33 is executed to form conductive bumps 404 and second conductive plugs 403 .
  • the second conductive plug 403 is formed in the second opening of the first dielectric layer 50 , and the second conductive plug 403 is connected to the conductive bump 404 and the first conductive bump respectively.
  • the traces 402 are in direct contact, and the conductive bumps 404 are electrically connected to the first conductive traces 402 through the second conductive plugs 403 .
  • the conductive bumps 404 and the second conductive plugs 403 can be formed by electrolytic plating, electrodeless plating, or other methods. Furthermore, the second conductive plug 403 and the conductive bump 404 can be formed in the same process step, which helps to simplify the packaging process.
  • the conductive bump 404 and the second conductive plug 403 may be made of metal material, such as metal copper.
  • the method for preparing the chip packaging structure further includes forming a metal tin layer 60 that covers the side of the conductive bump 404 and the surface on the side away from the semiconductor chip 10 .
  • the material of the metal tin layer 60 is preferably metal tin, but is not limited thereto.
  • step S4 is performed to form a plurality of first openings 3011 on the plastic sealing layer 301 .
  • the first opening The opening 3011 extends from the surface of the plastic sealing layer 301 away from the front surface 10 a of the semiconductor chip to the back surface of the semiconductor chip 10 or the back surface of the auxiliary chip 10 .
  • the back side of the semiconductor chip is a substrate, so the first opening 3011 can expose the substrate of the semiconductor chip.
  • the formation method of the first opening 3011 is preferably a laser method or a development method, but is not limited thereto.
  • step S5 is performed to form a second rewiring structure 70 on the side of the plastic encapsulation layer 301 away from the front surface 10 a of the semiconductor chip, and the second rewiring structure 70 also fills the first opening.
  • the second redistribution structure 70 includes a third conductive trace 702 located on a side of the plastic encapsulation layer 301 away from the front surface 10 a of the semiconductor chip and a third conductive plug 701 disposed in the first opening.
  • the third conductive plug 701 is formed in the first opening 3011 of the plastic sealing layer 301, and the third conductive plug 701 is connected to the third conductive trace 702 and the semiconductor chip respectively.
  • the back surface is in direct contact, and the third conductive trace 702 is electrically connected to the back surface of the semiconductor chip through the third conductive plug 701 .
  • the third conductive trace 702 and the third conductive plug 701 can be formed by electrolytic plating, electrodeless plating, or other methods. Furthermore, the third conductive plug 701 and the third conductive trace 702 can be formed in the same process step, which helps to simplify the packaging process.
  • the material of the third conductive trace 702 and the third conductive plug 701 may be a metal material, such as metal copper.
  • step S5 further includes forming a second dielectric layer 80 covering the second redistribution structure 70 .
  • the material of the second dielectric layer 80 may be a plastic film, PI, PBO, organic polymer film, organic polymer composite material or other materials with similar properties.
  • organic or inorganic fillers may be added to the second dielectric layer 80 .
  • the substrate and the substrate are connected by drilling, filling, and rewiring.
  • the source electrode replaces the existing methods of grinding exposed silicon and direct rewiring. That is to say, this application cancels the grinding and exposing silicon process, and subsequently uses the method of drilling, filling holes and wiring to realize the connection between the substrate and the source. This can avoid cracking of the semiconductor chip and auxiliary chip caused by excessive stress during the grinding operation, and can also avoid The chip packaging structure is delaminated. Therefore, the chip packaging structure obtained by the method for preparing the chip packaging structure provided in this embodiment has no problems with delamination and cracking.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

La présente demande concerne une structure d'encapsulation de puce. La structure d'encapsulation de puce comprend une puce semiconductrice, une puce auxiliaire, une couche d'encapsulation en plastique, une première structure de recâblage et une seconde structure de recâblage ; la couche d'encapsulation en plastique recouvre les surfaces latérales et les surfaces arrière de la puce semiconductrice et de la puce auxiliaire. Cela signifie que, dans la présente demande, la surface arrière de la puce semiconductrice et la surface arrière de la puce auxiliaire sont recouvertes de la couche d'encapsulation en plastique ; ainsi, la fissuration de la puce semiconductrice et de la puce auxiliaire peut être évitée, la stratification de la structure d'encapsulation de puce peut également être évitée et le rendement de produit est amélioré.
PCT/CN2023/107955 2022-07-26 2023-07-18 Structure d'encapsulation de puce et son procédé de préparation WO2024022174A1 (fr)

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CN218548408U (zh) * 2022-07-26 2023-02-28 矽磐微电子(重庆)有限公司 芯片封装结构

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JP2018006654A (ja) * 2016-07-06 2018-01-11 株式会社デンソー 電子装置
CN111341681A (zh) * 2020-04-02 2020-06-26 广东佛智芯微电子技术研究有限公司 一种低厚度3d堆叠封装结构及其制备方法
CN111599696A (zh) * 2020-05-28 2020-08-28 矽磐微电子(重庆)有限公司 半导体模块封装方法及半导体模块
CN111739867A (zh) * 2020-07-31 2020-10-02 矽磐微电子(重庆)有限公司 半导体封装方法及半导体封装结构
CN113611615A (zh) * 2021-07-29 2021-11-05 矽磐微电子(重庆)有限公司 芯片封装结构的制作方法
CN218548408U (zh) * 2022-07-26 2023-02-28 矽磐微电子(重庆)有限公司 芯片封装结构

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Publication number Priority date Publication date Assignee Title
JP2018006654A (ja) * 2016-07-06 2018-01-11 株式会社デンソー 電子装置
CN111341681A (zh) * 2020-04-02 2020-06-26 广东佛智芯微电子技术研究有限公司 一种低厚度3d堆叠封装结构及其制备方法
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CN113611615A (zh) * 2021-07-29 2021-11-05 矽磐微电子(重庆)有限公司 芯片封装结构的制作方法
CN218548408U (zh) * 2022-07-26 2023-02-28 矽磐微电子(重庆)有限公司 芯片封装结构

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