CN111739867A - Semiconductor packaging method and semiconductor packaging structure - Google Patents

Semiconductor packaging method and semiconductor packaging structure Download PDF

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Publication number
CN111739867A
CN111739867A CN202010759781.8A CN202010759781A CN111739867A CN 111739867 A CN111739867 A CN 111739867A CN 202010759781 A CN202010759781 A CN 202010759781A CN 111739867 A CN111739867 A CN 111739867A
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China
Prior art keywords
lead frame
chip
packaged
chips
layer
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CN202010759781.8A
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Chinese (zh)
Inventor
霍炎
涂旭峰
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SIPLP Microelectronics Chongqing Ltd
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SIPLP Microelectronics Chongqing Ltd
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Priority to CN202010759781.8A priority Critical patent/CN111739867A/en
Publication of CN111739867A publication Critical patent/CN111739867A/en
Priority to PCT/CN2020/141972 priority patent/WO2022021800A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The application provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor packaging method comprises the following steps: the lead frame and the chips to be packaged are attached to the carrier plate, and the chips to be packaged are located in the hollow area of the lead frame; covering the chip to be packaged, the lead frame and the exposed carrier plate through the encapsulating layer, and filling the encapsulating layer in the hollow area of the lead frame to form an encapsulating structural member; and forming a first rewiring structure electrically connected with the front surface of the chip to be packaged and the first surface of the lead frame on the first surface of the encapsulating structure, and forming a second rewiring structure electrically connected with the back surface of the chip to be packaged and the second surface of the lead frame on the second surface of the encapsulating structure. The semiconductor packaging structure is manufactured by the semiconductor packaging method. According to the semiconductor packaging structure, double-side interconnection packaging of the chip is achieved through the lead frame and the double-side rewiring interconnection process, thinning of the product is improved, and electrical reliability of the product can be enhanced.

Description

Semiconductor packaging method and semiconductor packaging structure
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor packaging method and a semiconductor packaging structure.
Background
As shown in fig. 1, a lead frame 30 ' and a wiring layer 40 ' are commonly used in the prior art to implement a double-sided interconnection package of two chips 10 ', and the specific structure is as follows: the back surfaces of the two chips 10 'are attached to the upper surface of the lead frame 30' through the conductive adhesive 20 'to realize back surface electric connection, and the wiring layer 40' is connected with the front surface of the chip 10 'through the copper columns 50', wherein the copper columns need to be implanted through an ultrasonic bond. In addition, the lead frame 30 'is disposed on the back side of the chip 10', resulting in a thick packaged product, which is limited when applied to wearing equipment or other scenes with high requirements on product thickness.
Disclosure of Invention
One aspect of the present application provides a semiconductor packaging method, comprising:
s1: the method comprises the following steps that a lead frame and a plurality of chips to be packaged are attached to a carrier plate, the front faces of the chips to be packaged face the carrier plate, the lead frame is provided with a hollowed-out area, the hollowed-out area penetrates through the lead frame along the thickness direction, and the chips to be packaged are located in the hollowed-out area;
s2: covering the chip to be packaged, the lead frame and the exposed carrier plate through an encapsulating layer, and filling the encapsulating layer into the hollow area of the lead frame to form an encapsulating structural member, wherein the encapsulating structural member comprises a first surface and a second surface opposite to the first surface, and the front surface of the chip to be packaged and the first surface of the lead frame are exposed out of the first surface;
s3: and forming a first rewiring structure on the first surface of the encapsulating structure, wherein the first rewiring structure is electrically connected with the front surface of the chip to be encapsulated and the first surface of the lead frame, forming a second rewiring structure on the second surface of the encapsulating structure, and the second rewiring structure is electrically connected with the back surface of the chip to be encapsulated and the second surface of the lead frame, which is arranged opposite to the first surface.
Optionally, the lead frame includes a plurality of connecting portions, the connecting portions divide the hollow areas into a plurality of spaces, and the chips to be packaged respectively located in different hollow areas are electrically connected through the connecting portions.
Optionally, the lead frame further includes a frame body, and the frame body is provided with the hollow area penetrating through the frame body along the thickness direction; the two ends of the connecting part are respectively connected with the two opposite sides of the frame body.
Optionally, the lead frame further includes a plurality of edge portions isolated from each other, one end of each edge portion is connected to the frame body, and the other end of each edge portion extends toward the hollow area; and a plurality of mutually isolated edge parts are arranged in each hollow-out area.
Optionally, the thickness of the lead frame is greater than the thickness of the chip to be packaged, and before step S3, the method further includes thinning the first surface of the encapsulation structure until the first surface of the lead frame is exposed.
Optionally, before step S3, the method includes:
forming a plurality of openings on the second surface of the encapsulation structure, wherein the openings are positioned right above the chip to be packaged so as to expose the back surface of the chip to be packaged;
in step S3, the second redistribution structure formed on the second surface of the encapsulation structure includes a conductive pillar formed in the opening, and the conductive pillar is electrically connected to the back surface of the chip to be packaged.
Optionally, the lead frame includes a first portion and a second portion from the first surface to the second surface of the encapsulation structure in the thickness direction, and the width of the first portion is greater than the width of the second portion.
A second aspect of the present application provides a semiconductor package structure, comprising:
the packaging structure comprises a lead frame, a plurality of chips and a packaging layer for packaging the lead frame and the chips, wherein the lead frame is provided with a hollow area, the hollow area penetrates through the lead frame along the thickness direction, the chips are located in the hollow area, the packaging layer is filled in the hollow area of the lead frame, the packaging structure comprises a first surface and a second surface opposite to the first surface, and the front surfaces of the chips and the first surface of the lead frame are exposed out of the first surface;
a first rewiring structure formed on the first surface of the encapsulation structure, the first rewiring structure being electrically connected to both the front surface of the chip and the first surface of the lead frame;
and the second rewiring structure is formed on the second surface of the encapsulating structural member and is electrically connected with the back surface of the chip and the second surface arranged opposite to the first surface.
Optionally, the lead frame includes a plurality of connecting portions, the connecting portions divide the hollow areas into a plurality of spaces, and the chips to be packaged respectively located in different hollow areas are electrically connected through the connecting portions.
Optionally, the lead frame further includes a plurality of edge portions that are isolated from each other, the edge portions are disposed along an inner peripheral edge of the encapsulating structure, one end of each edge portion is exposed to the surface of the encapsulating structure, and the other end of each edge portion extends toward the hollow area; and a plurality of mutually isolated edge parts are arranged in each hollow-out area.
Optionally, the second surface of the encapsulation structure has a plurality of openings, the openings are disposed corresponding to the chips, and the second redistribution structure includes conductive posts, which are formed in the openings and electrically connected to the back surfaces of the chips.
Optionally, the lead frame includes a first portion and a second portion from the first surface to the second surface of the encapsulation structure in the thickness direction, and the width of the first portion is greater than the width of the second portion.
According to the semiconductor packaging method and the semiconductor packaging structure provided by the embodiment of the application, the double-side interconnection packaging of the chip is realized through the lead frame and the double-side rewiring interconnection process, the thinning of the product is improved, and the electrical reliability of the product can be enhanced.
Specifically, the lead frame is provided with the hollow area, the hollow area penetrates through the lead frame along the thickness direction, and the chips to be packaged are located in the hollow area, namely, the chips to be packaged are embedded into the lead frame, so that the thickness of the product is greatly reduced, and the product is light and thin.
Compared with the prior art, the double-sided interconnection of the chip is realized by arranging the copper columns, the technical scheme in the application directly realizes the double-sided interconnection of the chip through the lead frame without the copper columns, so that the interconnection area is increased, a multilayer wiring process is realized, the degree of freedom of product design is increased, and the electrical reliability of the product is enhanced; meanwhile, the production cost is saved, and the overall production efficiency is improved. It should be noted that, in the prior art, if a plurality of copper pillars are provided, not only the positioning process in the manufacturing process is complicated, but also the positioning errors are accumulated because a plurality of independent copper pillars are provided; in the application, the lead frame is integrally formed, so that all parts on the lead frame are fixed on the carrier plate by one-time positioning, and are encapsulated in the encapsulating structural member, thereby greatly saving the production cost and improving the overall production efficiency.
The plurality of chips to be packaged are arranged in the hollow area of the lead frame, and the chips to be packaged and the lead frame are packaged together, so that the chips are prevented from being fixed by conductive adhesive, and the lead-in efficiency is improved.
Compared with the lead frame in the prior art, the structure of the lead frame of the semiconductor packaging structure is not required to be positioned below the chip, so that the structure is suitable for the chip with larger area, more chips can be discharged, and the structure has excellent applicability.
Drawings
Fig. 1 is a cross-sectional view of a semiconductor package structure in the prior art.
Fig. 2 is a flowchart of a semiconductor packaging method proposed according to embodiment 1 of the present application.
Fig. 3 is a schematic front structure diagram of a lead frame proposed according to embodiment 1 of the present application.
Fig. 4 is a schematic front view of a lead frame according to embodiment 1 of the present application.
Fig. 5(a) -5 (n) are process flow diagrams of a middle semiconductor packaging method proposed according to embodiment 1 of the present application.
Fig. 6 is a schematic structural diagram of a semiconductor package structure according to embodiment 1 of the present application.
Fig. 7(a) is a schematic view of front side connection of the proposed semiconductor package structure according to embodiment 1 of the present application.
Fig. 7(b) is a schematic view of back side connection of the semiconductor package structure proposed according to embodiment 1 of the present application.
Fig. 8 is a schematic structural diagram of another embodiment of a semiconductor package structure according to example 1 of the present application.
Fig. 9(a) -9 (g) are process flow diagrams of a semiconductor packaging method according to embodiment 2 of the present application.
Fig. 10 is a schematic structural diagram of a semiconductor package structure according to embodiment 2 of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. The use of the terms "a" or "an" and the like in the description and in the claims of this application do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" means two or more. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper" and/or "lower," and the like, are used for convenience of description and are not limited to a single position or orientation in space. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
Example 1
The embodiment provides a semiconductor packaging method and a semiconductor packaging structure.
Fig. 2 is a flowchart of a semiconductor packaging method proposed in the present embodiment. As shown in fig. 2, the semiconductor packaging method includes the steps of:
step 100: the method comprises the following steps that a lead frame and a plurality of chips to be packaged are attached to a carrier plate, the front faces of the chips to be packaged face the carrier plate, the lead frame is provided with a hollowed-out area, the hollowed-out area penetrates through the lead frame along the thickness direction, and the chips to be packaged are located in the hollowed-out area;
step 200: covering the chip to be packaged, the lead frame and the exposed carrier plate through an encapsulating layer, and filling the encapsulating layer into the hollow area of the lead frame to form an encapsulating structural member, wherein the encapsulating structural member comprises a first surface and a second surface which are oppositely arranged, and the front surface of the chip to be packaged and the first surface of the lead frame are exposed out of the first surface;
step 300: and forming a first rewiring structure on the first surface of the encapsulating structure, wherein the first rewiring structure is electrically connected with the front surface of the chip to be encapsulated and the first surface of the lead frame, forming a second rewiring structure on the second surface of the encapsulating structure, and the second rewiring structure is electrically connected with the back surface of the chip to be encapsulated and the second surface of the lead frame, which is arranged opposite to the first surface.
The semiconductor packaging method of the embodiment improves the thinning of the product and can enhance the electrical reliability of the product.
Specifically, the lead frame is provided with the hollow area, the hollow area penetrates through the lead frame along the thickness direction, and the chips to be packaged are located in the hollow area, namely, the chips to be packaged are embedded into the lead frame, so that the thickness of the product is greatly reduced, and the product is light and thin.
Compared with the prior art, the copper columns are required to be arranged to realize the positive double-sided interconnection of the chips, the technical scheme in the embodiment directly realizes the double-sided interconnection of the chips through the lead frame without the copper columns, so that the interconnection area is increased, the multilayer wiring process is realized, the degree of freedom of product design is increased, and the electrical reliability of the product is enhanced; meanwhile, the production cost is saved, and the overall production efficiency is improved. It should be noted that, in the prior art, if a plurality of copper pillars are provided, not only the positioning process in the manufacturing process is complicated, but also the positioning errors are accumulated because a plurality of independent copper pillars are provided; in the application, the lead frame is integrally formed, so that all parts on the lead frame are fixed on the carrier plate by one-time positioning, and are encapsulated in the encapsulating structural member, thereby greatly saving the production cost and improving the overall production efficiency.
The plurality of chips to be packaged are arranged in the hollow area of the lead frame, and the chips to be packaged and the lead frame are packaged together, so that the chips are prevented from being fixed by conductive adhesive, and the lead-in efficiency is improved.
Compared with the lead frame in the prior art, the structure of the lead frame of the semiconductor packaging structure of the embodiment has the advantages that the lead frame part structure below the chip is not needed, so that the structure is suitable for the chip with larger area, more chips can be discharged, and the structure has excellent applicability.
The specific structure of the lead frame 20 in this embodiment is as shown in fig. 3 and 4, each of the final semiconductor package structures after the package is completed and the dicing is performed corresponds to one lead frame 20, a plurality of interconnected lead frames 20 arranged in an array form the lead frame 2, and the lead frame 2 may also be formed by only one lead frame 20.
Each lead frame 20 includes a frame 22, and a hollow area 21 penetrating the frame 22 along a thickness direction T is formed in the frame 22. The number of the hollowed-out regions 21 of the lead frame 20 may be one or more.
The lead frame 20 further includes a connection portion 24, two ends of the connection portion 24 are respectively connected to two opposite sides of the frame 22, and the connection portion 24 divides the hollow areas 21 into a plurality of spaces, that is, adjacent hollow areas 21 are separated by the connection portion 24, and adjacent hollow areas 21 in the same lead frame 20 are separated by the connection portion 24.
Specifically, in the present embodiment, as shown in fig. 4, each lead frame 20 is divided into two hollow areas by the connection portion 24, that is, the number of the hollow areas 21 provided in each lead frame 20 is two, and the two hollow areas 21 are separated by the connection portion 24.
The connecting portion 24 includes a first portion 241, a middle portion 242, and a second portion 243 connected in sequence, where the first portion 241 forms a first included angle α with the middle portion 242, the second portion 243 forms a second included angle β with the middle portion 242, and the first portion 241 and the second portion 243 are respectively connected to two opposite sides of the frame 22. In this way, by providing a specific structure of the connection portion 24, a larger connection area can be achieved by the first portion 241 and the second portion 243. Preferably, the first included angle α and the second included angle β are both equal to 90 degrees, and the first portion 241 and the second portion 243 are parallel to each other, so that the structure of the connecting portion 24 is more stable. Preferably, the end of the first portion 241 away from the connecting portion 24 and the end of the second portion 243 away from the connecting portion 24 are both located on the same side of the connecting portion 24, so that the connecting portion 24 is more compact.
The lead frame 20 further comprises a plurality of edge portions 23 which are isolated from each other, one end of each edge portion 23 is connected with the frame body 22, and the other end of each edge portion 23 extends towards the hollow area 21; each hollowed-out area 21 is provided with a plurality of edge portions 23 which are isolated from each other. Specifically, the edge portion 23 includes a main body 231 and a support portion 232, and the support portion 232 is connected between the frame body 22 and the main body 231. The number of the supporting portions 232 may be one or plural, and when the number of the supporting portions 232 is plural, the plural supporting portions 232 are provided at intervals. The shape of the body 231 may be square, bar, or L-shaped. Preferably, the edge 23 of the L-shaped main body 231 is disposed at a corner of the hollow area 21 away from the connecting portion 24.
Further, the chips to be packaged, which are respectively located in the different hollow-out areas, are electrically connected through the connecting portions. Electrically connecting the front surface of one chip to be packaged with the back surface of the other chip to be packaged; or the front surface of one chip to be packaged is electrically communicated with the front surface of the other chip to be packaged; or the back surface of one chip to be packaged is electrically communicated with the back surface of the other chip to be packaged.
Each lead frame 20 includes a first surface 20a and a second surface 20b arranged oppositely along the thickness direction T, the first surface 20a is provided with a plurality of first electrical connection points, and the second surface 20b is provided with a plurality of second electrical connection points.
Specifically, as shown in fig. 5(a) -5 (n), the semiconductor packaging method of the present embodiment includes:
in step 100, as shown in fig. 5(a), the chip 11 to be packaged and the lead frame 20 are attached to the carrier 3 through an adhesive layer, with the back surface of the chip 11 to be packaged facing upward and the front surface facing the carrier 3. The chip 11 to be packaged includes a front surface 11a provided with pads, and a back surface 11b arranged opposite to the front surface 11a, and the back surface 11b is provided with a metal layer 111, so that the front surface 11a and the back surface 11b of the chip 11 to be packaged are both electrically led out. The lead frame 20 is provided with a hollow area 21, the hollow area 21 penetrates through the lead frame 20 along the thickness direction T, and the plurality of chips 11 to be packaged are located in the hollow area 21.
In the present embodiment, the thickness of the lead frame 20 is greater than the thickness of the chip 11 to be packaged, so as to protect the chip 11 to be packaged.
The adhesive layer is used to adhere the chip 11 to be packaged and the lead frame 20, and the adhesive layer may be made of a material that is easily peeled off so as to peel the carrier 3, the chip 11 to be packaged and the lead frame 20 away in a subsequent process, for example, a thermal release material that can be heated to lose its adhesiveness.
In other embodiments, the adhesive layer may have a two-layer structure, i.e., a thermal separation material layer and a chip attachment layer, the thermal separation material layer is adhered to the carrier plate 3 and loses its viscosity when heated, so as to be peeled off from the carrier plate 3, and the chip attachment layer has an adhesive material layer and can be used for adhering the chip 11 to be packaged. After the packaged chip 11 is peeled off from the carrier 3, the chip adhesion layer thereon can be removed by chemical cleaning. In one embodiment, the adhesive layer may be formed on the carrier plate 3 by lamination, printing, or the like.
The number of chips 11 to be packaged is plural. The number of the chips 11 to be packaged can be adjusted according to design requirements, and is not limited herein.
As mentioned above, since the lead frame 20 is integrally formed, that is, the frame, the connecting portion 24 and the edge portion 23 of the lead frame are integrally formed, each of the frame, the connecting portion 24 and the edge portion 23 of the lead frame is fixed on the carrier by one-time positioning, thereby greatly saving the production cost and improving the overall production efficiency.
In step 200, as shown in fig. 5(b), the encapsulating layer 14 covers the entire carrier 3, that is, the chip 11 to be packaged, the lead frame 20 and the exposed carrier 3, and fills the hollow area 21 of the lead frame 20, and the chip 11 to be packaged and the lead frame 20 are molded to form the encapsulating structure 10. The encapsulating structure 10 is a flat plate structure on which the rewiring and encapsulation can be continued after the carrier plate 3 has been peeled off.
The envelope structure 10 comprises a first surface 10a and a second surface 10b arranged opposite to each other, the second surface 10b of the envelope structure 10 being arranged opposite to the carrier plate 3, substantially flat and parallel to the surface of the carrier plate 3. The first surface 10a of the encapsulation structure 10 exposes the protective layer 30 of the front surface of the chip 11 to be encapsulated and the first surface 20a of the lead frame 20.
In one embodiment, the encapsulating layer 14 may be formed by laminating an epoxy resin film or a Molding film, or by Injection Molding (Injection Molding), Compression Molding (Compression Molding) or Transfer Molding (Transfer Molding) of an epoxy resin compound.
Optionally, before entering step 300, the packaging method further includes attaching the first support plate 41 to the second surface 10b of the packaging structure 10.
The first support plate 41 is attached to at least a portion of the second surface 10b of the envelope structure 10. As shown in fig. 5(c), in one embodiment, the first support plate 41 is attached on the second surface 10b of the envelope structure 10, and the first support plate 41 covers the entire area of the second surface 10b of the envelope structure 10.
The material strength of the first supporting plate 41 is greater than that of the encapsulating layer, so that the mechanical strength of the encapsulating structure in the encapsulating process can be effectively improved and guaranteed, adverse effects caused by deformation of structures are effectively inhibited, and the product encapsulating effect is improved. In other embodiments, the supporting plate may also be formed on the second surface 10b of the encapsulating structure 10 by Spraying (Spraying), Printing (Printing), Coating (Coating), or the like.
Next, before entering step 300, as shown in fig. 5(d), the packaging method further includes peeling off the carrier 3 to expose the first surface 10a of the encapsulated structure 10. The first surface 10a of the encapsulation structure 10 exposes the front surface of the chip 11 to be encapsulated and the first surface 20a of the lead frame 20.
Because the bonding layer between the carrier plate 3 and the chip to be packaged and the lead frame 20 is a thermal separation film, the bonding layer can reduce viscosity after being heated by a heating mode, and the carrier plate 3 is peeled. By peeling the carrier plate 3 by heating the adhesive layer, damage to the chip 11 to be packaged during peeling can be minimized. In other embodiments, the carrier plate 3 can also be peeled off directly mechanically.
After the carrier plate 3 is peeled off, the first surface 10a of the encapsulating structure 10 facing the carrier plate 3, the front surface of the chip 11 to be packaged, and the first surface 20a of the lead frame 20 are exposed. After peeling off the carrier plate 3, a first encapsulation structure 10 is obtained, which comprises the chip 11 to be encapsulated, the lead frame 20 and the encapsulation layer 14 encapsulating the chip 11 to be encapsulated and the lead frame 20. On the formed encapsulation structure 10, re-wiring or the like may be performed according to actual conditions, so that the chip 11 to be packaged is electrically connected with the outside.
It should be noted that the step of attaching the first support plate 41 may also be placed after peeling off the carrier plate 3.
Next, before proceeding to step 300, as shown in fig. 5(e), a protective layer 30 is formed on the first surface 10a of the encapsulation structure 10. Thereafter, as shown in fig. 5(f), a protective layer opening 31 is formed on the protective layer 30 at a position corresponding to the pad of the front surface of the chip 11 to be packaged and at a position corresponding to the first electrical connection point of the first surface 20a of the lead frame 20.
In the present embodiment, since the lead frame 20 and the chip 11 to be packaged are arranged on the same horizontal plane, when the protective layer 30 is punched to form the protective layer opening 31, the protective layer 30 is a transparent film layer, and besides the transparency of the protective layer 30, the lead frame 20 can also be used for assisting positioning, so as to improve the position accuracy of laser drilling.
In step 300, as shown in fig. 5(g), a first redistribution structure 50 is formed on the first surface 10a of the encapsulation structure 10, and the first redistribution structure 50 is electrically connected to the pads on the front surface of the chip 11 to be packaged and electrically connected to the first electrical connection points on the first surface 20a of the lead frame 20. The first rewiring structure 50 includes at least one first rewiring layer 51. In the present embodiment, the first redistribution structure 50 includes one first redistribution layer 51, but is not limited thereto, and may also include a plurality of first redistribution layers 51 according to design requirements, that is, the redistribution is performed on the front side of the chip to be packaged, for example, more redistribution structures may be formed in the same manner, and may be adjusted according to design requirements.
Since the passivation layer opening 31 is already formed on the passivation layer 30, at least the passivation layer opening 31 can be directly seen when the first redistribution layer 51 is formed, so that the first redistribution structure 50 can be aligned more accurately.
In forming the first redistribution layer 50, the conductive medium may be filled in the protection layer opening 31 of the protection layer 30 at the same time to form the conductive pillar 52, i.e., the first redistribution layer 51 and the conductive pillar 52 are formed in the same conductive layer forming process. The conductive pillars 52 form vertical connection structures in the protective layer openings 31, and the pads on the front surface 11a of the chip 11 to be packaged are electrically led out through the conductive pillars 52 and the first redistribution layer 51.
Next, as shown in fig. 5(h), a dielectric layer 60 is formed, and the dielectric layer 60 is formed on the first redistribution structure 50 and the first surface 10a of the exposed encapsulation structure 10. The dielectric layer 60 may be formed by a Molding film, or the dielectric layer 60 may be formed by Lamination (Printing) or Printing (Printing). The dielectric layer 60 may be made of an insulating material, such as one or more of polyimide, epoxy resin, and PBO (Polybenzoxazole), and preferably made of an epoxy compound.
As shown in fig. 5(i), after forming the dielectric layer 60, the encapsulation method further includes peeling off the first support plate 41. The first support plate 41 may be mechanically peeled directly or peeled by other methods, which are not limited in this application and may be set according to specific application environments.
Optionally, after peeling the first support plate 41, the packaging method further includes attaching a second support plate 42 to a side of the dielectric layer 60 away from the first surface 10a of the envelope structure 10.
The second support plate 42 is attached at least in a partial region of the side of the dielectric layer 60 facing away from the envelope structure 10. As shown in fig. 5(j), in one embodiment, the second support plate 42 is mounted on the dielectric layer 60, and the second support plate 42 is mounted on the whole area of the side of the dielectric layer 60 away from the encapsulating structure 10.
The material strength of the second support plate 42 is greater than that of the dielectric layer 60, so that the mechanical strength of the packaging structure in the packaging process can be effectively improved and ensured, adverse effects caused by deformation of each structure can be effectively inhibited, and the product packaging effect can be improved. In other embodiments, the support plate may also be formed on the dielectric layer 60 by Spraying (Spraying), Printing (Printing), Coating (Coating), or the like.
It should be noted that the step of attaching the second support plate 42 may also be performed before peeling the first support plate 41.
Optionally, as shown in fig. 5(k), before the second redistribution structure 70 is formed on the second surface 10b of the encapsulation structure 10, the encapsulation method further includes grinding the second surface 10b of the encapsulation structure 10 to reduce the thickness of the encapsulation structure 10. Preferably, it is thinned to expose the second surface 20b of the lead frame 20.
In the thinned encapsulating structure 10, since the thickness of the lead frame 20 is greater than that of the chip 11 to be encapsulated, the encapsulating layer 14 with a certain thickness is reserved on the back surface of the chip 11 to be encapsulated, so as to protect the chip 11 to be encapsulated.
It should be noted that, during packaging, due to consideration of a process of a chip production section and the like, a received chip to be packaged may be an ultra-thin chip, and in order to ensure that the chip is not damaged, the chip may not be further thinned through grinding and other processes, and meanwhile, when the chip 11 is an ultra-thin chip, the lead frame 20 may not be ground to a thickness consistent with that of the chip 11, because the lead frame 20 may be broken if it is ground to be too thin, and therefore, the encapsulation layer 14 with a certain thickness needs to be retained on the back of the chip and the back of the chip 11 needs to be communicated with the second rewiring structure 70 by drilling. Through the arrangement, the application can be suitable for the integral packaging of the ultra-thin multi-chip. Where ultra-thin multi-chip refers to chips with a thickness below 200 microns.
Next, as shown in fig. 5(l), a plurality of openings 15 are formed on the second surface 10b of the encapsulation structure 10, and the openings 15 are disposed corresponding to the chip 11 to be packaged so as to expose the back surface of the chip 11 to be packaged. I.e. openings are made in the encapsulation layer 14 on the back side of the chip 11 to be packaged to form the openings 15.
Next, as shown in fig. 5(m), a second rewiring structure 70 is formed on the second surface 10b of the encapsulation structure 10. The second re-wiring structure 70 is electrically connected to both the metal layer 111 on the back surface of the chip 11 to be packaged and the second electrical connection points on the second surface 20b of the lead frame 20.
It should be noted that the thickness of the rewiring structure (second rewiring structure 70) is much smaller than the thickness of the leadframe 30' in the prior art (as in fig. 1). The thickness of the general rewiring structure is 15um-45um, and the thickness of the lead frame 30' is 150um-450um, so that the rewiring structure not only realizes the function of wiring, but also improves the thinning of products.
In the present embodiment, since the lead frame 20 is electrically connected to both the first re-wiring structure 50 and the second re-wiring structure 70, the front-side and back-side interconnections of the chip 11 to be packaged are realized, i.e., the first re-wiring structure 50 on the first surface 10a of the encapsulation structure 10 and the second re-wiring structure 70 on the second surface 10b of the encapsulation structure 10 are communicated through the lead frame 20.
In this way, the electrical lead-out of the front surface 11a and the back surface 11b of the chip 11 to be packaged and the electrical connection of each electronic component (different multiple chips 11 to be packaged) inside the package of the semiconductor package structure 1 are realized by the first rewiring structure 50, the lead frame 20 and the second rewiring structure 70, and compared with the prior art in which the electrical connection is completed by leads, the semiconductor package structure of the present embodiment requires a smaller space, especially a space in the thickness direction; in addition, the pin extraction which finally concentrates the electrical connection on the lead frame is not needed, so the layout of the rewiring structure is more free and flexible.
Specifically, the electrical leading-out of the front surface 11a of the chip 11 to be packaged is realized by the electrical connection of the pad of the front surface 11a of the chip 11 to be packaged, the first rewiring structure 50, the lead frame 20 and the second rewiring structure 70 in sequence; the electrical lead-out of the back surface 11b of the chip 11 to be packaged is realized by directly electrically connecting with the second re-wiring structure 70; the interconnection of different chips 11 to be packaged, i.e. the interconnection of the same side or the interconnection of different sides, such as the interconnection of the front side of one chip 11 to be packaged and the back side of another chip 11 to be packaged, can be realized by the electrical connection of the first rewiring structure 50, the lead frame 20 and the second rewiring structure 70.
The second rewiring structure may include at least one second rewiring layer and a pin layer, and the pin layer is located on a side of the second rewiring layer away from the encapsulation structure. Alternatively, the second re-routing structure includes only one pin layer, as required by the design. The number of the second rewiring layers may be one, or may be adjusted according to design requirements, or may be multiple, that is, rewiring is repeatedly performed on the back surface of the chip to be packaged, for example, more rewiring structures may be formed in the same manner, and may be adjusted according to design requirements.
The semiconductor package 1 is electrically connected to the outside through the pin layer, and is mounted through the pin layer.
The material of the lead layer is tin, but not limited to tin, and may also be a nickel-gold alloy, or other metals.
In the present embodiment, referring to fig. 5(m), the second redistribution structure 70 includes a lead layer 71.
In forming the second re-wiring structure 70, the opening 15 of the encapsulation layer 14 may be simultaneously filled with a conductive medium to form the conductive pillar 72, i.e., the lead layer 71 and the conductive pillar 72 are formed in the same conductive layer forming process. The conductive posts 72 form vertical connection structures in the openings 15, and the pads on the back surface 11b of the chip 11 to be packaged are electrically led out through the conductive posts 72 and the pin layer 71.
Subsequently, the second support plate 42 is peeled off as shown in fig. 5 (n). The second supporting plate 42 can be directly and mechanically peeled off, or can be peeled off by other methods, which are not limited in this application and can be set according to the specific application environment.
Optionally, before or after peeling the second support plate 42, a step of cutting off the frame body of the lead frame 20 by laser or mechanical cutting is further included, and illustration of the step is omitted.
In addition, if a plurality of semiconductor package structures are packaged together, after the packaging is completed, the whole package structure is cut into a plurality of semiconductor package structures by laser or mechanical cutting. The structure of the semiconductor package 1 is shown in fig. 6.
Fig. 6 is a schematic structural diagram of a semiconductor package structure 1 obtained by the semiconductor packaging method according to the present embodiment. The semiconductor package structure 1 includes: an envelope structure 10, a first rewiring structure 50 and a second rewiring structure 70.
The encapsulation structure 10 includes a first surface 10a and a second surface 10b opposite to each other, the encapsulation structure 10 includes a lead frame 20 and a plurality of chips 11, and an encapsulation layer 14 for encapsulating the lead frame 20 and the plurality of chips 11, the lead frame 20 is provided with a hollow area, the hollow area penetrates through the lead frame 20 along a thickness direction T, the plurality of chips 11 are located in the hollow area, and the encapsulation layer 14 is filled in the hollow area of the lead frame 20.
The number of chips 11 is plural. The number of the chips 11 may be adjusted according to design requirements, and is not limited herein. In the present embodiment, the number of the chips 11 is two. The number of the hollowed-out regions 21 of the lead frame 20 may be one or more. In the present embodiment, the number of the hollow areas 21 provided on each lead frame 20 is two, but not limited thereto, and the number of the hollow areas 21 may be other numbers according to design requirements.
According to design requirements, a plurality of chips 11 may be placed in different hollow areas 21, or a plurality of chips 11 may be placed in the same hollow area 21.
The lead frame 20 further includes a plurality of connecting portions 24, the connecting portions 24 divide the hollow regions into a plurality of hollow regions, and the chips 11 respectively located in different hollow regions are electrically connected by the connecting portions 24.
Specifically, in the present embodiment, each lead frame 20 is divided into two hollow areas by the connecting portion 24, that is, the number of the hollow areas 21 provided in each lead frame 20 is two, and the two hollow areas 21 are separated by the connecting portion 24. The two chips 11 are respectively located in two different hollow areas.
The chip 11 includes a front surface provided with a pad and a back surface disposed opposite to the front surface, and the back surface is provided with a metal layer 111, so that the front surface and the back surface of the chip 11 are both electrically led out. The first surface 20a of the lead frame 20 is exposed to the first surface 10 a.
The first redistribution structure 50 is formed on the first surface 10a of the encapsulation structure 10 corresponding to the front surface of the chip 11, and the first redistribution structure 50 is electrically connected to the pads on the front surface of the chip 11 and electrically connected to the first electrical connection points on the first surface 20a of the lead frame 20.
The first rewiring structure 50 includes at least one first rewiring layer 51. In the present embodiment, the first redistribution structure 50 includes one first redistribution layer 51, but is not limited thereto, and may also include a plurality of first redistribution layers 51 according to design requirements, that is, the redistribution is performed on the front side of the chip, for example, more redistribution structures may be formed in the same manner, and may be adjusted according to design requirements.
The front surface of the encapsulation structure 10 is provided with a protection layer 30, and the protection layer 30 is located between the first rewiring structure 50 and the encapsulation structure 10. The passivation layer 30 has a passivation opening 31, and a conductive pillar 52 formed by filling a conductive medium is disposed in the passivation opening 31. The first redistribution layer 51 and the conductive pillar 52 may be formed in the same conductive layer forming process.
The second re-wiring structure 70 is formed on the second surface 10b of the encapsulation structure 10 corresponding to the back surface of the chip 11. The second re-wiring structure 70 is electrically connected to both the metal layer 111 on the back surface of the chip 11 and the second electrical connection points on the second surface 20b of the lead frame 20. The second re-wiring structure 70 includes at least one second re-wiring layer 71.
In the present embodiment, since the lead frame 20 is electrically connected to both the first re-wiring structure 50 and the second re-wiring structure 70, the front-side and back-side interconnections of the chip 11 are achieved, i.e., the first re-wiring structure 50 on the first surface 10a of the encapsulation structure 10 and the second re-wiring structure 70 on the second surface 10b of the encapsulation structure 10 are communicated through the lead frame 20.
In this way, the first rewiring structure 50, the lead frame 20 and the second rewiring structure 70 are used to electrically lead out the front and back surfaces of the chip 11 and electrically connect the electronic components (different chips 11) inside the package of the semiconductor package structure 1, and compared with the prior art in which electrical connection is performed by leads, the semiconductor package structure of the present embodiment requires a smaller space, particularly a space in the thickness direction; in addition, the pin extraction which finally concentrates the electrical connection on the lead frame is not needed, so the layout of the rewiring structure is more free and flexible.
Specifically, the electrical lead-out of the front surface of the chip 11 is realized by electrically connecting the pads of the front surface of the chip 11, the first rewiring structure 50, the lead frame 20, and the second rewiring structure 70 in sequence; electrical lead-out of the backside of the chip 11 is achieved by direct electrical connection with the second re-wiring structure 70; the interconnection of different chips 11, i.e., the same-side interconnection or different-side interconnections, such as the interconnection of the front surface of one of the chips 11 and the back surface of another chip 11, can be achieved by the electrical connection of the first re-wiring structure 50, the lead frame 20, and the second re-wiring structure 70.
The second rewiring structure may include at least one second rewiring layer and a pin layer, and the pin layer is located on a side of the second rewiring layer away from the encapsulation structure. Alternatively, the second re-routing structure includes only one pin layer, as required by the design. The number of layers of the second rewiring layer may be one, or may be adjusted according to design requirements, or may be multiple, that is, rewiring is repeatedly performed on the front surface of the chip, for example, more rewiring structures may be formed in the same manner, and may be adjusted according to design requirements. When the second rewiring structure comprises at least one second rewiring layer and a pin layer, the orthographic projection of the pin layer is positioned in the orthographic projection of the second rewiring layer. Namely, the distance between the adjacent pin layers is larger than the distance between the adjacent second rewiring layers corresponding to the adjacent pin layers, so that the finally formed semiconductor packaging product is not easy to be short-circuited when being welded by using tin or other materials, and the electrical performance of the product is improved.
The semiconductor package 1 is electrically connected to the outside through the pin layer, and is mounted through the pin layer.
The material of the lead layer is tin, but not limited to tin, and may also be a nickel-gold alloy, or other metals.
In the present embodiment, the second re-wiring structure 70 includes a lead layer 71.
The thickness of the lead frame 20 is greater than that of the chip 11, and the second surface 20b of the lead frame 20 is exposed to the second surface 10b of the encapsulation structure 10, that is, the thickness of the encapsulation structure 10 is equal to that of the lead frame 20, so as to realize the thinnest semiconductor package structure 1.
Since the thickness of the lead frame 20 is greater than that of the chip 11, a certain thickness of the encapsulating layer 14 remains on the back surface of the chip 11 to protect the chip 11.
As described above, in the packaging process, due to consideration of the process of the chip production section and the like, the received chip to be packaged may be an ultra-thin chip, and in order to ensure that the chip is not damaged, the chip may not be further thinned by the grinding and other processes, and meanwhile, when the chip 11 is an ultra-thin chip, the lead frame 20 may not be ground to the thickness consistent with that of the chip 11, and since the lead frame 20 may be broken if it is ground to be too thin, the encapsulation layer 14 with a certain thickness needs to be retained on the back of the chip and the communication between the back of the chip 11 and the second rewiring structure 70 is realized by drilling. Through the arrangement, the application can be suitable for the integral packaging of the ultra-thin multi-chip. Where ultra-thin multi-chip refers to chips with a thickness below 200 microns.
The second surface 10b of the encapsulation structure 10 is opened with an opening 15, and the opening 15 is disposed corresponding to the chip 11 to expose the back surface of the chip 11. I.e. by opening a hole in the encapsulation layer 14 on the back side of the chip 11 to form an opening 15. The second re-wiring structure 70 further includes a conductive post 72, the conductive post 72 is formed by filling a conductive medium in the opening 15, and the conductive post 72 is electrically connected to the back surface of the chip 11. The lead layer 71 and the conductive posts 72 may be formed in the same conductive layer forming process.
The encapsulation structure 10 further includes a dielectric layer 60, wherein the dielectric layer 60 is formed on the first redistribution structure 50 and the exposed first surface 10a of the encapsulation structure 10. The dielectric layer 60 may be formed by a Molding film, or the dielectric layer 60 may be formed by Lamination (Printing) or Printing (Printing). The dielectric layer 60 may be made of an insulating material, such as one or more of polyimide, epoxy resin, and PBO (Polybenzoxazole), and preferably made of an epoxy compound. When the front side of the chip is repeatedly re-wired, more dielectric layers can be formed in the same manner, and can be adjusted according to design requirements.
As shown in fig. 7(a) and 7(b), the connection portion 24 of the lead frame 20 includes a first portion 241, an intermediate portion 242, and a second portion 243 connected in sequence, the first portion 241 forming a first included angle α with the intermediate portion 242, and the second portion 243 forming a second included angle β with the intermediate portion 242. In this way, by providing a specific structure of the connection portion 24, a larger connection area can be achieved by the first portion 241 and the second portion 243. Preferably, the first included angle α and the second included angle β are both equal to 90 degrees, and the first portion 241 and the second portion 243 are parallel to each other, so that the structure of the connecting portion 24 is more stable. Preferably, the end of the first portion 241 away from the connecting portion 24 and the end of the second portion 243 away from the connecting portion 24 are both located on the same side of the connecting portion 24, so that the connecting portion 24 is more compact.
The lead frame 20 further includes a plurality of edge portions 23 separated from each other, one end of each edge portion 23 is exposed to the surface of the encapsulating structure 10, and the other end extends to the hollow area 21; each hollowed-out area 21 is provided with a plurality of edge portions 23 which are isolated from each other. Specifically, the edge portion 23 includes a main body 231 and a support portion 232, one end of the support portion away from the main body 231 is exposed to the surface of the enclosing structure 10, and the other end is connected to the main body 231. The number of the supporting portions 232 may be one or plural, and when the number of the supporting portions 232 is plural, the plural supporting portions 232 are provided at intervals. The shape of the body 231 may be square, bar, or L-shaped. Preferably, the edge 23 of the L-shaped main body 231 is disposed at a corner of the hollow area 21 away from the connecting portion 24.
As mentioned above, since the lead frame 20 is integrally formed and integrally positioned and encapsulated in the encapsulating structure 10, the production cost is greatly saved and the overall production efficiency is improved.
Further, in order to illustrate the connection relationship of the front surface of the chip 11 and the lead frame 20, and the connection relationship of the back surface of the chip 11 and the lead frame 20, a schematic diagram of front surface connection and a schematic diagram of back surface connection of the semiconductor package structures in fig. 7(a) and 7(b) are given. In the figure, only one schematic connection is made to the rewiring structure to explain the connection relationship. It can be seen that the lead frame 20 is electrically connected to both the first re-wiring structure 50 and the second re-wiring structure 70, so as to realize the interconnection of the front and back surfaces of the chips 11, and also to realize the double-sided interconnection of different chips 11 (wherein the front surface of one chip 11 and the back surface of another chip 11) through the electrical connection of the first re-wiring structure 50, the connection portion 24 of the lead frame 20, and the second re-wiring structure 70.
Specifically, the lead frame 20 in fig. 7(a) and 7(b) includes two upper and lower hollow areas 21 in the vertical direction, and each hollow area 21 is provided with one chip 11. In fig. 7(a), the front surface of the chip 11 in the upper hollow area 21 is electrically connected to the connection portion 24 and one of the edge portions 23 of the upper hollow area 21 through the first rewiring structure 50; the front surface of the chip 11 in the lower hollow area 21 is electrically connected to the two edge portions 23 of the lower hollow area 21 through the first rewiring structure 50. In fig. 7(b), the back surface of the chip 11 in the upper hollow area 21 is electrically connected to the other two edge portions 23 of the upper hollow area 21 through the second re-wiring structure 70; the back surface of the chip 11 in the lower hollow area 21 is electrically connected to the connection portion 24 through the second re-wiring structure 70. That is, the front surface of the chip 11 located in the upper hollow area 21 is electrically connected to the back surface of the chip 11 located in the lower hollow area 21 through the first rewiring structure 50, the connection portion 24 of the lead frame 20, and the second rewiring structure 70 in this order.
In another embodiment, as shown in fig. 8, the lead frame 20 includes a first portion 27 and a second portion 28 along the thickness direction T from the first surface to the second surface of the encapsulation structure 10, and the width w21 of the first portion 27 is greater than the width w22 of the second portion 28, i.e., the lead frame 20 is formed into a structure with a stepped cross section. In this way, the relatively wide contact surface of the first portion 27 may be beneficial for providing a relatively large area of support for the first rewiring structure 50 when forming the first rewiring structure 50 over the leadframe 20; moreover, the step-shaped structure can improve the bonding force between the lead frame 20 and the encapsulating layer and the strength of the pin layer 80 of the semiconductor packaging structure on the PCB, thereby improving the board-level reliability of the product.
The semiconductor packaging structure of the embodiment improves the thinning of the product by arranging the whole structure, and can enhance the electrical reliability of the product.
Specifically, a hollow area is arranged on the lead frame, penetrates through the lead frame along the thickness direction, and is used for positioning a plurality of chips in the hollow area, namely, the chips are embedded into the lead frame, so that the thickness of the product is greatly reduced, and the product is thinned.
Compared with the prior art, the copper columns are required to be arranged to realize the positive double-sided interconnection of the chips, the technical scheme in the embodiment directly realizes the double-sided interconnection of the chips through the lead frame without the copper columns, so that the interconnection area is increased, the multilayer wiring process is realized, the degree of freedom of product design is increased, and the electrical reliability of the product is enhanced; meanwhile, the production cost is saved, and the overall production efficiency is improved. It should be noted that, in the prior art, if a plurality of copper pillars are provided, not only the positioning process in the manufacturing process is complicated, but also the positioning errors are accumulated because a plurality of independent copper pillars are provided; in the application, the lead frame is integrally formed, so that all parts on the lead frame are fixed on the carrier plate by one-time positioning, and are encapsulated in the encapsulating structural member, thereby greatly saving the production cost and improving the overall production efficiency.
The plurality of chips are arranged in the hollow area of the lead frame, and the chips and the lead frame are encapsulated together, so that the chips are prevented from being fixed by using conductive adhesive, and the leading-in efficiency is improved.
Compared with the lead frame in the prior art, the structure of the lead frame of the semiconductor packaging structure of the embodiment has the advantages that the lead frame part structure below the chip is not needed, so that the structure is suitable for the chip with larger area, more chips can be discharged, and the structure has excellent applicability.
Example 2
The semiconductor packaging method of the present embodiment is substantially the same as the semiconductor packaging method of embodiment 1, except that in the semiconductor packaging method of the present embodiment, the step of forming the passivation layer 12 is performed before the chip 11 to be packaged and the lead frame 20 are attached to the carrier 3, and the first redistribution structure 50 directly forms the first surface 10a of the encapsulation structure 10.
Specifically, before step 100, as shown in fig. 9(a), a protective layer 12 is formed on the front surface of the chip 11 to be packaged. The chip 11 to be packaged includes a front surface 11a provided with pads, and a back surface 11b arranged opposite to the front surface 11a, and the back surface 11b is provided with a metal layer 111, so that the front surface 11a and the back surface 11b of the chip 11 to be packaged are both electrically led out.
As shown in fig. 9(b), protective layer openings 121 are formed on the protective layer 12 at positions corresponding to the pads of the front surface 11a of the chip 11 to be packaged, and each protective layer opening 121 is at least correspondingly located on a pad of the chip 11 to be packaged or a line led out from the pad, so that the pad of the front surface of the chip 11 to be packaged or the line led out from the pad is exposed from the protective layer opening 121.
In step 100, as shown in fig. 9(c), the chip 11 to be packaged and the lead frame 20 with the protective layer 12 formed on the front surface are attached to the carrier plate 3 through the adhesive layer, the back surface of the chip 11 to be packaged faces upward, and the front surface faces the carrier plate 3. The lead frame 20 is provided with a hollow area 21, the hollow area 21 penetrates through the lead frame 20 along the thickness direction T, and the plurality of chips 11 to be packaged are located in the hollow area 21.
In step 200, as shown in fig. 9(d), the entire carrier 3 is covered by the encapsulating layer 14, that is, the chip 11 to be packaged, the lead frame 20 and the exposed carrier 3 are filled in the hollow area 21 of the carrier 3, and the chip 11 to be packaged and the lead frame 20 are molded to form the encapsulating structure 10. The encapsulating structure 10 is a flat plate structure on which the rewiring and encapsulation can be continued after the carrier plate 3 has been peeled off.
After the carrier plate 3 is peeled off, as shown in fig. 9(e), the surface of the protective layer 12 is exposed, and the chip attachment layer in the adhesive layer is still present on the surface of the protective layer 12, and when the adhesive layer is removed by chemical means, the protective layer 12 can also protect the surface of the chip 11 to be packaged from being damaged. After the adhesive layer is completely removed, if the encapsulating material permeates in the adhesive layer, the surface can be flattened by adopting a chemical cleaning or grinding mode, so that the subsequent wiring is facilitated; without the protective layer 12, the surface of the chip 11 to be packaged cannot be treated chemically or by grinding so as not to damage the circuit on the front side of the chip 11 to be packaged.
In step 300, as shown in fig. 9(f), a first redistribution structure 50 is formed on the first surface 10a of the encapsulation structure 10, and the first redistribution structure 50 is electrically connected to the pads on the front surface of the chip 11 to be packaged and electrically connected to the first electrical connection points on the first surface 20a of the lead frame 20. The first rewiring structure 50 includes at least one first rewiring layer 51. In the present embodiment, the first redistribution structure 50 includes one first redistribution layer 51, but is not limited thereto, and may also include a plurality of first redistribution layers 51 according to design requirements, that is, the redistribution is performed on the front side of the chip to be packaged, for example, more redistribution structures may be formed in the same manner, and may be adjusted according to design requirements.
Since the passivation layer opening 121 is already formed on the passivation layer 12, at least the passivation layer opening 121 can be directly seen when the first redistribution layer 51 is formed, so that the first redistribution structure 50 can be aligned more accurately.
In forming the first redistribution layer 50, the conductive medium may be filled in the passivation layer opening 121 of the chip 11 to be packaged to form the conductive pillar 52 at the same time, i.e., the first redistribution layer 51 and the conductive pillar 52 are formed in the same conductive layer forming process. The conductive pillars 52 form vertical connection structures in the protective layer openings 121, and the pads on the front surface 11a of the chip 11 to be packaged are electrically led out through the conductive pillars 52 and the first redistribution layer 51.
Next, as shown in fig. 9(g), a dielectric layer 60 is formed, and the dielectric layer 60 is formed on the first redistribution structure 50 and the first surface 10a of the exposed encapsulation structure 10. The dielectric layer 60 may be formed by a Molding film, or the dielectric layer 60 may be formed by Lamination (Printing) or Printing (Printing). The dielectric layer 60 may be made of an insulating material, such as one or more of polyimide, epoxy resin, and PBO (Polybenzoxazole), and preferably made of an epoxy compound.
As shown in fig. 10, the present embodiment also provides a semiconductor structure 1 manufactured by the above semiconductor packaging method. The overall structure of the semiconductor structure 1 of this embodiment is substantially the same as that of embodiment 1, except that the protective layer 12 is disposed on the front surface of the chip 11, the orthographic projection of the protective layer 12 is the same as that of the chip 11, and the side of the protective layer 12 away from the chip 11 is flush with the first surface 10a of the encapsulation structure 10. That is, the protective layer 12 can protect the surface of the chip 11 from being damaged when the residual adhesive layer is chemically removed after the carrier sheet is peeled off by forming the protective layer on the front surface of the chip 11 before the chip 11 is attached to the carrier sheet in the packaging process. After the adhesive layer is completely removed, if the encapsulating material permeates in the adhesive layer, the surface can be flattened by adopting a chemical cleaning or grinding mode, so that the subsequent wiring is facilitated; without the protective layer 12, the surface of the chip 11 cannot be treated chemically or by grinding in order to avoid damaging the circuits on the front side of the chip 11.
In the present application, the structural embodiments and the method embodiments may be complementary to each other without conflict.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims (12)

1. A semiconductor packaging method, comprising:
s1: the method comprises the following steps that a lead frame and a plurality of chips to be packaged are attached to a carrier plate, the front faces of the chips to be packaged face the carrier plate, the lead frame is provided with a hollowed-out area, the hollowed-out area penetrates through the lead frame along the thickness direction, and the chips to be packaged are located in the hollowed-out area;
s2: covering the chip to be packaged, the lead frame and the exposed carrier plate through an encapsulating layer, and filling the encapsulating layer into the hollow area of the lead frame to form an encapsulating structural member, wherein the encapsulating structural member comprises a first surface and a second surface opposite to the first surface, and the front surface of the chip to be packaged and the first surface of the lead frame are exposed out of the first surface;
s3: and forming a first rewiring structure on the first surface of the encapsulating structure, wherein the first rewiring structure is electrically connected with the front surface of the chip to be encapsulated and the first surface of the lead frame, forming a second rewiring structure on the second surface of the encapsulating structure, and the second rewiring structure is electrically connected with the back surface of the chip to be encapsulated and the second surface of the lead frame, which is arranged opposite to the first surface.
2. The semiconductor packaging method according to claim 1, wherein the lead frame includes a plurality of connecting portions that partition the hollow regions, and the chips to be packaged that are respectively located in different hollow regions are electrically connected by the connecting portions.
3. The semiconductor packaging method according to claim 2, wherein the lead frame further comprises a frame body, and the frame body is provided therein with the hollowed-out region penetrating through the frame body in the thickness direction; the two ends of the connecting part are respectively connected with the two opposite sides of the frame body.
4. The semiconductor packaging method according to claim 3, wherein the lead frame further comprises a plurality of edge portions isolated from each other, one end of the edge portions is connected to the frame body, and the other end extends toward the hollow area; and a plurality of mutually isolated edge parts are arranged in each hollow-out area.
5. The semiconductor packaging method according to claim 1, wherein the thickness of the lead frame is greater than the thickness of the chip to be packaged, and before step S3, the method further comprises thinning the first surface of the encapsulation structure to expose the first surface of the lead frame.
6. The semiconductor packaging method according to claim 1, wherein before step S3, comprising:
forming a plurality of openings on the second surface of the encapsulation structure, wherein the openings are positioned right above the chip to be packaged so as to expose the back surface of the chip to be packaged;
in step S3, the second redistribution structure formed on the second surface of the encapsulation structure includes a conductive pillar formed in the opening, and the conductive pillar is electrically connected to the back surface of the chip to be packaged.
7. The semiconductor packaging method according to claim 1, wherein the lead frame includes a first portion and a second portion from the first surface to the second surface of the encapsulation structure in a thickness direction, and a width of the first portion is larger than a width of the second portion.
8. A semiconductor package, comprising:
the packaging structure comprises a lead frame, a plurality of chips and a packaging layer for packaging the lead frame and the chips, wherein the lead frame is provided with a hollow area, the hollow area penetrates through the lead frame along the thickness direction, the chips are located in the hollow area, the packaging layer is filled in the hollow area of the lead frame, the packaging structure comprises a first surface and a second surface opposite to the first surface, and the front surfaces of the chips and the first surface of the lead frame are exposed out of the first surface;
a first rewiring structure formed on the first surface of the encapsulation structure, the first rewiring structure being electrically connected to both the front surface of the chip and the first surface of the lead frame;
and the second rewiring structure is formed on the second surface of the encapsulating structural member and is electrically connected with the back surface of the chip and the second surface arranged opposite to the first surface.
9. The semiconductor package structure according to claim 8, wherein the lead frame includes a plurality of connecting portions, the connecting portions partition the hollow areas, and the chips to be packaged in the different hollow areas are electrically connected by the connecting portions.
10. The semiconductor package structure according to claim 8, wherein the lead frame further comprises a plurality of edge portions isolated from each other, the edge portions are disposed along an inner periphery of the encapsulating structure, one end of each edge portion is exposed to a surface of the encapsulating structure, and the other end of each edge portion extends toward the hollow area; and a plurality of mutually isolated edge parts are arranged in each hollow-out area.
11. The semiconductor package structure of claim 8, wherein the second surface of the encapsulation structure forms a plurality of openings, the openings corresponding to the chip, and the second redistribution structure comprises conductive posts formed in the openings and electrically connected to the back surface of the chip.
12. The semiconductor package structure of claim 8, wherein the lead frame includes a first portion and a second portion from the first surface to the second surface of the encapsulation structure in a thickness direction, the first portion having a width greater than a width of the second portion.
CN202010759781.8A 2020-07-31 2020-07-31 Semiconductor packaging method and semiconductor packaging structure Pending CN111739867A (en)

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