CN210200700U

CN210200700U - Chip structure

Info

Publication number: CN210200700U
Application number: CN201921299462.2U
Authority: CN
Inventors: Huixing Zhou; 周辉星
Original assignee: Pep Innovation Pte Ltd
Current assignee: Pep Innovation Pte Ltd
Priority date: 2019-03-11
Filing date: 2019-08-12
Publication date: 2020-03-27
Anticipated expiration: 2029-08-12
Also published as: CN110729257A; TWI772672B; TW202034481A; TWI719600B; TW202034491A; CN110729256A; TWI783166B; TWM597984U; TWM589898U; CN210182361U; CN110729258A; TWM591703U; CN210182362U; TW202034472A

Abstract

The present disclosure provides a chip structure, including: at least one die; a protective layer; a metal unit comprising at least one metal feature; a plastic packaging layer for packaging the bare chip and the metal unit; wherein the chip structure is connected to an external circuit through at least one metal feature; a dielectric layer. The packaging performance improvement brought by different metal characteristics is achieved by utilizing a plurality of metal characteristics of the metal units, and in addition, the protective layer is formed on the active surface of the wafer, so that the insulating layer application step after the plastic packaging layer forming step is omitted.

Description

Chip structure

Technical Field

The present disclosure relates to the field of semiconductor technology, and more particularly, to a chip structure.

Background

In panel-level packaging (panel-level package), a wafer is cut and separated into a plurality of bare chips, the bare chips are arranged and adhered to a carrier plate, and the plurality of bare chips are packaged simultaneously in the same process flow. The panel-level package has attracted considerable attention as a technology that has been developed in recent years, and has advantages of high production efficiency, low production cost, and suitability for mass production, compared to a conventional wafer-level package (wafer-level package).

Disclosure of Invention

The present disclosure is directed to a chip structure, comprising: at least one die; a protective layer; a metal unit comprising at least one metal feature; a plastic packaging layer for packaging the bare chip and the metal unit; wherein the chip structure is connected to an external circuit through at least one metal feature; a dielectric layer.

The present disclosure achieves improvements in packaging performance from different metal features by utilizing multiple metal features of a metal unit.

The metal features may include connection structures and heat dissipation structures, the connection structures being connected to electrical connection points on the active side of the die in the chip via conductive structures, and the packaged chip structure being connected to external circuit components, such as a PCB board, via the connection structures, instead of wire bonding (wire bonding) structures. Compared with a lead bonding packaging structure, the packaging process is simple, the mutual interference of signals among leads in the lead bonding structure is avoided, and the noise of the leads caused by vibration when the chip works is avoided. And the connecting structure is used for replacing a lead structure, so that the chip packaging structure is more suitable for chip packaging with large electric flux.

Further, the bare chip arranged on the carrier plate together with the metal structure is the bare chip with the protective layer, and as the bare chip arranged on the carrier plate has the protective layer in the disclosure, the step of forming the panel-level conductive layer can be directly performed without performing the step of applying the insulating layer after the step of forming the plastic package layer. Particularly, in a large-sized panel, if an insulating layer is formed on the entire panel, firstly, the process difficulty is much greater than that of forming a small-area protective layer, and secondly, the use amount of an insulating layer material is increased by forming the insulating layer on the entire panel.

Furthermore, the protective layer and the plastic package layer adopted in the disclosure have certain material characteristics, which can help to reduce warpage in the panel packaging process and enable the packaged chip structure to have a durable service cycle, and are particularly suitable for large-scale panel-level packaging and packaging of high-electric-flux and thin chips.

Drawings

Fig. 1 is a flowchart of a proposed chip packaging method according to an exemplary embodiment of the present disclosure;

fig. 2 to 15 are schematic flow diagrams of a chip packaging method according to an exemplary embodiment of the disclosure;

fig. 16 to 20 are schematic flow diagrams of a chip packaging method according to another exemplary embodiment of the present disclosure;

fig. 21 to 25 are schematic flow charts of a chip packaging method according to still another exemplary embodiment of the present disclosure;

fig. 26 to 28 are schematic flow diagrams of a chip packaging method according to yet another exemplary embodiment of the present disclosure;

29a, 29b, 29c, 29d, 29e are schematic diagrams of chip structures provided according to exemplary embodiments of the present disclosure obtained by using the above-described packaging methods;

fig. 30 is a schematic diagram of a packaged chip in use according to an example embodiment of the present disclosure.

Detailed Description

For the purpose of making the technical solutions of the present disclosure clearer and the technical effects thereof more obvious, the following detailed description and the description of the preferred embodiments of the present disclosure are given with reference to the accompanying drawings, which should not be construed as limiting the present disclosure or the only implementation forms of the present disclosure.

Fig. 1 is a flow chart of a chip packaging method according to embodiment 1 of the present disclosure. Referring to fig. 1, the method of the present disclosure includes the steps of:

in step S1, a wafer 100 is provided.

As shown in fig. 2, at least one wafer 100 is provided, the wafer 100 has a wafer active surface 1001 and a wafer back surface 1002, the wafer 100 includes a plurality of dies 113, wherein an active surface of each die constitutes the wafer active surface 1001, the active surface of each die in the wafer 100 forms a series of active components and passive components through a series of processes such as doping, deposition, etching, and the like, the active components include diodes, triodes, and the like, the passive components include a voltage device, a capacitor, a resistor, an inductor, and the like, and the active components and the passive components are connected by connecting wires to form a functional circuit, thereby realizing various functions. The wafer active side 1001 also includes electrical connection points 103 for leading out functional circuits and an insulating layer 105 for protecting the electrical connection points 103.

In step S2, the protective layer 107 is applied to the active surface 1001 of the wafer.

Fig. 3a-3b show optional process steps for applying the protective layer 107 on the active side 1001 of the wafer:

as shown in fig. 3a, a protective layer 107 is applied on the wafer active side 1001.

Preferably, the protective layer 107 is applied to the active side 1001 of the wafer in a laminated manner.

Optionally, before the step of applying the protective layer 107 on the active side 1001 of the wafer, the active side 1001 of the wafer and/or the side of the wafer 100 to which the protective layer 107 is applied are subjected to a physical and/or chemical treatment in order to make the bond between the protective layer 107 and the wafer 100 tighter. The treatment method may optionally be a plasma surface treatment to roughen the surface to increase the adhesion area and/or a chemical modifier promoting treatment to introduce modifying promoting groups between the wafer 100 and the protective layer 107, such as surface modifiers with both organic and inorganic affinity groups to increase the adhesion between the organic/inorganic interface layers.

As shown in fig. 3b, a passivation opening 109 is formed on the surface of the passivation layer 107.

Protective layer openings 109 are formed in the protective layer 107 at locations corresponding to the electrical connection points 103 on the active side 1001 of the wafer to expose the electrical connection points 103 on the active side 1001 of the wafer.

Preferably, there is a one-to-one correspondence between the resist openings 109 and the electrical connection points 103 on the active side 1001 of the wafer.

Optionally, each protective layer opening 109 of at least a portion of the protective layer openings 109 corresponds to a plurality of electrical connection points 103.

Optionally, at least a portion of the electrical connection points 103 correspond to the plurality of protective layer openings 109.

Optionally, at least a portion of the protective layer openings 109 do not have corresponding electrical connection points 103, or at least a portion of the electrical connection points 103 do not have corresponding protective layer openings 109.

And forming a protective layer opening by adopting a laser patterning or photoetching patterning mode.

If the resist opening is formed by laser patterning, an electroless plating process is preferably performed on the active side 1001 of the wafer to form a conductive coating on the electrical connection points 103 before the resist 107 is applied to the active side 1001 of the wafer. Optionally, the conductive coating is one or more layers of Cu, Ni, Pd, Au, Cr; preferably, the conductive protective layer is a Cu layer; the thickness of the conductive protective layer is preferably 2 to 3 μm. The conductive coating is not shown in the figures. The conductive cap layer can protect the electrical connection points 103 on the active side 1001 of the wafer from laser damage during the subsequent protective layer opening formation step.

Preferably, as shown in the partially enlarged view in fig. 3b, there is a gap between the lower surface 109a of the protective layer opening and the insulating layer 105, and preferably, the lower surface 109a of the protective layer opening is located at a position near the center of the electrical connection point 103.

In a preferred embodiment, the shape of the passivation opening 109 is such that the area of the upper surface 109b of the passivation opening is larger than the area of the lower surface 109a of the passivation opening, and the ratio of the area of the lower surface 109a of the passivation opening to the area of the upper surface 109b of the passivation opening is 60% to 90%.

At this time, the slope of the sidewall 109c of the opening of the protection layer may facilitate the filling of the conductive material, and the conductive material may be uniformly and continuously formed on the sidewall during the filling process.

Alternatively, the protective layer opening 109 may not be formed temporarily, and the protective layer opening 109 may be formed on the protective layer after the carrier is peeled off.

Optionally, the passivation layer opening 109 is filled with a conductive dielectric, such that the passivation layer opening 109 becomes the conductive filled via 124. At least a portion of the conductively filled vias 111 connect with electrical connection points 103 on the active side 1001 of the wafer. Such that the conductively filled vias 111 extend the electrical connection points 103 on the active side 1001 of the wafer uni-directionally to the surface of the protective layer that is formed around the conductively filled vias 111. The conductive medium may be gold, silver, copper, tin, aluminum, or combinations thereof, or other suitable conductive materials may be formed in the protective layer opening 109 by PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition process to form the conductively filled via 111.

Fig. 4a-4c show an alternative process step of applying the protective layer 107 on the active side 1001 of the wafer:

as shown in fig. 4a, a wafer conductive layer 130 is formed on the wafer active side 1001.

The wafer conductive layer 130 is a wafer conductive trace (wafer trace) 106. The wafer conductive traces 106 may be copper, gold, silver, tin, aluminum, or combinations thereof, or may be formed from other suitable conductive materials using PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process.

At least a portion of the wafer conductive traces 106 are connected to at least a portion of the electrical connection points 103 on the wafer active side 1001.

Optionally, wafer conductive traces 106 interconnect and lead out a plurality of electrical connection points 103 in at least a portion of the wafer active side 1001, and the die formed thereby is shown in die diagram a of fig. 6 b.

The formation of the wafer conductive traces 106 can reduce the number of protective layer openings 109 to be formed later in the process, and the plurality of electrical connection points 103 are first interconnected with each other by the wafer conductive traces 106 according to the circuit design, thereby eliminating the need to form a protective layer opening 109 on each electrical connection point 103.

Optionally, the wafer conductive traces 106 individually lead out at least a portion of the electrical connection points 103 on the wafer active side 1001, and the die formed thereby is shown in the die diagram B in fig. 6B.

The formation of the wafer conductive traces 106 helps to reduce the difficulty of the subsequent formation process of the protective layer openings 109. due to the presence of the wafer conductive traces 106, the protective layer opening lower surfaces 109a can be made to have a larger area, and correspondingly, the protective layer openings 109 can be made to have a larger area, especially on the wafer 100 having the less exposed electrical connection points 103, making the formation of the protective layer openings possible.

Although not shown in the figures, it is understood that the wafer conductive traces 106 individually lead out a portion of the electrical connection points 103 on the wafer active side 1001 and interconnect and lead out another portion of the electrical connection points 103 on the wafer active side 1001 to each other.

As shown in fig. 4b, a protective layer 107 is applied over the wafer active side 1001 and the wafer conductive layer 130.

In one embodiment, the protective layer 107 is applied by lamination.

Optionally, the active side 1001 of the wafer and/or the side of the wafer to which the protective layer 107 is applied to the wafer 100 are physically and/or chemically treated prior to the step of applying the protective layer 107 to make the bond between the protective layer 107 and the wafer 100 tighter. The treatment method may optionally be a plasma surface treatment to roughen the surface to increase the adhesion area and/or a chemical modifier promoting treatment to introduce modifying promoting groups between the wafer 100 and the protective layer 107, such as surface modifiers with both organic and inorganic affinity groups to increase the adhesion between the organic/inorganic interface layers.

As shown in fig. 4c, a passivation opening 109 is formed on the surface of the passivation layer 107.

At least a portion of the passivation opening 109 is positioned to correspond to the wafer conductive layer 130, and the wafer conductive layer 130 is exposed through the passivation opening 109; the resist opening 109 has a resist opening lower surface 109a and a resist opening upper surface 109 b.

In a preferred embodiment, the shape of the passivation opening 109 is such that the area of the upper surface 109b of the passivation opening is larger than the area of the lower surface 109a of the passivation opening, and the slope of the sidewall 109c of the passivation opening facilitates the filling of the conductive material, which is formed on the sidewall uniformly and continuously during the filling process.

Preferably, the contact area of the wafer conductive layer 130 with a single contact area of the electrical connection point 103 is smaller than the contact area of the wafer conductive layer 130 with a single contact area of the protective layer opening 109.

When the type of the wafer 100 is such that the area of the exposed electrical connection point 103 is small, a conductive layer is formed on the active surface 1001 of the wafer, and then a passivation opening is formed, so as to effectively reduce the difficulty in forming the passivation opening and prevent the passivation opening 109 from being difficult to form due to the undersize of the lower surface 109a of the passivation opening.

Optionally, a conductive medium is filled in the passivation opening 109, so that the passivation opening 109 becomes a conductive filled via 124, at least a portion of the conductive filled via 124 is connected to the wafer conductive layer 130, and the passivation layer surrounds the conductive filled via 124.

Fig. 5a to 5c show yet another optional process step of applying a protective layer 107 to the active side 1001 of the wafer.

As shown in fig. 5a, a wafer conductive trace (wafer trace)106 is formed on the wafer active side 1001.

The wafer conductive traces 106 may be copper, gold, silver, tin, aluminum, or combinations thereof, or may be formed from other suitable conductive materials using PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process.

The at least a portion of the die conductive traces 106 may be routed to interconnect and electrically connect the plurality of electrical connection points 103 in at least a portion to one another.

The at least a portion of the wafer conductive traces 106 may also be used to individually lead out at least a portion of the electrical connection points 103, and the die formed thereby is shown in the die diagram B of fig. 6 c.

As shown in fig. 5b, a wafer conductive stud (waferstud)111 is formed on the pad or connection point of the wafer conductive trace 106.

The shape of the wafer conductive stud 111 may be circular, or may be other shapes such as oval, square, linear, etc. Wafer conductive posts 111 may be one or more layers of copper, gold, silver, tin, aluminum, etc., or combinations thereof, or may be formed of other suitable conductive materials by utilizing PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process.

Alternatively, the wafer conductive pillars 111 may also be directly formed at the electrical connection points 103 on the wafer active surface 1001, and the electrical connection points 103 are led out, so as to form a die, see a die diagram C in fig. 6C.

Wafer conductive traces 106 and/or wafer conductive posts 111 are referred to as wafer conductive layers 130.

As shown in fig. 5c, a protective layer 107 is applied over the wafer conductive layer 130.

The passivation layer 107 is applied on the conductive layer 130 of the wafer to cover the conductive layer 130 of the wafer.

In one embodiment, the protective layer is applied by lamination.

In one embodiment, the protective layer 107 is applied such that the protective layer 107 completely covers the conductive layer 130 of the wafer, in which case, after the protective layer 107 is applied, the protective layer 107 is thinned to expose the conductive layer surface of the wafer.

In another embodiment, the protective layer 107 is applied to a thickness that exposes just the surface of the wafer conductive layer 130.

Optionally, before the step of applying the protective layer 107, the active side 1001 of the wafer on which the conductive layer 130 of the wafer is formed and/or the side of the wafer 100 to which the protective layer 107 is applied are subjected to a physical and/or chemical treatment to make the bond between the protective layer 107 and the wafer 100 tighter. The treatment method may optionally be a plasma surface treatment to roughen the surface to increase the adhesion area and/or a chemical modifier promoting treatment to introduce modifying promoting groups between the wafer 100 and the protective layer 107, such as surface modifiers with both organic and inorganic affinity groups to increase the adhesion between the organic/inorganic interface layers.

Step S2, in the process of applying the protective layer 107 on the wafer active surface 1001, the protective layer 107 may protect the die active surface 1131 from the penetration of the plastic molding material during the plastic molding process, thereby protecting the die active surface 1131 from being damaged; meanwhile, in the plastic packaging process, the position of the bare chip 113 on the carrier plate 117 is not easily moved by the plastic packaging pressure; in addition, the requirement for alignment accuracy in the subsequent panel-level conductive layer forming process can be reduced.

The protective layer 107 is formed by lamination (coating), coating (coating), printing (printing), etc., using an insulating material such as BCB benzocyclobutene, PI polyimide, PBO polybenzoxazole, a polymer matrix dielectric film, an organic polymer film, or other materials having similar insulating and structural characteristics.

Preferably, the young's modulus of the protective layer 107 is in the range of 1000 to 20000MPa, and more preferably, the young's modulus of the protective layer 107 is in the range of 1000 to 10000 MPa; further preferably, the Young's modulus of the protective layer 107 is 1000 to 7000, 4000 to 7000 or 4000 to 8000 MPa; the young's modulus of the protective layer 107 in the most preferred embodiment is 5500 MPa.

Preferably, the thickness of the protective layer 107 is in the range of 15 to 50 μm; more preferably, the thickness of the protective layer is in the range of 20 to 50 μm; in a preferred embodiment, the thickness of the protective layer 107 is 35 μm; in another preferred embodiment, the thickness of the protective layer 107 is 45 μm; in a further preferred embodiment, the thickness of the protective layer 107 is 50 μm.

When the Young's modulus of the protective layer 107 is in the range of 1000-; on the other hand, the protective layer may provide sufficient supporting force to allow the protective layer 107 to have sufficient support for the conductive layer formed on the surface thereof. Meanwhile, the thickness of the protective layer 107 is 15-50 μm, which ensures that the protective layer 107 can provide sufficient cushioning and support.

Particularly, in some kinds of chips, it is required to use a thin die for packaging, and the conductive layer has a certain thickness to form a large electric flux, in this case, the thickness of the protection layer 107 is selected to be 15-50 μm, and the Young's modulus of the protection layer 107 is selected to be 1000-10000 MPa. The soft and flexible protection layer 107 can form a buffer layer between the die 113 and the conductive layer formed on the surface of the protection layer, so that the conductive layer on the surface of the protection layer does not excessively press the die 113 during the use of the chip, and the die 113 is prevented from being broken by the pressure of the thick conductive layer. While the protective layer 107 has sufficient material strength, the protective layer 107 may provide sufficient support for a massive conductive layer.

When the young's modulus of the protection layer 107 is 1000-.

The die transfer process is a process (interconnection process) of rearranging and bonding the cut and separated die 113 to the carrier plate 117, and the die transfer process requires a die transfer apparatus (binder machine) including a lift pin for lifting up the die 113 on the wafer 100, and a suction head (binder head) for sucking up the lifted die 113 and transferring and bonding the die 113 to the carrier plate 117.

In the process of jacking up the bare chip 113 by the ejector pin, the bare chip 113, especially the thin bare chip 113, is brittle and is easy to be broken by the jacking pressure of the ejector pin, and the protective layer 107 with material characteristics can protect the brittle bare chip 113 and keep the integrity of the bare chip 113 even under the higher jacking pressure.

Preferably, the protective layer 107 is an organic/inorganic composite layer including filler particles. Further, the filler particles are inorganic oxidesParticles; further, the filler particles are SiO₂Particles; in one embodiment, the filler particles in the protective layer 107 are two or more different types of inorganic oxide particles, such as SiO₂Mixed TiO₂And (3) granules. Preferably, the filler particles in the protective layer 107, e.g. inorganic oxide particles, e.g. SiO₂Particles, e.g. SiO₂Mixed TiO₂The particles are spherical or ball-like. In a preferred embodiment, the filler particles in the protective layer 107, such as inorganic oxide particles, e.g. SiO₂Particles, e.g. SiO₂Mixed TiO₂The filling amount of the particles is more than 50%.

The organic material has the advantage of easy operation and application, the bare chip 113 to be packaged is made of an inorganic material such as silicon, and when the protective layer 107 is made of an organic material alone, the packaging process is difficult due to the difference between the material properties of the organic material and the inorganic material, which affects the packaging effect. By adopting the organic/inorganic composite material with inorganic particles added in the organic material, the material properties of the organic material can be modified, and the material has the characteristics of both the organic material and the inorganic material.

In particular, the Coefficient of Thermal Expansion (CTE) of the material, the silicon material die 113 has a low CTE, typically around 3ppm/K, and the protective layer 107 is an organic/inorganic composite layer including filler particles, which can reduce the CTE of the protective layer and reduce the difference between the properties of the organic layer and the inorganic layer in the package structure.

In a preferred embodiment, the protective layer 107 has a coefficient of thermal expansion in the range of 3 to 10ppm/K when (T < Tg); in a preferred embodiment, the protective layer 107 has a coefficient of thermal expansion of 5 ppm/K; in a preferred embodiment; the thermal expansion coefficient of the protective layer 107 was 7 ppm/K; in a preferred embodiment, the protective layer 107 has a coefficient of thermal expansion of 10 ppm/K.

In the next plastic packaging process, the bare chip 113 applied with the protective layer 107 expands and contracts correspondingly in the heating and cooling processes in the plastic packaging process, when the thermal expansion coefficient of the protective layer 107 is in the range of 3-10 ppm/K, the expansion and contraction degrees between the protective layer 107 and the bare chip 113 are kept relatively consistent, the connecting interface between the protective layer 107 and the bare chip 113 is not easy to generate interface stress, the combination between the protective layer 107 and the bare chip 113 is not easy to break, and the packaged chip structure is more stable.

The packaged chip is required to undergo cold and heat cycles frequently in the use process, the thermal expansion coefficient range of the protective layer 107 is 3-10 ppm/K, the thermal expansion coefficient range of the protective layer 107 is the same as or similar to that of the bare chip 113, the protective layer 107 and the bare chip 113 keep relatively consistent expansion and contraction degrees in the cold and heat cycles, interface fatigue is prevented from being accumulated on the interface between the protective layer 107 and the bare chip 113, the packaged chip has durability, and the service life of the chip is prolonged.

On the other hand, if the thermal expansion coefficient of the protective layer is too small, too many filler particles need to be filled in the composite material of the protective layer 107, and the young's modulus of the material is increased while the thermal expansion coefficient is further reduced, so that the flexibility of the material of the protective layer is reduced, the rigidity is too strong, and the buffer effect of the protective layer 107 is not good enough. The thermal expansion coefficient of the protective layer is optimally defined to be 5 to 10 ppm/k.

When the step of forming the opening of the protective layer by laser patterning is included, it is preferable that the filler particles in the protective layer 107, for example, inorganic oxide particles such as SiO, are present₂The particles have a diameter of less than 3 μm, and preferably the filler particles, such as inorganic oxide particles, e.g. SiO2 particles, in the protective layer 107 have a diameter of between 1 and 2 μm.

The diameter of the filler particles is controlled to be smaller than 3 μm, which is beneficial to forming a protective layer opening with a smoother side wall on the protective layer 107 in the laser patterning process, so that the material can be fully filled in the conductive material filling process, and the conductive material cannot be filled on the rear side of the side wall with the protrusion shielding side wall of the protective layer opening 109c with large size unevenness, which affects the conductive performance of the conductive filling through hole 124.

Meanwhile, the filling size of 1-2 μm can expose the filler with small particle size in the laser patterning process, so that the side wall 109c of the opening of the protective layer has certain roughness, the side wall with certain roughness can be in larger contact with the conductive material, the contact is tighter, and the conductive filling through hole 124 with good conductivity is formed.

The above-mentioned diameter size of the filler is an average value of the particle diameter.

Optionally, the tensile strength of the protective layer 107 is 20 to 50 MPa; in a preferred embodiment, the tensile strength of the protective layer 107 is 37 MPa.

Optionally, after the process of applying the protective layer 107 on the active surface 1001 of the wafer, the back side 1002 of the wafer is ground to thin the wafer 100 to a desired thickness.

Modern electronic devices are small and light, and chips tend to be thin, in this step, the wafer 100 sometimes needs to be thinned to a very thin thickness, however, the thin wafer 100 has great processing and transferring difficulty, and the grinding and thinning process has great process difficulty, and it is often difficult to thin the wafer 100 to a desired thickness. When the surface of the wafer 100 has the protective layer 107, the protective layer 107 having material properties can support the wafer 100, thereby reducing the difficulty in processing, transferring and thinning the wafer 100.

In step S3, the wafer 100 applied with the protective layer 109 is cut to form the die 113 having the protective layer 109.

As shown in fig. 6a, the wafer 100 with the protective layer 107 applied thereon is diced along dicing streets to obtain a plurality of dies 113 with protective layers formed thereon, wherein the dies 113 have die active surfaces 1131 and die back surfaces 1132.

As shown in fig. 6b, the wafer 100 formed with the wafer conductive layer 130 and the protective layer opening 109 formed by applying the protective layer 107 is diced along dicing streets to obtain a plurality of dies 113, wherein the dies 113 have a die active surface 1131 and a die back surface 1132.

In fig. 6b, a die diagram a shows a wafer conductive trace 106 interconnecting and leading out a plurality of electrical connection points 103 on the die active surface 1131.

The die diagram B in fig. 6B shows the individual lead-outs of the electrical connection points 103 on the die active surface 1131 by the wafer conductive traces 106.

As shown in fig. 6c, the wafer 100 formed with the wafer conductive layer 130 and the applied protective layer 107 is cut along the dicing streets to obtain a plurality of dies 113, and the dies 113 have a die active surface 1131 and a die back surface 1132.

In fig. 6c, a die diagram a shows a wafer conductive trace 106 interconnecting and leading out a plurality of electrical connection points 103 on the die active surface 1131.

The die diagram B in fig. 6c shows the individual lead-outs of the electrical connection points 103 on the die active surface 1131 by the wafer conductive traces 106.

In fig. 6C, a die diagram C shows that the wafer conductive posts 111 are directly formed on the electrical connection points 103 on the wafer active surface 1001, and the electrical connection points 103 are led out.

Optionally, before the step of separating the bare chip 113 by cutting the wafer 100, the step of performing plasma surface treatment on the surface of the wafer 100 with the protective layer 107 applied thereon to increase surface roughness, so that the adhesion of the bare chip 113 on the carrier plate 117 in the subsequent process is increased, and the bare chip 113 is not easily moved under the molding pressure.

Due to the material properties of the protective layer, the separated die 113 is free of burrs and chips (die chips) during the dicing process of the wafer 100.

It is understood that, where the process allows, after optionally cutting the wafer 100 into dies 113 to be packaged according to specific practical situations, the wafer conductive layer 130 and/or the protective layer 107 is formed on the die active surface 1131 of each die 113. The wafer conductive layer 130 refers to a conductive layer formed before the die 113 cut from the wafer 100 is attached to the carrier board.

Step S4, providing a metal structure.

According to the embodiment shown in fig. 7, the metal structure is a metal frame 200, the metal frame 200 being made up of an array of metal cells. The metal frame 200 may be a lead frame existing in the industry, or may be formed by etching or mechanically stamping a piece or a block of metal according to actual requirements. The metal to be patterned may be a single metal, such as copper, or an alloy. The metal surface may be partially or completely coated with a second metal, such as nickel and/or gold, to protect the metal sheet from environmental attack, such as oxidation. The thickness of the metal is not less than the thickness of the die 113. The metal to be patterned may be rectangular, or may also be square or in other shapes, as shown in fig. 7, the metal is patterned to include 4 same metal units, the outer contour of each metal unit is rectangular, and here, it is also exemplary that the number of the metal units is not limited to 4, and may be set according to actual needs, the shape of the metal units may also be rectangular or in other shapes, the hollow white area of the metal unit indicates that the metal is completely etched away, the remaining metal portion includes metal features, and different metal features may bring different performance improvements.

In fig. 7, the metal features comprise at least one connection pad 201, and these connection pads 201 are arranged inside the outline edge of the metal frame 200, and may be arranged at other positions according to actual needs, and the connection pads 201 are connected by a metal connecting rod 203 which is not etched away. The connection pads 201 correspond to the leads of the packaged die, and according to the present disclosure, after the packaged die 113 is packaged, the connection pads 201 are exposed, and the packaged die 113 is soldered to the circuit board through the connection pads 201 to realize connection with other circuit elements. The connecting rod 203 is retained during the metal patterning process to ensure that the connecting pads 201 and other features formed during the patterning process are connected to the outer contour of the metal frame 200, so that the features patterned on the metal frame 200 can be prevented from falling off during the metal frame transfer process. Alternatively, the metal sheet may be attached to the temporary support and patterned, and the support may be used to transfer the position of the metal frame after patterning is completed, in a manner that does not require patterning connection wires/links.

As shown in fig. 7, each metal unit in metal frame 200 includes a void 202, which void 202 is shown as a blank area, and the blank area is formed by etching a portion of the metal completely, and has an area larger than the surface area of die 113, so that die 113 and metal frame 200 are not contacted by die 113 when they are attached to a carrier board in a later step. According to the example in the figure, each metal unit includes one void 202, in further examples, a metal unit may also include two or more voids 202, each void 202 housing one or more dies 113. The adjacent metal frames 200 have a common outer contour edge, as shown in fig. 7, the metal frame 200 at the upper left corner and the metal frame 200 at the right and lower sides thereof have a common outer contour edge, so that all the metal frames 200 are connected into a whole.

The metal frame 200 of the present disclosure shown in fig. 7 is only exemplary, and the area of the whole metal block may be the same as the surface area of the carrier plate 117, and the shape is also the same as the shape of the carrier plate 117, and is preferably rectangular or oblong, but may be designed into other shapes according to actual needs. However, in the experimental process, it is found that when the area of the carrier plate 117 is relatively large, if the metal frame 200 is etched using the same large metal as the carrier plate 117, since the metal is relatively thin, when the area is relatively large, deformation is easily caused during the transfer process, and the operation is not easy. Therefore, preferably, two or more pieces of metal having the same area as the surface area of the carrier plate 117 may be used, and one or more metal frames 200 may be etched on each piece of metal, and each piece of metal after etching is sequentially disposed on the carrier plate 117 during the manufacturing process, and is pieced together to have the same surface area as the carrier plate 117.

In step S5, the die 113 with the protective layer 107 and the metal structure are disposed on the carrier board 117.

Fig. 8 a-9 show a preferred embodiment of providing a metal frame onto a carrier board in step S5.

Since the metal frame 200 is made of a thin metal material, and particularly when the area is large, the surface is easy to bend and deform during picking and placing, in order to more conveniently and accurately adhere the metal frame 200 to the carrier plate 117 in a planar state, the following method may be adopted:

as shown in fig. 8a and 8b, a temporary support plate 300 is provided, an adhesive layer 301 is formed on the surface of the temporary support plate 300, and the patterned metal frame 200 is attached to the temporary support plate 300 by means of adhesion, alternatively, the temporary support plate 300 may not be used, and the thick adhesive layer 301 may be directly used as the temporary support plate 300 to transport the patterned metal frame 200. Preferably, the temporary support plate 300 and the adhesive layer 301 are identical in shape and size to the carrier plate 117.

Preferably, as shown in fig. 8a, after the metal frame 200 is adhered to the temporary support plate 300, the link 203 is cut to separate the metal frame 200. Alternatively, each of the links 203 connecting the respective metal units is cut, whereby the respective metal units adhered to the temporary support plate 300 are separated from each other; the metal frame 200 on the entire temporary support plate 300 may be divided into two, four, six, or any other number of parts for cutting the link 203 of a specific area. Preferably, the cut line is along the midline of the linkage 203. The method has the advantages that: in the packaging process, it is often necessary to go through heating and cooling steps to separate an entire metal frame 200 into smaller-area units or directly into metal units separated from each other, so that in the heating and cooling steps of the packaging, the smaller-area metal frame 200 or metal units expand and contract independently of each other, and the degree of expansion and contraction of each unit or unit is small due to the smaller area, making the packaging process easier to control and operate.

Preferably, as shown in fig. 8b, after the metal frame 200 is adhered to the temporary support plate 300, the connecting rods 203 are separated and removed from the metal frame 200, thereby separating the metal units in the metal frame 200, which is embodied as the connection pads 201 as separate parts from each other in fig. 8 b. Since the features (features) on the metal frame can be independent of each other, board level testing can be performed before cutting, which can greatly reduce testing cost and time.

As shown in fig. 9, a carrier board 117 is provided, the carrier board 117 having a carrier board front side 1171 and a carrier board back side 1172. The shape of the carrier plate 117 is: the carrier 117 may be a small wafer substrate or a rectangular carrier with various sizes, especially large sizes, and the material of the carrier 117 may be metal, nonmetal, plastic, resin, glass, stainless steel, etc. Preferably, the carrier plate 117 is a large-size quadrilateral panel made of stainless steel.

The carrier board 117 has a carrier board front side 113 and a carrier board back side 115, and the carrier board front side 113 is a plane.

The die 113 is bonded and fixed to the carrier board 117 by an adhesive layer 121.

The adhesive layer 121 may be formed on the carrier plate front side 1171 by lamination, printing, spraying, coating, etc. In order to facilitate separation of the carrier board 117 and the die 113 subjected to back mold sealing in the subsequent process, the adhesive layer 121 is preferably made of a material that is easily separable, for example, a thermal separation material.

The metal frame 200 may be attached to the adhesive layer 121 by aligning and contacting the temporary support plate 300 with the surface of the metal frame 200 attached thereto facing the carrier front side 1171, the surface of the temporary support plate 300 having the same surface area and shape as the carrier plate 117, and then peeling off the temporary support plate 300 and removing the adhesive layer 301 on the metal frame 200, thereby completing the attachment of the metal frame 200.

In this step, it is preferable that the metal frame 200 is aligned to the carrier plate 117 by an alignment mark (the mark is not shown in the drawing) formed in advance on the carrier plate 117 and the metal frame 200, and the metal frame 200 is adhered to the carrier plate 117 by the adhesive layer 301.

Alternatively, a metal foil or a metal sheet may be attached to the temporary support plate 300 through the adhesive layer 301 on the temporary support plate 300, and then the metal foil or the metal sheet may be etched into a desired pattern to form the patterned metal frame 200, and then the metal frame 200 may be transferred onto the carrier plate 117.

The side of the metal frame 200 facing the carrier 117 is defined as the front side of the metal frame, and the side facing away from the carrier 117 is defined as the back side of the metal frame. The metal structure front side and the metal structure back side, the metal unit front side and the metal unit back side, the metal feature front side and the metal feature back side are also defined as such.

Fig. 10 shows an embodiment in which the die 113 is disposed on the carrier board 117 in step S5.

Since the metal frame 200, which is represented as the connection pad 201 in fig. 10, is already attached to the adhesive layer 121 on the front side 1171 of the carrier board, when the die 113 is continuously attached, it is ensured that the die 113 does not contact the metal frame 200, in this disclosure, the die 113 is attached to the vacant site 202 of the metal frame 200, and optionally one vacant site 202 corresponds to one die 113 or one vacant site 202 corresponds to a plurality of dies 113. Preferably, the carrier board 117 is provided with position marks for arranging the bare chip 113, the marks can be formed on the carrier board 117 by laser, mechanical patterning, and the like, and the bare chip 113 is also provided with alignment marks for aiming at the pasting position on the carrier board 117 during pasting. Fig. 10 is an exemplary view only, and fig. 10 shows only a bare chip 113 pasted on the adhesive layer 121 of the carrier board 117 in the form of the bare chip 113 with the protective layer 107 and the protective layer opening as shown in fig. 6 a; the die attached to the adhesive layer 121 of the carrier board 117 may also be in the form of a die with the wafer conductive layer 130 and the protective layer 107 and the protective layer opening 109 as shown in fig. 6b, or in the form of a die with the wafer conductive layer 130 and the protective layer 107 as shown in fig. 6 c. Meanwhile, the metal frame 200 adhered on the adhesive layer 121 may also be a metal frame 200 that is only cut without removing the link 203 as shown in fig. 8a, or may also be a metal frame 200 having the link 203 intact.

As shown in fig. 10, one metal unit corresponds to one bare chip 113, the number of the bare chips 113 on the carrier board 117 is the same as the number of the metal units on the carrier board 117, and the arrangement of the bare chips 113 corresponds to the arrangement of the metal units on the carrier board 117. The number and arrangement of the metal units are not limited to the arrangement shown in fig. 10, but can be customized according to actual needs.

In addition, one metal unit may correspond to a plurality of bare chips 113, the plurality of bare chips 113 are placed in a predetermined empty space 202, and particularly, the plurality of bare chips are a plurality of bare chips with different functions, arranged in the metal unit on the carrier plate 117 according to the requirements of actual products, packaged, and cut into a plurality of packages after the packaging is completed; whereby one package body includes a plurality of dies to form a multi-chip module (MCM), and the positions of the plurality of dies can be freely set according to the needs of an actual product.

The mounting sequence shown in fig. 9-10 is to mount the metal frame 200 onto the carrier plate 117 first and then mount the die 113 onto the carrier plate 117, but this is merely exemplary and it is also possible to mount the die 113 onto the carrier plate 117 first and then mount the metal frame 200 onto the carrier plate 117.

In step S6, a molding layer 123 is formed on the carrier board 117.

As shown in fig. 11, a molding layer 123 is covered on the entire carrier 117 for encapsulating the entire die 113 and the metal frame 200, which are represented as connection pads 201 in fig. 11, to reconstruct a flat plate structure, so that after the carrier 117 is peeled off, the next packaging step can be continued on the reconstructed flat plate structure.

The side of the molding layer 123 in contact with the carrier front side 1171 or the adhesive layer 121 is defined as a molding layer front side 1231. The side of the molding layer 123 facing away from the carrier front side 1171 or the adhesive layer 121 is defined as a molding layer back side 1232.

Preferably, the front molding layer 1231 and the back molding layer 1232 are substantially flat and parallel to the front carrier 1171.

The molding layer 123 may be formed by paste printing, injection molding, hot press molding, compression molding, transfer molding, liquid sealant molding, vacuum lamination, or other suitable forming methods. The molding layer 123 may be an organic composite material, a resin composite material, a polymer composite material, such as an epoxy resin with a filler, abf (ajinomotobuildup film), or other polymer with a suitable filler.

In one embodiment, the molding layer 123 is formed by molding an organic/inorganic composite material.

Optionally, before forming the molding compound layer 123, some pretreatment steps, such as chemical cleaning and plasma cleaning, may be performed to remove impurities on the surfaces of the die 113 and the metal frame 200, so that the connections between the molding compound layer 123 and the die 113, the metal frame 200 and the carrier board 117 can be more intimate and no delamination or cracking occurs.

Preferably, the thermal expansion coefficient of the plastic packaging layer 123 is 3-10 ppm/K; the molding layer 123 has a coefficient of thermal expansion of 5ppm/K in a preferred embodiment; in another preferred embodiment the molding layer 123 has a coefficient of thermal expansion of 7 ppm/K; in yet another preferred embodiment the molding layer 123 has a coefficient of thermal expansion of 10 ppm/K.

Preferably, the molding layer 123 and the protective layer 107 have the same or similar thermal expansion coefficients.

The thermal expansion coefficient of the plastic package layer 123 is selected to be 3-10 ppm/K, the thermal expansion coefficient is selected to be the same as or similar to that of the protective layer 107, the expansion and contraction degrees between the protective layer 107 and the plastic package layer 123 are kept consistent in the heating and cooling processes of the plastic package process, interface stress is not easily generated between the two materials, the thermal expansion coefficients of the plastic package layer, the protective layer and the bare chip are close to each other due to the low thermal expansion coefficient, the interfaces of the plastic package layer 123, the protective layer 107 and the bare chip 113 are tightly combined, and interface layer separation is avoided.

The packaged chip is often required to undergo a cold-hot cycle in the use process, because the thermal expansion coefficients of the protective layer 107, the plastic packaging layer 123 and the bare chip 113 are similar, in the cold-hot cycle process, the fatigue of the interfaces of the protective layer 107, the plastic packaging layer 123 and the bare chip 113 is small, and an interface gap is not easy to occur between the protective layer 107, the plastic packaging layer 123 and the bare chip 113, so that the service life of the chip is prolonged, and the applicable field of the chip is wide.

The difference between the thermal expansion coefficients of the bare chip 113 and the molding layer 123 also causes warpage of the molded panel assembly, and due to the warpage, it is difficult to position the bare chip 113 at the precise position in the panel assembly in the subsequent conductive layer forming process, which greatly affects the conductive layer forming process.

In particular, in the large panel packaging process, since the size of the panel is large, even if the panel is slightly warped, the position of the die in the outer peripheral portion of the panel away from the center is changed in a large size before the die is molded, so that in the large panel packaging process, solving the warping problem becomes one of the keys of the whole process, and the warping problem even limits the enlargement development of the panel size, and becomes a technical barrier in the large panel packaging process.

The thermal expansion coefficients of the protective layer 107 and the plastic packaging layer 123 are limited within the range of 3-10 ppm/K, and preferably, the plastic packaging layer 123 and the protective layer 107 have the same or similar thermal expansion coefficients, so that the generation of panel assembly warping can be effectively avoided, and the packaging process adopting a large panel is realized.

Meanwhile, in the plastic package process, since the plastic package pressure can generate pressure towards the carrier plate 117 on the back of the bare chip 113, the bare chip 113 is easily pressed into the adhesive layer 121 by the pressure, so that the bare chip 113 is sunk into the adhesive layer 121 in the process of forming the plastic package layer 123, after the plastic package layer 123 is formed, the bare chip 113 and the front surface 1231 of the plastic package layer are not in the same plane, the surface of the bare chip 113 protrudes out of the front surface 1231 of the plastic package layer to form a step-shaped structure, and in the subsequent panel-level conductive layer forming process, the panel-level conductive layer correspondingly generates the step-shaped structure, so that the package structure is unstable.

When the die active surface 1131 has the protective layer 107 with material properties, the buffer effect can be achieved under the molding pressure, and the die 113 is prevented from sinking into the adhesive layer 121, so that the generation of the step-like structure on the front surface 1231 of the molding layer is avoided.

In order to expose the metal frame 200, the molding layer 123 needs to be thinned, and the molding layer front surface 1231 can be thinned by mechanical grinding or polishing, and the thickness of the molding layer 123 is thinned to the back surface of the metal frame 200, so as to expose the features of the surface of the metal frame 200. As shown in fig. 12, when the thickness of the metal frame 200 is thicker than that of the die 113, the molding compound layer may be further thinned to the back side of the die 113, and the back sides of the metal frame 200 and the die 113 are exposed.

In step S7, the carrier board 117 is peeled off to form the panel assembly 150.

After the carrier board 117 is peeled off, the protection layer 107 on the die active surface 1131, the lower surface of the metal frame 200 and the molding compound front surface 1231 are exposed.

After the carrier board 117 is separated, the molding layer 123 coated with the die 113 and the metal frame 200 is defined as the panel assembly 150.

In step S8, a panel-level conductive layer and a dielectric layer 129 are formed.

A panel-level conductive layer is formed on the surface of the protective layer 107, and is connected to the electrical connection points 103 on the die active surface 1131 through the wafer conductive layer 130 and/or the conductive filled vias 124, and is connected to the metal frame 200. A dielectric layer 129 is formed on the panel-level conductive layer, and the dielectric layer 129 is used for covering and protecting the panel-level conductive layer. The panel-level conductive layer and the dielectric layer 129 may be one layer or a plurality of layers.

As shown in fig. 13, the panel-level conductive layer is represented as a panel-level conductive trace 125(panel level trace), and since the conductive filled via 124 is not formed in the process flow shown in the figure, optionally, the conductive filled via 124 and the panel-level conductive trace 125 are performed in the same conductive layer forming step. The conductively filled vias 124 and panel level conductive traces 125 are formed using a patterned conductive layer formation process. The conductively filled vias 124 and the panel conductive traces 125 can be copper, gold, silver, tin, aluminum, or combinations thereof, or can be formed from other suitable conductive materials using PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition process.

At least a portion of the panel-level conductive traces 125 are connected to the electrical connection points 103 on the die active side 103 and to the connection pads 201 through the conductive filled vias 124 and the electrical connection points 103 on the die active side are routed to the connection pads 201 through the panel-level conductive traces 125 and the conductive filled vias 124.

The pattern traces of panel level conductive traces 125 in fig. 13 are merely exemplary, and the pattern traces of panel level conductive traces 125 are connected according to a particular circuit design.

Alternatively, the conductive filled vias 124 and the panel-level conductive traces 125 can be formed in steps, such that the conductive filled vias 124 are formed before the panel-level conductive traces 125 are formed.

When the conductive filled vias 124 have been formed in the previous protective layer application step, the panel-level conductive layer formation step can be performed directly.

When the protective layer opening 109 has not been formed in the previous protective layer applying step, a step of forming the protective layer opening 109 needs to be included.

As shown in fig. 14, a dielectric layer 129 is formed on the panel level conductive traces 125.

Dielectric layer 129 is formed on the surface of the panel level conductive layer using any suitable method such as lamination, coating, spraying, printing, molding, and the like.

The dielectric layer 129 may be BCB benzocyclobutene, PI polyimide, PBO polybenzoxazole, abf (ajinomoto build up film), silicon dioxide, silicon nitride, silicon oxynitride, tantalum pentoxide, aluminum oxide, polymer matrix dielectric film, organic polymer film; organic composites, resin composites, polymer composites, such as epoxy with fillers, ABF, or other polymers with suitable fillers; other materials having similar insulating and structural properties are also possible. In one preferred embodiment the dielectric layer 129 is ABF. The dielectric layer 129 serves to protect the conductive layer and to insulate.

As shown in fig. 14, the dielectric layer 129 is higher than the height of the panel-level conductive traces 125, and the dielectric layer 129 completely encapsulates the panel-level conductive traces 125.

Due to the existence of the protective layer 107, the step of forming the panel-level conductive layer can be directly performed after the plastic packaging process is finished, so that the step of forming the panel-level conductive layer after an insulating layer is formed after the plastic packaging process is finished is avoided.

The panel level conductive and dielectric layers 129 shown in fig. 13 and 14 have only one layer, but alternatively, the panel level conductive and dielectric layers may be multiple layers.

When the panel-level conducting layer and the dielectric layer are multilayer, the steps of forming the multilayer panel-level conducting layer and the dielectric layer are as follows:

forming a first layer of panel-level conductive traces on the surface of the protective layer, and forming first layer of panel-level conductive convex columns on the electrical connection points of the first layer of panel-level conductive traces for being connected with the first layer of panel-level conductive traces and leading out the first layer of panel-level conductive convex columns;

forming a first dielectric layer on the first layer of panel-level conductive traces and the first layer of panel-level conductive posts, and covering the first layer of panel-level conductive traces and the first layer of panel-level conductive posts and exposing the surfaces of the first layer of panel-level conductive posts;

and forming a second panel-level conductive trace connected with the first panel-level conductive post on the surface of the first dielectric layer, and completely coating the second panel-level conductive trace by using the second dielectric layer.

At this time, an encapsulation structure having two panel-level conductive layers and a dielectric layer is formed.

And by analogy, a packaging structure of a plurality of panel-level conducting layers and dielectric layers can be formed.

When the panel-level conductive layer and the dielectric layer are multilayered, the step of forming the multilayered panel-level conductive layer and the dielectric layer may further include:

forming a first layer of panel-level conductive traces on the surface of the protective layer;

forming a first dielectric layer on the first panel level conductive trace, wherein the thickness of the first dielectric layer is larger than that of the first panel level conductive trace, and the first dielectric layer completely covers the first panel level conductive trace;

forming an opening on the first layer of dielectric layer by using a laser patterning or photoetching mode, wherein the opening is formed on the electric connection point of the first layer of panel-level conductive trace, and the electric connection point of the first layer of panel-level conductive trace is exposed;

filling the openings with a conductive material and forming second-level panel-level conductive traces on the first-level dielectric layer and at corresponding locations of the filled openings;

and forming a second dielectric layer on the second layer of panel-level conductive traces, wherein the thickness of the second dielectric layer is thicker than that of the second layer of panel-level conductive traces, and the second layer of panel-level conductive traces are completely wrapped by the second dielectric layer.

When each metal unit of the metal frame 200 corresponds to a plurality of dies 113, especially a plurality of dies with different functions, the package becomes a multi-chip package assembly with metal features, and the pattern design of the panel-level conductive layers of the plurality of dies is designed according to the electrical connection requirements of the actual product. The structure of the packaged chip is shown in fig. 29 e.

In step S8, in the step of forming the panel-level conductive layer and the dielectric layer 129 on the surface of the protection layer 107 of the die 113, fig. 13 and 14 show that the die 113 as shown in fig. 6a is used for packaging, it is understood that the die as shown in fig. 6b can also be used for packaging, the protection layer opening 109 is filled with a conductive material to form a conductive filled via 124, at least a portion of the conductive filled via 124 is connected with the wafer conductive trace 106, the wafer conductive trace 106 is led out from the protection layer 107, and the panel-level conductive trace 125 is formed on the surface of the protection layer 107, preferably, the conductive filled via 124 and the panel-level conductive trace 125 are formed in the same metal layer forming step. At least a portion of the panel-level conductive traces 125 are connected to at least a portion of the conductive filled vias 124 and to at least a portion of the bonding pads 201 of the metal frame 200, and the electrical connection points 103 on the die active surface 1131 are routed to the bonding pads 201 of the metal frame 200 through the wafer conductive layer 130, the conductive filled vias 124 and the panel-level conductive traces 125, and then electrically connected to the outside through the bonding pads 201. It is understood that the die shown in fig. 6c may be packaged, a panel-level conductive trace 125 is formed on the surface of the protection layer 107, at least a portion of the panel-level conductive trace 125 is connected to the wafer conductive post 111 and at least a portion of the metal frame 200, and the electrical connection point 103 on the active surface 1131 of the die is led to the connection pad 201 of the metal frame 200 through the wafer conductive layer 130 and the panel-level conductive layer to be electrically connected to the outside.

In step S9, a plurality of chips 500 are cut and formed.

As shown in fig. 15, the packaged single body is cut to form a packaged chip, and the cutting can be performed by using a machine or a laser.

When the metal frame 200 to be plastically packaged is the metal frame 200 including the connecting rod 203 as shown in fig. 8a, when the metal frame 200 is cut and separated, the connecting rod 203 needs to be cut at the periphery of the connecting rod 203 to be removed, so that the packaged chip 500 formed by the completed package does not include the connecting rod, and thus each metal feature in the metal unit of the metal frame 200 is independent.

Preferably, before or after the dicing and separating step, a surface treatment layer 131 is optionally formed on the die back surface 1132 and/or the exposed metal frame surface by electroplating, electroless plating or other suitable methods. For example, nickel palladium gold plating (ENEPIG) and Tin plating (Tin) are used.

Optionally, the surface treatment layer 131 may also be configured to realize back grounding (backing) of the chip 500, that is, the surface treatment layer 131 electrically connects the die back surface 1132 and the back surface-grounding-specific connection pad 201 according to the specific design of the circuit (that is, the back surface-grounding-specific connection pad is connected to the back surface grounding electrical connection point on the die active surface through the conductive structure).

The difference between embodiment 2 and embodiment 1 of the present disclosure is mainly the structure of the metal frame 200, and other similar parts are not described again, and only the parts different from embodiment 1 are described in this embodiment.

Fig. 16 shows a structure diagram of a metal frame 200 in embodiment 2 of the present disclosure, in embodiment 1, on the basis that the metal feature of the metal frame 200 is a connection pad 201, in embodiment 2, the metal feature of the metal frame 200 further includes a heat dissipation structure for dissipating heat, the heat dissipation structure is embodied as a heat dissipation pad 207 in fig. 16, the area of the heat dissipation pad 207 may be as large as possible to improve the heat dissipation effect if conditions allow, the shape of the heat dissipation pad 207 is not limited to a rectangle as shown in the figure, a square or other shape may also be used, the number of the heat dissipation pads 207 is not limited to one, and may be two or more according to needs. In order to prevent the heat dissipation pad 207 from separating from the metal frame 200, one or more connecting rods 203 are reserved between the heat dissipation pad 207 and the outer contour of the metal frame 200 to ensure that the heat dissipation pad 207 is connected with the metal frame 200 during the transfer of the metal frame 200. If the metal frame 200 is formed after the metal is first fixed to the temporary support plate 300 in the manner described in embodiment 1, the link 203 does not need to be formed, which is also applicable in the present embodiment.

At the time of transferring the metal frame 200, the metal frame 200 may be conveyed using the temporary support plate 300 and/or the adhesive layer 301 in the manner as described in embodiment 1. After the metal frame 200 is adhered to the temporary support plate 300, the link 203 may be cut, the metal frame 200 may be separated, or the link 203 may be separated and removed from the metal frame 200, thereby separating the metal units in the metal frame 200.

The protective layer formation step in example 2 was: referring to fig. 3a-3b, a protective layer 107 is applied over the wafer active side 1001; a resist opening 109 is formed in the surface of the resist 107. At least a portion of the passivation layer opening 109 is formed at a location on the active side 1001 of the wafer corresponding to the electrical connection point 103 and/or at a heat dissipation location on the active side 1001 of the wafer, exposing the electrical connection point 103 and the heat dissipation location. The heat dissipation location may be at the electrical connection point 103, since there is often accumulated heat to be dissipated at the electrical connection point, fig. 3b only shows the case where the heat dissipation location is at the electrical connection point 103, however, fig. 3b is merely exemplary, and the heat dissipation location may be at other locations requiring heat dissipation besides the electrical connection point 103.

Preferably, there is a one-to-one correspondence between the resist openings 109 and the electrical connection points 103 and/or heat dissipation locations on the active side 1001 of the wafer.

Optionally, each protective layer opening 109 of at least a portion of the protective layer openings 109 corresponds to a plurality of electrical connection points 103 and/or heat dissipation locations.

Optionally, at least a portion of the electrical connection points 103 and/or the heat dissipation locations correspond to the plurality of protective layer openings 109.

Optionally, a conductive material is filled in the protective layer opening 109 to form a conductive filling through hole 124, which may be performed after the plastic molding process.

The step of forming the opening of the protective layer may also be performed after the plastic encapsulation process.

An alternative process step for applying the protective layer 107 to the active side 1001 of the wafer is illustrated in FIGS. 4a-4 c:

as shown in fig. 4a, a wafer conductive layer 130 is formed on the wafer active side 1001. The wafer conductive layer 130 is embodied as a wafer conductive trace 106 in fig. 4 a.

Optionally, wafer conductive traces 106 interconnect and lead out a plurality of electrical connection points 103 in at least a portion of the wafer active side 1001 to each other.

Optionally, the wafer conductive traces 106 individually exit at least a portion of the electrical connection points 103 on the wafer active side 1001.

At least a portion of the die conductive traces 106 correspond to at least a portion of the heat dissipation locations on the active side 1001 of the die.

Fig. 4a only shows the case where the heat dissipation position is at the electrical connection point 103, however, fig. 4a is merely exemplary, and the heat dissipation position may be at other positions requiring heat dissipation other than the electrical connection point 103.

As shown in fig. 4b, a protective layer 107 is applied over the wafer active side 1001 and the wafer conductive traces 106.

At least a portion of the resist opening 109 is positioned to correspond to the wafer conductive trace 106, exposing the wafer conductive trace 106 through the resist opening 109.

Optionally, the conductive material is filled in the protective layer opening 109 to form a conductive filled through hole 124, which may also be performed after the plastic molding process.

Still another optional process step for applying the protective layer 107 to the active side 1001 of the wafer is illustrated in fig. 5 a-5 c.

A wafer conductive layer 130 is formed on the wafer active surface 1001, and the wafer conductive layer 130 is a wafer conductive trace 106 and/or a wafer conductive stud 111.

As shown in fig. 5a, wafer conductive traces 106 are formed on the wafer active side 1001.

Fig. 5a only shows the case where the heat dissipation location is at the electrical connection point 103, however, fig. 5a is merely exemplary,

as shown in fig. 5b, a wafer conductive post 111 is formed on a pad or connection point of the wafer conductive trace 106.

In the protective layer forming step in embodiment 2, the forming methods and materials of the conductive layer and the protective layer, and the shapes and forming methods of the openings of the protective layer are the same as those in embodiment 1, and are not described again.

The wafer 100 to which the protective layer has been applied in the above-described manner is diced to form the dies 113.

Fig. 17 shows that a bare chip 113 and a metal frame 200 are arranged on a carrier board 117, and the steps of the arrangement are similar to the method described in embodiment 1. In fig. 17, the connecting rod 203 of the metal frame 200 is cut to separate the metal frame 200 into several parts, but the connecting rod 203 of the metal frame 200 is not removed, and optionally, the connecting rod 203 may be removed from the metal frame 200. The die 113 shown in fig. 17 is in the form of die 113 in fig. 6b including wafer conductive layer 130 and protective layer opening 109. Fig. 17 is merely an example, and the die 113 arranged on the carrier board 117 may be in the form of a die as shown in fig. 6a or fig. 6 c.

Fig. 18 shows that the plastic layer 123 is formed on the carrier plate 117 to encapsulate all the dies 113 and the metal frame 200, and a flat plate structure is reconstructed, then the plastic layer 123 is thinned to expose the metal frame 200, and the carrier plate 117 is peeled off to form the panel assembly 150, and the method and steps are also similar to those described in embodiment 1.

Fig. 19 illustrates the formation of a panel level conductive and dielectric layer 129.

A panel-level conductive layer is formed on the surface of the protection layer 107, and in fig. 19, the panel-level conductive layer is embodied as a panel-level conductive trace 125, and since the conductive filled via 124 is not formed in the process flow shown in the figure, the conductive filled via 124 connected to the wafer conductive trace 106 needs to be formed by filling the protection layer opening 109 with a conductive filling material, and optionally, the conductive filled via 124 and the panel-level conductive trace 125 are performed in the same conductive layer forming step.

At least a portion of the panel-level conductive traces 125 are connected to at least a portion of the wafer conductive traces 106 through the conductive filled vias 124 to connect with electrical connection points 1131 on the die active side 1131 and to connect with connection pads 201 in the metal unit, and the electrical connection points 103 on the die active side are connected to the connection pads 201 through the panel-level conductive traces 125 and the conductive filled vias 124 and the wafer conductive layer 130.

At least a portion of the panel-level conductive traces 125 are connected to at least a portion of the wafer conductive traces 106 via the conductively filled vias 124 to connect to heat-dissipating sites on the die active surface 1131 and to connect to the heat-dissipating pads 207 in the metal unit, since the conductive material of the metal is also a good conductor of heat, heat can be transferred to the heat-dissipating pads 207 via the wafer conductive layer 130, the conductively filled vias 124, and the panel-level conductive layer and dissipated to the outside via the heat-dissipating pads 207. Of course, it is understood that the heat dissipation position may be provided with only a heat conductive material, and the heat is transferred to the heat dissipation pad 207 by using the heat conductive material.

The pattern traces of panel level conductive traces 125 in fig. 19 are merely exemplary, and the pattern traces of panel level conductive traces 125 are connected according to a particular circuit design.

Next, a dielectric layer 129 is formed on the panel-level conductive layer.

The panel-level conductive layer and the dielectric layer 129 may be one layer or a plurality of layers.

The materials and the formation method of the panel-level conductive layer and the dielectric layer 129 are similar to those in embodiment 1.

Fig. 19 shows that in the formation step of the panel level conductive and dielectric layers 129, a die 113 as shown in fig. 6b is used for packaging, it being understood that the die shown in fig. 6a may also be used for packaging, and the protective layer opening 109 is filled with a conductive material to form a conductive filled via 124 connected to the electrical connection point 103 and/or the heat dissipation location; the panel-level conductive traces 125 are formed on the surface of the protection layer 107, at least a portion of the panel-level conductive traces 125 are connected to the conductive filling vias 124 corresponding to the electrical connection points 103 and are connected to at least a portion of the connection pads 201 of the metal frame 200, the electrical connection points 103 on the die active surface 1131 are led to the connection pads 201 of the metal frame 200 through the conductive filling vias 124 and the panel-level conductive traces 125, and then electrically connected to the outside through the connection pads 201. At least a part of the panel-level conductive traces 125 are connected to at least a part of the conductive filled vias 124 corresponding to a heat dissipation position, which may be the position of the electrical connection point 103 or another position other than the electrical connection point 103, and are connected to at least a part of the heat dissipation pad 207 of the metal frame 200, so as to dissipate heat to the outside through the heat dissipation pad 207. It will be appreciated that the die shown in figure 6c may also be used for packaging.

As shown in fig. 20, the packaged single body is cut to form a packaged chip, and the cutting can be performed by using a machine or a laser.

The metal frame 200 in fig. 20 includes the tie bars 203, and when the cutting and separating are performed, the cutting needs to be performed on the peripheries of the tie bars 203 to remove the tie bars 203, so that the packaged chip 500 formed by the package completion does not include the tie bars, and thus each metal feature in the metal unit of the metal frame 200 is independent.

Compared with embodiment 1, the solution of embodiment 2 can dissipate heat generated during the use of the chip in time by means of the heat dissipation pad 207 due to the addition of the heat dissipation pad 207 of the heat dissipation structure.

The difference between embodiment 3 and embodiment 1 of the present disclosure is mainly the structure of the metal frame 200, and other similar parts are not described again, and only the parts different from embodiment 1 are described in this embodiment.

The formation step of the protective layer 107 is similar to that in embodiment 1, and is not described again here.

Fig. 21 shows a structure diagram of a metal frame 200 in embodiment 3 of the present disclosure, where, on the basis that the metal feature of the metal frame 200 in embodiment 1 is a connection pad 201, in embodiment 3, the metal feature of the metal frame 200 further includes a heat dissipation structure for dissipating heat, and the heat dissipation structure is embodied as a back heat sink 205 in fig. 21, although not shown in the figure, alternatively, the heat dissipation structure may also be embodied as a back heat sink plus a heat dissipation pad. As shown in fig. 21, the back fin 205 is integrally connected to the metal frame 200 by the tie bars 203 to secure the back fin 205 to the metal frame 200 during the transfer of the metal frame 200. The back side heat spreader 205 is formed by half etching (or stamping) the metal, and may also be understood as a thinning from the lower surface of the metal, with the upper surface, i.e., the back side heat spreader 507, remaining during the etching (or stamping) process, and the lower surface removed to form a void area, which is the void 202 in which the die 113 is placed. The tie bars 203 that connect the back side heat spreader 205 and the metal frame 200 are not half-etched (or stamped) to the same thickness as the metal sheet, and the tie bars 203, in addition to connecting the back side heat spreader 205 and the metal frame 200, can support the back side heat spreader 205 when the back side heat spreader 205 is applied to the die back surface 1132, keeping it horizontal and not prone to tilting. The number of tie bars 203 connected to the back fin 205 is shown as 2 in fig. 21, but the number may alternatively be 4, i.e., the four corners of the back fin 205 are all connected to the tie bars 203, or any other number. When the die 113 is received in the void 202, the die back side 1002 and the back side heat sink 205 are in contact for heat dissipation.

Fig. 22 shows the die 113 arranged on the carrier plate 117 with the application of a thermally conductive material 209 on the die backside 1132, the die 113 being connected to the backside heat sink by the thermally conductive material 209, the thermally conductive material 209 preferably being in a liquid or paste-like position, reducing the interfacial resistance to heat transfer.

Fig. 23 shows the metal frame 200 bonded to the carrier board 117, the die backside 1132 connected to the backside heat sink 205 through the thermally conductive material 209, and the heat generated by the packaged chip during use dissipated to the outside through the thermally conductive material 209 and the backside heat sink 205. The process of applying the metal frame 200 to the carrier board 117 may also be transferred through a temporary support board as in embodiment 1.

Fig. 24 shows the step of applying the molding layer 123 and the step of forming the panel-level conductive layer and the dielectric layer 129, which are similar to those described in embodiment 1 and will not be described again.

Alternatively, depending on the specific design of the circuit, back grounding with the back heatsink 205 may be achieved by electrically connecting the back ground electrical connection point 103 on the active side of the die to the back heatsink 20 using conductive structures, embodied as wafer level conductive layers and panel level conductive layers in fig. 24.

Fig. 25 shows the packaged die formed by dicing the individual packages.

When the back grounding of the chip is not implemented by using the conductive structure, optionally, the surface processing layer 131 may also be configured to implement the back grounding of the chip 500 (i.e., the surface processing layer 131 electrically connects the back heat sink 205 and the connection pad 201 specifically connected to the back grounding according to the specific design of the circuit (i.e., the connection pad specifically connected to the back grounding is a connection pad connected to the back grounding electrical connection point on the active surface of the die by the conductive structure). At this point, the backside heat sink 205 is a material that can conduct electricity, such as a metal thermal paste, through a thermal conductive material 209 applied to the backside of the die.

The difference between embodiment 4 and embodiment 1 of the present disclosure is mainly that before the step of molding, a metal layer is formed on the back surface of the wafer, and other same parts are not described again, and only different parts from embodiment 1 are described in this embodiment.

Fig. 26 shows that in embodiment 4 of the present disclosure, the metal layer 210 is formed on the wafer back side 1002 of the wafer 100, and the metal layer 210 is optionally one or more layers of aluminum, tin, nickel, gold, silver, lead, bismuth, copper, and combinations thereof, preferably copper, and is formed by electroplating, electroless plating, sputtering, or other suitable methods.

The formation of the passivation layer 107 on the active surface 1001 of the wafer 100 is similar to that of embodiment 1, and will not be described herein. The wafer 100 formed with the metal layer 210 and the protection layer 107 is cut and separated into the dies 113 having the metal layer 210 and the protection layer 107.

Alternatively, the formation step of the metal layer 210 is performed after the formation step of the protective layer 107 or the dicing separation step.

The die 113 and the metal frame 200 are then arranged on the carrier board 117, and the molding layer 123 is formed on the carrier board 117.

Fig. 27 shows the formation of the molding layer 123 for encapsulating the die 113 and the metal frame 200 on the carrier board 117, and the formation of the panel-level conductive layer and the dielectric layer 129, which are similar to those described in embodiment 1 and are not described again. Fig. 27 is an exemplary view only, and fig. 27 shows only a die 113 in the form of a die 113 having a protective layer 107 and a protective layer opening as shown in fig. 6 a; the die 113 may also be in the form of a die having a wafer conductive layer 130 and a protective layer 107 and a protective layer opening 109 as shown in fig. 6b, or in the form of a die having a wafer conductive layer 130 and a protective layer 107 as shown in fig. 6 c. Meanwhile, the metal frame 200 may also be a metal frame having a heat dissipation pad 207. The metal layer surface of the die backside 1132 and the metal feature backside are exposed from the molding layer backside by thinning the molding layer.

Preferably, the metal layer of the die backside 1132 and the at least one metal feature are electrically connected by a conductive material, optionally conductive glue 211, depending on the design. At this time, the metal layer of the die back surface 1132 and the entire metal frame are electrically connected. In the next step, when the surface treatment layer is formed by electroplating, the metal layer and the metal frame can form an electric connection path for conducting current, so that the surface treatment layer can be formed on the surface of the metal layer and the back surface of the metal frame without a seed layer. In this case, the link 203 should be retained in the metal frame.

In some embodiments, the conductive paste 211 may also be configured to realize back grounding (i.e., the conductive paste 211 electrically connects the metal layer 210 on the back side of the die and the connection pad 201 specifically connected to the back side ground according to the specific design of the circuit (i.e., the connection pad specifically connected to the back side ground is connected to the electrical connection point of the back side ground on the active side of the die through the conductive structure).

As shown in fig. 28, the packaged single body is cut and separated to form a packaged chip.

Preferably, before or after the dicing and separating step, a surface treatment layer 131 is optionally formed on the die back surface 1132 and/or the exposed metal frame surface by electroplating, electroless plating or other suitable methods. For example, nickel palladium gold plating (ENEPIG) and Tin plating (Tin) are used. When the surface treatment layer 131 is formed by electroplating, the metal layer on the back surface of the die and the metal frame are electrically connected into a whole by the conductive paste 211, so that the whole of the conduction of the electroplating current is formed during electroplating, and the electroplating step can be directly performed without forming a seed layer.

Compared with the scheme of the embodiment 1, the scheme of the embodiment 4 has the advantages that the metal layer 210 is additionally arranged on the back surface of the bare chip 113, and the metal layer can enhance heat dissipation, so that heat generated in the using process of the chip is dissipated in time; and the formation of the surface treatment layer is made easier by the combination of the conductive paste 211.

According to another aspect of the present disclosure, there is also provided a chip structure, preferably manufactured by the method of the present disclosure described above, but not limited to only the above method.

Fig. 29a, 29b, 29c, 29d, 29e are schematic diagrams of chip structures obtained by the packaging method provided by the exemplary embodiment of the present disclosure. As shown, a chip 500 includes: at least one die 113; a protective layer 107; a metal unit comprising at least one metal feature; a molding layer 123 for encapsulating the die 113 and the metal unit; wherein the chip structure is connected to an external circuit through at least one metal feature.

In some embodiments, chip 500 further includes conductive structures through which at least one metal feature on a metal element is connected to die 113. In some embodiments, the metal features include a connection structure and/or a heat dissipation structure.

Specifically, as shown in fig. 29a, the metal features a connection structure, which is embodied as a connection pad 201, and the chip 500 is connected to an external circuit through at least one connection pad 201.

As shown in fig. 29a, the conductive structure includes a conductive filled via 124 and a panel-level conductive layer, which is shown as a panel-level conductive trace 125, and may also be a panel-level conductive trace 125 and a panel-level conductive stud, which may be one layer as shown or multiple layers; the conductive filled via 124 is formed by filling the opening of the passivation layer with a conductive material, and at least a portion of the conductive filled via 124 is connected to the electrical connection point 103; the panel-level conductive layer is formed on the surface of the protective layer 107 and the front surface 1231 of the plastic package layer, at least a part of the panel-level conductive layer is connected with the conductive filling through hole 124 and connected with the connecting pad 201, and the surface of the protective layer 107, the front surface 1231 of the plastic package layer and the front surface of the connecting pad 201 are flush.

In some embodiments, the conductively filled via 124 has a lower conductively filled via surface and an upper conductively filled via surface, and the ratio of the area of the lower conductively filled via surface to the upper conductively filled via surface is between 60% and 90%.

In some embodiments, there is a gap between the lower surface of the conductively filled via and the insulating layer 105, preferably at a location near the center of the electrical connection point 103.

In some embodiments, the electrical connection points 103 have a conductive coating formed thereon.

Fig. 29a is merely exemplary, and the conductive structure may also include a wafer conductive layer 130, a conductive filled via 124, and a panel level conductive layer, and may also include a wafer conductive layer 130 and a panel level conductive layer.

The die backside 1132 and the metal unit backside, specifically the connection pad backside, are exposed from the molding layer backside 1232, and the exposed portion from the molding layer backside 1232 has a surface treatment layer 131. Optionally, the surface treatment layer 131 may also be configured to realize back grounding (backing) of the chip 500, that is, the surface treatment layer 131 electrically connects the die back surface 1132 and the back surface-grounding-specific connection pad 201 according to the specific design of the circuit (that is, the back surface-grounding-specific connection pad is connected to the back surface grounding electrical connection point on the die active surface through the conductive structure).

The chip 500 further includes a dielectric layer 129 that covers the panel-level conductive layer, with the outermost dielectric layer 129 completely covering the panel-level conductive layer.

As shown in fig. 29b, the metal features are a connection structure and a heat dissipation structure, the connection structure is embodied as a connection pad 201, and the chip 500 is connected with an external circuit through at least one connection pad 201; the heat dissipation structure is embodied as a heat dissipation pad 207.

Shown in fig. 29b, the conductive structure includes a wafer level conductive layer 130, which is shown as wafer conductive trace 106, a conductive filled via 124, and a panel level conductive layer, which is shown as panel level conductive trace 125, which may also be panel level conductive trace 125 and panel level conductive stud, which may be one layer as shown or multiple layers; at least a portion of the wafer conductive layer 130 is connected to the electrical connection points 103 and/or heat dissipation locations; the conductive filled via 124 is formed by filling the passivation opening 109 with a conductive material; at least a portion of the conductively filled via 124 is connected to the wafer conductive layer; the panel-level conductive layer is formed on the surface of the protective layer 107 and the front surface 1231 of the plastic packaging layer, at least a part of the panel-level conductive layer is connected with the conductive filling through holes 124 and is connected with the metal unit, and the surface of the protective layer 107, the front surface 1231 of the plastic packaging layer and the front surface of the metal unit are flush.

In some embodiments, at least a portion of the wafer conductive layer 130 interconnects and leads the plurality of electrical connection points 103 to one another, and in other embodiments, at least a portion of the wafer conductive layer 130 leads the electrical connection points 103 individually.

Optionally, the contact area of the wafer conductive layer 130 with a single contact area of the electrical connection point 103 is smaller than the contact area of the wafer conductive layer 130 with a single contact area of the conductively filled via 124.

The conductive filled via has a conductive filled via lower surface and a conductive filled via upper surface, and optionally, the area of the conductive filled via lower surface is smaller than the area of the conductive filled via upper surface.

Fig. 29b is merely exemplary, and the conductive structure may also include a conductive filled via 124 and a panel level conductive layer; the conductive structure may also be a wafer level conductive layer including a wafer conductive layer 130 and a panel level conductive layer.

The die backside 1132 and the metal unit backsides, specifically the connection pad backsides and the heat spreader pad backsides, are exposed from the molding layer backside 1232, and the exposed portion from the molding layer backside 1232 has a surface treatment layer 131. Optionally, the surface treatment layer 131 may also be configured to realize back grounding of the chip 500, that is, the surface treatment layer 131 electrically connects the die back surface 1132 with the back surface-specific ground connection pad 201 according to the specific design of the circuit (that is, the back surface-specific ground connection pad is connected to the back surface ground connection point on the die active surface through the conductive structure).

As shown in fig. 29c, the metal features are a connection structure embodied as connection pads 201 and a heat dissipation structure embodied as a backside heat sink 205, optionally the backside heat sink 205 is applied to the backside of the die by a thermally conductive material 209. The chip 500 is connected to an external circuit through at least one connection pad 201. In some embodiments, the heat dissipation structures may be a heat sink pad 207 and a backside heat sink 205.

As shown in fig. 29c, the conductive structure includes a wafer conductive layer 130 and a panel level conductive layer, which is shown as panel level conductive traces 125, and the panel level conductive layer may also be panel level conductive traces 125 and panel level conductive posts, and the panel level conductive layer may be one layer as shown or multiple layers; the wafer conductive layer includes a wafer conductive trace 106 and a wafer conductive post 111; at least a portion of the die conductive traces 106 are connected to the electrical connection points 103 and/or heat dissipation locations; at least a portion of the wafer conductive posts 111 are formed on the wafer conductive traces 106; the panel-level conductive layer is formed on the surface of the protective layer 107 and the front surface 1231 of the plastic packaging layer, at least a part of the panel-level conductive layer is connected with the wafer conductive posts 111 and is connected with the metal unit, and the surface of the protective layer 107, the front surface 1231 of the plastic packaging layer and the front surface of the metal unit are flush.

In some embodiments, at least a portion of the wafer conductive traces 106 individually exit the electrical connection points 103; in other embodiments, at least a portion of the wafer conductive traces 106 interconnect and lead out the plurality of electrical connection points 103 from one another.

Optionally, the wafer conductive layer is a wafer conductive post 111, and at least a portion of the wafer conductive post is connected to the electrical connection point 103 and/or the heat dissipation position.

Fig. 29c is merely exemplary, and the conductive structure may also include a conductive filled via 124 and a panel level conductive layer, and may also include a wafer conductive layer 130, a conductive filled via 124 and a panel level conductive layer.

Alternatively, depending on the specific design of the circuit, the back side grounding with the back side heat sink 205 may be achieved by electrically connecting the back side grounding electrical connection point 103 on the active side of the die with the back side heat sink 20 using a conductive structure.

The die backside 1132 and the metal unit backside, specifically the backside of the backside heat sink 205, are exposed from the molding layer backside 1232, and the exposed portion of the molding layer backside 1232 has a surface treatment layer 131. When the back grounding of the chip is not implemented by using the conductive structure, optionally, the surface processing layer 131 may also be configured to implement the back grounding of the chip 500 (i.e., the surface processing layer 131 electrically connects the back heat sink 205 and the connection pad 201 specifically connected to the back grounding according to the specific design of the circuit (i.e., the connection pad specifically connected to the back grounding is a connection pad connected to the back grounding electrical connection point on the active surface of the die by the conductive structure). At this point, the backside heat sink 205 is a material that can conduct electricity, such as a metal thermal paste, through a thermal conductive material 209 applied to the backside of the die.

According to a structure such as that shown in fig. 29a and 29b, optionally, the die backside 1132 may also have a metal layer 210, and the metal layer 210 surface is exposed from the molding layer backside 1232. The metal feature has a metal feature backside that is exposed from the molding layer backside 1232. Preferably, the surface of the metal layer 201 and the back of the at least one metal feature are connected by a conductive adhesive 211.

Some embodiments of package structures with metal layers 210 and conductive glue 211 are shown in fig. 29 d.

According to the structures shown in fig. 29a, 29b and 29c, for example, optionally, a plurality of bare chips 113 are provided in the chip structure, preferably, the bare chips 113 are bare chips 113 with different functions, and the bare chips 113 are electrically connected according to product design. One embodiment of a package structure having a plurality of dies 113 is shown in fig. 29 e.

In the chip structure, the young's modulus of the protective layer 107 is preferably within any one of the following numerical ranges or values: 1000-20000MPa, 1000-10000MPa, 4000-8000MPa, 1000-7000 MPa, 4000-7000 MPa, 5500 MPa.

The protective layer 107 is soft, has good flexibility and elasticity, has enough support for a panel conductive layer formed on the surface of the protective layer, and is particularly suitable for packaging a thin bare chip with large electric flux.

In some embodiments, the material of the protective layer 107 is an organic/inorganic composite material. Preferably, the organic/inorganic composite material obtained by adding the inorganic particles to the organic material is adopted, so that the material properties of the organic material are modified, and the material has the characteristics of both the organic material and the inorganic material.

In some embodiments, the thickness of the protective layer 107 is any one of the following ranges or values: 15 to 50 μm, 20 to 50 μm, 35 μm, 45 μm, 50 μm. This thickness range ensures that the protective layer 107 can provide adequate cushioning and support.

In some embodiments, the coefficient of thermal expansion of the protective layer 107 is any one of the following ranges or values: 3 to 10ppm/K, 5ppm/K, 7ppm/K, 10 ppm/K.

In some embodiments, the coefficient of thermal expansion of the molding layer 123 is within any one of the following ranges or values: 3 to 10ppm/K, 5ppm/K, 7ppm/K, 10 ppm/K.

In some embodiments, the protective layer 107 and the molding layer 123 have the same or similar coefficients of thermal expansion. The accumulation of interface fatigue at the interfaces among the protective layer 107, the plastic package layer 123 and the bare chip 113 is avoided, so that the packaged chip has durability, and the service life of the chip is prolonged.

Fig. 30 is an exemplary illustration of a chip 500 in use, during which the chip 500 is connected to a circuit board or substrate 400 via at least one metal feature, shown as connection pad 201.

The chip structure in the present disclosure may replace a wire bonding (wire bonding) structure. Compared with a lead bonding packaging structure, the packaging process is simple, the mutual interference of signals among leads in the lead bonding structure is avoided, and the noise of the leads caused by vibration when the chip works is avoided. And the connecting structure is used for replacing a lead structure, so that the chip packaging structure is more suitable for chip packaging with large electric flux.

The above-mentioned embodiments are intended to provide further detailed descriptions of the technical solutions and technical effects of the present disclosure, but it should be understood by those skilled in the art that the above-mentioned embodiments are not intended to limit the present disclosure, and any modifications, equivalents, improvements, etc. made within the spirit of the present disclosure should be included in the scope of the present disclosure.

Claims

1. A chip structure, comprising:

at least one die;

a protective layer;

a metal unit comprising at least one metal feature;

a plastic packaging layer for packaging the bare chip and the metal unit;

wherein the chip structure is connected to an external circuit through at least one metal feature;

a dielectric layer.

2. The chip structure according to claim 1, further comprising a conductive structure comprising a wafer conductive layer and a panel level conductive layer; at least one metal feature on the metal unit is connected to the die through a conductive structure.

3. The chip structure according to claim 2, wherein the wafer conductive layer comprises wafer conductive traces and wafer conductive posts; at least a portion of the die conductive traces are connected to electrical connection points and/or heat dissipation locations; at least a portion of the wafer conductive posts are formed on the wafer conductive traces; the panel-level conductive layer is formed on the surface of the protective layer and the front surface of the plastic packaging layer, at least one part of the panel-level conductive layer is connected with the wafer conductive convex column and is connected with the metal unit, and the surface of the protective layer, the front surface of the plastic packaging layer and the front surface of the metal unit are flush.

4. The chip structure according to claim 3, wherein at least a portion of the wafer conductive traces individually route out the electrical connection points and/or at least a portion of the wafer conductive traces interconnect and route out a plurality of the electrical connection points to each other.

5. The chip structure according to any of claims 1-4, wherein the metal features comprise a connection structure and/or a heat dissipation structure; the connecting structure comprises a connecting pad; the heat dissipation structure comprises a heat dissipation pad.

6. The chip structure according to claim 5, wherein the heat spreading structure further comprises a backside heat spreader applied to the backside of the die by a thermally conductive material.

7. The chip structure according to any of claims 1 to 4, wherein a metal layer is applied to the back side of the die, and the surface of the metal layer is exposed from the back side of the molding layer.

8. The chip structure of claim 7, wherein the metal features have metal feature back surfaces exposed from a back surface of a molding layer, and wherein the metal layer surface and at least one of the metal feature back surfaces are connected by a conductive adhesive.

9. The chip structure according to any of claims 1-4, wherein the die backside and the metal unit backside are exposed from the molding layer backside, and the portion exposed from the molding layer backside has a surface treatment layer.

10. The chip structure according to any one of claims 1 to 4, wherein the at least one die is a plurality of dies, the plurality of dies are dies with different functions, and the plurality of dies are electrically connected according to a product design.

11. The chip structure according to any of claims 2-4, wherein the dielectric layer is adapted to cover the panel-level conductive layer, and the outermost dielectric layer completely covers the panel-level conductive layer.