TWI691028B - 包括電感器之堆疊的半導體晶粒及相關之方法 - Google Patents
包括電感器之堆疊的半導體晶粒及相關之方法 Download PDFInfo
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- TWI691028B TWI691028B TW107129808A TW107129808A TWI691028B TW I691028 B TWI691028 B TW I691028B TW 107129808 A TW107129808 A TW 107129808A TW 107129808 A TW107129808 A TW 107129808A TW I691028 B TWI691028 B TW I691028B
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Abstract
本發明技術之若干實施例係關於半導體裝置、包括半導體裝置之系統以及製造及操作半導體裝置之方法。在一些實施例中,一種半導體裝置包含:一基板;一第一晶粒,其安裝至該基板且包括第一電感器;及一第二晶粒,其在一偏移位置中安裝至該第一晶粒且包括第二電感器。該等第一電感器在該第一晶粒之一作用側處,且該等第二電感器在該第二晶粒之一作用側處。該等第一電感器之至少一部分接近且電感耦合至該等第二電感器。該半導體裝置進一步包含:第一複數個互連件,其將該基板電耦合至該第一晶粒;及第二複數個互連件,其將該第二晶粒電耦合至該基板。該第一複數個互連件自該基板之一上表面延伸至該第一晶粒之該作用側,且該第二複數個互連件自該第二晶粒之該作用側延伸至該基板之下表面。
Description
本發明大體上係關於半導體裝置,且更特定言之係關於包括電感器之半導體晶粒。
半導體裝置通常提供於具有多個已連接晶粒之封裝中,其中各種晶粒之電路元件係以各種方式連接。舉例而言,多晶粒封裝可利用自每一晶粒至插入件之焊線在不同晶粒中之元件之間提供連接。雖然有時需要不同晶粒中之電路元件之間的直接電連接,但在其他狀況下,可能需要無線地(例如,經由電感耦合、電容耦合或其類似方法)連接來自不同晶粒之元件。為了促進不同晶粒中之電路元件之間的無線通信,線圈可設置於晶粒上,使得多晶粒堆疊中之鄰近晶粒可具有無線地通信之接近線圈。
提供用於無線通信之線圈的一種方法涉及以堆疊之面對背配置將兩個晶粒封裝於半導體封裝中,使得每一晶粒上之線圈分離個別晶粒之厚度。此方法通常涉及充分薄化晶粒以減小一個晶粒上之線圈與鄰近晶粒上之對應線圈之間的距離。然而,藉由此方法,線圈之間的距離仍相對較大,此係因為晶粒仍需要足夠厚以維持最小強度以供在製造程序期間處置。為了補償此厚度且確保晶粒之間的足夠數據傳輸,線圈之大小趨向
於增大,此進而增加封裝中之晶粒之成本且需要在晶粒上佔據額外空間。另外,因為晶粒經薄化,因此其相對較弱且較易於破裂或破碎,進而降低總製造良率且增加不必要的成本。因此,需要提供具有用於無線通信之線圈之半導體裝置的其他方法。
在一實施例中,一種半導體裝置包含:一封裝基板,其具有一上表面及一下表面;晶粒之一堆疊,其附接至該基板之該上表面,其中該堆疊包括一第一晶粒及一第二晶粒,該第一晶粒其包括一前側及在該前側處之一或多個第一電感器,該第二晶粒安置於該第一晶粒上方且自該第一晶粒偏移,該第二晶粒包括面向該第一晶粒之一前側及在該第二晶粒之該前側處之一或多個第二電感器,其中該等第二電感器中之一或多者電感耦合至一或多個第一電感器;第一複數個焊線,其將該基板之該上表面上的第一複數個基板焊墊電耦合至該第一晶粒之該前側上的第一複數個晶粒焊墊;及第二複數個焊線,其將該基板之該下表面上的第二複數個基板焊墊電耦合至該第二晶粒之該前側上的第二複數個晶粒焊墊。
在另一實施例中,一種半導體裝置包含:一基板,其具有一上表面及一下表面;一第一晶粒,其安裝至該基板且包括一作用側及在該作用側處之複數個第一電感器;一第二晶粒,其在一偏移位置中安裝至該第一晶粒,使得該第二晶粒之一部分延伸超出該第一晶粒,其中該第二晶粒包括面向該第一晶粒之一作用側及在該第二晶粒之該作用側處之複數個第二電感器,且其中該等第一電感器中之一或多者電感耦合至一或多個對應第二電感器;第一複數個互連件,其將該基板電耦合至該第一晶粒;及第二複數個互連件,其將該第二晶粒之該作用側電耦合至基板之該下表
面且自該第二晶粒之該作用側延伸至基板之該下表面。
在另一實施例中,一種製造一半導體裝置之方法,該方法包含:將一第一晶粒安裝至一基板之一上表面;將一第二晶粒安置於該第一晶粒上方且自該第一晶粒偏移,使得該第二晶粒之一部分延伸超出該第一晶粒;將該第一晶粒之一作用側處之一或多個第一電感器電感耦合至該第二晶粒之一作用側處之一或多個第二電感器;及經由一第一焊線將該基板之一下表面處的一第一基板焊墊電耦合至該第二晶粒之該部分處的一第一晶粒焊墊。
100:半導體裝置
110:封裝基板
112a:上表面
112b:下表面
120a:第一晶粒/半導體晶粒
120b:第二晶粒/第二半導體晶粒
121a:第一側
121b:第二側
122a:第一側
122b:第二側
125a:第一電感器
125b:第二電感器
127a:作用表面
128a:作用表面
129a:第一周邊部分
129b:第二周邊部分
133:收發器線圈
134a:第一端部
134b:第二端部
135:接收器線圈
136a:第一端部
136b:第二端部
140:第一晶粒附接材料
142:第二晶粒附接材料
143:側向邊緣
144:側向邊緣
145:側向邊緣
150:互連件
152:互連件
154:基板焊墊
155:晶粒焊墊
156:晶粒焊墊
158:基板焊墊
160:電連接器
170:囊封體
171b:下表面
200:半導體裝置
300:半導體裝置
320a:第三晶粒/第三半導體晶粒
320b:第四晶粒/第四半導體晶粒
321a:第一側
322a:第一側
325a:第三電感器
325b:第四電感器
329a:第三周邊部分
329b:第四周邊部分
340:第三晶粒附接材料
342:第四晶粒附接材料
350:互連件
352:互連件
356:晶粒焊墊
358:晶粒焊墊
400:半導體裝置
405a:第一堆疊組態
405b:第二堆疊組態
410:基板
420a:第三晶粒
420b:第四晶粒
425a:第三電感器
425b:第四電感器
429a:第五周邊部分
450:互連件
452:互連件
490:垂直軸線
500:半導體裝置
590:系統
592:電源
596:處理器
598:子系統/組件
1A-1A:線
1B-1B:線
1C-1C:線
1D-1D:線
D1:第一距離
D2:第二距離
W1:第一寬度
W2:第二寬度
W3:第三寬度
W4:第四寬度
圖1A為根據本發明技術之一實施例之具有電感器之半導體裝置的橫截面示意圖。
圖1B為根據本發明技術之一實施例之沿圖1A之線1B-1B截取的圖1A中所展示之半導體裝置的示意性頂部平面圖。
圖1C為根據本發明技術之一實施例之圖1A中所展示之半導體裝置之放大部分的示意性橫截面圖。
圖1D為根據本發明技術之一實施例之沿圖1C之線1D-1D截取的圖1A中所展示之半導體裝置之電感器的示意性俯視圖。
圖2A至圖2D為根據本發明技術之一實施例之形成半導體裝置之方法的示意性橫截面圖。
圖3及圖4為根據本發明技術之其他實施例之具有電感器之半導體裝置的示意性橫截面圖。
圖5為包括根據本發明技術之實施例組態之半導體晶粒總成之系統的示意圖。
在以下描述中,論述眾多具體細節以提供對本發明技術之實施例的透徹及能夠實現的描述。然而,熟習相關技術者將認識到,本發明可在無此等具體細節中之一或多者之情況下實踐。在其他情況下,未展示或未詳細描述通常與半導體裝置相關聯之熟知結構或操作,以免混淆技術之其他態樣。一般而言,應理解,除了本文中所揭示之彼等具體實施例之外,各種其他裝置、系統及方法亦可在本發明技術之範疇內。
如上文所論述,由於對半導體封裝中之晶粒之間的無線通信之需要愈來愈高,半導體裝置被不斷地設計。因此,根據本發明技術之半導體裝置之若干實施例可將前側線圈設置於以面對面配置來配置之鄰近半導體晶粒上,該等前側線圈可將無線通信提供鄰近晶粒,同時僅消耗半導體裝置之相對較小面積。在一些實施例中,一種半導體裝置包含:基板;第一晶粒,其安裝至基板且包括第一電感器;及第二晶粒,其在偏移位置中安裝至第一晶粒且包括第二電感器。第一電感器在第一晶粒之作用側處,且第二電感器在第二晶粒之作用側處。第一電感器之至少一部分電感耦合至第二電感器。半導體裝置進一步包含:第一複數個互連件,其將基板電耦合至第一晶粒;及第二複數個互連件,其將第二晶粒電耦合至基板。第一複數個互連件自基板之上表面延伸至第一晶粒之作用側,且第二複數個互連件自第二晶粒之作用側延伸至基板之下表面。
圖1A為沿圖1B之線1A-1A截取之半導體裝置100(「裝置100」)的示意性橫截面圖,且圖1B為沿圖1A之線1B-1B截取之裝置100的示意性頂部平面圖。一同參考圖1A及1B,裝置100包括具有上表面112a及與上表面112a相對之下表面112b的封裝基板110(「基板110」),及附
接至基板110之上表面112a的晶粒之堆疊。基板110可包括重佈結構、插入件、印刷電路板、介電隔片、另一半導體晶粒(例如,邏輯晶粒)或相關技術中已知的另一合適基板。基板110可由適用於半導體處理方法之數種基板材料中之任一種形成,該等基板材料包括矽、玻璃、砷化鎵、氮化鎵、有機積層板及其類似物。另外,用於記憶體、控制器、處理器及其類似者之積體電路可形成於基板110上及/或形成於基板110中。在所說明之實施例中,基板包括上表面112a處之第一複數個基板焊墊158及下表面112b處之第二複數個基板焊墊154。晶粒之堆疊可包括安裝於基板110上方之第一晶粒120a及安裝於第一晶粒120a上方之第二晶粒120b。
第一晶粒120a及第二晶粒120b係以面對面配置來配置,使得第一晶粒120a之作用側面朝第二晶粒120b之作用側。另外,第二晶粒120b在偏移位置中安裝於第一晶粒120a上方,使得第二晶粒120b之側向邊緣144延伸超出第一晶粒120a之側向邊緣143達第一寬度(W1)。因而,第二晶粒120b之部分129a(例如,第一周邊部分)突出於第一晶粒120a之上。類似地,在第一晶粒120a及第二晶粒120b之相對端部處,第一晶粒120a之部分129b(例如,第二周邊部分)延伸超出第二晶粒120b達第二寬度(W2)。在一些實施例中,第一寬度(W1)與第二寬度(W2)可為相等的。第一晶粒120a及第二晶粒120b可各自具有積體電路或組件、資料儲存元件、處理組件及/或製造於半導體基板上之其他特徵。舉例而言,第一晶粒120a及第二晶粒120b可包括整合式記憶體電路及/或邏輯電路,且可包括各種類型之半導體組件及功能性特徵,諸如動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、快閃記憶體、其他形式之積體電路記憶體、處理電路、成像組件及/或其他半導體特徵。在一些實施例
中,第一晶粒120a及第二晶粒120b可為均質或相同的(例如,製造為具有相同設計及規格之記憶體晶粒),而在其他實施例中,半導體晶粒120a至120b可彼此不同(例如,不同類型之記憶體晶粒或控制器、邏輯及/或記憶體晶粒之組合)。
第一晶粒120a包括第一側121a(例如,前側或作用側)及與第一側121a相對之第二側121b(例如,背側)。類似地,第二晶粒120b包括面向第一晶粒120a之第一側121a的第一側122a(例如,前側或作用側)及與第二晶粒120b之第一側122a相對的第二側122b(例如,背側)。第二晶粒120b之第一周邊部分129a及第一晶粒120a之第二周邊部分129b經曝光以使得其可由焊線存取。第一晶粒120a進一步包括在第一側121a之第二周邊部分129b處的第一複數個晶粒焊墊156,且第二晶粒120b進一步包括在第一側122a之第一周邊部分129a處的第二複數個晶粒焊墊155。在一些實施例中,除了先前所描述之焊墊之外或作為該等焊墊之替代,第一晶粒120a及/或第二晶粒120b可包括在其前側及/或背側上之金屬跡線。
裝置100可進一步包括(a)至少部分地形成於第一晶粒120a之第二側121b與基板110之上表面112a之間的第一晶粒附接材料140,及(b)至少部分地形成於第一晶粒120a之第一側121a與第二晶粒120b之第一側122a之間的第二晶粒附接材料142。第一晶粒附接材料140及第二晶粒附接材料142可為(例如)黏著膜(例如,晶粒附接膜)、環氧樹脂、膠帶、糊狀物或其他合適材料。在一些實施例中,第一晶粒附接材料140及第二晶粒附接材料142為相同材料及/或具有實質上相同的厚度。如圖1A之實施例中所展示,第二晶粒附接材料142延伸至第一晶粒120a之側向邊緣143,且因此不延伸至第二晶粒120b之第一周邊部分129a上。然而,在其
他實施例中,第二晶粒附接材料142可至少部分地在第一周邊部分129a上方延伸。同樣,在第一晶粒120a及第二晶粒120b之相對端部處,第二晶粒附接材料142可延伸至第二晶粒120b之邊緣,或至少部分地延伸至第一晶粒120a之第二周邊部分129b上。
裝置100進一步包括複數個電感器(例如,線圈)。第一晶粒120a包括在第一晶粒120a之第一側121a處的複數個第一電感器125a,且第二晶粒120b包括在第二晶粒120b之第一側121a處的複數個第二電感器125b。在圖1A之所說明實施例中,第一晶粒120a及第二晶粒120b係以面對面配置來配置,且因此第一電感器125a及第二電感器125b定位成彼此接近。第一晶粒120a上之第一電感器125a之至少一部分大體上與第二晶粒120b上之第二電感器125b對準。在一些實施例中,第一電感器125a可包括與第二電感器125b對準之電感器(例如,作用電感器)之第一部分及不與第二電感器125b對準之電感器(例如,非作用或孤立電感器)之第二部分。在圖1A之所說明實施例中,舉例而言,第一晶粒120a之最外第一電感器125a中之一者不與對應第二電感器125b對準,且第二晶粒120b之最外第二電感器125b中之一者不與對應第一電感器125a對準。對準之第一電感器125a及第二電感器125b經電感耦合(示意性地展示為130)且能夠無線地在彼此之間且因此在第一晶粒120a與第二晶粒120b之間傳達數據。
基板110、第一晶粒120a及第二晶粒120b經由複數個互連件(例如,焊線、導電鏈路、貫穿基板通路(TSV)等等)電耦合至彼此。裝置100包括將基板110電耦合至第一晶粒120a之第一複數個互連件150及將基板110電耦合至第二晶粒120b之第二複數個互連件152。第一複數個互連件150在第一側121a處在基板110之上表面112a處的第一複數個基板焊
墊158與第一晶粒110a之第二周邊部分129b處的對應第一複數個晶粒焊墊156之間延伸。在一些實施例中,第一複數個互連件150可在基板110與第一晶粒120a及/或第二晶粒120b之間遞送功率及/或資料信號。在圖1A之所說明實施例中,基板110(或例如第一晶粒120a之上表面)上方之第一複數個互連件150(例如,焊線)的最大高度不大於基板110上方之第二晶粒120b的高度。亦即,第一複數個互連件150不向上延伸超出與第二晶粒120b之上表面共面的平面。第二複數個互連件152在第一側122a處在基板110之下表面112b處的第二複數個基板焊墊154與第二晶粒110b之第一周邊部分129a處的對應第二複數個晶粒焊墊158之間延伸。在一些實施例中,第二複數個互連件152可在基板110與第二晶粒120b及/或第一晶粒120a之間遞送功率及/或資料信號。雖然圖1A之所說明實施例展示了在基板110之端部處在側向邊緣145上方延伸的第二複數個互連件152,但在一些實施例中,第二複數個互連件152可至少部分地延伸穿過基板110。在此類實施例中,基板110之側向邊緣145將至少延伸超出第一晶粒120a之側向邊緣143,且第二複數個互連件152將延伸穿過基板110之窗(例如,孔)。
儘管圖1B之所說明實施例展示了第一複數個基板焊墊158中之每一者與對應第一複數個晶粒焊墊之間的個別焊線,但在一些實施例中,個別焊線亦可在個別基板焊墊158之間及/或在個別晶粒焊墊156之間延伸。舉例而言,個別基板焊墊158可經由焊線直接地電耦合至彼此,且個別晶粒焊墊156可經由焊線直接地電耦合至彼此。類似地,個別焊線亦可在個別基板焊墊154及/或個別晶粒焊墊158之間延伸。舉例而言,個別基板焊墊154可經由焊線直接地電耦合至彼此,且個別晶粒焊墊156可經
由焊線直接地電耦合至彼此。另外,在一些實施例中,並非每一基板焊墊158皆可直接地電耦合至晶粒焊墊156。
裝置100可進一步包括囊封(例如,密封)基板110之至少一部分、第一晶粒120a及/或第二晶粒120b且保護此等組件中之一或多者免受污染及/或實體損壞的囊封體170(例如,模具材料)。第一複數個互連件150及第二複數個互連件152至少部分地由囊封體170囊封。在圖1A之所說明實施例中,第一複數個互連件150被完全囊封,且第二複數個互連件152僅被部分地囊封。然而,在一些實施例中,裝置100之高度(例如,厚度)及在裝置100中使用之囊封體170之總量可減少。舉例而言,囊封體170可僅延伸至晶粒之最上結構之僅略微上方,或延伸至最外晶粒(例如,第二晶粒120b)之最外表面,藉此曝光最外晶粒之上部分(例如,第二晶粒120b之第二側122b)。減少裝置100中之囊封體170之量可降低裝置100響應於改變之溫度而變形的傾向。詳言之,囊封體大體上具有高於矽半導體晶粒之熱膨脹係數(CTE)。因此,藉由減小囊封體170之高度來減小囊封體170之體積可減小裝置100之總平均CTE(例如,藉由增大由第一晶粒120a及第二晶粒120b佔據之相對體積)。
此外,在一些實施例中,囊封體170可至少部分地填充自第一晶粒120a突出之第二晶粒120b之第一周邊部分129a下方的空間。囊封體170可因此支撐第一周邊部分129a以防止第二半導體晶粒120b由於外力而造成之變形或其他損壞。此外,在基板110為不包括預成型基板之重佈結構的實施例中,囊封體亦可為裝置100提供所要結構強度。舉例而言,囊封體170可經選擇以在外力被施加至裝置100時防止裝置100變形、彎曲等等。因此,在一些實施例中,重佈結構可製成極薄的(例如,小於
50μm),此係由於重佈結構無需提供具有極大結構強度之裝置100。因此,裝置100之總高度(例如,厚度)可進一步減小。
裝置100可進一步包括經組態以將裝置電耦合至外部封裝部位之電連接器160(例如,焊球、導電凸塊、導電柱、導電環氧樹脂及/或其他合適導電元件)。在一些實施例中,電連接器160在基板110之下表面112b上形成球柵陣列陣列。在某些實施例中,可省略電連接器160,且下表面112b可直接連接至外部裝置或電路。
圖1C為沿圖1D之線1C-1C截取之裝置100之放大部分的示意性橫截面圖,且圖1D為沿圖1C之線1D-1D截取之裝置100之電感器的示意性俯視圖。一同參考圖1C及圖1D,第一電感器125a及第二電感器125b可各自包含一或多個線圈,該一或多個線圈包括收發器線圈133及接收器線圈135。收發器線圈133及接收器線圈135可為平坦的或彼此垂直偏移,且可包括與標準半導體金屬化程序相容之數種導電材料中之任一種,包括銅、金、鎢或其合金。第一電感器125a及第二電感器125b係由導體(例如,導電跡線)形成。如圖1D之所說明實施例中所展示,第一電感器125a之收發器線圈133包括沿扭曲路徑連接之第一端部134a及第二端部134b。類似地,第一電感器125a之接收器線圈135包括沿類似扭曲路徑連接之第一端部136a及第二端部136b。收發器線圈133之第一端部134a及第二端部134b中之每一者及接收器線圈135之第一端部136a及第二端部136b中之每一者可連接至第一晶粒120a之電路。收發器線圈133及接收器線圈135各自包括約一又四分之三匝(例如,路徑圍繞第一端部134a、136a旋轉約540°)。第一電感器125a及第二電感器125b各自包括線圈直徑(),且分別與個別第一晶粒120a及第二晶粒120b之作用表面分離。舉例而言,第一
電感器125a在第一側121a處與第一晶粒120a之作用表面127a分離第一距離(D1),且第二電感器125b在第一側122a處與第二晶粒120b之作用表面128a分離第二距離(D2)。因而,第一電感器125a及第二電感器125b分別嵌入於第一晶粒120a及第二晶粒120b中,且彼此分離第一距離(D1)、第二距離(D2)及第一晶粒附接材料140之厚度。如下文更詳細地解釋,第一距離(D1)及第二距離(D2)可取決於裝置100之特定設計需要及/或線圈直徑()而變化。
儘管圖1D之所說明實施例中之第一電感器125a包括約二又二分之一匝,但在其他實施例中,線圈之匝數可變化。舉例而言,兩個線圈之間的電感耦合之效率可取決於電感器之匝數,使得增加匝數可准許在第一電感器125a與第二電感器125b之間進行較高效的無線通信(例如,藉此增大線圈可通信之距離)。然而,如熟習相關技術者將易於理解的,增加匝數一般會(例如,在減小跡線之大小及間隔不可行的情況下)增大由電感器消耗之面積,使得可基於線圈間隔、無線通信效率及電路面積之間的所要平衡而選擇線圈之匝數。
另外,儘管圖1C之實例中之第一電感器125a及第二電感器125b中之每一者已說明為具有相同直徑(),但在其他實施例中,鄰近晶粒(例如,電感耦合之面對面晶粒)中之無線通信電感器無需具有相同大小(例如,或形狀)。舉例而言,第一晶粒上之電感器可具有任何大小,包括約80與600微米之間,且第二晶粒上之電感器可具有選自同一範圍之不同大小。儘管匹配無線通信線圈之線圈大小可實現空間之最高效使用及最小材料成本,但在一些實施例中,一側上之空間限制可能使得需要具有不同大小之線圈。舉例而言,可能需要在第一晶粒(或第一晶粒之作用側)上提
供較大電感器,此係因為第一晶粒(或第一晶粒之作用側)上之空間限制並不與相關聯緊密置放(例如)電路元件之第二晶粒(或第二晶粒之作用側)上之空間限制一樣苛刻。此可促進較容易對準或實現略微較佳耦合,而不增大對應第一電感器125a及/或第二電感器125b之大小。
本發明技術之一個優點為,第一晶粒120a及第二晶粒120b之厚度並非資料傳輸之限制因素。不同於晶粒厚度需要相對較薄以確保足夠資料傳輸的以面對背配置在晶粒之間進行無線通信之傳統方法,本文中所揭示之面對面配置將第一電感器125a及第二電感器125b安置成接近彼此接近,使得其不分離第一晶粒125a及/或第二晶粒125b之厚度。因此,很大程度上避免了與傳統使用之薄晶粒相關聯的問題,包括破裂或破碎。
本發明技術之另一優點為,可基於線圈直徑而設計晶粒。如先前所提及,用於電感耦合之傳統系統及方法(例如,面對背配置)之缺陷為每一晶粒上之線圈之大小必須相對較大,此係因為鄰近晶粒上之線圈至少分離晶粒中之一者之厚度。因此,需要增大線圈之大小,此增加了材料成本、製造時間及晶粒上由線圈佔據之空間。本發明技術藉由以下操作來解決此問題:以面對面配置置放線圈,藉此減小線圈之大小(例如,直徑或厚度),以及材料成本、製造時間及晶粒上之佔據空間。
圖2A至圖2D為說明形成半導體裝置200(「裝置200」)之方法的示意性橫截面圖。大體而言,半導體裝置(例如,裝置100)可製造(例如)為離散元件或較大晶圓或面板。在晶圓級或面板級製造中,較大半導體裝置在經單體化以形成複數個個別裝置之前形成。為了易於解釋及理解,圖2A至圖2D說明單一裝置之製造。然而,熟習相關技術者將理解,半導體裝置之製造可按比例調整成晶圓級及/或面板級,亦即,以包括更
多組件以便能夠單體化成多於一個半導體裝置,同時包括類似特徵且使用如本文中所描述之類似程序。
首先參考圖2A,裝置200包括第一晶粒120a,第一晶粒120a安置於基板110上,使得第一晶粒120a之側向邊緣142與基板110之對應側向邊緣對準。如先前描述,基板110包括上表面112a處之第一複數個基板焊墊158及下表面112b處之第二複數個基板焊墊154。第一晶粒120a包括第一側121a處之第一複數個晶粒焊墊156及第一側121a處之第一複數個電感器125a。第一晶粒120a藉由實質上覆蓋第一晶粒120a之第二側121b的第一晶粒附接材料140附接至基板110。在第一晶粒120a經安置至基板110上之前,第一晶粒附接材料140可形成於第一晶粒120a之第二側121b上方。替代地,在第一晶粒120a經安置至基板110上之前,第一晶粒附接材料140可形成於基板之上表面112a上方。
圖2B展示在(a)第二晶粒120b已安置於第一晶粒120a上方及(b)基板110已經由第一複數個互連件150電耦合至第一晶粒120a之後的裝置200。將第二晶粒120b安置於第一晶粒120a上方包括將第二晶粒120b與第一晶粒120a對準,使得第一晶粒120a上之第一電感器125a之至少一部分與第二晶粒120b上之對應第二電感器125b對準。在一些實施例中,第一晶粒120a可包括第一側121a處之多個對準標記(未圖示)以確保第一電感器125a與對應第二電感器125b之至少一部分對準。第二晶粒120b可包括第一側122a處之類似或相同對準標記。
第二晶粒120b可經由第二晶粒附接材料142附接至第一晶粒120a之至少一部分。第二晶粒附接材料144可大體上類似於或等同於第一晶粒附接材料140。在圖2B之所說明實施例中,第二晶粒附接材料142
不在第二晶粒120b之第一周邊部分129a上方延伸,或自該第一周邊部分129a移除。在一些實施例中,第二晶粒附接材料142的確在第一周邊部分129a上方延伸。在此類實施例中,在將第二複數個晶粒焊墊155電耦合至第二複數個晶粒焊墊154之前,第二晶粒附接材料142自第二晶粒120b之第二複數個晶粒焊墊155剝落或以其他方式自該第二複數個晶粒焊墊155移除,或被阻止覆蓋該第二複數個晶粒焊墊155(圖2C)。
製造裝置200進一步包括經由第一複數個互連件150將第一複數個基板焊墊158電耦合至第一複數個晶粒焊墊156。在第二晶粒120b安置於第一晶粒120a上方之後,或在一些實施例中在第二晶粒120b經安置之前,第一複數個互連件150可直接地耦合至第一複數個基板焊墊158及第一複數個晶粒焊墊156。如先前描述,第一複數個互連件150可將功率提供至第一晶粒120a,且經由第一電感器125a及第二電感器125b間接地將功率提供至第二晶粒120b。
如圖2C中所展示,製造裝置200包括(a)翻轉裝置,及(b)將第二晶粒120b電耦合至基板110。將第二晶粒120b電耦合至基板110可包括將第二複數個互連件152在基板110之下表面112b處的第二複數個基板焊墊154與第二晶粒120b之第一側122a處的第二複數個晶粒焊墊155之間延伸。如先前參考圖1A所描述,基板110之側向邊緣145可延伸超出第一晶粒120a之側向邊緣143,且第二複數個互連件152可延伸穿過基板110中之窗而非圍繞基板110之側向邊緣,如圖2C中所展示。第二複數個互連件152可將資料信號提供至基板110及第二晶粒120b/自基板110及第二晶粒120b提供資料信號,且間接地將資料信號提供至基板110及第一晶粒120a/自基板110及第一晶粒120a提供資料信號。在一些實施例中,在翻轉裝置
200以保護第二晶粒120b及裝置200上之其他組件免受在半導體製造程序期間可能發生之損壞(例如,實體損壞)之前,保護膜(未圖示)可安置於第二晶粒120b之第二側122b上方。
圖2D展示在(a)再次翻轉裝置200及(b)將囊封體170安置於基板110之上表面112a上方且至少部分地圍繞第一晶粒120a及第二晶粒120b、第一複數個互連件150及第二複數個互連件152之後的裝置200。囊封體170可由樹脂、環氧樹脂、基於聚矽氧之材料、聚醯亞胺及/或在相關技術中使用或已知的其他合適樹脂形成。在沈積後,囊封體170可由UV光、化學硬化劑、熱或在相關技術中已知的其他合適烘烤方法烘烤。儘管在圖2D之所說明實施例中,囊封體170包括大體上與基板110之上表面112a共面從而曝光複數個互連件152的下表面171b,但在其他實施例中,囊封體170之下表面171b可大體上與基板110之下表面112b共面,且藉此至少部分地囊封複數個互連件152。在又其他實施例中,囊封體170可具有完全不同的形狀(例如,圓角輪廓、不規則邊緣形狀等等)。可在單一步驟中,或在其中沈積囊封體且接著研磨以按需要平坦化之多個步驟中形成囊封體170。
圖3為根據本發明技術之另一實施例之半導體裝置300(「裝置300」)的示意性橫截面圖。更具體言之,此實施例說明為具有多於兩個堆疊之半導體晶粒。裝置300包括大體上類似於先前所描述之裝置100的特徵。舉例而言,裝置300包括基板110、安置於基板110上方之第一晶粒120a、以側向偏移之面對面配置安置於第一晶粒120上方之第二晶粒120b、將基板110電耦合至第一晶粒120a之第一複數個互連件150及將基板110電耦合至第二晶粒120b之第二複數個互連件152。
裝置300進一步包括第三半導體晶粒320a(「第三晶粒320a」)及在側向偏移位置中安置於第三晶粒320a上方之第四半導體晶粒320b(「第四晶粒320b」)。第三晶粒320a及第四晶粒320b之結構、功能及空間定向可大體上類似於或等同於先前所描述之第一晶粒120a及第二晶粒120b之彼等結構、功能及空間定向。舉例而言,第三晶粒320a及第四晶粒320b係以面對面配置來配置,使得第三晶粒320a之作用側面朝第四晶粒320b之作用側。另外,第四晶粒320b在偏移位置中安裝於第三晶粒320a上方,使得第四晶粒320b之側向邊緣在第二晶粒120b延伸超出第一晶粒120a之相同方向上延伸超出第三晶粒320a之側向邊緣達第三寬度(W3)。因而,第四晶粒320b之部分329a(例如,第三周邊部分)自第三晶粒320a突出。類似地,在第三晶粒320a及第四晶粒320b之相對端部處,第三晶粒320a之部分329b(例如,第四周邊部分)延伸超出第四晶粒320b達第四寬度(W4)。第三寬度(W3)及第四寬度(W4)可彼此相等,及/或等於第一寬度(W1)及第二寬度(W2)。
第三晶粒320a包括第一側321a(例如,前側或作用側)及與第一側321a相對之第二側321b(例如,背側)。類似地,第四晶粒320b包括面向第三晶粒320a之第一側322a的第一側322a(例如,前側或作用側)及與第四晶粒320b之第一側322a相對的第二側322b(例如,背側)。在第四晶粒320b之第一側322b處的第四晶粒320b之第三周邊部分329a被曝光,且第三晶粒320a之第四周邊部分329b被曝光。第三晶粒320a進一步包括在第一側321a之第四周邊部分329b處的第三複數個晶粒焊墊356,且第四晶粒320b進一步包括在第一側322a之第三周邊部分329a處的第四複數個晶粒焊墊358。在一些實施例中,除了先前所描述之焊墊之外或作為
該等焊墊之替代,第三晶粒320a及/或第四晶粒320b可包括在其前側及/或背側上之金屬跡線。
裝置300可進一步包括至少部分地形成於第三晶粒320a之第二側321b與第二晶粒120b之第二側122b之間的第三晶粒附接材料340,及至少部分地形成於第三晶粒320a之第一側321a與第四晶粒320b之第一側322a之間的第四晶粒附接材料342。第三晶粒附接材料340及第四晶粒附接材料342可為(例如)黏著膜(例如,晶粒附接膜)、環氧樹脂、膠帶、糊狀物或其他合適材料。在一些實施例中,第三晶粒附接材料340及第四晶粒附接材料342為相同材料及/或具有實質上相同的厚度,且可類似於或等同於先前所描述之第一晶粒附接材料140及第二晶粒附接材料142。如圖3之實施例中所展示,第四晶粒附接材料342可僅在第三晶粒320a與第四晶粒320b之間延伸。在其他實施例中,第四晶粒附接材料342可至少部分地延伸至第四晶粒320之第三周邊部分329a及/或第三晶粒320a之第四周邊部分329b上。
裝置300進一步包括複數個電感器(例如,線圈)。第三晶粒320a包括在第三晶粒320a之第一側321a處的複數個第三電感器325a,且第四晶粒320b包括在第四晶粒320b之第一側321a處的複數個第四電感器325b。在圖3之所說明實施例中,第三晶粒320a及第四晶粒320b係以面對面配置來配置,且因此複數個第三電感器325a及第四電感器325b定位成彼此接近。第三晶粒320a上之第三電感器325a之至少一部分大體上與第四晶粒320b上之第四電感器325b對準。在一些實施例中,第三電感器325a可包括與第四電感器325b對準之電感器(例如,作用電感器)之第一部分及不與第四電感器325b對準之電感器(例如,非作用或孤立電感器)之第
二部分。在圖3之所說明實施例中,舉例而言,第三晶粒320a之最外第三電感器325a中之一者不與對應第四電感器325b對準,且第四晶粒320b之最外第四電感器325b中之一者不與對應第三電感器325a對準。對準之第三電感器325a及第四電感器325b經電感耦合(示意性地展示為330)且能夠無線地在彼此之間且因此在第三晶粒320a與第四晶粒320b之間傳達數據。
基板110以及第一晶粒120a、第二晶粒120b、第三晶粒320a及第四晶粒320b經由複數個互連件電耦合至彼此。除了第一複數個互連件150及第二複數個互連件152之外,裝置300亦包括(a)將第一晶粒120a電耦合至第三晶粒320a且間接地電耦合至基板110之第三複數個互連件350,及(b)將第四晶粒320b電耦合至第二晶粒120b且間接地電耦合至基板110之第四複數個互連件352。第三複數個互連件350在第一晶粒120a之第二周邊部分129b處的第一複數個晶粒焊墊156與第三晶粒310a之第四周邊部分329b處的對應第三複數個晶粒焊墊356之間延伸。除了第三複數個互連件之外或作為其替代,第三晶粒320a可經由另外複數個互連件直接地電耦合至基板110。在一些實施例中,第三複數個互連件350可在第一晶粒120a與(a)第三晶粒320a及/或(b)第四晶粒320b之間遞送功率及/或資料信號。在圖3之所說明實施例中,第三複數個互連件350不向上延伸超出與第四晶粒320b之上表面共面的平面。第四複數個互連件352在第二晶粒120b之第一周邊部分129a處的第二複數個晶粒焊墊158與第四晶粒310b之第三周邊部分329a處的對應第四複數個晶粒焊墊358之間延伸。在一些實施例中,第四複數個互連件352可在第四晶粒320b與(a)第二晶粒320b及/或(b)基板110之間遞送功率及/或資料信號。除了第四複數個互連件之外
或作為其替代,第四晶粒320b可經由另外複數個互連件直接地電耦合至基板110。
如先前描述,第一複數個基板焊墊158及第二複數個基板焊墊154及/或第一複數個晶粒焊墊156及第二複數個晶粒焊墊158可在多個組態中電耦合至彼此。類似地,第三複數個晶粒焊墊356及第四複數個晶粒焊墊358可在多個組態中電耦合至第一複數個基板焊墊158及第二複數個基板焊墊154及/或第一複數個晶粒焊墊156及第二複數個晶粒焊墊158。舉例而言,個別基板焊墊356可經由焊線直接地電耦合至彼此,且個別晶粒焊墊358可經由焊線直接地電耦合至彼此。另外,在一些實施例中,並非每一個別晶粒焊墊356皆可直接地電耦合至對應晶粒焊墊156,而是可經由另一晶粒焊墊356間接地耦合至晶粒焊墊156。類似地,並非每一個別晶粒焊墊358皆可直接地電耦合至對應晶粒焊墊158,而是可經由另一晶粒焊墊358間接地耦合至晶粒焊墊158。
儘管圖3之所說明實施例僅展示四個晶粒之堆疊(例如,120a至120b及320a至320b),但一般熟習相關技術者將理解,在類似組態中可安裝額外晶粒。舉例而言,可包括六個晶粒、八個晶粒、十個晶粒等等之堆疊。因而,本發明技術之優點為能夠將多個晶粒併入初始雙晶粒堆疊上方之雙晶粒堆疊中,而無需更改初始雙晶粒堆疊之組態。
裝置300可進一步包括囊封(例如,密封)基板110之至少一部分、第一晶粒120a、第二晶粒120b、第三晶粒320a及/或第四晶粒320b的囊封體370(例如,模具材料)。在圖3之所說明實施例中,第一複數個互連件150、第三複數個互連件350及第四複數個互連件352由囊封體370囊封,且第二複數個互連件152僅部分地由囊封體370囊封。囊封體370可
大體上類似於先前所描述之囊封體170。
圖4為根據本發明技術之另一實施例之半導體裝置400(「裝置400」)的示意性橫截面圖。更具體言之,裝置400包括與第一堆疊組態405a間隔開之第二堆疊組態405b。第一堆疊組態405a可對應於先前所描述之裝置100,且第二堆疊組態405b可對應於在結構、功能及空間定向上大體類似於裝置100之裝置。在所說明實施例中,第二堆疊組態405b繞跨越第一堆疊組態405a與第二堆疊組態405b之間的垂直軸線490反射地等同於第一堆疊組態。第二堆疊組態405b包括基板410、安置於基板410上方之第三晶粒420a及以偏移面對面配置安置於第三晶粒420上方之第四晶粒420b。第四晶粒420b自第三晶粒420a偏移,使得部分(例如,第五周邊部分)429a朝向第一堆疊配置405b延伸。第三晶粒420a包括複數個第三電感器425a,且第四晶粒420b包括複數個第四電感器425b。第三電感器425a之至少一部分電感耦合至第四電感器425b。裝置300進一步包括將基板410電耦合至第三晶粒420a之第三複數個互連件450,及將第三晶粒420b電耦合至第五周邊部分429a處之基板410的第四複數個互連件452。
上文參考圖1A至圖4所描述之半導體裝置中之任一者可併入至多種較大及/或較複雜系統中之任一者中,其代表性實例為在圖5中示意性地展示之系統590。系統590可包括半導體裝置500(「裝置500」)、電源592、驅動器594、處理器596及/或其他子系統或組件598。裝置500可包括大體上類似於上文所描述之彼等裝置的特徵。所得系統590可執行廣泛多種功能中之任一者,例如記憶體儲存、資料處理及/或其他合適功能。因此,代表性系統590可包括但不限於手持型裝置(例如,行動電話、平板電腦、數位閱讀器及數位音訊播放器)、電腦及器具。系統590之組件
可容納於單一單元中或遍及多個互連單元(例如,經由通信網路)而分佈。系統590之組件亦可包括遠端裝置及廣泛多種電腦可讀媒體中之任一者。
本發明並不意欲為窮盡性的或將本發明技術限制為本文中所揭示之精確形式。儘管本文出於說明之目的揭示了具體實施例,但如一般熟習相關技術者將認識到,可在不背離本發明技術之情況下進行各種等效修改。在一些狀況下,未展示或詳細地描述熟知結構及功能以避免不必要地混淆本發明技術之實施例之描述。儘管本文中可以特定次序呈現方法之步驟,但替代實施例可以不同次序執行該等步驟。類似地,在其他實施例中,可合併或消除在特定實施例之情形下揭示的本發明技術之某些態樣。此外,雖然可在彼等實施例之情形下揭示與本發明技術之某些實施例相關聯的優點,但其他實施例亦可展現此類優點,且並非全部實施例皆必須展現此類優點或本文中所揭示之其他優點以落入技術之範疇內。因此,本發明及相關聯技術可涵蓋本文未明確展示或描述之其他實施例,且本發明只受隨附申請專利範圍限制。
除非上下文以其他方式明確指示,否則在本發明中,單數術語「一(a/an)」及「該(the)」包括複數參照物。類似地,在提及兩項或多於兩項之清單時,除非明確地限制字語「或」僅意謂排除其他項之單個項,否則該清單中使用「或」應解釋為包括(a)該清單中之任何單個項,(b)該清單中之所有項,或(c)該清單中各項之任何組合。另外,通篇使用術語「包含」、「包括」及「具有」意謂至少包括所敍述特徵,使得不排除任何較多數目個相同特徵及/或額外類型之其他特徵。本文中對「一個實施例」、「一實施例」或類似表述之提及意謂結合實施例描述之特定特徵、結構、操作或特性可包括於本發明技術之至少一個實施例中。因此,此等
片語或表述在本文中之出現未必皆指同一實施例。此外,在一或多個實施例中,各種特定特徵、結構、操作或特性可以任何合適方式組合。
100‧‧‧半導體裝置
110‧‧‧封裝基板
112a‧‧‧上表面
112b‧‧‧下表面
120a‧‧‧第一晶粒/半導體晶粒
120b‧‧‧第二晶粒/第二半導體晶粒
121a‧‧‧第一側
121b‧‧‧第二側
122a‧‧‧第一側
122b‧‧‧第二側
125a‧‧‧第一電感器
125b‧‧‧第二電感器
129a‧‧‧第一周邊部分
129b‧‧‧第二周邊部分
140‧‧‧第一晶粒附接材料
142‧‧‧第二晶粒附接材料
143‧‧‧側向邊緣
144‧‧‧側向邊緣
145‧‧‧側向邊緣
150‧‧‧互連件
152‧‧‧互連件
154‧‧‧基板焊墊
155‧‧‧晶粒焊墊
156‧‧‧晶粒焊墊
158‧‧‧基板焊墊
160‧‧‧電連接器
170‧‧‧囊封體
171b‧‧‧下表面
1B-1B‧‧‧線
W1‧‧‧第一寬度
W2‧‧‧第二寬度
Claims (18)
- 一種半導體裝置,其包含:一封裝基板,其具有一上表面及一下表面;晶粒之一堆疊,其附接至該基板之該上表面,其中該堆疊包括一第一晶粒,其包括一前側及在該前側處之一或多個第一電感器;及一第二晶粒,其安置於該第一晶粒上方且自該第一晶粒偏移,該第二晶粒包括面向該第一晶粒之一前側及在該第二晶粒之該前側處之一或多個第二電感器,其中該等第二電感器中之一或多者電感耦合至該等第一電感器之一或多者;第一複數個焊線,其將該基板之該上表面上的第一複數個基板焊墊電耦合至該第一晶粒之該前側上的第一複數個晶粒焊墊;第二複數個焊線,其將該基板之該下表面上的第二複數個基板焊墊電耦合至該第二晶粒之該前側上的第二複數個晶粒焊墊;及一模具材料,其囊封該堆疊及該基板之至少一部分,其中該模具材料僅覆蓋該第二複數個焊線之各者之一部分。
- 如請求項1之裝置,其中該第二複數個晶粒焊墊位於突出於該第一晶粒之上的該第二晶粒之一周邊部分上。
- 如請求項1之裝置,其進一步包含在該基板與該第一晶粒之間的一第一晶粒附接膜及在該第一晶粒與該第二晶粒之間的一第二晶粒附接膜。
- 如請求項1之裝置,其中該等第一電感器包括與對應第二電感器對準之一或多個作用電感器及不與第二電感器對準之一或多個孤立電感器。
- 如請求項1之裝置,其中該第一晶粒及該第二晶粒為均質的。
- 如請求項1之裝置,其中該第一晶粒及該第二晶粒經組態以經由該等第一電感器及該等第二電感器無線地通信。
- 一種半導體裝置,其包含:一封裝基板,其具有一上表面及一下表面;晶粒之一堆疊,其附接至該基板之該上表面,其中該堆疊包括一第一晶粒,其包括一前側及在該前側處之一或多個第一電感器;及一第二晶粒,其安置於該第一晶粒上方且自該第一晶粒偏移,該第二晶粒包括面向該第一晶粒之一前側及在該第二晶粒之該前側處之一或多個第二電感器,其中該等第二電感器中之一或多者電感耦合至該等第一電感器之一或多者;第一複數個焊線,其將該基板之該上表面上的第一複數個基板焊墊電耦合至該第一晶粒之該前側上的第一複數個晶粒焊墊;及第二複數個焊線,其將該基板之該下表面上的第二複數個基板焊墊電耦合至該第二晶粒之該前側上的第二複數個晶粒焊墊,其中該等第一電感器及該等第二電感器中之一或多者各自包括一收 發器線圈及一接收器線圈,其中該接收器線圈與該收發器線圈分離且大體上與該收發器線圈共面。
- 如請求項1之裝置,其中該第一晶粒包括矽,且其中該等第一電感器嵌入於該第一晶粒中,使得每一第一電感鏈路與該第一晶粒之一作用表面分離該矽之一部分。
- 如請求項1之裝置,其進一步包含在該基板之一背側處且經組態以將該基板電耦合至一外部封裝部位的複數個電連接器。
- 一種半導體裝置,其包含:一封裝基板,其具有一上表面及一下表面;晶粒之一堆疊,其附接至該基板之該上表面,其中該堆疊包括-一第一晶粒,其包括一前側及在該前側處之一或多個第一電感器;及一第二晶粒,其安置於該第一晶粒上方且自該第一晶粒偏移,該第二晶粒包括面向該第一晶粒之一前側及在該第二晶粒之該前側處之一或多個第二電感器,其中該等第二電感器中之一或多者電感耦合至該等第一電感器之一或多者;一第三晶粒,其安置於該第二晶粒上方,該第三晶粒包括一前側及在該第三晶粒之該前側處之一或多個第三電感器;及一第四晶粒,其安置於該第三晶粒上方且自該第三晶粒偏移,該第四晶粒包括面向該第三晶粒之一前側及在該第四晶粒之該前側處 之一或多個第四電感器,其中該等第四電感器中之一或多者電感耦合至該等第三電感器中之該一或多者;第一複數個焊線,其將該基板之該上表面上的第一複數個基板焊墊電耦合至該第一晶粒之該前側上的第一複數個晶粒焊墊;及第二複數個焊線,其將該基板之該下表面上的第二複數個基板焊墊電耦合至該第二晶粒之該前側上的第二複數個晶粒焊墊。
- 如請求項10之裝置,其進一步包含:第三複數個焊線,其將該第一晶粒電耦合至該第三晶粒;及一第四複數個焊線,其將該第二晶粒之該前側上的該第二複數個晶粒焊墊電耦合至該第四晶粒之該前側上的第三複數個晶粒焊墊。
- 如請求項10之裝置,其中該第二晶粒在一第一方向上自該第一晶粒偏移,該第四晶粒在該第一方向上自該第三晶粒偏移,且該第三晶粒沿垂直於該基板之該上表面的一軸線與該第二晶粒對準。
- 一種半導體裝置,其包含:一基板,其具有一上表面及一下表面;一第一晶粒,其安裝至該基板且包括一作用側及在該作用側處之複數個第一電感器;一第二晶粒,其在一偏移位置中安裝至該第一晶粒,使得該第二晶 粒之一部分延伸超出該第一晶粒,其中該第二晶粒包括面向該第一晶粒之一作用側及在該第二晶粒之該作用側處之複數個第二電感器,且其中該等第一電感器中之一或多者電感耦合至一或多個對應第二電感器;第一複數個互連件,其將該基板電耦合至該第一晶粒;第二複數個互連件,其將該第二晶粒之該作用側電耦合至基板之該下表面且自該第二晶粒之該作用側延伸至基板之該下表面;及一模具材料,其囊封該堆疊、該第一晶粒及該第二晶粒之至少一部分,其中該模具材料僅覆蓋該第二複數個互連件之各者之一部分。
- 如請求項13之裝置,其中該第二複數個互連件將該基板之該下表面處的第一複數個基板焊墊電耦合至該第二晶粒之延伸超出該第一晶粒之該部分處的第一複數個晶粒焊墊。
- 如請求項13之裝置,其中該第一晶粒及該第二晶粒為均質的。
- 如請求項13之裝置,其中該第一晶粒包括矽,且其中該等第一電感器嵌入於該第一晶粒中,使得該等第一電感器中之每一者與該第一晶粒之一第一表面分離該矽之一部分。
- 一種半導體裝置,其包含:一第一堆疊封裝,其包括:一第一基板,其具有一上表面及一下表面;一第一晶粒,其安裝至該基板且包括一作用側及在該作用側處之複 數個第一電感器;一第二晶粒,其在一偏移位置中安裝至該第一晶粒,使得該第二晶粒之一部分延伸超出該第一晶粒,其中該第二晶粒包括面向該第一晶粒之一作用側及在該第二晶粒之該作用側處之複數個第二電感器,且其中該等第一電感器中之一或多者電感耦合至一或多個對應第二電感器;第一複數個互連件,其將該基板電耦合至該第一晶粒;第二複數個互連件,其將該第二晶粒之該作用側電耦合至基板之該下表面且自該第二晶粒之該作用側延伸至基板之該下表面一第二堆疊封裝,其與該第一堆疊封裝間隔開且包括:一第二基板,其具有一上表面及一下表面;一第三晶粒,其安裝至該第二基板之該上表面且包括一作用側及在該第三晶粒之該作用側處之複數個第三電感器;一第四晶粒,其在一偏移位置中安裝至該第三晶粒,使得該第四晶粒之一邊緣延伸超出該第三晶粒之一對應邊緣,其中該第四晶粒包括一作用側及在該第四晶粒之該作用側處之複數個第四電感器,且其中該等第三電感器中之一或多者電感耦合至一或多個對應第四電感器;第三複數個互連件,其將該第二基板電耦合至該第三晶粒;及第四複數個互連件,其將該第四晶粒之該作用側電耦合至第二基板之該下表面且自該第四晶粒之該作用側延伸至第二基板之該下表面。
- 如請求項17之裝置,其進一步包含至少部分地囊封第一堆疊組態及第二堆疊組態之一模具材料。
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JP5635759B2 (ja) | 2009-10-15 | 2014-12-03 | 学校法人慶應義塾 | 積層半導体集積回路装置 |
KR101212722B1 (ko) * | 2010-02-26 | 2013-01-09 | 에스케이하이닉스 주식회사 | 멀티 칩 패키지 |
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JP6271221B2 (ja) * | 2013-11-08 | 2018-01-31 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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JP6482973B2 (ja) * | 2015-07-10 | 2019-03-13 | 富士電機株式会社 | ガスセンサ |
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US20050206010A1 (en) * | 2004-03-18 | 2005-09-22 | Noquil Jonathan A | Multi-flip chip on lead frame on over molded IC package and method of assembly |
JP2014038880A (ja) * | 2012-08-10 | 2014-02-27 | Keio Gijuku | 積層集積回路 |
US20170040246A1 (en) * | 2015-08-07 | 2017-02-09 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
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KR102136785B1 (ko) | 2020-07-23 |
US10217726B1 (en) | 2019-02-26 |
KR20190119170A (ko) | 2019-10-21 |
TW201921615A (zh) | 2019-06-01 |
CN110494976A (zh) | 2019-11-22 |
CN110494976B (zh) | 2021-08-31 |
US20190067253A1 (en) | 2019-02-28 |
WO2019046019A1 (en) | 2019-03-07 |
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