JP5635759B2 - 積層半導体集積回路装置 - Google Patents
積層半導体集積回路装置 Download PDFInfo
- Publication number
- JP5635759B2 JP5635759B2 JP2009237872A JP2009237872A JP5635759B2 JP 5635759 B2 JP5635759 B2 JP 5635759B2 JP 2009237872 A JP2009237872 A JP 2009237872A JP 2009237872 A JP2009237872 A JP 2009237872A JP 5635759 B2 JP5635759 B2 JP 5635759B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- coil
- transmission
- semiconductor chip
- communication
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 104
- 238000004891 communication Methods 0.000 claims description 132
- 230000005540 biological transmission Effects 0.000 claims description 131
- 230000015654 memory Effects 0.000 claims description 63
- 238000003475 lamination Methods 0.000 claims description 2
- 238000012546 transfer Methods 0.000 description 34
- 238000010168 coupling process Methods 0.000 description 19
- 238000005859 coupling reaction Methods 0.000 description 19
- 238000000034 method Methods 0.000 description 15
- 230000008878 coupling Effects 0.000 description 14
- 230000001939 inductive effect Effects 0.000 description 14
- 230000000694 effects Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 230000001965 increasing effect Effects 0.000 description 7
- 230000000149 penetrating effect Effects 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 240000004050 Pentaglottis sempervirens Species 0.000 description 1
- 235000004522 Pentaglottis sempervirens Nutrition 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000005672 electromagnetic field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000002195 synergetic effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/645—Inductive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06506—Wire or wire-like electrical connections between devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H04B5/26—
-
- H04B5/72—
Description
メモリチップ102:メモリチップ101よりx方向に150μmシフトして積層。
メモリチップ103:メモリチップ102よりx方向に150μmシフトして積層。
メモリチップ104:メモリチップ103よりy方向に150μmシフトして積層。
メモリチップ105:メモリチップ104よりy方向に150μmシフトして積層。
メモリチップ106:メモリチップ105より−x方向に150μmシフトして積層。
メモリチップ107:メモリチップ106より−x方向に150μmシフトして積層。
メモリチップ108:メモリチップ107より−y方向に150μmシフトして積層。
メモリチップ109:メモリチップ108より−y方向に150μmシフトして積層。
なお、メモリチップ109はメモリチップ101の真上に重なる。
チップ101とチップ102:コイル3012とコイル3021
チップ102とチップ103:コイル3022とコイル3031
チップ103とチップ104:コイル3033とコイル3042
チップ104とチップ105:コイル3043とコイル3052
チップ105とチップ106:コイル3054とコイル3063
チップ106とチップ107:コイル3064とコイル3073
チップ107とチップ108:コイル3071とコイル3084
チップ108とチップ109:コイル3081とコイル3094
このようにして、一つのメモリチップ10に4個の送受信用コイル30を配置することによって、メモリチップ10をスライドさせて積層した場合にも、近距離チップ間通信が可能になる。
1)非同期通信方式の場合:最大通信距離はコイルの直径の1/3程度
2)同期通信方式の場合:最大通信距離はコイルの直径の1/2程度
3)受信器に増幅器を備えた同期通信方式の場合:最大通信距離はコイルの直径の1倍程度
11 メモリアレイ領域
13 制御回路
14,15 磁界減衰膜
20,30 送受信用コイル
21,31 送信コイル
22,32 受信コイル
23,33 送信器
24,34 受信器
40 コントローラチップ
41 送受信用コイル
50 NANDフラッシュメモリチップ
51 メモリアレイ領域
52 送受信用コイル
60 コントローラチップ
Claims (4)
- 同一外観形状の半導体チップを4枚以上積層した積層構造を有する積層半導体集積回路装置であって、
前記各半導体チップに長距離チップ間通信用の第1の送受信用コイルと、
前記第1の送受信用コイルよりサイズの小さな近距離チップ間通信用の第2の送受信用コイルとを備え、
前記第1の送受信用コイル及び前記第2の送受信用コイルが多角形状のコイルであり、前記第1の送受信用コイル及び前記第2の送受信用コイルに内接する円の直径が、コイルのサイズに応じて設定したチップ間通信距離の1倍乃至3倍であり、且つ、前記第1の送受信用コイルに内接する円の直径が、前記半導体チップの積層ピッチの4倍乃至36倍である積層半導体集積回路装置。 - 前記積層構造が、最下層の前記半導体チップに対して、前記半導体チップの二対の対向辺の内、一方の対向辺を一致させるとともに、他方の対辺を前記一方の対向辺の延在方向に沿った第1の方向に順次所定のピッチでずらして積層した所定枚数の第1の半導体チップ群と、
前記第1の半導体チップ群の最上層の半導体チップに対して前記他方の対向辺を一致させるとともに、前記一方の対辺を前記他方の対向辺の延在方向に沿った第2の方向に順次所定のピッチでずらして積層した所定枚数の第2の半導体チップ群と、
前記第2の半導体チップ群の最上層の半導体チップに対して前記一方の対向辺を一致させるとともに、前記他方の対辺を前記第1の方向と反対方向の第3の方向に順次所定のピッチでずらして積層した前記第1の半導体チップ群と同じ枚数の第3の半導体チップ群と、
前記第3の半導体チップ群の最上層の半導体チップに対して前記他方の対向辺を一致させるとともに、前記一方の対辺を前記第2の方向と反対方向の第4の方向に順次所定のピッチでずらして積層した前記第2の半導体チップ群と同じ枚数の第4の半導体チップ群とを少なくとも有する請求項1に記載の積層半導体集積回路装置。 - 前記積層構造の最上層の前記半導体チップの上或いは最下層の前記半導体チップの下に、前記半導体チップよりサイズの小さく、且つ、チップ間通信用として前記第2の送受信用コイルのサイズと同じサイズの第3の送受信用コイルのみを有する異なった外観形状の半導体チップとを積層した請求項1または請求項2に記載の積層半導体集積回路装置。
- 前記同一外観形状の半導体チップは、フラッシュメモリチップであり、前記異なった外観形状の半導体チップが、前記フラッシュメモリの動作を制御するコントローラチップである請求項3に記載の積層半導体集積回路装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009237872A JP5635759B2 (ja) | 2009-10-15 | 2009-10-15 | 積層半導体集積回路装置 |
PCT/JP2010/067727 WO2011046071A1 (ja) | 2009-10-15 | 2010-10-08 | 積層半導体集積回路装置 |
US13/501,879 US8744349B2 (en) | 2009-10-15 | 2010-10-08 | Multi-stack semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009237872A JP5635759B2 (ja) | 2009-10-15 | 2009-10-15 | 積層半導体集積回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011086738A JP2011086738A (ja) | 2011-04-28 |
JP5635759B2 true JP5635759B2 (ja) | 2014-12-03 |
Family
ID=43876121
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009237872A Active JP5635759B2 (ja) | 2009-10-15 | 2009-10-15 | 積層半導体集積回路装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8744349B2 (ja) |
JP (1) | JP5635759B2 (ja) |
WO (1) | WO2011046071A1 (ja) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5671200B2 (ja) * | 2008-06-03 | 2015-02-18 | 学校法人慶應義塾 | 電子回路 |
EP2548226A4 (en) * | 2010-03-18 | 2013-11-20 | Mosaid Technologies Inc | MULTICHIP PACKAGE WITH ADJUSTED MATRIZE STACKING AND MANUFACTURING METHOD THEREFOR |
US9086452B2 (en) * | 2012-08-10 | 2015-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimensional integrated circuit and method for wireless information access thereof |
US9653927B2 (en) | 2012-08-10 | 2017-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Composite integrated circuits and methods for wireless interactions therewith |
JP2015069658A (ja) * | 2013-09-26 | 2015-04-13 | 富士通株式会社 | メモリ |
JP2015073146A (ja) * | 2013-10-01 | 2015-04-16 | ソニー株式会社 | 記録装置 |
US9886193B2 (en) | 2015-05-15 | 2018-02-06 | International Business Machines Corporation | Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration |
WO2017010011A1 (ja) * | 2015-07-16 | 2017-01-19 | 株式会社PEZY Computing | 半導体スイッチ装置 |
CN107924870B (zh) * | 2015-07-16 | 2022-04-05 | Pezy计算股份有限公司 | 半导体装置 |
JP6686048B2 (ja) * | 2016-01-18 | 2020-04-22 | ウルトラメモリ株式会社 | 半導体装置 |
US9928460B1 (en) * | 2017-06-16 | 2018-03-27 | Google Llc | Neural network accelerator tile architecture with three-dimensional stacking |
US10217726B1 (en) | 2017-08-31 | 2019-02-26 | Micron Technology, Inc. | Stacked semiconductor dies including inductors and associated methods |
EP3849095B1 (en) * | 2018-10-10 | 2024-04-17 | Siemens Aktiengesellschaft | System and modules for communication |
US11689065B2 (en) * | 2019-02-15 | 2023-06-27 | Honda Motor Co., Ltd. | System and methods for charging a device |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE60129793T2 (de) * | 2000-01-28 | 2008-04-30 | Interuniversitair Micro-Electronica Centrum Vzw | Verfahren zum transfer und stapeln von halbleiterbausteinen |
JP2007305143A (ja) | 2001-03-09 | 2007-11-22 | Ricoh Co Ltd | 情報処理装置および情報処理方法 |
JP4131544B2 (ja) | 2004-02-13 | 2008-08-13 | 学校法人慶應義塾 | 電子回路 |
JP4193060B2 (ja) | 2004-06-04 | 2008-12-10 | 学校法人慶應義塾 | 電子回路 |
JP4677598B2 (ja) | 2004-08-05 | 2011-04-27 | 学校法人慶應義塾 | 電子回路 |
JP4124365B2 (ja) | 2004-08-24 | 2008-07-23 | 学校法人慶應義塾 | 電子回路 |
JP5024740B2 (ja) | 2004-09-30 | 2012-09-12 | 学校法人慶應義塾 | Lsiチップ試験装置 |
JP2006173986A (ja) | 2004-12-15 | 2006-06-29 | Keio Gijuku | 電子回路 |
JP2006173415A (ja) | 2004-12-16 | 2006-06-29 | Keio Gijuku | 電子回路 |
JP4926653B2 (ja) | 2006-10-31 | 2012-05-09 | 京セラ株式会社 | プラズマ発生体、反応装置及び光源装置 |
JP5034455B2 (ja) | 2006-11-24 | 2012-09-26 | マツダ株式会社 | カーテンエアバッグ装置を備えた車両の内装構造 |
JP2008146248A (ja) | 2006-12-07 | 2008-06-26 | Nippon Telegraph & Telephone West Corp | プローブデータ解析システム |
JP5149554B2 (ja) * | 2007-07-17 | 2013-02-20 | 株式会社日立製作所 | 半導体装置 |
US20090027162A1 (en) * | 2007-07-23 | 2009-01-29 | Forster Ian J | Controllable rfid device, and method |
WO2009069532A1 (ja) * | 2007-11-26 | 2009-06-04 | Keio University | 電子回路 |
JP5231043B2 (ja) | 2008-02-21 | 2013-07-10 | 株式会社荏原製作所 | 可搬式排水ポンプ装置 |
US9305606B2 (en) * | 2009-08-17 | 2016-04-05 | Micron Technology, Inc. | High-speed wireless serial communication link for a stacked device configuration using near field coupling |
-
2009
- 2009-10-15 JP JP2009237872A patent/JP5635759B2/ja active Active
-
2010
- 2010-10-08 US US13/501,879 patent/US8744349B2/en active Active
- 2010-10-08 WO PCT/JP2010/067727 patent/WO2011046071A1/ja active Application Filing
Also Published As
Publication number | Publication date |
---|---|
US8744349B2 (en) | 2014-06-03 |
JP2011086738A (ja) | 2011-04-28 |
US20120217658A1 (en) | 2012-08-30 |
WO2011046071A1 (ja) | 2011-04-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5635759B2 (ja) | 積層半導体集積回路装置 | |
KR101608757B1 (ko) | 인덕터를 포함하는 집적 회로 소자, 집적 회로 장치, 및 삼차원 실장 회로 장치 | |
US7385281B2 (en) | Semiconductor integrated circuit device | |
KR101009502B1 (ko) | 반도체 장치 | |
US20090134489A1 (en) | System including an inter-chip communication system | |
JP5325495B2 (ja) | 半導体装置及びその製造方法 | |
KR101495823B1 (ko) | 전자회로 | |
CN102089826B (zh) | 邻近光存储器模块 | |
US8283944B2 (en) | Electronic circuit device | |
US9749020B2 (en) | Integrated circuit and layered circuit provided therewith | |
JP5426966B2 (ja) | 半導体集積回路装置 | |
Han | Wireless Interconnect using Inductive Coupling in 3D-ICs. | |
Saito et al. | 47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking | |
JP5791326B2 (ja) | 積層集積回路装置 | |
JP6005438B2 (ja) | 積層集積回路 | |
CN111508921B (zh) | 具有双面对外接点的半导体芯片组 | |
JP2012156186A (ja) | 積層型半導体集積回路装置 | |
CN111952298B (zh) | 神经网络智能芯片及其形成方法 | |
TW202412218A (zh) | 半導體模組及其製造方法 | |
CN103218648A (zh) | 一种近场通信芯片 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20120927 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140212 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140410 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20141007 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20141017 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5635759 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |