JP6005438B2 - 積層集積回路 - Google Patents
積層集積回路 Download PDFInfo
- Publication number
- JP6005438B2 JP6005438B2 JP2012178719A JP2012178719A JP6005438B2 JP 6005438 B2 JP6005438 B2 JP 6005438B2 JP 2012178719 A JP2012178719 A JP 2012178719A JP 2012178719 A JP2012178719 A JP 2012178719A JP 6005438 B2 JP6005438 B2 JP 6005438B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- coil
- integrated circuit
- stacked
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
図6の構造と図1の構造を積み重ねることで、任意の奇数枚数のチップ積層に対して、実施例1に説明したことを実現できる。例えば、図5でチップ8を取り除いてチップ7を図6のチップ3と同様にすれば、積層枚数を7枚にできる。
12…接着剤
13…電源線
14…バンプ
21…シールド層
C1、C2 コイル
P1 パッド
Claims (3)
- 第1コイルに接続される第1送受信器を有する第1チップと、
該第1チップと背中合わせに積層され、前記第1コイルと誘導結合する第2コイルに接続される第2送受信器を有する第2チップと、
該第2チップの表面に積層され第2チップに電源を供給する回路基板と、
該回路基板を挟んで前記第2チップと向かい合わせに積層され、前記第2送受信器と通信する第3送受信器を有し前記回路基板から電源を供給される第3チップと
を備え、
前記第2チップは前記第1コイル及び第2コイルと疎結合であり前記第2送受信器と接続される第3コイルを有し、前記第3チップは前記第1コイル及び第2コイルと疎結合であり前記第3コイルと誘導結合し前記第3送受信器と接続される第4コイルを有し、前記第2送受信器と第3送受信器とは前記回路基板を介して前記第3コイルと第4コイルとの誘導結合により通信することを特徴とする積層集積回路。 - 前記第1チップと第2チップとは、絶縁性かつ熱伝導性の接着剤により接着され積層されていることを特徴とする請求項1記載の積層集積回路。
- 前記第1チップと第2チップとの間には、絶縁性かつ熱伝導性の材料が挟まれていることを特徴とする請求項1記載の積層集積回路。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012178719A JP6005438B2 (ja) | 2012-08-10 | 2012-08-10 | 積層集積回路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012178719A JP6005438B2 (ja) | 2012-08-10 | 2012-08-10 | 積層集積回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014038880A JP2014038880A (ja) | 2014-02-27 |
JP6005438B2 true JP6005438B2 (ja) | 2016-10-12 |
Family
ID=50286802
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012178719A Active JP6005438B2 (ja) | 2012-08-10 | 2012-08-10 | 積層集積回路 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP6005438B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6336688B1 (ja) * | 2017-02-13 | 2018-06-06 | 新電元工業株式会社 | 電子モジュール |
US10217726B1 (en) * | 2017-08-31 | 2019-02-26 | Micron Technology, Inc. | Stacked semiconductor dies including inductors and associated methods |
JP7251951B2 (ja) * | 2018-11-13 | 2023-04-04 | 新光電気工業株式会社 | 半導体装置及び半導体装置の製造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001024150A (ja) * | 1999-07-06 | 2001-01-26 | Sony Corp | 半導体装置 |
JP4878502B2 (ja) * | 2006-05-29 | 2012-02-15 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
-
2012
- 2012-08-10 JP JP2012178719A patent/JP6005438B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
JP2014038880A (ja) | 2014-02-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101009502B1 (ko) | 반도체 장치 | |
WO2009139372A1 (ja) | インダクタ素子、集積回路装置、及び、三次元実装回路装置 | |
JP2014011169A (ja) | シリコンインターポーザ及びこれを備える半導体装置 | |
US9165893B2 (en) | Semiconductor device including coupling conductive pattern | |
KR20100094516A (ko) | 전자회로 | |
JP4858692B2 (ja) | チップ積層型半導体装置 | |
US8736074B2 (en) | Multi chip semiconductor device | |
JP2014533895A (ja) | スタック半導体素子のためのインターポーザー | |
JP4445511B2 (ja) | マルチチップ半導体装置 | |
JP6005438B2 (ja) | 積層集積回路 | |
JP2008109094A (ja) | 素子搭載用基板および半導体モジュール | |
JP4199724B2 (ja) | 積層型半導体パッケージ | |
JP4580004B2 (ja) | 半導体装置 | |
JP2008103725A (ja) | 可撓性フィルム、並びにこれを用いた半導体パッケージ及び製造方法 | |
JP6142800B2 (ja) | 半導体装置及びその製造方法 | |
KR20090118747A (ko) | 관통 전극을 가지는 반도체 칩 패키지 및 인쇄회로기판 | |
US9224682B2 (en) | Semiconductor device | |
KR102339899B1 (ko) | 반도체 패키지, 모듈 기판 및 이를 포함하는 반도체 패키지 모듈 | |
JP2014222728A (ja) | 半導体パッケージ | |
JP2002033443A (ja) | 半導体モジュール | |
US7999370B2 (en) | Semiconductor chip capable of increased number of pads in limited region and semiconductor package using the same | |
JP2010109111A (ja) | 半導体集積回路 | |
JP2011211077A (ja) | 半導体積層パッケージ及びその製造方法 | |
CN106158816A (zh) | 封装基板 | |
JP2010177530A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20150515 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20160304 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20160330 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160530 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20160713 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20160713 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20160817 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20160907 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6005438 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |