JP2014038880A - 積層集積回路 - Google Patents
積層集積回路 Download PDFInfo
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- JP2014038880A JP2014038880A JP2012178719A JP2012178719A JP2014038880A JP 2014038880 A JP2014038880 A JP 2014038880A JP 2012178719 A JP2012178719 A JP 2012178719A JP 2012178719 A JP2012178719 A JP 2012178719A JP 2014038880 A JP2014038880 A JP 2014038880A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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Abstract
【解決手段】チップ1とチップ2は裏面同士を接着剤12によって接着されて積層され、その際、コイル1とコイル2が誘導結合する位置に配置される。チップ3とチップ4も同様に積層される。チップ2とチップ3は、間に回路基板を挟んで表面同士を向かい合わせて積層される。チップ2とチップ3はパンプ接続する電源線13によって通信する。チップ1、4、及び回路基板への電源供給は、パッケージ基板からのボンディングワイヤ11による。チップ1にはパッケージ基板に空けた穴を通してパッケージ基板の裏側からボンディングワイヤ11で電源線を配線している。
【選択図】図1
Description
図6の構造と図1の構造を積み重ねることで、任意の奇数枚数のチップ積層に対して、実施例1に説明したことを実現できる。例えば、図5でチップ8を取り除いてチップ7を図6のチップ3と同様にすれば、積層枚数を7枚にできる。
12…接着剤
13…電源線
14…バンプ
21…シールド層
C1、C2 コイル
P1 パッド
Claims (5)
- 第1コイルに接続される第1送受信器を有する第1チップと、
該第1チップと背中合わせに積層され、前記第1コイルと誘導結合する第2コイルに接続される第2送受信器を有する第2チップと、
該第2チップの表面に積層され第2チップに電源を供給する回路基板と、
該回路基板を挟んで前記第2チップと向かい合わせに積層され、前記第2送受信器と通信する第3送受信器を有し前記回路基板から電源を供給される第3チップと
を備えることを特徴とする積層集積回路。 - 前記第2送受信器と第3送受信器とは前記回路基板を介して有線により通信することを特徴とする請求項1記載の積層集積回路。
- 前記第2チップは前記第2コイル及び第3コイルと疎結合であり前記第2送受信器と接続される第4コイルを有し、前記第3チップは前記第2コイル及び第3コイルと疎結合であり第4コイルと誘導結合し前記第3送受信器と接続される第5コイルを有し、前記第2送受信器と第3送受信器とは前記回路基板を介して前記第4コイルと第5コイルとの誘導結合により通信することを特徴とする請求項1記載の積層集積回路。
- 前記第1チップと第2チップとは、絶縁性かつ熱伝導性の接着剤により接着され積層されていることを特徴とする請求項1乃至3いずれかに記載の積層集積回路。
- 前記第1チップと第2チップとの間には、絶縁性かつ熱伝導性の材料が挟まれていることを特徴とする請求項1乃至3いずれかに記載の積層集積回路。
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JP2014038880A true JP2014038880A (ja) | 2014-02-27 |
JP6005438B2 JP6005438B2 (ja) | 2016-10-12 |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108738369A (zh) * | 2017-02-13 | 2018-11-02 | 新电元工业株式会社 | 电子模块 |
US10217726B1 (en) | 2017-08-31 | 2019-02-26 | Micron Technology, Inc. | Stacked semiconductor dies including inductors and associated methods |
JP2020080370A (ja) * | 2018-11-13 | 2020-05-28 | 新光電気工業株式会社 | 半導体装置及び半導体装置の製造方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001024150A (ja) * | 1999-07-06 | 2001-01-26 | Sony Corp | 半導体装置 |
JP2007318003A (ja) * | 2006-05-29 | 2007-12-06 | Nec Electronics Corp | 半導体装置 |
-
2012
- 2012-08-10 JP JP2012178719A patent/JP6005438B2/ja active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001024150A (ja) * | 1999-07-06 | 2001-01-26 | Sony Corp | 半導体装置 |
JP2007318003A (ja) * | 2006-05-29 | 2007-12-06 | Nec Electronics Corp | 半導体装置 |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108738369A (zh) * | 2017-02-13 | 2018-11-02 | 新电元工业株式会社 | 电子模块 |
US10217726B1 (en) | 2017-08-31 | 2019-02-26 | Micron Technology, Inc. | Stacked semiconductor dies including inductors and associated methods |
WO2019046019A1 (en) * | 2017-08-31 | 2019-03-07 | Micron Technology, Inc. | STACKED SEMICONDUCTOR CHIPS COMPRISING INDUCTORS, AND ASSOCIATED METHODS |
US10446527B2 (en) | 2017-08-31 | 2019-10-15 | Micron Technology, Inc. | Stacked semiconductor dies including inductors and associated methods |
KR20190119170A (ko) * | 2017-08-31 | 2019-10-21 | 마이크론 테크놀로지, 인크 | 인덕터를 포함하는 적층형 반도체 다이 및 연관된 방법 |
CN110494976A (zh) * | 2017-08-31 | 2019-11-22 | 美光科技公司 | 包含电感器的堆叠半导体裸片及相关的方法 |
TWI691028B (zh) * | 2017-08-31 | 2020-04-11 | 美商美光科技公司 | 包括電感器之堆疊的半導體晶粒及相關之方法 |
KR102136785B1 (ko) | 2017-08-31 | 2020-07-23 | 마이크론 테크놀로지, 인크 | 인덕터를 포함하는 적층형 반도체 다이 및 연관된 방법 |
CN110494976B (zh) * | 2017-08-31 | 2021-08-31 | 美光科技公司 | 包含电感器的堆叠半导体裸片及相关的方法 |
JP2020080370A (ja) * | 2018-11-13 | 2020-05-28 | 新光電気工業株式会社 | 半導体装置及び半導体装置の製造方法 |
JP7251951B2 (ja) | 2018-11-13 | 2023-04-04 | 新光電気工業株式会社 | 半導体装置及び半導体装置の製造方法 |
US11817422B2 (en) | 2018-11-13 | 2023-11-14 | Shinko Electric Industries Co., Ltd. | Semiconductor device |
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