JP6449439B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP6449439B2 JP6449439B2 JP2017508905A JP2017508905A JP6449439B2 JP 6449439 B2 JP6449439 B2 JP 6449439B2 JP 2017508905 A JP2017508905 A JP 2017508905A JP 2017508905 A JP2017508905 A JP 2017508905A JP 6449439 B2 JP6449439 B2 JP 6449439B2
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- Prior art keywords
- main surface
- substrate
- contact signal
- interposer substrate
- interposer
- Prior art date
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- 239000000758 substrate Substances 0.000 claims description 357
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- 239000000463 material Substances 0.000 claims description 11
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 26
- 229910052710 silicon Inorganic materials 0.000 description 26
- 239000010703 silicon Substances 0.000 description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
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- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000001939 inductive effect Effects 0.000 description 3
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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Description
第1素子第1主面22は、ベース基板内部端子面11に対向している。各々の第1素子信号送受信端子24は、第1素子導電性部材24Aを介して、各々の第1素子側ベース基板内部端子13Aに電気的に接続されている。第1素子導電性部材24Aは、ハンダ、導電性接着剤等の導電性部材である。そのため、第1素子信号送受信端子24と第1素子側ベース基板内部端子13Aとは、接触して信号の送受信が可能であるといえる。第1素子20は、第1素子導電性部材24Aによって、ベース基板10の上に固定されている。第1素子20は、ベース基板10にフェイスダウン接続されることになる。
各々の第1素子非接触信号送受信コイル本体部25Bは、導電性部材を介して、複数の第1素子側ベース基板内部端子13Aに電気的に接続されない。
各々の第2素子非接触信号送受信コイル本体部35Bは、導電性部材を介して、複数の第2素子側ベース基板内部端子13Bに電気的に接続されない。
同様に、インターポーザー基板40は、第2素子第2主面非接触信号送受信部対向領域33Bを覆うとともに、第2素子第2主面端子対向領域33Aの一部も覆っている。
複数のベース基板内部端子13が設けられたベース基板内部端子面11を有するベース基板10と、第1素子第1主面22と、第1素子第1主面22と反対の面である第1素子第2主面23とを有する第1素子基板21であって、第1素子第1主面22側に設けられた第1素子信号送受信端子24と、第1素子第1主面22側に設けられた第1素子非接触信号送受信コイル25と、を有する第1素子20と、第2素子第1主面32と、第2素子第1主面32と反対の面である第2素子第2主面33とを有する第2素子基板31であって、第2素子第1主面32側に設けられた第2素子信号送受信端子34と、第2素子第1主面32側に設けられた第2素子非接触信号送受信コイル35と、を有する第2素子30と、インターポーザー基板第1非接触信号送受信コイル43と、インターポーザー基板第1主面41を有するインターポーザー基板40であって、インターポーザー基板第1主面41側に設けられたインターポーザー基板第1非接触信号送受信コイル43と、インターポーザー基板第1主面41側に設けられ、インターポーザー基板第1非接触信号送受信コイル43と電気的に接続されたインターポーザー基板第2非接触信号送受信コイル44と、を有するインターポーザー基板40を備えている。そして、第1素子20は、第1素子第1主面22がベース基板内部端子面11に対向するようにベース基板10上に配置されており、第1素子信号送受信端子24と複数のベース基板内部端子13の1つとは、接触して信号の送受信が可能であり、第2素子30は、第2素子第1主面32がベース基板内部端子面11に対向するようにベース基板10上に配置されており、第2素子信号送受信端子34と複数のベース基板内部端子13の1つとは、接触して信号の送受信が可能であり、インターポーザー基板40は、インターポーザー基板第1主面41が第1素子第2主面23及び前記第2素子第2主面33に対向するように第1素子20及び第2素子30に跨って配置されており、インターポーザー基板第1非接触信号送受信コイル43は、第1素子基板21を介して、第1素子非接触信号送受信コイル25と非接触に信号の送受信が可能であり、インターポーザー基板第2非接触信号送受信コイル44は、第2素子基板31を介して、第2素子非接触信号送受信コイル35と非接触に信号の送受信が可能である。
次に、本発明の第2実施形態について、図3を参照しながら説明する。図3は、本発明の第2実施形態の半導体装置1Aを説明するための図であり、図3(A)は、第2実施形態の半導体装置1Aの断面図、図3(B)は、インターポーザー基板40をインターポーザー基板第1主面から見た平面図である。
第2実施形態の半導体装置1Aにおいては、第1素子基板21、第2素子基板31及びインターポーザー基板40は、シリコンで形成されており、インターポーザー基板40のインターポーザー基板第1主面41は、シリコンが露出した露出部分を有し、露出部分は、第1素子第2主面端子対向領域23Aの一部及び第2素子第2主面端子対向領域33Aの一部に接触している。そのため、インターポーザー基板40が大きくなっても、第1素子側露出部分41B及び第2素子側露出部分41Cが存在するため、第1素子20の熱や第2素子30の熱は放熱される。そのため、インターポーザー基板40の形状は、第1素子第2主面非接触信号送受信部対向領域23B及び第2素子第2主面非接触信号送受信部対向領域33Bの形状による制約を受けないだけでなく、第1素子20や第2素子30で発生する熱による制約も受け難い。
次に、本発明の第3実施形態について、図4を参照しながら説明する。図4は、インターポーザー基板の配置のバリエーションを説明するための図であり、図4(A)は、3つの素子にインターポーザー基板を適用した場合を示す図、図4(B)は、4つの素子にインターポーザー基板を適用した場合を示す図、図4(C)は、5つの素子にインターポーザー基板を適用した場合を示す図である。
10 ベース基板
11 ベース基板内部端子面(ベース基板端子面)
12 ベース基板外部端子面
13 ベース基板内部端子(ベース基板端子)
13A 第1素子側ベース基板内部端子
13B 第2素子側ベース基板内部端子
14 ベース基板外部端子
20 第1素子
21 第1素子基板
22 第1素子第1主面
22A 第1素子絶縁層
23 第1素子第2主面
23A 第1素子第2主面端子対向領域
23B 第1素子第2主面非接触信号送受信部対向領域
24 第1素子信号送受信端子
24A 第1素子導電性部材
25 第1素子非接触信号送受信コイル(第1素子非接触信号送受信部)
25A 第1素子非接触信号送受信コイル配線部
25B 第1素子非接触信号送受信コイル本体部
25C 第1素子非接触信号送受信コイル用ビアホール
30 第2素子
31 第2素子基板
32 第2素子第1主面
32A 第2素子絶縁層
33 第2素子第2主面
33A 第2素子第2主面端子対向領域
33B 第2素子第2主面非接触信号送受信部対向領域
34 第2素子信号送受信端子
34A 第2素子導電性部材
35 第2素子非接触信号送受信コイル(第2素子非接触信号送受信部)
40 インターポーザー基板
41 インターポーザー基板第1主面
41A インターポーザー基板絶縁層
41B 第1素子側露出部分
41C 第2素子側露出部分
42 インターポーザー基板第2主面
43 インターポーザー基板第1非接触信号送受信コイル(インターポーザー基板第1非接触信号送受信部)
44 インターポーザー基板第2非接触信号送受信コイル(インターポーザー基板第2非接触信号送受信部)
45 インターポーザー基板配線
Claims (2)
- 複数のベース基板端子が設けられたベース基板端子面を有するベース基板と、
第1素子第1主面と、前記第1素子第1主面と反対の面である第1素子第2主面とを有する第1素子基板と、前記第1素子基板の前記第1素子第1主面側に設けられた第1素子信号送受信端子と、前記第1素子基板の前記第1素子第1主面側に設けられた第1素子非接触信号送受信部と、を有する第1素子と、
第2素子第1主面と、前記第2素子第1主面と反対の面である第2素子第2主面とを有する第2素子基板と、前記第2素子基板の前記第2素子第1主面側に設けられた第2素子信号送受信端子と、前記第2素子基板の前記第2素子第1主面側に設けられた第2素子非接触信号送受信部と、を有する第2素子と、
インターポーザー基板第1主面を有するインターポーザー基板であって、前記インターポーザー基板第1主面側に設けられたインターポーザー基板第1非接触信号送受信部と、前記インターポーザー基板第1主面側に設けられ、前記インターポーザー基板第1非接触信号送受信部と電気的に接続されたインターポーザー基板第2非接触信号送受信部と、を有するインターポーザー基板と、を備え、
前記第1素子は、前記第1素子第1主面が前記ベース基板端子面に対向するように前記ベース基板上に配置されており、前記第1素子信号送受信端子と前記複数のベース基板端子の1つとは、接触して信号の送受信が可能であり、
前記第2素子は、前記第2素子第1主面が前記ベース基板端子面に対向するように前記ベース基板上に配置されており、前記第2素子信号送受信端子と前記複数のベース基板端子の1つとは、接触して信号の送受信が可能であり、
前記インターポーザー基板は、前記インターポーザー基板第1主面が前記第1素子第2主面及び前記第2素子第2主面に対向するように前記第1素子及び前記第2素子に跨って配置されており、前記インターポーザー基板第1非接触信号送受信部は、前記第1素子基板を介して、前記第1素子非接触信号送受信部と非接触に信号の送受信が可能であり、前記インターポーザー基板第2非接触信号送受信部は、前記第2素子基板を介して、前記第2素子非接触信号送受信部と非接触に信号の送受信が可能であり、
前記第1素子第2主面は、前記第1素子第1主面における前記第1素子信号送受信端子が設けられている領域の反対の面である第1素子第2主面端子対向領域と、前記第1素子第1主面における前記第1素子非接触信号送受信部が設けられている領域の反対の面である第1素子第2主面非接触信号送受信部対向領域と、を有し、
前記第2素子第2主面は、前記第2素子第1主面における前記第2素子信号送受信端子が設けられている領域の反対面である第2素子第2主面端子対向領域と、前記第2素子第1主面における前記第2素子非接触信号送受信部が設けられている領域の反対面である第2素子第2主面非接触信号送受信部対向領域と、を有し、
前記インターポーザー基板の前記インターポーザー基板第1主面は、前記第1素子第2主面非接触信号送受信部対向領域及び前記第2素子第2主面非接触信号送受信部対向領域に対向し、前記第1素子第2主面端子対向領域の一部及び前記第2素子第2主面端子対向領域の一部の少なくとも一方にも対向しており、
前記第1素子基板、前記第2素子基板及び前記インターポーザー基板は、半導体材料で形成されており、前記インターポーザー基板の前記インターポーザー基板第1主面は、前記半導体材料が露出した露出部分を有し、前記露出部分は、前記第1素子第2主面端子対向領域の一部及び前記第2素子第2主面端子対向領域の一部の少なくとも一方に接触している半導体装置。 - 前記第1素子非接触信号送受信部、前記第2素子非接触信号送受信部、前記インターポーザー基板第1非接触信号送受信部及び前記インターポーザー基板第2非接触信号送受信部は、配線により形成されたコイルである請求項1に記載の半導体装置。
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