WO2016157387A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2016157387A1
WO2016157387A1 PCT/JP2015/059999 JP2015059999W WO2016157387A1 WO 2016157387 A1 WO2016157387 A1 WO 2016157387A1 JP 2015059999 W JP2015059999 W JP 2015059999W WO 2016157387 A1 WO2016157387 A1 WO 2016157387A1
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WIPO (PCT)
Prior art keywords
main surface
substrate
contact signal
interposer substrate
interposer
Prior art date
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PCT/JP2015/059999
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English (en)
French (fr)
Inventor
齊藤　元章
Original Assignee
株式会社ＰＥＺＹ Ｃｏｍｐｕｔｉｎｇ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 株式会社ＰＥＺＹ Ｃｏｍｐｕｔｉｎｇ filed Critical 株式会社ＰＥＺＹ Ｃｏｍｐｕｔｉｎｇ
Priority to JP2017508905A priority Critical patent/JP6449439B2/ja
Priority to US15/549,589 priority patent/US10192836B2/en
Priority to PCT/JP2015/059999 priority patent/WO2016157387A1/ja
Priority to EP15887540.1A priority patent/EP3279938B1/en
Publication of WO2016157387A1 publication Critical patent/WO2016157387A1/ja

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Definitions

  • the present invention relates to a semiconductor device including an interposer substrate having a non-contact signal transmission / reception unit.
  • a semiconductor device including a silicon interposer 60 provided with inductors 304 and 324 functioning as non-contact signal transmitting / receiving units is known (see FIG. 4 of Patent Document 1).
  • two elements semiconductor chip 10 and semiconductor chip 20
  • the silicon interposer 60 is disposed on the surface of the two elements 10 and 20 where the wiring and terminals are provided.
  • a semiconductor device including a third module 90 provided with couplers 92 and 93 that function as non-contact signal transmission / reception units (FIGS. 22 and 23 of Patent Document 2).
  • a semiconductor device including a third module 90 provided with couplers 92 and 93 that function as non-contact signal transmission / reception units (FIGS. 22 and 23 of Patent Document 2).
  • two elements the first module 70 and the second module 80 transmit and receive signals to and from each other via the third module 90.
  • the third module 90 is electrically connected to the first module 70 via a bonding wire 79, and is electrically connected to the second module 80 via a bonding wire 89.
  • the semiconductor device has a configuration that can be easily reduced in size. Further, it is desirable that the semiconductor device has a configuration that can be easily manufactured.
  • the silicon interposer 60 is disposed on the surface on which the wiring and terminals of the two elements (semiconductor chip 10 and semiconductor chip 20) are formed.
  • the area of the semiconductor chip 10 where the non-contact transmitting / receiving unit 302 is formed and the width of the area where the non-contact transmitting / receiving unit 322 of the semiconductor chip 20 is formed are: A means of narrowing can be considered. When this means is adopted, it is necessary to narrow the width of the silicon interposer 60 in accordance with the width of the narrowed region.
  • the width of the silicon interposer 60 is reduced, the width in the depth direction remains the same, so the aspect ratio (aspect ratio) of the silicon interposer 60 is increased. That is, the silicon interposer 60 has an extremely long shape (for example, a shape having an aspect ratio of 10 to 100). Such an elongated silicon interposer 60 is likely to have a poor yield. In addition, the elongated silicon interposer 60 is likely to be difficult to handle. For this reason, the semiconductor device of Patent Document 1 cannot be said to have a configuration that can be reduced in size, and cannot be said to be a configuration that can be easily manufactured.
  • the interposer 90 (third module 90) is provided with non-contact signal transmitting / receiving units 92 and 93 and terminals corresponding to the bonding wires 79 and 89. Therefore, the interposer 90 (third module 90) tends to have a complicated structure.
  • the non-contact signal transmitting / receiving units 92 and 93 are aligned and the terminals corresponding to the bonding wires 79 and 89 are aligned. Will be performed at the same time. Therefore, assembly of the first module 70, the second module 80, and the interposer 90 (third module 90) is required to be aligned with high accuracy. Therefore, it cannot be said that the semiconductor device disclosed in Patent Document 2 has a configuration that can be easily reduced in size and that can be easily manufactured.
  • An object of the present invention is to provide a semiconductor device including an interposer substrate having a non-contact signal transmission / reception unit, having a configuration that can be easily reduced in size and that can be easily manufactured. To do.
  • the present invention provides a base substrate having a base substrate terminal surface provided with a plurality of base substrate terminals, a first element first main surface, and a first element first surface which is a surface opposite to the first element first main surface.
  • a first element substrate having two main surfaces, a first element signal transmission / reception terminal provided on the first element first main surface side of the first element substrate, and the first element substrate of the first element substrate.
  • a first element having a first element non-contact signal transmission / reception unit provided on one main surface side; a second element first main surface; and a second element that is a surface opposite to the second element first main surface.
  • a second element substrate having an element second main surface; a second element signal transmitting / receiving terminal provided on the second element first main surface side of the second element substrate; and the second element substrate.
  • a second element having a second element non-contact signal transmitting / receiving unit provided on the element first main surface side, and an interposer substrate first main surface
  • An interposer substrate having an interposer substrate first non-contact signal transmission / reception unit provided on the first main surface side of the interposer substrate, and an interposer substrate provided on the first main surface side of the interposer substrate.
  • An interposer substrate having an interposer substrate second non-contact signal transmission / reception unit electrically connected to the first non-contact signal transmission / reception unit, wherein the first element is the first element first main surface Is arranged on the base substrate so as to face the base substrate terminal surface, and the first element signal transmission / reception terminal and one of the plurality of base substrate terminals can be in contact with each other to transmit / receive signals.
  • the second element is disposed on the base substrate such that the first main surface of the second element faces the terminal surface of the base substrate, and the second element signal transmitting / receiving terminal And one of the plurality of base substrate terminals can contact and transmit / receive signals, and the interposer substrate has the first main surface of the first element and the second main surface of the interposer substrate.
  • the interposer substrate Arranged across the first element and the second element so as to face the element second main surface, the interposer substrate first non-contact signal transmitting and receiving unit via the first element substrate, the Signals can be transmitted and received in a non-contact manner with the first element non-contact signal transmitting / receiving unit, and the second non-contact signal transmitting / receiving unit transmits and receives the second element non-contact signal via the second element substrate.
  • the present invention relates to a semiconductor device capable of transmitting and receiving signals in a non-contact manner.
  • the first element second main surface is a first element second main surface terminal facing region that is an opposite surface of the first element first main surface to the region where the first element signal transmission / reception terminal is provided.
  • a first element second main surface non-contact signal transmission / reception unit facing region which is a surface opposite to a region where the first element non-contact signal transmission / reception unit is provided on the first element first main surface
  • the second element second main surface is a second element second main surface terminal facing region that is a surface opposite to the region where the second element signal transmission / reception terminal is provided on the second element first main surface;
  • a second element second main surface non-contact signal transmission / reception unit facing region which is a surface opposite to a region where the second element non-contact signal transmission / reception unit is provided in the second element first main surface
  • the first main surface of the interposer substrate of the interposer substrate is the first element.
  • a second main surface non-contact signal transmitting / receiving unit facing region and the second element second main surface non-contact signal transmitting / receiving unit facing region, a part of the first element second main surface terminal facing region and the second element second You may also oppose at least one of a part of 2 main surface terminal opposing area
  • first element substrate, the second element substrate, and the interposer substrate are formed of a semiconductor material, and the first main surface of the interposer substrate of the interposer substrate is exposed with the semiconductor material exposed.
  • the exposed portion may be in contact with at least one of a part of the first element second main surface terminal opposing region and a part of the second element second main surface terminal opposing region.
  • the first element non-contact signal transmitting / receiving unit, the second element non-contact signal transmitting / receiving unit, the interposer substrate first non-contact signal transmitting / receiving unit, and the interposer substrate second non-contact signal transmitting / receiving unit are formed by wiring. It may be a coil.
  • a semiconductor device including an interposer substrate having a non-contact signal transmission / reception unit, having a configuration that can be easily reduced in size and that can be easily manufactured. it can.
  • FIGS. 1A to 1B are views for explaining a semiconductor device 1 according to a first embodiment of the present invention, in which FIG. 1A is a plan view and FIG. 1B is a cross-sectional view along AA.
  • A is a figure for demonstrating the 1st element 20, the 2nd element 30, and the interposer substrate 40
  • (A) is the top view which looked at the 1st element 20 from the 1st element 1st main surface 22
  • (B) is a plan view of the second element 30 as viewed from the second element first main surface 32
  • (C) is a plan view of the interposer substrate 40 as viewed from the first main surface of the interposer substrate.
  • FIG. 7A to 7B are views for explaining a semiconductor device 1A according to a second embodiment of the present invention
  • FIG. 5A is a cross-sectional view of the semiconductor device 1A according to the second embodiment
  • FIG. FIG. 3 is a plan view of the interposer substrate 40 as viewed from the first main surface of the interposer substrate.
  • (A) to (C) are diagrams for explaining variations of the arrangement of the interposer substrate, (A) is a diagram showing a case where the interposer substrate is applied to three elements, and (B) is The figure which shows the case where an interposer board
  • FIG. 1A and 1B are diagrams for explaining a semiconductor device 1 according to a first embodiment of the present invention, in which FIG. 1A is a plan view and FIG. 1B is a cross-sectional view along AA.
  • FIG. 2 is a diagram for explaining the first element 20, the second element 30, and the interposer substrate 40, and FIG. 2A shows the first element 20 viewed from the first element first main surface 22.
  • 2B is a plan view of the second element 30 as viewed from the second element first main surface 32
  • FIG. 2C is a plan view of the interposer substrate 40 from the first main surface 41 of the interposer substrate.
  • FIG. 1A is a plan view
  • FIG. 1B is a cross-sectional view along AA.
  • FIG. 2 is a diagram for explaining the first element 20, the second element 30, and the interposer substrate 40
  • FIG. 2A shows the first element 20 viewed from the first element first main surface 22.
  • 2B is a plan view of the second element 30 as viewed
  • non-contact transmission / reception of signals means that one transmission / reception unit that transmits / receives signals and the other transmission / reception unit that transmits / receives signals are not in contact with each other and are conductive members (solder, It means that signals are transmitted and received without going through any one or more of a conductive adhesive, a wire and the like.
  • contacting to transmit / receive a signal means that one transmitting / receiving unit that transmits / receives a signal and the other transmitting / receiving unit that transmits / receives a signal contact each other to transmit / receive a signal, or a conductive member ( It means that signals are transmitted / received via any one or more of solder, conductive adhesive, wire and the like.
  • the semiconductor device 1 includes a base substrate 10, a first element 20, a second element 30, and an interposer substrate 40.
  • the base substrate 10 includes a base substrate internal terminal surface 11 as a base substrate terminal surface, a base substrate external terminal surface 12, a plurality of base substrate internal terminals 13 as a plurality of base substrate terminals, and a plurality of base substrate external terminals 14. And having.
  • the base substrate 10 is a printed wiring board.
  • the base substrate internal terminal surface 11 is an upper main surface of the base substrate 10.
  • the base substrate external terminal surface 12 is a surface opposite to the base substrate internal terminal surface 11 and is a main surface on the lower side of the base substrate 10.
  • the plurality of base substrate internal terminals 13 are provided on the base substrate internal terminal surface 11.
  • the plurality of base substrate internal terminals 13 include a plurality of first element side base substrate internal terminals 13A that are electrically connected to a first element signal transmission / reception terminal 24 (described later) of the first element 20 and a second element 30 A plurality of second element side base substrate internal terminals 13B that are electrically connected to a two element signal transmitting / receiving terminal 34 (described later).
  • the plurality of base substrate external terminals 14 are provided on the base substrate external terminal surface 12.
  • the plurality of base substrate internal terminals 13 and the plurality of base substrate external terminals 14 are electrically connected via internal wiring (not shown) and via holes (not shown) provided inside the base substrate 10.
  • Each base board external terminal 14 is electrically connected to a terminal of a circuit board (not shown) provided inside an electric device or the like.
  • the semiconductor device 1 exhibits a predetermined function in an electronic device or the like by being electrically connected to a terminal of a circuit board (not shown) provided inside the electrical device or the like.
  • the first element 20 includes a first element substrate 21, 35 (a plurality of) first element signal transmission / reception terminals 24, and a plurality of first element non-contact signal transmission / reception units. 7 (a plurality) of first element non-contact signal transmitting / receiving coils 25. Seven (a plurality of) first element non-contact signal transmitting / receiving coils 25 are arranged in a line.
  • the first element 20 is an element including one or more first element signal processing circuits (not shown) that perform predetermined signal processing.
  • the first element 20 can be a CPU, a memory, or the like.
  • the first element substrate 21 is a substrate formed of silicon.
  • the first element substrate 21 has a first element first main surface 22 and a first element second main surface 23.
  • the first element first main surface 22 is a lower main surface of the first element substrate 21.
  • the first element second main surface 23 is a surface opposite to the first element first main surface 22 and is an upper main surface of the first element substrate 21.
  • a first element insulating layer 22A including a single layer or a plurality of layers of silicon oxide films is provided on the first element first main surface 22 side of the first element substrate 21, a first element insulating layer 22A including a single layer or a plurality of layers of silicon oxide films is provided. Therefore, the first element first main surface 22 is a surface formed of a silicon oxide film.
  • the first element second main surface 23 is a surface from which silicon is exposed, and no terminals or coils are provided.
  • each first element signal transmitting / receiving terminal 24 is provided on the first element insulating layer 22A.
  • Each first element signal transmission / reception terminal 24 is electrically connected to a first element signal processing circuit (not shown) via an internal wiring (not shown) or a via hole (not shown) provided in the first element insulating layer 22A.
  • the first element insulating layer 22A is represented by being provided with diagonal lines.
  • a first element insulating layer 22A is provided on the entire surface of the first element substrate 21 on the first element first main surface 22 side.
  • each first element non-contact signal transmitting / receiving coil 25 is provided on the first element insulating layer 22A.
  • Each first element non-contact signal transmission / reception coil 25 includes a first element non-contact signal transmission / reception coil wiring part 25A, a first element non-contact signal transmission / reception coil body part 25B, and a first element non-contact signal transmission / reception coil via hole 25C.
  • the first element non-contact signal transmitting / receiving coil main body 25B is a coil configured by wiring.
  • a first element non-contact signal transmitting / receiving coil main body 25B is connected to one end of the first element non-contact signal transmitting / receiving coil main body 25B, and the other end of the first element non-contact signal transmitting / receiving coil main body 25B is The first element non-contact signal transmitting / receiving coil via hole 25C is connected.
  • the first element non-contact signal transmitting / receiving coil via hole 25C is a first element signal processing circuit (not shown) via an internal wiring (not shown) or a via hole (not shown) provided in the first element insulating layer 22A. And are electrically connected.
  • the first element non-contact signal transmitting / receiving coil main body 25B is provided inside the first element non-contact signal transmitting / receiving coil wiring part 25A, the first element non-contact signal transmitting / receiving coil via hole 25C, and the first element insulating layer 22A. It is electrically connected to a first element signal processing circuit (not shown) via wiring (not shown).
  • the surface of the first element second main surface 23 opposite to the region where the first element signal transmission / reception terminal 24 is provided on the first element first main surface 22 is defined as the first element second main surface 23. This is referred to as a terminal facing region 23A. Further, in the first element second main surface 23, the surface opposite to the area where the first element non-contact signal transmitting / receiving coil main body 25 ⁇ / b> B is provided in the first element first main surface 22 is the first element second main surface 23. This is referred to as a surface non-contact signal transmitting / receiving unit facing region 23B.
  • the second element 30 includes a second element substrate 31, 35 (a plurality) second element signal transmission / reception terminals 34, and a plurality of second element non-contact signal transmission / reception units. 7 (a plurality of) second element non-contact signal transmitting / receiving coils 35. Seven (plural) second element non-contact signal transmitting / receiving coils 35 are arranged in a line.
  • the second element 30 is an element including one or more second element signal processing circuits (not shown) that perform predetermined signal processing.
  • the second element 30 can be a CPU, a memory, or the like.
  • the second element 30 may be an element having the same function as the first element 20 or an element having a different function.
  • the second element substrate 31 is a substrate formed of silicon.
  • the second element substrate 31 has a second element first main surface 32 and a second element second main surface 33.
  • the second element first main surface 32 is a lower main surface of the second element substrate 31.
  • the second element second main surface 33 is a surface opposite to the second element first main surface 32 and is an upper main surface of the second element substrate 31.
  • a second element insulating layer 32A including a single layer or a plurality of layers of silicon oxide films is provided on the second element first main surface 32 side of the second element substrate 31. Therefore, the second element first main surface 32 is a surface formed of a silicon oxide film.
  • the second element second main surface 33 is a surface from which silicon is exposed, and no terminals or coils are provided.
  • the plurality of second element signal transmitting / receiving terminals 34 are provided on the second element insulating layer 32A.
  • the plurality of second element signal transmission / reception terminals 34 are electrically connected to a second element signal processing circuit (not shown) via an internal wiring (not shown) or a via hole (not shown) provided in the second element insulating layer 32A.
  • the second element insulating layer 32A is expressed by being provided with diagonal lines.
  • the second element insulating layer 32 ⁇ / b> A is provided on the entire surface of the second element substrate 31 on the second element first main surface 32 side.
  • each second element non-contact signal transmitting / receiving coil 35 is provided on the second element insulating layer 32A.
  • Each second element non-contact signal transmission / reception coil 35 includes a second element non-contact signal transmission / reception coil wiring part 35A, a second element non-contact signal transmission / reception coil body part 35B, and a second element non-contact signal transmission / reception coil via hole 35C.
  • the second element non-contact signal transmitting / receiving coil main body 35B is a coil constituted by wiring.
  • a second element non-contact signal transmission / reception coil main body 35B is connected to one end of the second element non-contact signal transmission / reception coil wiring section 35A, and the other end of the second element non-contact signal transmission / reception coil main body 35B is The second element non-contact signal transmitting / receiving coil via hole 35C is connected.
  • the second element non-contact signal transmitting / receiving coil via hole 35 ⁇ / b> C is a second element signal processing circuit (not shown) via an internal wiring (not shown) or a via hole (not shown) provided in the second element insulating layer 32 ⁇ / b> A. And are electrically connected.
  • the second element non-contact signal transmitting / receiving coil main body 35B is provided inside the second element non-contact signal transmitting / receiving coil wiring part 35A, the second element non-contact signal transmitting / receiving coil via hole 35C, and the second element insulating layer 32A. It is electrically connected to a second element signal processing circuit (not shown) via wiring (not shown).
  • the surface of the second element second main surface 33 opposite to the region where the second element signal transmission / reception terminal 34 is provided in the second element first main surface 32 is defined as the second element second main surface. This is referred to as a terminal facing region 33A.
  • the second element second main surface 33 has a surface opposite to the second element first main surface 32 opposite to the region where the second element non-contact signal transmitting / receiving coil main body 35B is provided. This is referred to as a surface non-contact signal transmitting / receiving unit facing region 33B.
  • the interposer substrate 40 includes an interposer substrate first main surface 41, an interposer substrate second main surface 42, and a plurality of interposer substrate first non-contact signal transmission / reception units.
  • the interposer substrate 40 is a substrate formed of silicon.
  • the interposer substrate first main surface 41 is a lower main surface of the interposer substrate 40.
  • the interposer substrate second main surface 42 is a surface opposite to the interposer substrate first main surface 41 and is an upper main surface of the interposer substrate 40.
  • an interposer substrate insulating layer 41A including a single layer or a plurality of layers of silicon oxide films is provided on the interposer substrate first main surface 41 side of the interposer substrate 40. Therefore, the interposer substrate first main surface 41 is a surface formed of a silicon oxide film.
  • the second main surface 42 of the interposer substrate is a surface from which silicon is exposed, and no terminals or coils are provided.
  • each interposer substrate first non-contact signal transmitting / receiving coil 43 and each interposer substrate second non-contact signal transmitting / receiving coil 44 are interposer substrate insulated. It is provided on the layer 41A.
  • the interposer substrate insulating layer 41A is represented by being provided with diagonal lines.
  • an interposer substrate insulating layer 41 ⁇ / b> A is provided on the entire surface of the interposer substrate 40 on the first main surface 41 side of the interposer substrate 40.
  • each interposer substrate first non-contact signal transmission / reception coil 43 and each interposer substrate second non-contact signal transmission / reception coil 44 are coils constituted by wiring.
  • the interposer substrate first non-contact signal transmitting / receiving coil 43 and the interposer substrate second non-contact signal transmitting / receiving coil 44 are electrically connected by an interposer substrate wiring 45. That is, the interposer substrate first non-contact signal transmitting / receiving coil 43 is connected to one end of the interposer substrate wiring 45, and the interposer substrate second non-contact signal transmitting / receiving coil is connected to the other end of the interposer substrate wiring 45. 44 is connected.
  • the interposer substrate wiring 45 is provided on the interposer substrate insulating layer 41A.
  • the first element 20 is disposed on the base substrate 10.
  • the first element first main surface 22 faces the base substrate internal terminal surface 11.
  • Each first element signal transmitting / receiving terminal 24 is electrically connected to each first element side base substrate internal terminal 13A via a first element conductive member 24A.
  • the first element conductive member 24A is a conductive member such as solder or a conductive adhesive. Therefore, it can be said that the first element signal transmission / reception terminal 24 and the first element side base substrate internal terminal 13A are in contact with each other and can transmit and receive signals.
  • the first element 20 is fixed on the base substrate 10 by the first element conductive member 24A.
  • the first element 20 is face-down connected to the base substrate 10.
  • Each first element non-contact signal transmitting / receiving coil main body 25B is not electrically connected to the plurality of first element side base substrate internal terminals 13A via the conductive member.
  • the second element 30 is disposed on the base substrate 10.
  • the second element first main surface 32 faces the base substrate internal terminal surface 11.
  • Each second element signal transmission / reception terminal 34 is electrically connected to each second element side base substrate internal terminal 13B via a second element conductive member 34A.
  • the second element conductive member 34A is a conductive member such as solder or a conductive adhesive. Therefore, it can be said that the second element signal transmission / reception terminal 34 and the second element side base substrate internal terminal 13B are in contact with each other and can transmit and receive signals.
  • the second element 30 is fixed on the base substrate 10 by the second element conductive member 34A.
  • the second element 30 is face-down connected to the base substrate 10.
  • Each of the second element non-contact signal transmitting / receiving coil main body portions 35B is not electrically connected to the plurality of second element side base substrate internal terminals 13B via the conductive member.
  • the interposer substrate 40 is disposed across the first element 20 and the second element 30.
  • the interposer substrate first main surface 41 faces the first element second main surface 23 and the second element second main surface 33. More specifically, the interposer substrate first main surface 41 is opposed to the first element second main surface non-contact signal transmitting / receiving unit facing region 23B and the second element second main surface non-contact signal transmitting / receiving unit facing region 33B.
  • the first element second main surface terminal facing area 23A and the second element second main surface terminal facing area 33A are also opposed to each other.
  • the interposer substrate first main surface 41 is in contact with the first element second main surface 23 and the second element second main surface 33.
  • the interposer substrate 40 is fixed to the first element 20 and the second element 30 with an adhesive.
  • the interposer substrate 40 covers the first element second main surface non-contact signal transmitting / receiving portion facing area 23B and also covers a part of the first element second main surface terminal facing area 23A. Similarly, the interposer substrate 40 covers the second element second main surface non-contact signal transmitting / receiving portion facing area 33B and also covers a part of the second element second main surface terminal facing area 33A.
  • Each interposer substrate first non-contact signal transmission / reception coil 43 faces each first element non-contact signal transmission / reception coil main body 25B. Therefore, the interposer substrate first non-contact signal transmission / reception coil 43 and the first element non-contact signal transmission / reception coil main body 25 ⁇ / b> B can transmit and receive signals in a non-contact manner via the first element substrate 21. More specifically, the interposer substrate first non-contact signal transmission / reception coil 43 and the first element non-contact signal transmission / reception coil main body 25B are non-contacted via the first element substrate 21 by inductive coupling generated between the two coils. Contact signal can be transmitted and received.
  • the first element substrate 21 is thinned so that signals can be transmitted and received in a non-contact manner between the first non-contact signal transmitting / receiving coil 43 and the first element non-contact signal transmitting / receiving coil body 25B. ing.
  • the thickness of the first element substrate 21 is 5 ⁇ m to 25 ⁇ m.
  • Each interposer substrate second non-contact signal transmission / reception coil 44 faces each second element non-contact signal transmission / reception coil main body 35B. Therefore, the interposer substrate second non-contact signal transmission / reception coil 44 and the second element non-contact signal transmission / reception coil body 35 ⁇ / b> B can transmit and receive signals in a non-contact manner via the second element substrate 31. More specifically, the interposer substrate second non-contact signal transmission / reception coil 44 and the second element non-contact signal transmission / reception coil main body 35B are non-contacted via the second element substrate 31 by inductive coupling generated between the two coils. Contact signal can be transmitted and received.
  • the second element substrate 31 is thinned so that signals can be transmitted and received in a non-contact manner between the interposer substrate second non-contact signal transmitting / receiving coil 44 and the second element non-contact signal transmitting / receiving coil body 35B. ing.
  • the thickness of the second element substrate 31 is 5 ⁇ m to 25 ⁇ m.
  • the interposer substrate first non-contact signal transmitting / receiving coil 43 and the interposer substrate second non-contact signal transmitting / receiving coil 44 are electrically connected by the interposer substrate wiring 45. Therefore, the first element 20 and the second element 30 can transmit and receive signals via the interposer substrate 40.
  • a signal output from a first element signal processing circuit is transmitted as a first element transmission signal S1 from the first element non-contact signal transmitting / receiving coil main body 25B.
  • the first element transmission signal S ⁇ b> 1 is received by the interposer substrate first non-contact signal transmission / reception coil 43 and transmitted from the interposer substrate second non-contact signal transmission / reception coil 44 via the interposer substrate wiring 45.
  • the first element transmission signal S1 transmitted from the interposer substrate second non-contact signal transmission / reception coil 44 is received by the second element non-contact signal transmission / reception coil body 35B of the second element 30.
  • the second element transmission signal S2 transmitted from the second element non-contact signal transmission / reception coil main body part 35B includes the interposer substrate second non-contact signal transmission / reception coil 44, the interposer substrate wiring 45, and the interposer substrate first non-contact.
  • the signal is received by the first element non-contact signal transmitting / receiving coil main body 25 ⁇ / b> B of the first element 20 via the contact signal transmitting / receiving coil 43.
  • a base substrate 10 having a base substrate internal terminal surface 11 provided with a plurality of base substrate internal terminals 13, a first element first main surface 22, and a first surface opposite to the first element first main surface 22.
  • a first element substrate 21 having an element second main surface 23, the first element signal transmitting / receiving terminal 24 provided on the first element first main surface 22 side, and the first element first main surface 22 side.
  • the first element 20 having the first element non-contact signal transmitting / receiving coil 25 provided, the second element first main surface 32, and the second element first surface which is the surface opposite to the second element first main surface 32.
  • the second element substrate 31 having the two main surfaces 33, the second element signal transmitting / receiving terminal 34 provided on the second element first main surface 32 side, and the second element first main surface 32 side.
  • a second element 30 having a second element non-contact signal transmitting / receiving coil 35, and an interposer substrate first
  • An interposer substrate 40 having a contact signal transmitting / receiving coil 43 and an interposer substrate first main surface 41, an interposer substrate first non-contact signal transmitting / receiving coil 43 provided on the interposer substrate first main surface 41 side,
  • the interposer substrate having the interposer substrate second non-contact signal transmitting / receiving coil 44 provided on the first main surface 41 side of the interposer substrate and electrically connected to the first non-contact signal transmitting / receiving coil 43 of the interposer substrate.
  • the first element 20 is arranged on the base substrate 10 such that the first element first main surface 22 faces the base substrate internal terminal surface 11, and the first element signal transmission / reception terminal 24 and the plurality of base substrates are arranged. Signals can be transmitted and received in contact with one of the internal terminals 13, and the second element 30 is formed on the base substrate 10 so that the second element first main surface 32 faces the base substrate internal terminal surface 11.
  • the second element signal transmission / reception terminal 34 and one of the plurality of base substrate internal terminals 13 are in contact with each other and can transmit and receive signals, and the interposer substrate 40 has an interposer substrate first main surface 41.
  • the coil 43 is Signals can be transmitted and received in a non-contact manner with the first element non-contact signal transmitting / receiving coil 25 via the first element substrate 21, and the interposer substrate second non-contact signal transmitting / receiving coil 44 is interposed via the second element substrate 31.
  • signals can be transmitted and received without contact with the second element non-contact signal transmitting / receiving coil 35.
  • the shape of the interposer substrate 40 is not restricted by the shapes of the first element second main surface non-contact signal transmitting / receiving unit facing region 23B and the second element second main surface non-contact signal transmitting / receiving unit facing region 33B. Therefore, in the semiconductor device 1 of the first embodiment, the region where the first element non-contact signal transmission / reception coil 25 and the region where the second element non-contact signal transmission / reception coil 35 are provided on the first element substrate 21 can be reduced in size. Therefore, the semiconductor device 1 of the first embodiment has a configuration that can be reduced in size.
  • the interposer substrate 40 when the semiconductor device 1 is manufactured, the interposer substrate 40 can be disposed last. Further, in the semiconductor device 1, an increase in the aspect ratio of the interposer substrate 40 is suppressed. For example, when the interposer substrate 40 is disposed only in the first element second main surface non-contact signal transmitting / receiving unit facing region 23B and the second element second main surface non-contact signal transmitting / receiving unit facing region 33B, the interposer substrate 40 is disposed. May be a substrate having a large aspect ratio (for example, 10 or more).
  • the interposer substrate 40 includes not only the first element second main surface non-contact signal transmitting / receiving unit facing region 23B and the second element second main surface non-contact signal transmitting / receiving unit facing region 33B, but also the first element second main surface. Since the terminal facing region 23A and the second element second main surface terminal facing region 33A are also disposed, an increase in the aspect ratio of the interposer substrate 40 is suppressed. Further, the interposer substrate 40 is formed with only coils and wirings, and no active elements that need to be supplied with a power supply voltage are disposed. Therefore, the interposer substrate 40 does not need to be supplied with a power supply voltage, and does not require wiring or terminals for supplying the power supply voltage. Therefore, the semiconductor device 1 has a configuration that can be easily manufactured.
  • the first element 20 and the second element 30 can transmit and receive signals in a non-contact manner via the interposer substrate 40. For this reason, impedance matching is not required for connection between the first element 20 and the second element 30 (or the accuracy of impedance matching is relaxed compared to a semiconductor device that contacts and transmits and receives signals). .
  • first element second main surface 23 of the first element substrate 21 is not covered with the interposer substrate 40. Therefore, the heat generated in the first element 20 is radiated from the first element second main surface 23.
  • a part of the second element second main surface 33 of the second element substrate 31 is not covered with the interposer substrate 40. Therefore, the heat generated in the second element 30 is radiated from the second element second main surface 33.
  • the first element second main surface 23 is a first element second main surface terminal facing region that is the opposite surface of the first element first main surface 22 to the region where the first element signal transmission / reception terminal 24 is provided. 23A, and the first element second main surface non-contact signal transmitting / receiving unit facing region 23B, which is the opposite surface of the first element first main surface 22 to the region where the first element non-contact signal transmitting / receiving coil 25 is provided.
  • the second element second main surface 33 has a second element second main surface terminal facing region which is the opposite surface of the second element first main surface 32 to the region where the second element signal transmitting / receiving terminal 34 is provided.
  • a second element second main surface non-contact signal transmitting / receiving unit facing region 33B which is the opposite surface of the second element first main surface 32 to the region where the second element non-contact signal transmitting / receiving coil 35 is provided, Interposer of interposer substrate 40
  • the plate first main surface 41 faces the first element second main surface non-contact signal transmitting / receiving unit facing region 23B and the second element second main surface non-contact signal transmitting / receiving unit facing region 33B, and the first element second main surface It also faces at least one of a part of the terminal facing region 23A and a part of the second element second main surface terminal facing region 33A.
  • the semiconductor device 1 of the first embodiment has a configuration that can be further reduced in size and can be manufactured more easily.
  • FIG. 3 is a diagram for explaining a semiconductor device 1A according to the second embodiment of the present invention.
  • FIG. 3A is a cross-sectional view of the semiconductor device 1A according to the second embodiment, and FIG. It is the top view which looked at the interposer board
  • the second embodiment will be described mainly with respect to differences from the first embodiment, and detailed description of the same configuration as the first embodiment will be omitted. For the points that are not particularly described, the description of the first embodiment is applied as appropriate.
  • the semiconductor device 1 ⁇ / b> A includes a base substrate 10, a first element 20, a second element 30, and an interposer substrate 40 made of silicon as a main component. I have.
  • the configuration of the interposer substrate 40 is different from the configuration of the interposer substrate 40 in the semiconductor device 1 of the first embodiment.
  • the interposer substrate first main surface 41 of the interposer substrate 40 in the semiconductor device 1A of the second embodiment is the same as that of the semiconductor device 1 of the first embodiment.
  • the interposer substrate insulating layer 41A including a single layer or a plurality of layers of silicon oxide film is provided only near the center of the interposer substrate 40 on the first main surface 41 side of the interposer substrate. .
  • a portion where the interposer substrate insulating layer 41A is not provided on the side of the first main surface 41 of the interposer substrate is a portion where silicon is exposed.
  • the portion on the first element 20 side is the first element side exposed portion 41B
  • the portion on the second element 30 side is the second element side exposed portion 41C.
  • the interposer substrate insulating layer 41A is expressed by being provided with diagonal lines.
  • the interposer substrate first main surface 41 of the interposer substrate 40 in the semiconductor device 1A of the second embodiment includes a surface formed of a silicon oxide film and a surface from which silicon is exposed.
  • the first element side exposed portion 41B is in contact with the first element second main surface terminal facing region 23A, and the second element side exposed portion 41C is in contact with the second element second main surface terminal facing region 33A. Yes.
  • the thermal conductivity of silicon (about 160 W / m ⁇ K) is larger than that of the silicon oxide film (about 1.3 W / m ⁇ K). Therefore, the first element side exposed portion 41 ⁇ / b> B in the interposer substrate 40 functions as a heat radiating part that radiates heat generated in the first element 20 by contacting the first element second main surface 23. Similarly, the second element-side exposed portion 41 ⁇ / b> C in the interposer substrate 40 functions as a heat radiating part that radiates heat generated in the second element 30 by contacting the second element second main surface 33.
  • the semiconductor device 1A of the second embodiment having the above configuration, the following effects are exhibited.
  • the first element substrate 21, the second element substrate 31, and the interposer substrate 40 are made of silicon, and the interposer substrate first main surface 41 of the interposer substrate 40 is The exposed portion has exposed silicon, and the exposed portion is in contact with a part of the first element second main surface terminal opposing region 23A and a part of the second element second main surface terminal opposing region 33A. Therefore, even if the interposer substrate 40 becomes large, the first element-side exposed portion 41B and the second element-side exposed portion 41C exist, so that the heat of the first element 20 and the heat of the second element 30 are dissipated.
  • the shape of the interposer substrate 40 is not limited by the shapes of the first element second main surface non-contact signal transmitting / receiving unit facing region 23B and the second element second main surface non-contact signal transmitting / receiving unit facing region 33B.
  • it is difficult to be restricted by heat generated in the first element 20 and the second element 30.
  • FIG. 4A and 4B are diagrams for explaining variations of the arrangement of the interposer substrate.
  • FIG. 4A shows a case where the interposer substrate is applied to three elements
  • FIG. 4C is a diagram showing a case where an interposer substrate is applied to one element
  • FIG. 4C is a diagram showing a case where an interposer substrate is applied to five elements.
  • the third embodiment will be described mainly focusing on differences from the first embodiment, and detailed description of the same configuration as the first embodiment will be omitted. For the points that are not particularly described, the description of the first embodiment is applied as appropriate.
  • the interposer substrate 40 can be disposed so as to straddle the first element 20, the second element 30, and the third element 50.
  • the first element 20, the second element 30, and the third element 50 can transmit and receive signals to and from each other via the interposer substrate 40.
  • the lower left element is the first element 20, the lower right element is the second element 30, and the upper element is the third element 50.
  • the first element 20, the second element 30, and the third element 50 can be interchanged.
  • the upper element may be the first element 20 (or the second element 30)
  • the lower left element (or the lower right element) may be the second element 30 (or the first element 20).
  • the size of the first element 20 and the size of the second element 30 may be different.
  • the interposer substrate 40 may be disposed so as to straddle the first element 20, the second element 30, the third element 50, and the fourth element 60.
  • the first element 20, the second element 30, the third element 50 and the fourth element 60 can transmit and receive signals to and from each other via the interposer substrate 40.
  • the first element 20 may be an upper left element, a lower left element, an upper right element, or a lower right element.
  • the upper left element may be the first element 20 (or the second element 30)
  • the lower right element may be the second element 30 (or the first element 20).
  • the first element 20 and the second element 30 may be arranged so as not to have opposing sides.
  • the interposer substrate 40 may be disposed so as to straddle the first element 20, the second element 30, the third element 50, the fourth element 60, and the fifth element 70. Is possible.
  • the first element 20, the second element 30, the third element 50, the fourth element 60, and the fifth element 70 can transmit and receive signals to and from each other via the interposer substrate 40.
  • the first element 20 may be any of an upper left element, an upper right element, a lower left element, a lower center element, and a lower right element.
  • the second element 30 may be any of an upper left element, an upper right element, a lower left element, a lower center element, and a lower right element.
  • the left element may be the first element 20 (or the second element 30)
  • the lower right element may be the second element 30 (or the first element 20).
  • the first element 20 and the second element 30 may be arranged such that they do not have opposing sides and there are other elements in between.
  • the contactless signal transmission / reception uses inductive coupling between the coils, but the present invention is not limited to this.
  • Non-contact signal transmission / reception may be non-contact signal transmission / reception using magnetic resonance between coils, or non-contact signal transmission / reception using optical signals or sound wave signals. Good.
  • the interposer substrate 40 is made of silicon, but is not limited to this.
  • the interposer substrate 40 may be formed of a semiconductor material other than silicon.
  • a semiconductor material means a material having a property as a semiconductor and a material that can have a property as a semiconductor by being doped with impurities.
  • the interposer substrate 40 may be a substrate other than a substrate formed of a semiconductor material, for example, a substrate formed of glass or a resin material. Further, the interposer substrate 40 may be a printed wiring board.
  • the base substrate 10 is a printed wiring board, but is not limited to this.
  • the base substrate 10 may be a substrate formed of a semiconductor material such as silicon. Further, the base substrate 10 itself may be a semiconductor element having a signal processing function.
  • the interposer substrate 40 is fixed to the first element 20 and the second element 30 with an adhesive, but is not limited thereto.
  • the interposer substrate 40 may be fixed to the first element 20 and the second element 30 using an adhesive or a fixing member other than the adhesive.
  • the interposer substrate 40 may be fixed to the first element 20 and the second element 30 by a direct bonding technique such as room temperature bonding.
  • the interposer substrate first main surface 41 is in contact with a part of the first element second main surface 23 and a part of the second element second main surface 33.
  • the interposer substrate first main surface 41 only needs to face the first element second main surface 23 and the second element second main surface 33.
  • the interposer substrate 40 may be disposed at a distance from the first element second main surface 23 and the second element second main surface 33 by a spacer or the like.
  • the interposer substrate first main surface 41 includes a part of the first element second main surface terminal facing region 23A and the second element second main surface terminal facing region 33A. Although it faced a part, it is not limited to this.
  • the interposer substrate first main surface 41 only needs to face at least one of a part of the first element second main surface terminal facing region 23A and a part of the second element second main surface terminal facing region 33A.
  • the exposed portion of the first main surface 41 of the interposer substrate is part of the first element second main surface terminal facing area 23A and part of the second element second main surface terminal facing area 33A.
  • the exposed portion of the first main surface 41 of the interposer substrate may be in contact with at least one of a part of the first element second main surface terminal facing region 23A and a part of the second element second main surface terminal facing region 33A. That's fine.
  • the interposer substrate first main surface 41 only one of the first element side exposed portion 41B and the second element side exposed portion 41C may be present.
  • the interposer substrate first main surface 41 includes the most heat generating region and the second element second main surface terminal facing region in the first element second main surface terminal facing region 23A. You may arrange
  • the first element non-contact signal transmitting / receiving coil 25 is provided on the first element insulating layer 22A.
  • the first element non-contact signal transmitting / receiving coil 25 may be provided inside the first element insulating layer 22A.
  • the first element non-contact signal transmitting / receiving coil 25 may be exposed on the first element insulating layer 22A or may not be exposed.
  • the 1st element non-contact signal transmission / reception coil 25 should just be provided in the 1st element 1st main surface 22 side.
  • the first element first main surface 22 side is a portion closer to the first element first main surface 22 than the first element second main surface 23 in the thickness direction of the first element substrate 21 (first element first 1 including the surface of the main surface 22).
  • the second element non-contact signal transmitting / receiving coil 35 is provided on the second element insulating layer 32A, but is not limited thereto.
  • the second element non-contact signal transmitting / receiving coil 35 may be provided inside the second element insulating layer 32A. That is, the second element non-contact signal transmitting / receiving coil 35 may be exposed on the second element insulating layer 32A or may not be exposed.
  • the 2nd element non-contact signal transmission / reception coil 35 should just be provided in the 2nd element 1st main surface 32 side.
  • the second element first main surface 32 side is a portion closer to the second element first main surface 32 than the second element second main surface 33 in the thickness direction of the second element substrate 31 (second element first 1 including the surface of the main surface 32).
  • the interposer substrate first non-contact signal transmission / reception coil 43, the interposer substrate second non-contact signal transmission / reception coil 44, and the interposer substrate wiring 45 are provided on the interposer substrate insulating layer 41A, but are not limited thereto. .
  • the interposer substrate first non-contact signal transmitting / receiving coil 43, the interposer substrate second non-contact signal transmitting / receiving coil 44, and the interposer substrate wiring 45 are composed of the interposer substrate first non-contact signal transmitting / receiving coil 43, the interposer substrate second non-contact.
  • the signal transmitting / receiving coil 44 and the interposer substrate wiring 45 may be provided inside.
  • the interposer substrate first non-contact signal transmitting / receiving coil 43, the interposer substrate second non-contact signal transmitting / receiving coil 44, and the interposer substrate wiring 45 may be exposed on the interposer substrate insulating layer 41A. It may not be exposed. Moreover, the interposer board
  • the interposer substrate first main surface 41 side means a portion closer to the interposer substrate first main surface 41 than the interposer substrate second main surface 42 in the thickness direction of the interposer substrate 40 (interposer substrate first Including the surface of the main surface 41).
  • the number of first element signal transmission / reception terminals 24 in the first element 20 is 35
  • the number of second element signal transmission / reception terminals 34 in the second element 30 is 35.
  • the number of first element signal transmission / reception terminals 24 and the number of second element signal transmission / reception terminals 34 may be any number.
  • the number of the 1st element non-contact signal transmission / reception coils 25 in the 1st element 20 was 7, and the number of the 2nd element non-contact signal transmission / reception coils 35 in the 2nd element 30 was 7, it is not limited to this. .
  • first element non-contact signal transmitting / receiving coils 25 and second element non-contact signal transmitting / receiving coils 35 may be any number.
  • the first element non-contact signal transmission / reception coil 25 and the second element non-contact signal transmission / reception coil 35 are arranged in one row, but may be arranged in two or more rows. .
  • the first element insulating layer 22A, the second element insulating layer 32A, and the interposer substrate insulating layer 41A are formed of a silicon oxide film. It may be formed of an insulating member.
  • Base substrate 11
  • Base substrate internal terminal surface 12
  • Base board external terminal surface 13
  • Base board internal terminal 13
  • Second element side base substrate internal terminal 14
  • Base substrate external terminal 20
  • 1st element 21 1st element substrate 22
  • 1st element 1st principal surface 22A 1st element insulation layer
  • 23 1st element 2nd principal surface
  • 23A 1st element 2nd principal surface terminal opposing region 23B 1st element 2nd principal surface
  • Non-contact signal transmitter / receiver facing region 24
  • First element signal transmitter / receiver terminal 24A
  • First element conductive member 25
  • First element non-contact signal transmitter / receiver coil 25
  • First element non-contact signal transmission / reception coil body part 25
  • First element non-contact signal transmission / reception coil body part 25C
  • First element non-contact signal transmission / reception coil via hole 30
  • 2nd element 31 2nd element substrate 32
  • 2nd element 1st main surface 32
  • 2nd element insulating layer 33

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Abstract

　ベース基板１０と、第１素子２０と、第２素子３０と、インターポーザー基板４０と、を備え、第１素子２０はベース基板１０上に配置されており、第１素子信号送受信端子２４と複数のベース基板端子１３とは、接触して信号の送受信が可能であり、第２素子３０はベース基板１０上に配置されており、第２素子信号送受信端子３４と複数のベース基板端子１３とは、接触して信号の送受信が可能であり、インターポーザー基板４０は、第１素子２０及び第２素子３０に跨って配置されており、インターポーザー基板第１非接触信号送受信部４３は、第１素子基板を介して、第１素子非接触信号送受信部２５と非接触に信号の送受信が可能であり、インターポーザー基板第２非接触信号送受信部４４は、第２素子基板３１を介して、第２素子非接触信号送受信部３５と非接触に信号の送受信が可能である半導体装置。

Description

半導体装置
　本発明は、非接触信号送受信部を有するインターポーザー基板を備えた半導体装置に関する。
　従来、非接触信号送受信部として機能するインダクタ３０４，３２４が設けられたシリコンインターポーザー６０を備えた半導体装置が知られている（特許文献１の図４参照。）。この特許文献１の半導体装置においては、シリコンインターポーザー６０を介して、２つの素子（半導体チップ１０，半導体チップ２０）が、互いに信号の送受信を行っている。シリコンインターポーザー６０は、２つの素子１０，２０における配線や端子が設けられた面に配置されている。
　また、非接触信号送受信部として機能する結合器９２，９３が設けられた第３モジュール９０を備えた半導体装置が知られている（特許文献２の図２２，図２３）。この特許文献２の半導体装置においては、第３モジュール９０を介して、２つの素子（第１モジュール７０，第２モジュール８０）が、互いに信号の送受信を行っている。第３モジュール９０は、第１モジュール７０にボンディングワイヤ７９を介して電気的に接続されており、第２モジュール８０にボンディングワイヤ８９を介して電気的に接続されている。
特開２０１０－２５１６６３号公報 特開２０１４－３３４３２号公報
　ところで、半導体装置は、小型化が容易な構成であることが望ましい。また、半導体装置は、製造が容易な構成であることが望ましい。
　特許文献１の半導体装置においては、シリコンインターポーザー６０が、２つの素子（半導体チップ１０，半導体チップ２０）における配線や端子が形成された面に配置されている。特許文献１の半導体装置を小型化する手段として、半導体チップ１０の非接触送受信部３０２が形成されている領域と、半導体チップ２０の非接触送受信部３２２が形成されている領域の幅と、を狭くする手段が考えられる。この手段が採用される場合、狭くした領域の幅に合わせて、シリコンインターポーザー６０の幅も狭くする必要がある。
　しかし、シリコンインターポーザー６０の幅が狭くされても、奥行き方向の幅はそのままであるため、シリコンインターポーザー６０のアスペクト比（縦横比）が大きくなる。すなわち、シリコンインターポーザー６０は、極めて細長い形状（例えば、アスペクト比が１０～１００となる形状。）となってしまう。この様な細長い形状のシリコンインターポーザー６０は、歩留まりが悪いものになる可能性が高い。また、細長い形状のシリコンインターポーザー６０は、ハンドリング困難なものになる可能性が高い。そのため、特許文献１の半導体装置は、小型化が可能な構成であるとはいえず、また、製造が容易な構成であるともいえない。
　引用文献２の半導体装置においては、インターポーザー９０（第３モジュール９０）は、非接触信号送受信部９２，９３が設けられるとともに、ボンディングワイヤ７９，８９に対応する端子が設けられる。よって、インターポーザー９０（第３モジュール９０）は、複雑な構造になる傾向がある。また、第１モジュール７０、第２モジュール８０及びインターポーザー９０（第３モジュール９０）を組み立てる際、非接触信号送受信部９２，９３の位置合わせと、ボンディングワイヤ７９，８９に対応する端子の位置合わせとが同時に行われることになる。そのため、第１モジュール７０、第２モジュール８０及びインターポーザー９０（第３モジュール９０）の組み立ては、高精度の位置合わせた要求されることになる。よって、特許文献２の半導体装置は、小型化が容易な構成であるとはいえず、また、製造が容易な構成であるともいえない。
　本発明は、非接触信号送受信部を有するインターポーザー基板を備えた半導体装置であって、小型化が容易な構成であり、製造が容易になり得る構成である半導体装置を提供することを目的とする。
　本発明は、複数のベース基板端子が設けられたベース基板端子面を有するベース基板と、第１素子第１主面と、前記第１素子第１主面と反対の面である第１素子第２主面とを有する第１素子基板と、前記第１素子基板の前記第１素子第１主面側に設けられた第１素子信号送受信端子と、前記第１素子基板の前記第１素子第１主面側に設けられた第１素子非接触信号送受信部と、を有する第１素子と、第２素子第１主面と、前記第２素子第１主面と反対の面である第２素子第２主面とを有する第２素子基板と、前記第２素子基板の前記第２素子第１主面側に設けられた第２素子信号送受信端子と、前記第２素子基板の前記第２素子第１主面側に設けられた第２素子非接触信号送受信部と、を有する第２素子と、インターポーザー基板第１主面を有するインターポーザー基板であって、前記インターポーザー基板第１主面側に設けられたインターポーザー基板第１非接触信号送受信部と、前記インターポーザー基板第１主面側に設けられ、前記インターポーザー基板第１非接触信号送受信部と電気的に接続されたインターポーザー基板第２非接触信号送受信部と、を有するインターポーザー基板と、を備え、前記第１素子は、前記第１素子第１主面が前記ベース基板端子面に対向するように前記ベース基板上に配置されており、前記第１素子信号送受信端子と前記複数のベース基板端子の１つとは、接触して信号の送受信が可能であり、前記第２素子は、前記第２素子第１主面が前記ベース基板端子面に対向するように前記ベース基板上に配置されており、前記第２素子信号送受信端子と前記複数のベース基板端子の１つとは、接触して信号の送受信が可能であり、前記インターポーザー基板は、前記インターポーザー基板第１主面が前記第１素子第２主面及び前記第２素子第２主面に対向するように前記第１素子及び前記第２素子に跨って配置されており、前記インターポーザー基板第１非接触信号送受信部は、前記第１素子基板を介して、前記第１素子非接触信号送受信部と非接触に信号の送受信が可能であり、前記インターポーザー基板第２非接触信号送受信部は、前記第２素子基板を介して、前記第２素子非接触信号送受信部と非接触に信号の送受信が可能である半導体装置に関する。
　また、前記第１素子第２主面は、前記第１素子第１主面における前記第１素子信号送受信端子が設けられている領域の反対面である第１素子第２主面端子対向領域と、前記第１素子第１主面における前記第１素子非接触信号送受信部が設けられている領域の反対面である第１素子第２主面非接触信号送受信部対向領域と、を有し、前記第２素子第２主面は、前記第２素子第１主面における前記第２素子信号送受信端子が設けられている領域の反対の面である第２素子第２主面端子対向領域と、前記第２素子第１主面における前記第２素子非接触信号送受信部が設けられている領域の反対の面である第２素子第２主面非接触信号送受信部対向領域と、を有し、前記インターポーザー基板の前記インターポーザー基板第１主面は、前記第１素子第２主面非接触信号送受信部対向領域及び前記第２素子第２主面非接触信号送受信部対向領域に対向し、前記第１素子第２主面端子対向領域の一部及び前記第２素子第２主面端子対向領域の一部の少なくとも一方にも対向してもよい。
　また、前記第１素子基板、前記第２素子基板及び前記インターポーザー基板は、半導体材料で形成されており、前記インターポーザー基板の前記インターポーザー基板第１主面は、前記半導体材料が露出した露出部分を有し、前記露出部分は、前記第１素子第２主面端子対向領域の一部及び前記第２素子第２主面端子対向領域の一部の少なくとも一方に接触していてもよい。
　また、前記第１素子非接触信号送受信部、前記第２素子非接触信号送受信部、前記インターポーザー基板第１非接触信号送受信部及び前記インターポーザー基板第２非接触信号送受信部は、配線により形成されたコイルであってもよい。
　本発明によれば、非接触信号送受信部を有するインターポーザー基板を備えた半導体装置であって、小型化が容易な構成であり、製造が容易になり得る構成である半導体装置を提供することができる。
（Ａ）～（Ｂ）は、本発明の第１実施形態の半導体装置１を説明するための図であり、（Ａ）は平面図、（Ｂ）はＡ－Ａ断面図である。 は、第１素子２０、第２素子３０及びインターポーザー基板４０を説明するための図であり、（Ａ）は、第１素子２０を第１素子第１主面２２から見た平面図、（Ｂ）は、第２素子３０を第２素子第１主面３２から見た平面図、（Ｃ）は、インターポーザー基板４０をインターポーザー基板第１主面から見た平面図である。 （Ａ）～（Ｂ）は、本発明の第２実施形態の半導体装置１Ａを説明するための図であり、（Ａ）は、第２実施形態の半導体装置１Ａの断面図、（Ｂ）は、インターポーザー基板４０をインターポーザー基板第１主面から見た平面図である。 （Ａ）～（Ｃ）は、インターポーザー基板の配置のバリエーションを説明するための図であり、（Ａ）は、３つの素子にインターポーザー基板を適用した場合を示す図、（Ｂ）は、４つの素子にインターポーザー基板を適用した場合を示す図、（Ｃ）は、５つの素子にインターポーザー基板を適用した場合を示す図である。
［第１実施形態］以下、本発明の第１実施形態について、図面を参照しながら説明する。図１は、本発明の第１実施形態の半導体装置１を説明するための図であり、図１（Ａ）は平面図、図１（Ｂ）はＡ－Ａ断面図である。図２は、第１素子２０、第２素子３０及びインターポーザー基板４０を説明するための図であり、図２（Ａ）は、第１素子２０を第１素子第１主面２２から見た平面図、図２（Ｂ）は、第２素子３０を第２素子第１主面３２から見た平面図、図２（Ｃ）は、インターポーザー基板４０をインターポーザー基板第１主面４１から見た平面図である。
　以下の説明において、「非接触に信号を送受信する」とは、信号を送受信する一方の送受信部と、信号を送受信する他方の送受信部とが、互いに接触せず、且つ導電性部材（半田、導電性接着剤、ワイヤ等のいずれか１つ以上）を介さずに信号を送受信することを意味する。また、「接触して信号を送受信する」とは、信号を送受信する一方の送受信部と、信号を送受信する他方の送受信部とが、互いに接触して信号を送受信するか、又は導電性部材（半田、導電性接着剤、ワイヤ等のいずれか１つ以上）を介して信号を送受信することを意味する。
　図１に示されるように、半導体装置１は、ベース基板１０と、第１素子２０と、第２素子３０と、インターポーザー基板４０と、を備える。
　ベース基板１０は、ベース基板端子面としてのベース基板内部端子面１１と、ベース基板外部端子面１２と、複数のベース基板端子としての複数のベース基板内部端子１３と、複数のベース基板外部端子１４と、を有する。ベース基板１０は、プリント配線基板である。ベース基板内部端子面１１は、ベース基板１０の上側の主面である。ベース基板外部端子面１２は、ベース基板内部端子面１１の反対の面であり、ベース基板１０の下側の主面である。
　図１（Ｂ）に示されるように、複数のベース基板内部端子１３は、ベース基板内部端子面１１に設けられている。複数のベース基板内部端子１３は、第１素子２０の第１素子信号送受信端子２４（後述）と電気的に接続される複数の第１素子側ベース基板内部端子１３Ａと、第２素子３０の第２素子信号送受信端子３４（後述）と電気的に接続される複数の第２素子側ベース基板内部端子１３Ｂと、で構成される。
　複数のベース基板外部端子１４は、ベース基板外部端子面１２に設けられている。複数のベース基板内部端子１３と複数のベース基板外部端子１４とは、ベース基板１０の内部にもうけられた内部配線（不図示）やビアホール（不図示）を介して、電気的に接続されている。各々のベース基板外部端子１４は、電気機器等の内部に設けられる回路基板（不図示）の端子に電気的に接続される。半導体装置１は、電気機器等の内部に設けられる回路基板（不図示）の端子に電気的に接続されることによって、電子機器等において、所定の機能を発揮する。
　図１（Ｂ）に示されるように、第１素子２０は、第１素子基板２１と、３５個（複数）の第１素子信号送受信端子２４と、複数の第１素子非接触信号送受信部としての７個（複数）の第１素子非接触信号送受信コイル２５と、を有する。７個（複数）の第１素子非接触信号送受信コイル２５は、一列に並んでいる。第１素子２０は、所定の信号処理を行う第１素子信号処理回路（不図示）を１つ以上含む素子である。第１素子２０は、ＣＰＵ、メモリ等であり得る。
　第１素子基板２１は、シリコンで形成された基板である。第１素子基板２１は、第１素子第１主面２２と、第１素子第２主面２３と、を有する。
　第１素子第１主面２２は、第１素子基板２１の下側の主面である。第１素子第２主面２３は、第１素子第１主面２２の反対の面であり、第１素子基板２１の上側の主面である。第１素子基板２１の第１素子第１主面２２側には、単層又は複数層のシリコン酸化膜を含む第１素子絶縁層２２Ａが設けられている。そのため、第１素子第１主面２２は、シリコン酸化膜で形成された面となっている。また、第１素子第２主面２３は、シリコンが露出した面であり、端子やコイルは設けられていない。
　図１（Ｂ）及び図２（Ａ）に示されるように、各々の第１素子信号送受信端子２４は、第１素子絶縁層２２Ａの上に設けられている。各々の第１素子信号送受信端子２４は、第１素子絶縁層２２Ａの内部に設けられた内部配線（不図示）やビアホール（不図示）を介して第１素子信号処理回路（不図示）と電気的に接続されている。なお、図２（Ａ）において、第１素子絶縁層２２Ａは、一部に斜線が設けられることによって表現されている。図２（Ａ）から分かるように、第１素子基板２１の第１素子第１主面２２側の全面には、第１素子絶縁層２２Ａが設けられている。
　図２（Ａ）に示されるように、各々の第１素子非接触信号送受信コイル２５は、第１素子絶縁層２２Ａの上に設けられている。各々の第１素子非接触信号送受信コイル２５は、第１素子非接触信号送受信コイル配線部２５Ａと、第１素子非接触信号送受信コイル本体部２５Ｂと、第１素子非接触信号送受信コイル用ビアホール２５Ｃと、で構成される。第１素子非接触信号送受信コイル本体部２５Ｂは、配線によって構成されたコイルである。第１素子非接触信号送受信コイル配線部２５Ａの一端には、第１素子非接触信号送受信コイル本体部２５Ｂが接続されており、第１素子非接触信号送受信コイル本体部２５Ｂの他端には、第１素子非接触信号送受信コイル用ビアホール２５Ｃが接続されている。
　第１素子非接触信号送受信コイル用ビアホール２５Ｃは、第１素子絶縁層２２Ａの内部に設けられた内部配線（不図示）やビアホール（不図示）を介して第１素子信号処理回路（不図示）と電気的に接続されている。第１素子非接触信号送受信コイル本体部２５Ｂは、第１素子非接触信号送受信コイル配線部２５Ａ、第１素子非接触信号送受信コイル用ビアホール２５Ｃ及び第１素子絶縁層２２Ａの内部にもうけられた内部配線（不図示）を介して、第１素子信号処理回路（不図示）と電気的に接続されている。
　以下の説明において、第１素子第２主面２３のうち、第１素子第１主面２２における第１素子信号送受信端子２４が設けられている領域の反対の面を第１素子第２主面端子対向領域２３Ａという。また、第１素子第２主面２３のうち、第１素子第１主面２２における第１素子非接触信号送受信コイル本体部２５Ｂが設けられている領域の反対の面を第１素子第２主面非接触信号送受信部対向領域２３Ｂという。
　図１（Ｂ）に示されるように、第２素子３０は、第２素子基板３１と、３５個（複数）の第２素子信号送受信端子３４と、複数の第２素子非接触信号送受信部としての７個（複数）の第２素子非接触信号送受信コイル３５と、を有する。７個（複数）の第２素子非接触信号送受信コイル３５は、一列に並んでいる。第２素子３０は、所定の信号処理を行う第２素子信号処理回路（不図示）を１つ以上含む素子である。第２素子３０は、ＣＰＵ、メモリ等であり得る。第２素子３０は、第１素子２０と同じ機能を有する素子であってもよいし、異なる機能を有する素子であってもよい。
　第２素子基板３１は、シリコンで形成された基板である。第２素子基板３１は、第２素子第１主面３２と、第２素子第２主面３３と、を有する。
　第２素子第１主面３２は、第２素子基板３１の下側の主面である。第２素子第２主面３３は、第２素子第１主面３２の反対の面であり、第２素子基板３１の上側の主面である。第２素子基板３１の第２素子第１主面３２側には、単層又は複数層のシリコン酸化膜を含む第２素子絶縁層３２Ａが設けられている。そのため、第２素子第１主面３２は、シリコン酸化膜で形成された面となっている。また、第２素子第２主面３３は、シリコンが露出した面であり、端子やコイルは設けられていない。
　図１（Ｂ）及び図２（Ｂ）に示されるように、複数の第２素子信号送受信端子３４は、第２素子絶縁層３２Ａの上に設けられている。複数の第２素子信号送受信端子３４は、第２素子絶縁層３２Ａの内部に設けられた内部配線（不図示）やビアホール（不図示）を介して第２素子信号処理回路（不図示）と電気的に接続されている。なお、図２（Ｂ）において、第２素子絶縁層３２Ａは、一部に斜線が設けられることによって表現されている。図２（Ｂ）から分かるように、第２素子基板３１の第２素子第１主面３２側の全面には、第２素子絶縁層３２Ａが設けられている。
　図２（Ｂ）に示されるように、各々の第２素子非接触信号送受信コイル３５は、第２素子絶縁層３２Ａの上に設けられている。各々の第２素子非接触信号送受信コイル３５は、第２素子非接触信号送受信コイル配線部３５Ａと、第２素子非接触信号送受信コイル本体部３５Ｂと、第２素子非接触信号送受信コイル用ビアホール３５Ｃと、で構成される。第２素子非接触信号送受信コイル本体部３５Ｂは、配線によって構成されたコイルである。第２素子非接触信号送受信コイル配線部３５Ａの一端には、第２素子非接触信号送受信コイル本体部３５Ｂが接続されており、第２素子非接触信号送受信コイル本体部３５Ｂの他端には、第２素子非接触信号送受信コイル用ビアホール３５Ｃが接続されている。
　第２素子非接触信号送受信コイル用ビアホール３５Ｃは、第２素子絶縁層３２Ａの内部に設けられた内部配線（不図示）やビアホール（不図示）を介して第２素子信号処理回路（不図示）と電気的に接続されている。第２素子非接触信号送受信コイル本体部３５Ｂは、第２素子非接触信号送受信コイル配線部３５Ａ、第２素子非接触信号送受信コイル用ビアホール３５Ｃ及び第２素子絶縁層３２Ａの内部に設けられた内部配線（不図示）を介して、第２素子信号処理回路（不図示）と電気的に接続されている。
　以下の説明において、第２素子第２主面３３のうち、第２素子第１主面３２における第２素子信号送受信端子３４が設けられている領域の反対の面を第２素子第２主面端子対向領域３３Ａという。また、第２素子第２主面３３のうち、第２素子第１主面３２における第２素子非接触信号送受信コイル本体部３５Ｂが設けられている領域の反対の面を第２素子第２主面非接触信号送受信部対向領域３３Ｂという。
　図１（Ｂ）に示されるように、インターポーザー基板４０は、インターポーザー基板第１主面４１と、インターポーザー基板第２主面４２と、複数のインターポーザー基板第１非接触信号送受信部としての複数のインターポーザー基板第１非接触信号送受信コイル４３と、複数のインターポーザー基板第２非接触信号送受信部としての複数のインターポーザー基板第２非接触信号送受信コイル４４と、を有する。インターポーザー基板４０は、シリコンで形成された基板である。インターポーザー基板第１主面４１は、インターポーザー基板４０の下側の主面である。インターポーザー基板第２主面４２は、インターポーザー基板第１主面４１の反対の面であり、インターポーザー基板４０の上側の主面である。インターポーザー基板４０のインターポーザー基板第１主面４１側には、単層又は複数層のシリコン酸化膜を含むインターポーザー基板絶縁層４１Ａが設けられている。そのため、インターポーザー基板第１主面４１は、シリコン酸化膜で形成された面となっている。また、インターポーザー基板第２主面４２は、シリコンが露出した面であり、端子やコイルは設けられていない。
　図１（Ｂ）及び図２（Ｃ）に示されるように、各々のインターポーザー基板第１非接触信号送受信コイル４３及び各々のインターポーザー基板第２非接触信号送受信コイル４４は、インターポーザー基板絶縁層４１Ａの上に設けられている。なお、図２（Ｃ）において、インターポーザー基板絶縁層４１Ａは、一部に斜線が設けられることによって表現されている。図２（Ｃ）から分かるように、インターポーザー基板４０のインターポーザー基板第１主面４１側の全面には、インターポーザー基板絶縁層４１Ａが設けられている。
　図２（Ｃ）に示されるように、各々のインターポーザー基板第１非接触信号送受信コイル４３及び各々のインターポーザー基板第２非接触信号送受信コイル４４は、配線によって構成されたコイルである。インターポーザー基板第１非接触信号送受信コイル４３と、インターポーザー基板第２非接触信号送受信コイル４４とは、インターポーザー基板配線４５によって電気的に接続されている。すなわち、インターポーザー基板配線４５の一端には、インターポーザー基板第１非接触信号送受信コイル４３が接続されており、インターポーザー基板配線４５の他端には、インターポーザー基板第２非接触信号送受信コイル４４が接続されている。なお、インターポーザー基板配線４５は、インターポーザー基板絶縁層４１Ａの上に設けられている。
　図１に示されるように、第１素子２０は、ベース基板１０の上に配置されている。
　第１素子第１主面２２は、ベース基板内部端子面１１に対向している。各々の第１素子信号送受信端子２４は、第１素子導電性部材２４Ａを介して、各々の第１素子側ベース基板内部端子１３Ａに電気的に接続されている。第１素子導電性部材２４Ａは、ハンダ、導電性接着剤等の導電性部材である。そのため、第１素子信号送受信端子２４と第１素子側ベース基板内部端子１３Ａとは、接触して信号の送受信が可能であるといえる。第１素子２０は、第１素子導電性部材２４Ａによって、ベース基板１０の上に固定されている。第１素子２０は、ベース基板１０にフェイスダウン接続されることになる。
　各々の第１素子非接触信号送受信コイル本体部２５Ｂは、導電性部材を介して、複数の第１素子側ベース基板内部端子１３Ａに電気的に接続されない。
　第２素子３０は、ベース基板１０の上に配置されている。第２素子第１主面３２は、ベース基板内部端子面１１に対向している。各々の第２素子信号送受信端子３４は、第２素子導電性部材３４Ａを介して、各々の第２素子側ベース基板内部端子１３Ｂに電気的に接続されている。第２素子導電性部材３４Ａは、ハンダ、導電性接着剤等の導電性部材である。そのため、第２素子信号送受信端子３４と第２素子側ベース基板内部端子１３Ｂとは、接触して信号の送受信が可能であるといえる。第２素子３０は、第２素子導電性部材３４Ａによって、ベース基板１０の上に固定されている。第２素子３０は、ベース基板１０にフェイスダウン接続されることになる。
　各々の第２素子非接触信号送受信コイル本体部３５Ｂは、導電性部材を介して、複数の第２素子側ベース基板内部端子１３Ｂに電気的に接続されない。
　図１に示されるように、インターポーザー基板４０は、第１素子２０及び第２素子３０に跨って配置されている。インターポーザー基板第１主面４１は、第１素子第２主面２３及び第２素子第２主面３３に対向している。より具体的には、インターポーザー基板第１主面４１は、第１素子第２主面非接触信号送受信部対向領域２３Ｂ及び第２素子第２主面非接触信号送受信部対向領域３３Ｂと対向し、第１素子第２主面端子対向領域２３Ａの一部及び第２素子第２主面端子対向領域３３Ａの一部とも対向している。また、インターポーザー基板第１主面４１は、第１素子第２主面２３及び第２素子第２主面３３に接触している。インターポーザー基板４０は、接着剤によって、第１素子２０及び第２素子３０に固定される。
　インターポーザー基板４０は、第１素子第２主面非接触信号送受信部対向領域２３Ｂを覆うとともに、第１素子第２主面端子対向領域２３Ａの一部も覆っている。
　同様に、インターポーザー基板４０は、第２素子第２主面非接触信号送受信部対向領域３３Ｂを覆うとともに、第２素子第２主面端子対向領域３３Ａの一部も覆っている。
　各々のインターポーザー基板第１非接触信号送受信コイル４３は、各々の第１素子非接触信号送受信コイル本体部２５Ｂと対向している。そのため、インターポーザー基板第１非接触信号送受信コイル４３と第１素子非接触信号送受信コイル本体部２５Ｂとは、第１素子基板２１を介して、非接触に信号の送受信が可能である。より具体的には、インターポーザー基板第１非接触信号送受信コイル４３と第１素子非接触信号送受信コイル本体部２５Ｂとは、両コイル間に生じる誘導結合によって、第１素子基板２１を介した非接触な信号の送受信が可能である。なお、第１素子基板２１は、インターポーザー基板第１非接触信号送受信コイル４３と第１素子非接触信号送受信コイル本体部２５Ｂとの間で、非接触に信号の送受信が可能な程度に薄くされている。例えば、第１素子基板２１の厚みは、５μｍ～２５μｍである。
　各々のインターポーザー基板第２非接触信号送受信コイル４４は、各々の第２素子非接触信号送受信コイル本体部３５Ｂと対向している。そのため、インターポーザー基板第２非接触信号送受信コイル４４と第２素子非接触信号送受信コイル本体部３５Ｂとは、第２素子基板３１を介して、非接触に信号の送受信が可能である。より具体的には、インターポーザー基板第２非接触信号送受信コイル４４と第２素子非接触信号送受信コイル本体部３５Ｂとは、両コイル間に生じる誘導結合によって、第２素子基板３１を介した非接触な信号の送受信が可能である。なお、第２素子基板３１は、インターポーザー基板第２非接触信号送受信コイル４４と第２素子非接触信号送受信コイル本体部３５Ｂとの間で、非接触に信号の送受信が可能な程度に薄くされている。例えば、第２素子基板３１の厚みは、５μｍ～２５μｍである。
　上述したように、インターポーザー基板第１非接触信号送受信コイル４３とインターポーザー基板第２非接触信号送受信コイル４４とは、インターポーザー基板配線４５によって電気的に接続されている。よって、第１素子２０と第２素子３０とは、インターポーザー基板４０を介して、信号の送受信が可能である。
　例えば、第１素子信号処理回路（不図示）から出力された信号は、第１素子非接触信号送受信コイル本体部２５Ｂから第１素子送信信号Ｓ１として送信される。第１素子送信信号Ｓ１は、インターポーザー基板第１非接触信号送受信コイル４３で受信され、インターポーザー基板配線４５を介して、インターポーザー基板第２非接触信号送受信コイル４４から送信される。インターポーザー基板第２非接触信号送受信コイル４４から送信された第１素子送信信号Ｓ１は、第２素子３０の第２素子非接触信号送受信コイル本体部３５Ｂで受信される。同様に、第２素子非接触信号送受信コイル本体部３５Ｂから送信される第２素子送信信号Ｓ２は、インターポーザー基板第２非接触信号送受信コイル４４、インターポーザー基板配線４５、インターポーザー基板第１非接触信号送受信コイル４３を介して、第１素子２０の第１素子非接触信号送受信コイル本体部２５Ｂで受信される。
　以上の構成を有する第１実施形態の半導体装置１によれば、以下の効果が奏される。
　複数のベース基板内部端子１３が設けられたベース基板内部端子面１１を有するベース基板１０と、第１素子第１主面２２と、第１素子第１主面２２と反対の面である第１素子第２主面２３とを有する第１素子基板２１であって、第１素子第１主面２２側に設けられた第１素子信号送受信端子２４と、第１素子第１主面２２側に設けられた第１素子非接触信号送受信コイル２５と、を有する第１素子２０と、第２素子第１主面３２と、第２素子第１主面３２と反対の面である第２素子第２主面３３とを有する第２素子基板３１であって、第２素子第１主面３２側に設けられた第２素子信号送受信端子３４と、第２素子第１主面３２側に設けられた第２素子非接触信号送受信コイル３５と、を有する第２素子３０と、インターポーザー基板第１非接触信号送受信コイル４３と、インターポーザー基板第１主面４１を有するインターポーザー基板４０であって、インターポーザー基板第１主面４１側に設けられたインターポーザー基板第１非接触信号送受信コイル４３と、インターポーザー基板第１主面４１側に設けられ、インターポーザー基板第１非接触信号送受信コイル４３と電気的に接続されたインターポーザー基板第２非接触信号送受信コイル４４と、を有するインターポーザー基板４０を備えている。そして、第１素子２０は、第１素子第１主面２２がベース基板内部端子面１１に対向するようにベース基板１０上に配置されており、第１素子信号送受信端子２４と複数のベース基板内部端子１３の１つとは、接触して信号の送受信が可能であり、第２素子３０は、第２素子第１主面３２がベース基板内部端子面１１に対向するようにベース基板１０上に配置されており、第２素子信号送受信端子３４と複数のベース基板内部端子１３の１つとは、接触して信号の送受信が可能であり、インターポーザー基板４０は、インターポーザー基板第１主面４１が第１素子第２主面２３及び前記第２素子第２主面３３に対向するように第１素子２０及び第２素子３０に跨って配置されており、インターポーザー基板第１非接触信号送受信コイル４３は、第１素子基板２１を介して、第１素子非接触信号送受信コイル２５と非接触に信号の送受信が可能であり、インターポーザー基板第２非接触信号送受信コイル４４は、第２素子基板３１を介して、第２素子非接触信号送受信コイル３５と非接触に信号の送受信が可能である。
　そのため、インターポーザー基板４０の形状は、第１素子第２主面非接触信号送受信部対向領域２３Ｂ及び第２素子第２主面非接触信号送受信部対向領域３３Ｂの形状による制約を受けない。よって、第１実施形態の半導体装置１において、第１素子基板２１における第１素子非接触信号送受信コイル２５を設ける領域及び第２素子非接触信号送受信コイル３５を設ける領域は、小型化され得る。よって、第１実施形態の半導体装置１は、小型化が可能な構成である。
　更に、半導体装置１の構成から明らかなように、半導体装置１が製造される際、インターポーザー基板４０は最後に配置され得る。また、半導体装置１においては、インターポーザー基板４０のアスペクト比が大きくなることが抑制される。例えば、インターポーザー基板４０が第１素子第２主面非接触信号送受信部対向領域２３Ｂ及び第２素子第２主面非接触信号送受信部対向領域３３Ｂのみに配置されるとすると、インターポーザー基板４０は、アスペクト比が大きい（例えば、１０以上）の基板になってしまう可能性がある。しかし、インターポーザー基板４０は、第１素子第２主面非接触信号送受信部対向領域２３Ｂ及び第２素子第２主面非接触信号送受信部対向領域３３Ｂだけでなく、第１素子第２主面端子対向領域２３Ａ及び第２素子第２主面端子対向領域３３Ａにも配置されるため、インターポーザー基板４０のアスペクト比が大きくなることは抑制される。また、インターポーザー基板４０は、コイル及び配線しか形成されておらず、電源電圧の供給が必要な能動素子は配置されていない。よって、インターポーザー基板４０には、電源電圧の供給は不要であり、電源電圧供給のための配線や端子も不要である。そのため、半導体装置１は、製造が容易になり得る構成である。
　また、第１実施形態の半導体装置１において、第１素子２０と第２素子３０とは、インターポーザー基板４０を介して、非接触に信号の送受信が可能である。そのため、第１素子２０と第２素子３０との接続にあたり、インピーダンス整合は不要である（又は、接触して信号の送受信を行う半導体装置に比べて、インピーダンス整合の精度が緩和されている。）。
　また、第１素子基板２１の第１素子第２主面２３の一部は、インターポーザー基板４０に覆われていない状態になっている。よって、第１素子２０で発生する熱は、第１素子第２主面２３から放熱される。そして、第２素子基板３１の第２素子第２主面３３の一部は、インターポーザー基板４０に覆われていない状態になっている。よって、第２素子３０で発生する熱は、第２素子第２主面３３から放熱される。
　また、第１素子第２主面２３は、第１素子第１主面２２における第１素子信号送受信端子２４が設けられている領域の反対の面である第１素子第２主面端子対向領域２３Ａと、第１素子第１主面２２における第１素子非接触信号送受信コイル２５が設けられている領域の反対面である第１素子第２主面非接触信号送受信部対向領域２３Ｂと、を有し、第２素子第２主面３３は、第２素子第１主面３２における第２素子信号送受信端子３４が設けられている領域の反対面である第２素子第２主面端子対向領域３３Ａと、第２素子第１主面３２における第２素子非接触信号送受信コイル３５が設けられている領域の反対の面である第２素子第２主面非接触信号送受信部対向領域３３Ｂと、を有し、インターポーザー基板４０のインターポーザー基板第１主面４１は、第１素子第２主面非接触信号送受信部対向領域２３Ｂ及び第２素子第２主面非接触信号送受信部対向領域３３Ｂに対向し、第１素子第２主面端子対向領域２３Ａの一部及び第２素子第２主面端子対向領域３３Ａの一部の少なくとも一方にも対向している。
　そのため、第１実施形態の半導体装置１は、より小型化が可能な構成であり、製造がより容易になり得る構成となる。
　［第２実施形態］
　次に、本発明の第２実施形態について、図３を参照しながら説明する。図３は、本発明の第２実施形態の半導体装置１Ａを説明するための図であり、図３（Ａ）は、第２実施形態の半導体装置１Ａの断面図、図３（Ｂ）は、インターポーザー基板４０をインターポーザー基板第１主面から見た平面図である。
　第２実施形態については、主として、第１実施形態と異なる点を中心に説明し、第１実施形態と同様な構成については、詳細な説明を省略する。特に説明しない点は、第１実施形態についての説明が適宜適用される。
　図３に示されるように、第２実施形態の半導体装置１Ａは、ベース基板１０と、第１素子２０と、第２素子３０と、シリコンを主成分として材料で形成されたインターポーザー基板４０を備えている。第２実施形態の半導体装置１Ａにおいて、インターポーザー基板４０の構成が、第１実施形態の半導体装置１におけるインターポーザー基板４０の構成と異なる。
　図３（Ａ）及び図３（Ｂ）に示されるように、第２実施形態の半導体装置１Ａにおけるインターポーザー基板４０のインターポーザー基板第１主面４１は、第１実施形態の半導体装置１におけるインターポーザー基板４０とは異なり、単層又は複数層のシリコン酸化膜を含むインターポーザー基板絶縁層４１Ａは、インターポーザー基板４０のインターポーザー基板第１主面４１側の中央付近のみに設けられている。インターポーザー基板第１主面４１側におけるインターポーザー基板絶縁層４１Ａが設けられていない部分は、シリコンが露出した部分となっている。シリコンが露出した部分のうち、第１素子２０側の部分が第１素子側露出部分４１Ｂであり、第２素子３０側の部分が第２素子側露出部分４１Ｃである。図３（Ｂ）において、インターポーザー基板絶縁層４１Ａは、一部に斜線が設けられることによって表現されている。第２実施形態の半導体装置１Ａにおけるインターポーザー基板４０のインターポーザー基板第１主面４１は、シリコン酸化膜で形成された面とシリコンが露出した面とで構成される。
　第１素子側露出部分４１Ｂは、第１素子第２主面端子対向領域２３Ａに接触しており、第２素子側露出部分４１Ｃは、第２素子第２主面端子対向領域３３Ａに接触している。
　シリコンの熱伝導率（約１６０Ｗ／ｍ・Ｋ）は、シリコン酸化膜の熱伝導率（約１．３Ｗ／ｍ・Ｋ）と比べて、熱伝導率が大きい。そのため、インターポーザー基板４０における第１素子側露出部分４１Ｂは、第１素子第２主面２３と接触することによって、第１素子２０で発生する熱を放熱する放熱部として機能する。同様に、インターポーザー基板４０における第２素子側露出部分４１Ｃは、第２素子第２主面３３と接触することによって、第２素子３０で発生する熱を放熱する放熱部として機能する。
　以上の構成を有する第２実施形態の半導体装置１Ａによれば、以下の効果が奏される。
　第２実施形態の半導体装置１Ａにおいては、第１素子基板２１、第２素子基板３１及びインターポーザー基板４０は、シリコンで形成されており、インターポーザー基板４０のインターポーザー基板第１主面４１は、シリコンが露出した露出部分を有し、露出部分は、第１素子第２主面端子対向領域２３Ａの一部及び第２素子第２主面端子対向領域３３Ａの一部に接触している。そのため、インターポーザー基板４０が大きくなっても、第１素子側露出部分４１Ｂ及び第２素子側露出部分４１Ｃが存在するため、第１素子２０の熱や第２素子３０の熱は放熱される。そのため、インターポーザー基板４０の形状は、第１素子第２主面非接触信号送受信部対向領域２３Ｂ及び第２素子第２主面非接触信号送受信部対向領域３３Ｂの形状による制約を受けないだけでなく、第１素子２０や第２素子３０で発生する熱による制約も受け難い。
　［第３実施形態］
　次に、本発明の第３実施形態について、図４を参照しながら説明する。図４は、インターポーザー基板の配置のバリエーションを説明するための図であり、図４（Ａ）は、３つの素子にインターポーザー基板を適用した場合を示す図、図４（Ｂ）は、４つの素子にインターポーザー基板を適用した場合を示す図、図４（Ｃ）は、５つの素子にインターポーザー基板を適用した場合を示す図である。
　第３実施形態については、主として、第１実施形態と異なる点を中心に説明し、第１実施形態と同様な構成については、詳細な説明を省略する。特に説明しない点は、第１実施形態についての説明が適宜適用される。
　図４（Ａ）に示されるように、インターポーザー基板４０は、第１素子２０、第２素子３０及び第３素子５０に跨るように配置されることも可能である。第１素子２０、第２素子３０及び第３素子５０は、インターポーザー基板４０を介して、相互に信号の送受信が可能である。
　なお、図４（Ａ）において、便宜上、左下の素子が第１素子２０とされ、右下の素子が第２素子３０とされ、上の素子が第３素子５０とされている。しかし、第１素子２０、第２素子３０及び第３素子５０は、相互に入れ替え可能である。例えば、上の素子が第１素子２０（又は第２素子３０）であり、左下の素子（又は右下の素子）が第２素子３０（又は第１素子２０）であってもよい。例えば、第１素子２０の大きさと第２素子３０の大きさとは、異なっていてもよい。
　図４（Ｂ）に示されるように、インターポーザー基板４０は、第１素子２０、第２素子３０、第３素子５０及び第４素子６０に跨るように配置されることも可能である。第１素子２０、第２素子３０、第３素子５０及び第４素子６０は、インターポーザー基板４０を介して、相互に信号の送受信が可能である。
　なお、図４（Ｂ）において、第１素子２０は、左上の素子、左下の素子、右上の素子及び右下の素子のいずれであってもよい。例えば、左上の素子が第１素子２０（又は第２素子３０）であり、右下の素子が第２素子３０（又は第１素子２０）であってもよい。例えば、第１素子２０と第２素子３０とは、対向する辺を持たない配置であってもよい。
　図４（Ｃ）に示されるように、インターポーザー基板４０は、第１素子２０、第２素子３０、第３素子５０、第４素子６０及び第５素子７０に跨るように配置されることも可能である。第１素子２０、第２素子３０、第３素子５０、第４素子６０及び第５素子７０は、インターポーザー基板４０を介して、相互に信号の送受信が可能である。
　なお、図４（Ｃ）において、第１素子２０は、左上の素子、右上の素子、左下の素子、下側中央の素子及び右下の素子のいずれであってもよい。また、第２素子３０は、左上の素子、右上の素子、左下の素子、下側中央の素子及び右下の素子のいずれであってもよい。例えば、左の素子が第１素子２０（又は第２素子３０）であり、右下の素子が第２素子３０（又は第１素子２０）であってもよい。例えば、第１素子２０と第２素子３０とは、対向する辺を持たず、且つ、間に他の素子が存在するような配置であってもよい。
　以上、本発明の第１実施形態～第３実施形態について説明した。しかし、本発明は、上記実施形態に限定されることはなく、特許請求の範囲に記載された技術的範囲において種々に変形可能である。
　また、第１実施形態～第３実施形態において、非接触な信号の送受信は、コイル間の誘導結合が利用されていたが、これに限定されない。非接触な信号の送受信は、コイル間の磁気共鳴が利用されていた非接触な信号の送受信であってもよいし、光信号や音波信号が利用された非接触な信号の送受信であってもよい。
　また、第１実施形態～第３実施形態において、インターポーザー基板４０は、シリコンで形成されていたが、これに限定されない。インターポーザー基板４０は、シリコン以外の半導体材料で形成されていてもよい。なお、半導体材料とは、半導体としての性質を有する材料及び不純物がドープされることによって半導体としての性質を有するようになり得る材料を意味する。また、インターポーザー基板４０は、半導体材料で形成された基板以外であってもよく、例えば、ガラスや樹脂材料で形成された基板であってもよい。また、インターポーザー基板４０は、プリント配線基板であってもよい。
　また、第１実施形態～第３実施形態において、ベース基板１０は、プリント配線基板であったが、これに限定されない。ベース基板１０は、シリコン等の半導体材料で形成された基板であってもよい。また、ベース基板１０自体が、信号処理機能を有する半導体素子であってもよい。
　また、第１実施形態～第３実施形態において、インターポーザー基板４０は、接着剤によって、第１素子２０及び第２素子３０に固定されていたが、これに限定されない。インターポーザー基板４０は、接着剤又は接着剤以外の固定部材を用いて、第１素子２０及び第２素子３０に固定されていてもよい。また、インターポーザー基板４０は、常温接合等の直接接合技術によって、第１素子２０及び第２素子３０に固定されていてもよい。
　また、第１実施形態、第３実施形態において、インターポーザー基板第１主面４１は、第１素子第２主面２３の一部及び第２素子第２主面３３の一部に接触していたが、これに限定されない。インターポーザー基板第１主面４１は、第１素子第２主面２３及び第２素子第２主面３３に対向していればよい。例えば、インターポーザー基板４０は、スペーサー等によって、第１素子第２主面２３及び第２素子第２主面３３から間隔を空けて配置されていてもよい。
　また、第１実施形態～第３実施形態において、インターポーザー基板第１主面４１は、第１素子第２主面端子対向領域２３Ａの一部及び第２素子第２主面端子対向領域３３Ａの一部に対向していたが、これに限定されない。インターポーザー基板第１主面４１は、第１素子第２主面端子対向領域２３Ａの一部及び第２素子第２主面端子対向領域３３Ａの一部の少なくとも一方に対向していればよい。
　また、第２実施形態において、インターポーザー基板第１主面４１の露出部分は、第１素子第２主面端子対向領域２３Ａの一部及び第２素子第２主面端子対向領域３３Ａの一部に接触していたが、これに限定されない。インターポーザー基板第１主面４１の露出部分は、第１素子第２主面端子対向領域２３Ａの一部及び第２素子第２主面端子対向領域３３Ａの一部の少なくとも一方に接触していればよい。例えば、インターポーザー基板第１主面４１において、第１素子側露出部分４１Ｂ及び第２素子側露出部分４１Ｃのいずれか一方のみが存在していてもよい。
　また、第１実施形態～第３実施形態において、インターポーザー基板第１主面４１は、第１素子第２主面端子対向領域２３Ａにおける最も発熱する領域及び第２素子第２主面端子対向領域３３Ａにおける最も発熱する領域に対向しないように配置されていてもよい。第１素子第２主面端子対向領域２３Ａにおける最も発熱する領域及び第２素子第２主面端子対向領域３３Ａにおける最も発熱する領域は、インターポーザー基板４０によって覆われていない方が、放熱され易いことがあり得るからである。
　また、第１実施形態～第３実施形態において、第１素子非接触信号送受信コイル２５は、第１素子絶縁層２２Ａの上に設けられていたが、これに限定されない。第１素子非接触信号送受信コイル２５は、第１素子絶縁層２２Ａの内部に設けられていてもよい。第１素子非接触信号送受信コイル２５は、第１素子絶縁層２２Ａの上に露出していてもよいし、露出していなくてもよい。第１素子非接触信号送受信コイル２５は、第１素子第１主面２２側に設けられていればよい。なお、第１素子第１主面２２側とは、第１素子基板２１の厚み方向において、第１素子第２主面２３よりも第１素子第１主面２２に近い部分（第１素子第１主面２２の表面を含む。）を意味する。
　第２素子非接触信号送受信コイル３５は、第２素子絶縁層３２Ａの上に設けられていたが、これに限定されない。第２素子非接触信号送受信コイル３５は、第２素子絶縁層３２Ａの内部に設けられていてもよい。すなわち、第２素子非接触信号送受信コイル３５は、第２素子絶縁層３２Ａの上に露出していてもよいし、露出していなくてもよい。第２素子非接触信号送受信コイル３５は、第２素子第１主面３２側に設けられていればよい。なお、第２素子第１主面３２側とは、第２素子基板３１の厚み方向において、第２素子第２主面３３よりも第２素子第１主面３２に近い部分（第２素子第１主面３２の表面を含む。）を意味する。
　インターポーザー基板第１非接触信号送受信コイル４３、インターポーザー基板第２非接触信号送受信コイル４４及びインターポーザー基板配線４５は、インターポーザー基板絶縁層４１Ａの上に設けられていたが、これに限定されない。インターポーザー基板第１非接触信号送受信コイル４３、インターポーザー基板第２非接触信号送受信コイル４４及びインターポーザー基板配線４５は、インターポーザー基板第１非接触信号送受信コイル４３、インターポーザー基板第２非接触信号送受信コイル４４及びインターポーザー基板配線４５は、内部に設けられていてもよい。すなわち、インターポーザー基板第１非接触信号送受信コイル４３、インターポーザー基板第２非接触信号送受信コイル４４及びインターポーザー基板配線４５は、インターポーザー基板絶縁層４１Ａの上に露出していてもよいし、露出していなくてもよい。また、インターポーザー基板第１非接触信号送受信コイル４３、インターポーザー基板第２非接触信号送受信コイル４４及びインターポーザー基板配線４５は、インターポーザー基板第１主面４１側に設けられていていればよい。なお、インターポーザー基板第１主面４１側とは、インターポーザー基板４０の厚み方向において、インターポーザー基板第２主面４２よりもインターポーザー基板第１主面４１に近い部分（インターポーザー基板第１主面４１の表面を含む。）を意味する。
　また、第１実施形態～第３実施形態において、第１素子２０における第１素子信号送受信端子２４の数は３５であり、第２素子３０における第２素子信号送受信端子３４の数は３５であったが、これに限定されない。第１素子信号送受信端子２４及び第２素子信号送受信端子３４の数は、いくつであってもよい。また、第１素子２０における第１素子非接触信号送受信コイル２５の数は７であり、第２素子３０における第２素子非接触信号送受信コイル３５の数は７であったが、これに限定されない。第１素子非接触信号送受信コイル２５及び第２素子非接触信号送受信コイル３５の数は、いくつであってもよい。また、図２において、第１素子非接触信号送受信コイル２５及び第２素子非接触信号送受信コイル３５は、１列に並んで設けられていたが、２列以上に並んで設けられていてもよい。
　また、第１実施形態～第２実施形態において、第１素子絶縁層２２Ａ、第２素子絶縁層３２Ａ及びインターポーザー基板絶縁層４１Ａは、シリコン酸化膜で形成されていたが、シリコン窒化膜等の絶縁部材で形成されていてもよい。
　１，１Ａ　半導体装置
　１０　　ベース基板
　１１　ベース基板内部端子面（ベース基板端子面）
　１２　ベース基板外部端子面
　１３　　ベース基板内部端子（ベース基板端子）
　１３Ａ　第１素子側ベース基板内部端子
　１３Ｂ　第２素子側ベース基板内部端子
　１４　　ベース基板外部端子
 
　２０　　第１素子
　２１　　第１素子基板
　２２　　第１素子第１主面
　２２Ａ　第１素子絶縁層
　２３　　第１素子第２主面
　２３Ａ　第１素子第２主面端子対向領域
　２３Ｂ　第１素子第２主面非接触信号送受信部対向領域
　２４　　第１素子信号送受信端子
　２４Ａ　第１素子導電性部材
　２５　　第１素子非接触信号送受信コイル（第１素子非接触信号送受信部）
　２５Ａ　第１素子非接触信号送受信コイル配線部
　２５Ｂ　第１素子非接触信号送受信コイル本体部
　２５Ｃ　第１素子非接触信号送受信コイル用ビアホール
 
　３０　　第２素子
　３１　　第２素子基板
　３２　　第２素子第１主面
　３２Ａ　第２素子絶縁層
　３３　第２素子第２主面
　３３Ａ　第２素子第２主面端子対向領域
　３３Ｂ　第２素子第２主面非接触信号送受信部対向領域
　３４　　第２素子信号送受信端子
　３４Ａ　第２素子導電性部材
　３５　　第２素子非接触信号送受信コイル（第２素子非接触信号送受信部）
 
４０　　　インターポーザー基板
４１　　インターポーザー基板第１主面
４１Ａ　インターポーザー基板絶縁層
４１Ｂ　　第１素子側露出部分
４１Ｃ　　第２素子側露出部分
４２　　インターポーザー基板第２主面
４３　　　インターポーザー基板第１非接触信号送受信コイル（インターポーザー基板第１非接触信号送受信部）
４４　　　インターポーザー基板第２非接触信号送受信コイル（インターポーザー基板第２非接触信号送受信部）
４５　　　インターポーザー基板配線

Claims (4)

  1. 　複数のベース基板端子が設けられたベース基板端子面を有するベース基板と、
    　第１素子第１主面と、前記第１素子第１主面と反対の面である第１素子第２主面とを有する第１素子基板と、前記第１素子基板の前記第１素子第１主面側に設けられた第１素子信号送受信端子と、前記第１素子基板の前記第１素子第１主面側に設けられた第１素子非接触信号送受信部と、を有する第１素子と、
    　第２素子第１主面と、前記第２素子第１主面と反対の面である第２素子第２主面とを有する第２素子基板と、前記第２素子基板の前記第２素子第１主面側に設けられた第２素子信号送受信端子と、前記第２素子基板の前記第２素子第１主面側に設けられた第２素子非接触信号送受信部と、を有する第２素子と、
    　インターポーザー基板第１主面を有するインターポーザー基板であって、前記インターポーザー基板第１主面側に設けられたインターポーザー基板第１非接触信号送受信部と、前記インターポーザー基板第１主面側に設けられ、前記インターポーザー基板第１非接触信号送受信部と電気的に接続されたインターポーザー基板第２非接触信号送受信部と、を有するインターポーザー基板と、を備え、
    　前記第１素子は、前記第１素子第１主面が前記ベース基板端子面に対向するように前記ベース基板上に配置されており、前記第１素子信号送受信端子と前記複数のベース基板端子の１つとは、接触して信号の送受信が可能であり、
    　前記第２素子は、前記第２素子第１主面が前記ベース基板端子面に対向するように前記ベース基板上に配置されており、前記第２素子信号送受信端子と前記複数のベース基板端子の１つとは、接触して信号の送受信が可能であり、
    　前記インターポーザー基板は、前記インターポーザー基板第１主面が前記第１素子第２主面及び前記第２素子第２主面に対向するように前記第１素子及び前記第２素子に跨って配置されており、前記インターポーザー基板第１非接触信号送受信部は、前記第１素子基板を介して、前記第１素子非接触信号送受信部と非接触に信号の送受信が可能であり、前記インターポーザー基板第２非接触信号送受信部は、前記第２素子基板を介して、前記第２素子非接触信号送受信部と非接触に信号の送受信が可能である半導体装置。
  2. 　前記第１素子第２主面は、前記第１素子第１主面における前記第１素子信号送受信端子が設けられている領域の反対の面である第１素子第２主面端子対向領域と、前記第１素子第１主面における前記第１素子非接触信号送受信部が設けられている領域の反対の面である第１素子第２主面非接触信号送受信部対向領域と、を有し、
    　前記第２素子第２主面は、前記第２素子第１主面における前記第２素子信号送受信端子が設けられている領域の反対面である第２素子第２主面端子対向領域と、前記第２素子第１主面における前記第２素子非接触信号送受信部が設けられている領域の反対面である第２素子第２主面非接触信号送受信部対向領域と、を有し、
    　前記インターポーザー基板の前記インターポーザー基板第１主面は、前記第１素子第２主面非接触信号送受信部対向領域及び前記第２素子第２主面非接触信号送受信部対向領域に対向し、前記第１素子第２主面端子対向領域の一部及び前記第２素子第２主面端子対向領域の一部の少なくとも一方にも対向している請求項１に記載の半導体装置。
  3. 　前記第１素子基板、前記第２素子基板及び前記インターポーザー基板は、半導体材料で形成されており、前記インターポーザー基板の前記インターポーザー基板第１主面は、前記半導体材料が露出した露出部分を有し、前記露出部分は、前記第１素子第２主面端子対向領域の一部及び前記第２素子第２主面端子対向領域の一部の少なくとも一方に接触している請求項２に記載の半導体装置。
  4. 　前記第１素子非接触信号送受信部、前記第２素子非接触信号送受信部、前記インターポーザー基板第１非接触信号送受信部及び前記インターポーザー基板第２非接触信号送受信部は、配線により形成されたコイルである請求項１～３のいずれかに記載の半導体装置。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7299651B1 (ja) 2022-06-24 2023-06-28 株式会社Premo 半導体モジュール、半導体チップ及び半導体モジュールの製造方法
WO2023249086A1 (ja) * 2022-06-24 2023-12-28 株式会社Premo 半導体モジュール、半導体チップ及び半導体モジュールの製造方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10269734B2 (en) * 2015-07-16 2019-04-23 Ultramemory Inc. Semiconductor element
US11031341B2 (en) * 2017-03-29 2021-06-08 Intel Corporation Side mounted interconnect bridges
CN112889149B (zh) * 2019-01-18 2023-09-08 华为技术有限公司 一种多中介层互联的集成电路

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007318003A (ja) * 2006-05-29 2007-12-06 Nec Electronics Corp 半導体装置
JP2010103611A (ja) * 2008-10-21 2010-05-06 Keio Gijuku 電子回路
JP2010109112A (ja) * 2008-10-30 2010-05-13 Hitachi Ltd 半導体集積回路
JP2010251663A (ja) * 2009-04-20 2010-11-04 Renesas Electronics Corp 半導体装置
JP2011187823A (ja) * 2010-03-10 2011-09-22 Denso Corp 半導体装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5214525B2 (ja) 2009-04-20 2013-06-19 ルネサスエレクトロニクス株式会社 半導体装置
JP6216951B2 (ja) 2012-07-12 2017-10-25 学校法人慶應義塾 方向性結合式通信装置
KR102123991B1 (ko) 2013-03-11 2020-06-17 삼성전자주식회사 반도체 패키지 및 이를 구비하는 전자 시스템

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007318003A (ja) * 2006-05-29 2007-12-06 Nec Electronics Corp 半導体装置
JP2010103611A (ja) * 2008-10-21 2010-05-06 Keio Gijuku 電子回路
JP2010109112A (ja) * 2008-10-30 2010-05-13 Hitachi Ltd 半導体集積回路
JP2010251663A (ja) * 2009-04-20 2010-11-04 Renesas Electronics Corp 半導体装置
JP2011187823A (ja) * 2010-03-10 2011-09-22 Denso Corp 半導体装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7299651B1 (ja) 2022-06-24 2023-06-28 株式会社Premo 半導体モジュール、半導体チップ及び半導体モジュールの製造方法
WO2023249086A1 (ja) * 2022-06-24 2023-12-28 株式会社Premo 半導体モジュール、半導体チップ及び半導体モジュールの製造方法
JP2024002506A (ja) * 2022-06-24 2024-01-11 株式会社Premo 半導体モジュール、半導体チップ及び半導体モジュールの製造方法

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