CN111508921B - 具有双面对外接点的半导体芯片组 - Google Patents

具有双面对外接点的半导体芯片组 Download PDF

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CN111508921B
CN111508921B CN201911302705.8A CN201911302705A CN111508921B CN 111508921 B CN111508921 B CN 111508921B CN 201911302705 A CN201911302705 A CN 201911302705A CN 111508921 B CN111508921 B CN 111508921B
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semiconductor chip
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CN111508921A (zh
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王智彬
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Abstract

本发明实施例提出一种具有双面对外接点的半导体芯片组。此半导体芯片组的相对的第一侧面与第二侧面都各自设有对外的电路接点，半导体芯片的第一侧面或第二侧面上设置有芯片电路组，而此半导体芯片组的第一侧面的电路接点与第二侧面的电路接点皆对内连接至芯片电路，且用于连接此半导体芯片组以外的接点，包括至此半导体芯片组以外的讯号及电源传输接口(如封装基板或电路板)上的讯号及电源接点或是至此半导体芯片组以外的另一半导体芯片组上的讯号及电源接点。

Description

具有双面对外接点的半导体芯片组
【技术领域】
本发明涉及半导体技术领域，尤其涉及一种具有双面对外接点的半导体芯片组。
【背景技术】
半导体制程技术的高速发展使得半导体芯片中的电路密度越来越大，于是同样大小的半导体芯片能够容纳的电路和功能也越来越多，而就内存芯片来说，单位面积芯片上的内存储存密度越来越大，但此快速发展趋势已到了临界点，单位时间下单位面积芯片上的组件密度渐渐由指数成长趋缓到线性成长，为了维持高成长趋势，许多芯片堆栈技术也应运而生。然而，受限于种种因素，堆栈后的半导体芯片组合无法提供足够数量的接点用于各电路的输入/输出，且堆栈后的各个芯片端的电源及对地接点至封装完成的半导体组件外部电源及接地点的电感与电组最小值也因相同因素而受限。这个问题使得每一个堆栈后的半导体芯片组合所能够提供的功能及带宽受到限制，并进而限制了层半导体芯片尺寸的缩小程度。
【发明内容】
因此，本发明提供一种具有双面对外接点的半导体芯片组，其可提供较现有技术更多的输入/输出及电源接点，减少接点数量对半导体芯片组中的电路数量的限制，并突破外部电源及接地点连接到各芯片端的电源及接地点的电感与电阻最小值瓶颈。
具体地，本发明实施例提供了一种具有双面对外接点的半导体芯片组，此半导体芯片组外围相对的第一侧面与第二侧面都各自设有电路接点，第一侧面或第二侧面上设置有芯片电路组，且第一侧面的电路接点与第二侧面的电路接点用于连接此半导体芯片组以外的电路接点；其中，该第一侧面的电路接点与该第二侧面的电路接点用于通过打线接合或以锡球连接至该半导体芯片以外的电路接点；其中，该第一侧面的电路接点与该第二侧面的电路接点用于通过打线接合或以锡球连接至该半导体芯片以外的电路接点。
在本发明的一个实施例中，上述的芯片电路组设置于第一侧面，且芯片电路组连接到第一侧面的电路接点。
在本发明的一个实施例中，上述的芯片电路组设置于第一侧面，且芯片电路组经由贯穿半导体芯片的硅贯孔而连接到第二侧面的电路接点。
在本发明的一个实施例中，上述的半导体芯片组为一个半导体芯片，第一侧面与第二侧面为此半导体芯片相对的两侧面，芯片电路组设置于第一侧面并连接到第一侧面的电路接点，且芯片电路组另外经由贯穿半导体芯片的硅贯孔而连接到第二侧面的电路接点。
在本发明的一个实施例中，上述的半导体芯片组包括堆栈而成的多个半导体芯片，这些芯片中有一个第一芯片及一个第二芯片，第一芯片的相对两侧面各自设置有电路接点，第二芯片的相对两侧面各自设置有电路接点，第一芯片及第二芯片的电路接点用于连接此半导体芯片以外的电路。
在本发明的一个实施例中，第一芯片上设置有电性相接的第一控制电路及第一操作电路，第二芯片上设置有电性相接的第二控制电路及第二操作电路，第二控制电路经由贯穿第一芯片的硅贯孔而与第一操作电路电性相接；其中，在第一控制电路运作时，第一控制电路控制第一操作电路的操作方式，而在第一控制电路关闭时，第二控制电路同时控制第一操作电路及第二操作电路的操作方式。
在本发明的一个实施例中，上述的半导体芯片组包括多个堆栈的内存芯片。
另外，本发明实施例提出一种具有正反双面对外接点的半导体芯片，该半导体芯片具有相对的一第一侧面及一第二侧面，该第一侧面适于设置一芯片电路组，该第一侧面及该第二侧面分别设置有至少一对外接点，且该第二侧面的该至少一对外接点中的至少一者通过一硅贯孔连接至该芯片电路组；其中，该第一侧面的该至少一对外接点中的至少一者与该第二侧面的该至少一对外接点中的至少一者连接至该半导体芯片外的电源或信号。
在本发明的一个实施例中，上述的第一侧面的该至少一对外接点中的至少一者与该第二侧面的该至少一对外接点中的至少一者，通过锡球直接连接打线或重分布导体介质连接至该半导体芯片外的电源或信号。
在本发明的一个实施例中，上述的多个该半导体芯片之间可以部分或是全部的对外接点相互连接以构成一半导体芯片组，而位于该半导体芯片组中之任一该些半导体芯片上的对外接点亦可以同时作为该半导体芯片组的电源或是讯号的对外/对内传导接点。
通过以上技术，本发明所提供的具有双面对外接点的半导体芯片组可以在半导体芯片组的前侧(设置有电路的那一侧)及背侧(与前侧相对的那一侧)都设置输入/输出及电源接点，因此可提供更多的输入/输出堆栈的接点，减少接点数量对半导体芯片组中的电路数量的限制。
通过以下参考附图的详细说明，本发明的其它方面和特征变得明显。但是应当知道，该附图仅仅为解释的目的设计，而不是作为本发明的范围的限定。还应当知道，除非另外指出，不必要依比例绘制附图，它们仅仅利图概念地说明此处描述的结构和流程。
【附图说明】
此处所说明的附图用来提供对本发明的进一步理解，构成本发明的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1为本发明一实施例的具有双面对外接点的半导体晶片组的电路模块示意图；
图2为图1所示的实施例中沿着剖面线AA’所得的剖面图；
图3为图1所示的实施例中沿着剖面线BB’所得的剖面图；
图4为本发明一实施例的具有双面对外接点的半导体晶片组的剖面示意图；
图5为本发明一实施例的具有双面对外接点的半导体晶片组的剖面示意图；
图6为本发明一实施例的具有双面对外接点的半导体晶片组中的两个晶片的电路模块图；
图7为本发明一实施例的具有双面对外接点的半导体晶片组与其他半导体晶片连接的结构示意图；
图8为本发明一实施例的具有双面对外接点的半导体晶片组的剖面示意图；
图9为本发明一实施例的具有双面对外接点的半导体芯片组的结构示意图。
【附图标记说明】
10、40、50、80、82、84、90：半导体晶片组；
10A、10B、12A、12B：侧面；
12、42、44、52、54、72、74、92、94、96、9000、9100、9200：半导体芯片；
56、97、98：间隔层；
100：第一电路模块；
110：第二电路模块；
120：第三电路模块；
130、150、420、422、440、442、842：导电结构；
140、160、424、428、444、448、520、540、542、922、926、 942、946、962、966、9002、9003、9004、9005、9006、9008、9102、 9103、9104、9105、9106、9202、9203、9204、9205、9210：电路接点；
426、446、580、802、924、944、964、9010：硅贯孔；
430、450、9300、9302、9304、9306：导线；
720：第一控制电路；
722：第一操作电路；
740：第二控制电路；
742：第二操作电路；
920：基底；
972、982：导电贯孔；
AA’、BB’：剖面线；
9320、9322：晶锡球。
【具体实施方式】
为了使本领域普通技术人员更好地理解本发明的技术方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分的实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本发明保护的范围。
请参照图1，其为根据本发明一实施例的具有双面对外接点的半导体芯片组的电路模块示意图。在本实施例中，半导体芯片组10包括一个半导体芯片12，在半导体芯片组10的侧面10A(相当于半导体芯片12的侧面12A)处设置了包括第一电路模块100、第二电路模块110及第三电路模块120的一组芯片电路组，并且在侧面10A/12A 上设置了适于与半导体芯片组10以外的电路进行电性连接的电路接点140，以及在与侧面10A/12A相对的侧面10B(相当于半导体芯片 12的侧面12B)上设置了适于与半导体芯片组10以外的电路进行电性连接的电路接点160。为了使页面简洁，所以并没有把图1的全部组件都进行标号，其中，所有实线圆圈表示的都是设置在侧面10A/12A 上的电路接点140，所有虚线圆圈表示的都是设置在侧面10B/12B上的电路接点160，由各电路模块延伸到电路接点140的实线长条形图案代表设置在侧面10A/12A上且具有电性连接特性的介质，由各电路模块延伸到电路接点160的虚线长条形图案代表设置在侧面10B/12B 上且具有电性连接特性的介质。前述的第一电路模块100、第二电路模块110及第三电路模块120各自连接到电路接点140或160以从半导体芯片组10以外的电路接受输入信号或电源或者将信号输出至半导体芯片组10以外的电路。
芯片电路组中的每一个电路模块可以只连接到电路接点140或 160，或者同时连接到电路接点140与160。各电路模块可以是直接连接到电路接点140或160，也可以如图中所示的经过具有电性连接特性的介质而连接到电路接点140或160。此外，虽然在本实施例中的第一电路模块100、第二电路模块110及第三电路模块120之间并未连接有用于信号交换的电路，但即使这些电路模块之间连接有用于信号交换的电路也不会影响本案技术的施行。
接下来请参照图2，其为图1所示的实施例沿着剖面线AA’所得的剖面图。从图2所示的剖面图可以理解，电路接点140与导电结构130(例如是重分布层(Redistributionlayer，RDL))是设置在侧面10A/12A上，而电路接点160与导电结构150则是设置在侧面10B/12B上。另请参照图3，其为图1所示的实施例沿着剖面线BB’所得的剖面图。从图3所示的剖面图可以理解，电路接点160与导电结构150是设置在侧面10B/12B上，第三电路模块120埋设在半导体芯片12中靠近侧面10A/12A的位置处，而且第三电路模块120经由硅贯孔300及导电结构150而电性连接到电路接点160。在某些实施例中，电路接点160可以设置在硅贯孔300的一端，于是第三电路模块120可以经由硅贯孔300而直接连接到电路接点160。
以上实施例描述的是适用于仅包含一个半导体芯片的半导体芯片组上的技术。但本案技术也可以运用在包含由多个半导体芯片堆栈而成的半导体芯片组上，具体说明如后。
请参照图4，其根据本发明一实施例的具有双面对外接点的半导体芯片组的剖面示意图。在本实施例中，半导体芯片组40包括了堆栈的两个半导体芯片42及44。在半导体芯片42相对的两个侧面上分别设置了电路接点424以及电路接点428，并在适当的位置处设置了导电结构420与422，以及在半导体芯片42中设置了贯穿半导体芯片42的硅贯孔426；在半导体芯片44相对的两个侧面上分别设置了电路接点444及电路接点448，并在适当的位置处设置了导电结构 440及442，以及在半导体芯片44中设置了贯穿半导体芯片44的硅贯孔446。其中，通过导电结构420、硅贯孔426、电路接点428、导电结构440以及硅贯孔446的连接，设置在半导体芯片组40上侧的内部电路(未绘出)可以被电性连接至设置在半导体芯片组40下侧的电路接点448并经过电路接点448而连接到半导体芯片组40以外的外部电路或信号。当然，通过其它的电路结构，内部电路也可以经过电路接点424或444以及对应的导线430与450而连接到半导体芯片组40以外的外部电路或信号。
在本实施例中，电路接点424、444及448可以被用来连接到半导体芯片组40以外的电路接点，例如，电路接点424与444可以分别通过打线接合(Bonding Wire)的方式对外连接，而电路接点448 则可以通过晶锡球(Micro Bump)的结构对外连接，但并不以此为限。于是，半导体芯片组40用于对外连接的电路接点的数量可以比现有技术中的半导体芯片组用于对外连接的电路接点的数量来得更多。另外，如果只需要在半导体芯片组40外围的相对两侧提供电路接点就可以获得足够数量的电路接点，那么就可以不需要制作电路接点444。举例来说，请参照图5，其为根据本发明一实施例的具有双面对外接点的半导体芯片组的剖面示意图，其中半导体芯片组50包括堆栈的两个半导体芯片52及54，而在半导体芯片52与54之间则设置了间隔层56以确保半导体芯片52与54的电路不会产生预期之外的电性连接。在本实施例中，半导体芯片54在相对的两侧分别提供了电路接点540及542，而半导体芯片52则仅在相当于半导体芯片组50外围的侧面上提供了电路接点520，并且利用贯穿半导体芯片组50的硅贯孔580使得设置于芯片52上的电路(未绘出)接点可以连接到电路接点542。
为了在半导体芯片组相对的两侧面都提供电路接点，当半导体芯片组包含了两个以上堆栈在一起的半导体芯片的时候，距离最远的两个半导体芯片必须各在一个侧面提供电路接点。以图4所示的实施例为例，为了使半导体芯片组40外围相对的两个侧面能提供电路接点，必须在半导体芯片42中距离半导体芯片44最远的侧面上设置电路接点424，并且必须在半导体芯片44中距离半导体芯片42最远的侧面上设置电路接点448；类似的，以图5所示的实施例为例，为了使半导体芯片组50外围相对的两个侧面能提供电路接点，必须在半导体芯片52中距离半导体芯片54最远的侧面上设置电路接点520，并且必须在半导体芯片54中距离半导体芯片52最远的侧面上设置电路接点542。
必须说明的是，当半导体芯片组包含了两个以上堆栈在一起的半导体芯片的时候，这些半导体芯片除了利用如图4或图5所示的方式来进行堆栈之外，也可以利用任何合理的方式来进行堆栈，亦即，半导体芯片的堆栈方式可以视实际状况需求来改变，这并不影响本案技术的施行。除此之外，为了减少设计上的复杂度，可以利用具备同样电路接点图案(pattern)的多个半导体芯片来堆栈成所需要的半导体芯片组。请参照图8，其为根据本发明一实施例的具有双面对外接点的半导体芯片组的剖面示意图。在本实施例中，半导体芯片组90 包含了三个具有相同电路接点结构的半导体芯片92、94与96，其中半导体芯片92与94之间以间隔层97予以电性隔离，半导体芯片94 与96之间以间隔层98予以电性隔离。如图所示，半导体芯片92在一个侧面上设置了电路接点922，并在另一个侧面上设置了电路接点926，而在基底920中则采用硅贯孔924以提供将芯片电路组(未绘出)及/或堆栈于其上的半导体芯片与电路接点926电性耦接时的电性通路。类似的，半导体芯片94在相对的两个侧面上设置了电路接点942及946，并以硅贯孔944作为将芯片电路组(未绘出)及/或堆栈于其上的半导体芯片(在此处为半导体芯片92)与电路接点946 电性耦接时的电性通路；半导体芯片96在相对的两个侧面上设置了电路接点962及966，并以硅贯孔964作为将芯片电路组(未绘出) 及/或堆栈于其上的半导体芯片(在此处为半导体芯片94)与电路接点966电性耦接时的电性通路。通过贯穿间隔层97的导电贯孔972 可以将电路接点926电性耦接至硅贯孔944，而通过贯穿间隔层98 的导电贯孔982则可以将电路接点946电性耦接至硅贯孔964，如此即可完成多个半导体芯片之间的电性通路。
进一步的，通过上述堆栈在一起的半导体芯片可以通过硅贯孔而进行彼此的电性连结的技术，还可以获得其它的优点。请参照图6，其为根据本发明一实施例的半导体芯片组中的两个半导体芯片的电路方块图。在本实施例中，半导体芯片72包括了第一控制电路720 以及第一操作电路722，半导体芯片74包括了第二控制电路740以及第二操作电路742。第一控制电路720用以提供信号至第一操作电路722以控制第一操作电路722的操作方式，其中，第一控制电路 720所提供的信号可以包括但不限于偏压电位信号、电力信号、数据信号以及控制信号。类似的，第二控制电路740用以提供信号至第二操作电路742以控制第二操作电路742的操作方式，而且第二控制电路740还经由贯穿芯片72的硅贯孔(如先前实施例中所述者)而与第一操作电路722电性相接。当半导体芯片正常运作的时候，第一控制电路720提供信号至第一操作电路722以控制第一操作电路722的操作方式，第二控制电路740提供信号至第二操作电路742以控制第二操作电路742的操作方式。当堆栈的半导体芯片组进入休眠状态或是动态随机存取内存的自刷新模式的时候，为了节省电力的消耗，可以使一部份半导体芯片上的控制电路停止操作，而由堆栈的半导体芯片组中另一部分半导体芯片上的控制电路来集中控制。假设在半导体芯片组进入休眠状态的时候使第一控制电路720停止运作，此时可以利用第二控制电路740提供的数字信号或偏压电位透过在硅贯孔来同时控制第一操作电路722及第二操作电路742的操作方式。
以实际的例子来看，图6所示的半导体芯片72及74可以是内存芯片，那么第一控制电路720及第二控制电路740可以是内存芯片中的内存细胞自刷新频率及相关讯号产生器或者电压转换器之类的电路，而第一操作电路722及第二操作电路742则可以是内存细胞数组。通过停止全部或部份第一控制电路720的操作，可以进一步降低内存芯片在计算机休眠期间并可包括内存芯片在自刷新模式期间所耗费的电力。
通过使用本案提供的具有双面对外接点的半导体芯片组，整个电子装置的电路安排可以有更大的弹性，例如，请参考图7，其中因为运用了具有双面对外接点的半导体芯片组80，所以半导体芯片组80 可以在其两侧分别与不同的半导体芯片组82及84来进行连接。其中，半导体芯片组80一侧的电路接点直接与半导体芯片组84的电路接点电性相接，而半导体芯片组80另一侧的电路接点则经由半导体芯片组82的外部连接路线(Externalconnection rail)电性连接到半导体芯片组82。除此之外，通过半导体芯片组80两侧的电路接点以及贯穿半导体芯片组80的硅贯孔802，信号可以同时在半导体芯片组80及半导体芯片组84与半导体芯片组82之间进行传递；或者，信号也可以通过导电结构842而得以在半导体芯片组82与半导体芯片组84之间进行传递。
在一个实施例中，半导体芯片组80的具体结构可以采用类似图 4所示的堆栈的两个以上的半导体芯片的结构，而且当半导体芯片组 80使用了类似图4所示的堆栈的两个以上的半导体芯片的结构的时候，半导体芯片组80与半导体芯片组84之间的连结可以是以图4中的电路接点424或444中的一者或者两者一起来完成；或者，除了使用电路接点424或444之外，还可以选择性搭配使用晶锡球(Micro Bump)或者导线430或450来完成半导体芯片组80与半导体芯片组 84之间的连结结构。
当然，多个半导体芯片之间不一定需要做成堆叠的结构。请参照图9，其为本发明一实施例的具有双面对外接点的半导体芯片组的结构示意图。在本实施例中，半导体芯片组包括了三个半导体芯片9000、 9100与9200，其中，半导体芯片9000上设有电路接点9002、9003、 9004、9005、9006与9008，半导体芯片9100上设有电路接点9102、9103、9104、9105与9106，半导体芯片9200上设有电路接点9202、 9203、9204与9205及电路模组9210。在这三个半导体芯片9000、 9100与9200中的任一个电路接点都可以用来与此半导体芯片组之外的电路进行信号或电源的交接，而且这三个半导体芯片9000、9100 与9200之间也可以利用这些接点以及适当的具有电性连接特性的介质而建立电性连接关系。例如，电路接点9002可以利用导线9302而与电路接点9102建立电性连接；电路接点9008经由硅贯孔9010以及晶锡球9320而与电路接点9202建立电性连接(晶锡球9320直接连接到电路接点9202)；电路接点9006利用导线9300而与电路接点 9106建立电性连接，并且还可以进一步经由硅贯孔9110以及晶锡球 9322而与电路接点9204建立电性连接(晶锡球9322直接连接到电路接点9204)；电路接点9003可以利用导线9304而与电路接点9203 建立电性连接；电路接点9105可以利用导线9306而与电路接点9205 建立电性连接。当然，在本实施例中利用导线9300、9302、9304与 9306所建立的电性连接关系也可以利用其它手段来完成。
应注意的是，在半导体芯片9000、9100与9200上都可以设置有一到多个电路模组，而这些电路模组与各电路接点之间有可能存在电性连接的关系。但是为了使图式简单易懂，因此在图9之中仅简单画出了一部份的电路接点及电路模组以作为说明之用，但这并不代表本实施例的半导体芯片组中仅仅包含了在图中绘示出来的这些电路单元以及电性连接关系。
必须说明的是，在上述各实施例中可以但不限于采用打线接合(Bonding Wire)或晶锡球(Micro Bump)直接连接的方式将半导体芯片组的对外接点连接至其它外部电路。
综上所述，通过使用本案提供的具有双面对外接点的半导体芯片组，可以在半导体芯片组的前侧(设置有电路的那一侧)及背侧(与前侧相对的那一侧)都设置电路接点，因此可提供更多的输入/输出接点。此外，由于半导体芯片组的前侧及背侧都存在电路接点，所以在连接不同半导体芯片组时的设计方式也可以更多元化，更有机会减少电子装置所需占用的体积。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的包含范围之内。

Claims (10)

1.一种具有双面对外接点的半导体芯片组，其特征在于，该半导体芯片组外围的相对的一第一侧面与一第二侧面都各自设有电路接点，且该第一侧面或该第二侧面上设置有一芯片电路组，该第一侧面的电路接点与该第二侧面的电路接点用于连接该半导体芯片组以外的电路接点；
其中，该第一侧面的电路接点与该第二侧面的电路接点用于通过打线接合或以锡球连接至该半导体芯片以外的电路接点；
当分别设置在该第一侧面和该第二侧面的两个电路接点连接至该半导体芯片组以外的同一基板上时，该两个电路接点分别连接于该同一基板的两个不同电路接点。
2.如权利要求1所述的半导体芯片组，其特征在于，该芯片电路组设置于该第一侧面，且该芯片电路组连接到该第一侧面的电路接点。
3.如权利要求1所述的半导体芯片组，其特征在于，该芯片电路组设置于该第一侧面，且该芯片电路组经由贯穿该半导体芯片组的一硅贯孔连接到该第二侧面的电路接点。
4.如权利要求1所述的半导体芯片组，其特征在于，该半导体芯片组为一单一半导体芯片，该第一侧面与该第二侧面为该单一半导体芯片相对的两侧面，该芯片电路组设置于该第一侧面，该芯片电路组连接到该第一侧面的电路接点，且该芯片电路组另外经由贯穿该半导体芯片的一硅贯孔连接到该第二侧面的电路接点。
5.如权利要求1所述的半导体芯片组，其特征在于，该半导体芯片组包括堆栈的多个半导体芯片，该多个半导体芯片中有一第一芯片及一第二芯片，该第一芯片的相对两侧面各自设置有电路接点，该第二芯片的相对两侧面各自设置有电路接点，该第一芯片及该第二芯片的电路接点用于连接该半导体芯片以外的电路或电源接点。
6.如权利要求5所述的半导体芯片组，其特征在于，该第一芯片上设置有电性相接的一第一控制电路及一第一操作电路，该第二芯片上设置有电性相接的一第二控制电路及一第二操作电路，该第二控制电路经由贯穿该第一芯片的一硅贯孔而与该第一操作电路电性相接；其中，在该第一控制电路运作时，该第一控制电路控制该第一操作电路的操作方式，而在该第一控制电路关闭时，该第二控制电路同时控制该第一操作电路及该第二操作电路的操作方式。
7.如权利要求1所述的半导体芯片组，其特征在于，该半导体芯片组包括堆栈的多个内存芯片。
8.一种具有正反双面对外接点的半导体芯片，其特征在于，该半导体芯片具有相对的一第一侧面及一第二侧面，该第一侧面适于设置一芯片电路组，该第一侧面及该第二侧面分别设置有至少一对外接点，且该第二侧面的该至少一对外接点中的至少一者通过一硅贯孔连接至该芯片电路组；
其中，该第一侧面的该至少一对外接点中的至少一者与该第二侧面的该至少一对外接点中的至少一者连接至该半导体芯片外的电源或信号；
当分别设置在该第一侧面和该第二侧面的两个对外接点连接至该半导体芯片以外的同一基板上时，该两个对外接点分别连接于该同一基板的不同电路接点。
9.如权利要求8所述的半导体芯片，其特征在于，该第一侧面的该至少一对外接点中的至少一者与该第二侧面的该至少一对外接点中的至少一者，通过打线接合或以锡球连接至该半导体芯片外的电源或信号。
10.如权利要求8所述的半导体芯片，其特征在于，多个该半导体芯片之间部分或是全部的对外接点相互连接以构成一半导体芯片组，而位于该半导体芯片组中之任一该些半导体芯片上的对外接点可同时作为该半导体芯片组的电源或是讯号的对外/对内传导接点。
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