US20050067683A1 - Memory expansion and chip scale stacking system and method - Google Patents

Memory expansion and chip scale stacking system and method Download PDF

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Publication number
US20050067683A1
US20050067683A1 US10/978,149 US97814904A US2005067683A1 US 20050067683 A1 US20050067683 A1 US 20050067683A1 US 97814904 A US97814904 A US 97814904A US 2005067683 A1 US2005067683 A1 US 2005067683A1
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Prior art keywords
plural
integrated circuits
memory
access system
memory access
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Abandoned
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US10/978,149
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Russell Rapport
James Cady
James Wilder
David Roper
James Wehrly
Jeff Buchle
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Entorian Technologies Inc
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Entorian Technologies Inc
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Priority to US10/005,581 priority Critical patent/US6576992B1/en
Priority to US10/453,398 priority patent/US6914324B2/en
Application filed by Entorian Technologies Inc filed Critical Entorian Technologies Inc
Priority to US10/978,149 priority patent/US20050067683A1/en
Publication of US20050067683A1 publication Critical patent/US20050067683A1/en
Application status is Abandoned legal-status Critical

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    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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Abstract

The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access. This favorably changes the impedance characteristics exhibited by a DIMM board populated with stacked modules. In a preferred embodiment, FET multiplexers for example, under logic control select particular data lines associated with particular levels of stacked modules populated upon a DIMM for connection to a controlling chip set in a memory expansion system.

Description

    TECHNICAL FIELD
  • The present invention relates to aggregating integrated circuits and, in particular, to stacking integrated circuits in chip-scale packages and providing such stacked integrated circuits on boards.
  • BACKGROUND OF THE INVENTION
  • A variety of techniques are used to stack packaged integrated circuits. Some methods require special packages, while other techniques stack conventional packages. In some stacks, the leads of the packaged integrated circuits are used to create a stack, while in other systems, added structures such as rails provide all or part of the interconnection between packages. In still other techniques, flexible conductors with certain characteristics are used to selectively interconnect packaged integrated circuits.
  • The predominant package configuration employed during the past decade has encapsulated an integrated circuit (IC) in a plastic surround typically having a rectangular configuration. The enveloped integrated circuit is connected to the application environment through leads emergent from the edge periphery of the plastic encapsulation. Such “leaded packages” have been the constituent elements most commonly employed by techniques for stacking packaged integrated circuits.
  • Leaded packages play an important role in electronics, but efforts to miniaturize electronic components and assemblies have driven development of technologies that preserve circuit board surface area. Because leaded packages have leads emergent from peripheral sides of the package, leaded packages occupy more than a minimal amount of circuit board surface area. Consequently, alternatives to leaded packages known as chip scale packaging or “CSP” have recently gained market share.
  • CSP refers generally to packages that provide connection to an integrated circuit through a set of contacts (often embodied as “bumps” or “balls”) arrayed across a major surface of the package. Instead of leads emergent from a peripheral side of the package, contacts are placed on a major surface and typically emerge from the planar bottom surface of the package.
  • The goal of CSP is to occupy as little area as possible and, preferably, approximately the area of the encapsulated IC. Therefore, CSP leads or contacts do not typically extend beyond the outline perimeter of the package. The absence of “leads” on package sides renders most stacking techniques devised for leaded packages inapplicable for CSP stacking.
  • The previous known methods for stacking CSPs typically present complex structural arrangements and thermal or high frequency performance issues. For example, thermal performance is a characteristic of importance in CSP stacks. To increase dissipation of heat generated by constituent CSPs and the module, the thermal gradient between the lower CSP and upper CSP in a CSP stack or module should be minimized.
  • Memory expansion is one of the many fields in which stacked module solutions provide advantages. For example, the well-known DIMM board is frequently populated with stacked modules from those such as the assignee of the present invention. This adds capacity to the board without adding sockets.
  • A memory expansion board such as a DIMM, for example, provides plural sites for memory IC placement (i.e., sockets) arranged along both major surfaces of a board having an array of contacts dispersed along at least one board edge. Although stacking reduces interconnect length per unit of memory, and thus takes advantage of the general rule that interconnects that are less than half the spatial extent of the leading edge of a signal operate as a lumped element more than a transmission line, it does increase the raw number of devices on a DIMM board. Consequently, despite the reduction in interconnect length per unit of memory, signals accessing data stored in memory circuits physically placed on the DIMM board are typically presented with relatively high impedance as the number of devices on the bus is increased by stacking.
  • What is needed, therefore, is a technique and system for stacking CSPs that provides a thermally efficient, reliable structure that performs well at higher frequencies but does not add excessive height to the stack yet allows production at reasonable cost with readily understood and managed materials and methods and allows significant reductions in interconnect lengths and/or loading when employed in memory expansion boards and design.
  • SUMMARY OF THE INVENTION
  • The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. Although the present invention is applied most frequently to chip scale packages that contain one die, it may be employed with chip scale packages that include more than one integrated circuit die.
  • Multiple numbers of CSPs may be stacked in accordance with the present invention. A four-high CSP stacked module is preferred for use with the disclosed high performance memory access system while, for many applications, a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention is preferred. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or two or more conductive layers with preferred embodiments having two conductive layers.
  • The flex circuitry is partially wrapped above a form standard. A form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard can take many configurations and may be used where flex circuits are used to connect CSPs to one another in stacked modules having two or more constituent ICs. For example, in stacked modules that include four CSPs, three form standards are employed in preferred embodiments, although fewer may be used. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material, a metal for example, such as copper would be preferred, to improve thermal performance.
  • In a preferred embodiment of the present invention, four-high stacked CSP modules are disposed on a memory expansion boards in accordance with the memory expansion system and methods of the present invention which may be employed with CSP or other IC stacked modules. A high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access. This favorably changes the impedance characteristics exhibited by the board loading. The high speed DQ selection switch may be implemented, in a preferred embodiment, for example, with a high speed FET switch. FET multiplexers for example, under logic control select particular data lines associated with particular levels of the DIMM-populated stacked modules for connection to a controlling chip set in a memory expansion system in accordance with a preferred embodiment.
  • SUMMARY OF THE DRAWINGS
  • FIG. 1 is an elevation view of a high-density circuit module devised in accordance with a preferred four-high embodiment of the present invention.
  • FIG. 2 is an elevation view of a stacked high-density circuit module devised in accordance with a preferred two-high embodiment of the present invention.
  • FIG. 3 depicts, in enlarged view, the area marked “A” in FIG. 2.
  • FIG. 4 depicts in enlarged view, the area marked “B” in FIG. 2.
  • FIG. 5 is an enlarged depiction of an exemplar connection in stacked module devised in accordance with a preferred embodiment.
  • FIG. 6 depicts a flexible circuit connective set of flex circuits that has a single conductive layer.
  • FIG. 7 depicts a four-high stacked module mounted on a memory expansion board in accordance with a preferred embodiment of the present invention.
  • FIG. 8 depicts a memory expansion board or DIMM mounted with four-high modules.
  • FIG. 9 depicts a memory system devised in accordance with the present invention.
  • DESCRIPTION OF PREFERRED EMBODIMENTS
  • FIG. 1 is an elevation view of module 10 devised in accordance with a preferred embodiment of the present invention. Module 10 is comprised of four CSPs: level four CSP 12, level three CSP 14, level two CSP 16, and level one CSP 18. Each of the CSPs has an upper surface 20 and a lower surface 22 and opposite lateral edges 24 and 26 and typically include at least one integrated circuit surrounded by a plastic body 27. The body need not be plastic, but a large majority of packages in CSP technologies are plastic. Those of skill will realize that the present invention may be devised to create modules with different size CSPs and that the constituent CSPs may be of different types within the same module 10. For example, one of the constituent CSPs may be a typical CSP having lateral edges 24 and 26 that have an appreciable height to present a “side” while other constituent CSPs of the same module 10 may be devised in packages that have lateral edges 24 and 26 that are more in the character of an edge rather than a side having appreciable height.
  • The invention is used with CSP packages of a variety of types and configurations such as, for example, those that are die-sized, as well those that are near chip-scale as well as the variety of ball grid array packages known in the art. It may also be used with those CSP-like packages that exhibit bare die connectives on one major surface. Thus, the term CSP should be broadly considered in the context of this application. Collectively, these will be known herein as chip scale packaged integrated circuits (CSPs) and preferred embodiments will be described in terms of CSPs, but the particular configurations used in the explanatory figures are not, however, to be construed as limiting. For example, the elevation views of FIGS. 1 and 2 are depicted with CSPs of a particular profile known to those in the art, but it should be understood that the figures are exemplary only. The invention may be employed to advantage in the wide range of CSP configurations available in the art where an array of connective elements is available from at least one major surface. The invention is advantageously employed with CSPs that contain memory circuits, but may be employed to advantage with logic and computing circuits where added capacity without commensurate PWB or other board surface area consumption is desired.
  • Typical CSPs, such as, for example, ball-grid-array (“BGA”), micro-ball-grid array, and fine-pitch ball grid array (“FBGA”) packages have an array of connective contacts embodied, for example, as leads, bumps, solder balls, or balls that extend from lower surface 22 of a plastic casing in any of several patterns and pitches. An external portion of the connective contacts is often finished with a ball of solder. Shown in FIG. 1 are contacts 28 along lower surfaces 22 of the illustrated constituent CSPs 12, 14, 16, and 18. Contacts 28 provide connection to the integrated circuit or circuits within the respective packages. In embodiments of the present invention, module 10 may be devised to present a lower profile by stripping from the respective CSPs, the balls depicted in FIG. 1 as contacts 28 and providing a connection facility at contact 28 that results from solder paste that is applied either to the pad contact of the CSP that is typically present under or within the typical ball contacts provided on CSP devices or to the contact sites on the flex circuitry to be connected to contact 28.
  • In FIG. 1, iterations of flex circuits (“flex”, “flex circuits” or “flexible circuit structures”) 30 and 32 are shown connecting various constituent CSPs. Any flexible or conformable substrate with an internal layer connectivity capability may be used as a flex circuit in the invention. The entire flex circuit may be flexible or, as those of skill in the art will recognize, a PCB structure made flexible in certain areas to allow conformability around CSPs and rigid in other areas for planarity along CSP surfaces may be employed as an alternative flex circuit in the present invention. For example, structures known as rigid-flex may be employed.
  • Form standard 34 is shown disposed adjacent to upper surface 20 of each of the CSPs below level four CSP 12. Form standard 34 may be fixed to upper surface of the respective CSP with an adhesive 36 which preferably is thermally conductive. Form standard 34 may also, in alternative embodiments, merely lay on upper surface 20 or be separated from upper surface 20 by an air gap or medium such as a thermal slug or non-thermal layer. However, where form standard 34 is a thermally conductive material such as the copper that is employed in a preferred embodiment, layers or gaps interposed between form standard 34 and the respective CSP (other than thermally conductive layers such as adhesive) are not highly preferred.
  • Form standard 34 is, in a preferred embodiment, devised from copper to create, as shown in the depicted preferred embodiment of FIG. 1, a mandrel that mitigates thermal accumulation while providing a standard sized form about which flex circuitry is disposed. Form standard 34 may take other shapes and forms such as for example, an angular “cap” that rests upon the respective CSP body. It also need not be thermally enhancing although such attributes are preferable. The form standard 34 allows the invention to be employed with CSPs of varying sizes, while articulating a single set of connective structures useable with the varying sizes of CSPs. Thus, a single set of connective structures such as flex circuits 30 and 32 (or a single flexible circuit in the mode where a single flex is used in place of the flex circuit pair 30 and 32) may be devised and used with the form standard 34 method and/or systems disclosed herein to create stacked modules with CSPs having different sized packages. This will allow the same flexible circuitry set design to be employed to create iterations of a stacked module 10 from constituent CSPs having a first arbitrary dimension X across attribute Y (where Y may be, for example, package width), as well as modules 10 from constituent CSPs having a second arbitrary dimension X prime across that same attribute Y. Thus, CSPs of different sizes may be stacked into modules 10 with the same set of connective structures (i.e. flex circuitry). Further, as those of skill will recognize, mixed sizes of CSPs may be implemented into the same module 10, such as would be useful to implement embodiments of a system-on-a-stack such as those disclosed in co-pending application U.S. patent application Ser. No. 10/136,890, filed May 2, 2002, which is hereby incorporated by reference and commonly owned by the assignee of the present application.
  • Preferably, portions of flex circuits 30 and 32 are fixed to form standard 34 by adhesive 35 which is preferably a tape adhesive, but may be a liquid adhesive or may be placed in discrete locations across the package. Preferably, adhesive 35 is thermally conductive.
  • In a preferred embodiment, flex circuits 30 and 32 are multi-layer flexible circuit structures that have at least two conductive layers examples of which are those described in U.S. application Ser. No. 10/005,581 which has been incorporated by reference herein. Other embodiments may, however, employ flex circuitry, either as one circuit or two flex circuits to connect a pair of CSPs, that have only a single conductive layer.
  • Preferably, the conductive layers are metal such as alloy 110. The use of plural conductive layers provides advantages and the creation of a distributed capacitance across module 10 intended to reduce noise or bounce effects that can, particularly at higher frequencies, degrade signal integrity, as those of skill in the art will recognize. Module 10 of FIG. 1 has plural module contacts 38 collectively identified as module array 40. Connections between flex circuits are shown as being implemented with inter-flex contacts 42 which are shown as balls but may be low profile contacts constructed with pads and/or rings that are connected with solder paste applications to appropriate connections. Appropriate fills such as those indicated by conformal media reference 41 can provide added structural stability and coplanarity where desired. Media 41 is shown only as to CSPs 14 and 16 and only on one side to preserve clarity of view.
  • FIG. 2 shows a two-high module 10 devised in accordance with a preferred embodiment of the invention. FIG. 2 has an area marked “A” that is subsequently shown in enlarged depiction in FIG. 3 and an enlarged area marked “B” that is shown subsequently in enlarged depiction in FIG. 4.
  • FIG. 3 depicts in enlarged view, the area marked “A” in FIG. 2. FIG. 3 illustrates in a preferred embodiment, one arrangement of a form standard 34 and its relation to flex circuitry 32 in a two-high module 10. The internal layer constructions of flex circuitry 32 are not shown in this figure. Also shown are adhesives 35 between flex circuit 32 and form standard 34. Those of skill will note that adhesive 35 is not required but is preferred and the site of its application may be determined as being best in the area between CSPs with a smaller amount near the terminal point of form standard 34 as shown in FIG. 3. Also shown in FIG. 3 is an application of adhesive 36 between form standard 34 and CSP 18.
  • FIG. 4 illustrates the connection between example contact 28 and module contact 38 through a lower flex contact 44 to illustrate a preferred solid metal path from level one CSP 18 to module contact 38 and, therefore, to an application PWB or memory expansion board to which the module is connectable. As those of skill in the art will understand, heat transference from module 10 is thereby encouraged.
  • Flex 30 is shown in FIG. 4 to be comprised of multiple layers. This is merely an exemplar flexible circuitry that may be employed with the present invention. Single conductive layer and other variations on the described flexible circuitry may, as those of skill will recognize, be employed to advantage in the present invention. Flex 30 has a first outer surface 50 and a second outer surface 52. Flex circuit 30 has at least two conductive layers interior to first and second outer surfaces 50 and 52. There may be more than two conductive layers in flex 30 and flex 32. In the depicted preferred embodiment, first conductive layer 54 and second conductive layer 58 are interior to first and second outer surfaces 50 and 52. Intermediate layer 56 lies between first conductive layer 54 and second conductive layer 58. There may be more than one intermediate layer, but one intermediate layer of polyimide is preferred.
  • As depicted in FIG. 4 and seen in more detail in figures found in U.S. application Ser. No. 10/005,581 which has been incorporated by reference, lower flex contact 44 is preferably comprised from metal at the level of second conductive layer 58 interior to second outer surface 52.
  • FIG. 5 is an enlarged depiction of an exemplar area around a lower flex contact 44 in a preferred embodiment. Windows 60 and 62 are opened in first and second outer surface layers 50 and 52 respectively, to provide access to particular lower flex contacts 44 residing at the level of second conductive layer 58 in the flex. In a two-high embodiment of module 10, the upper flex contacts 42 are contacted by contacts 28 of second level CSP 16. Lower flex contacts 44 and upper flex contacts 42 are particular areas of conductive material (preferably metal such as alloy 110) at the level of second conductive layer 58 in the flex. Upper flex contacts 42 and lower flex contacts 44 are demarked in second conductive layer 58 and, as will be shown in subsequent Figs., may be connected to or isolated from the conductive plane of second conductive layer 58. Demarking a lower flex contact 44 from second conductive layer 58 is represented in FIG. 5 by demarcation gap 63 shown at second conductive layer 58. Where an upper or lower flex contact 42 or 44 is not completely isolated from second conductive layer 58, demarcation gaps do not extend completely around the flex contact. Contacts 28 of first level CSP 18 pass through a window 60 opened through first outer surface layer 50, first conductive layer 54, and intermediate layer 56, to contact an appropriate lower flex contact 44. Window 62 is opened through second outer surface layer 52 through which module contacts 36 pass to contact the appropriate lower flex contact 44.
  • Respective ones of contacts 28 of second level CSP 16 and first level CSP 18 are connected at the second conductive layer 58 level in flex circuits 30 and 32 to interconnect appropriate signal and voltage contacts of the two CSPs. In a preferred embodiment, respective contacts 28 of second level CSP 16 and first level CSP 18 that convey ground (VSS) signals are connected at the first conductive layer 54 level in flex circuits 30 and 32 by vias that pass through intermediate layer 56 to connect the levels as will subsequently be described in further detail. Thereby, CSPs 16 and 18 are connected. Consequently, when flex circuits 30 and 32 are in place about first level CSP 18, respective contacts 28 of each of CSPs 16 and 18 are in contact with upper and lower flex contacts 42 and 44, respectively. Selected ones of upper flex contacts 42 and lower flex contacts 44 are connected. Consequently, by being in contact with lower flex contacts 44, module contacts 38 are in contact with both CSPs 16 and 18.
  • In a preferred embodiment, module contacts 38 pass through windows 62 opened in second outer layer 52 to contact lower CSP contacts 44. In some embodiments, as is shown in incorporated U.S. application Ser. No. 10/005,581, module 10 will exhibit a module contact array that has a greater number of contacts than do the constituent CSPs of module 10. In such embodiments, some of module contacts 38 may contact lower flex contacts 44 that do not contact one of the contacts 28 of first level CSP 18 but are connected to contacts 28 of second level CSP 16. This allows module 10 to express a wider datapath than that expressed by the constituent CSPs 16 or 18. A module contact 38 may also be in contact with a lower flex contact 44 to provide a location through which different levels of CSPs in the module may be enabled when no unused CSP contacts are available or convenient for that purpose.
  • In a preferred embodiment, first conductive layer 54 is employed as a ground plane, while second conductive layer 58 provides the functions of being a signal conduction layer and a voltage conduction layer. Those of skill will note that roles of the first and second conductive layers may be reversed with attendant changes in windowing and use of commensurate interconnections.
  • FIG. 6 depicts a flexible circuit connective set of flex circuits 30 and 32 that has a single conductive layer 64. It should be understood with reference to FIG. 6 that flex circuits 30 and 32 extend further than shown and have portions which are, in the construction of module 10 brought about the curvature areas 66 of form standard 34 that mark the lateral extent of this example of a preferred form standard and are then disposed above the body of CSP 18 or the respective CSP of the module and therefore, the form standard. In this single conductive layer flex embodiment of module 10, there are shown first and second outer layers 50 and 52 and intermediate layer 56. Also shown in FIG. 6 are a set of single layer lower flex contacts 68 demarked at the level of conductive layer 64.
  • Form standard 34 is shown attached to the body 27 of first level CSP 18 through an adhesive. In some embodiments, it may also be positioned to directly contact body 27 of the respective CSP. Form standard 34 may take many different configurations to allow a connective flex circuitry to be prepared exhibiting a single set of dimensions which may, when used in conjunction with form standard 34, be employed to create stacked modules 10 from CSPs of a variety of different dimensions. In a preferred embodiment, form standard 34 will present a lateral extent broader than the upper major surface of the CSP over which it is disposed. Thus, the CSPs from one manufacturer may be aggregated into a stacked module 10 with the same flex circuitry used to aggregate CSPs from another manufacturer into a different stacked module 10 despite the CSPs from the two different manufacturers having different dimensions.
  • Further, heat transference can be improved with use of a form standard 34 comprised of heat transference material such as a metal or preferably, copper or a copper compound or alloy to provide a significant sink for thermal energy. Such thermal enhancement of module 10 particularly presents opportunities for improvement of thermal performance where larger numbers of CSPs are aggregated in a single stacked module 10.
  • FIG. 7 depicts a four-high stacked module 10 mounted on a memory expansion board 70 in accordance with a preferred embodiment of the present invention. As do typical DIMM boards, expansion board 70 shown in FIG. 7 has a set of contacts along one edge that as depicted are set in socket connector 72. Those contacts connect module 10 to a logic system on or connected to board 74 on which expansion board 70 is mounted. It should be understood that in a preferred embodiment of the memory expansion system and method provided herein, expansion board 70 will be populated with nine such modules 10 per side for a total of 72 devices if the stacked modules are each comprised from four devices.
  • FIG. 8 depicts memory expansion board 70 mounted with four-high modules 10. As those of skill will recognize, using four-high stacked modules on expansion board 70 reduces the interconnect length for the number of devices accessed but increase the total number of devices and, therefore, the impedance and particularly, the capacitive loading presented by a densely populated DIMM board.
  • FIG. 9 depicts a memory system 80 devised in accordance with the present invention. In a preferred mode, system 80 is employed with stacked modules 10 devised in accordance with the present invention. The preferred embodiment is for a DDRII registered DIMM populated with 4 high stacked modules 10 although it may be employed with an equivalent number of DRAMs, i.e., 72 devices of either leaded or CSP packaging aggregated in stacks of any number of levels.
  • Chipset 82 depicted in FIG. 9 typically includes a microprocessor or memory controller that controls the memory access with system 80. Clock 84 is provided to decode logic 86 on each of depicted memory expansion boards 70 (1), 70 (2), 70 (3), and 70 (4). Those of skill will understand that system 80 and its methods may be employed with one or more DIMMs or other memory expansion boards 70. It may also be employed off a memory expansion board to access separately, the integrated circuits from which stacked circuit modules are comprised. Decode logic 86 on each of memory expansion boards 70 (1), 70 (2), 70 (3), and 70 (4) provides a decoding of the respective CS signals provided to the respective memory expansion boards 70 as shown in FIG. 9. As those of skill will understand, the particular interconnection employed in the system should preferably be devised to minimize and balance power consumption across the circuit modules employed in the system.
  • As shown in the example depicted in FIG. 9, CS0, CS1, CS2, and CS3 are provided to memory expansion board 70 (1) from chipset 82 while CS4, CS5, CS6, and CS7 are provided to memory expansion board 70 (2) as are CS8, CS9, CS10, and CS11 provided to memory expansion board 70 (3) and CS12, CS13, CS14, and CS15 are provided to memory expansion board 70 (4).
  • In a preferred embodiment, memory expansion boards 70 are populated with nine four high CSP modules 10 per side. The depiction of FIG. 9 shows, however, only one module 10 per memory expansion board 70 to preserve clarity of the view. The shown module 10 is exploded to depict the four levels of module 10 which, in a preferred construction of module 10 include CSPs 18, 16, 14, and 12 with the form standard 34. However, those of skill will recognize that modules employed with system 80 need not have four levels and need not be CSP devices although that is preferred.
  • Thus, decode logic 86 may, on the appropriate signal from clock 84, generate a level select signal which, in a preferred embodiment, is a multi-bit signal that controls a multiplexing switch 90 associated with several data lines. Switch 90 is in a preferred embodiment, a high speed switch and a FET muliplexer would provide a preferred multiplexing switch 90 in the practice of a preferred mode of the invention. The fan out of multiplexing switch 90 may be any that provides a selection capability to a variety of device data lines from a DQ line from chipset 82. The DQ lines between chipset 82 and switches 90 are depicted by double-headed arrows 94(1), 94(2), 94(3) and 94(4). As with the depiction of stacked modules 10, only one multiplexing switch 90 is shown per memory expansion board 70, but those of skill will understand that multiple multiplexing switches 90 are employed in practice of the depicted preferred embodiment of the invention. The number of multiplexing switches 90 will depend upon the fan out ratios. For example, use of nine 8:32 multiplexing switches 90 would be preferred (if available) or 4:8 or 1:4 multiplexing switches 90 will also provide advantages as an example. It should be understood that there are merely examples and that a variety of multiplexing switches and ratios may be employed for multiplexing switches 90 although the type of switch and the ratios will affect the loading figures. Consequently, a FET mux is preferred for multiplexing switch 90 and a ratio of 1:4 is one of the preferred ratios to employ.
  • The depiction in FIG. 9 is illustrative only and not meant to be limiting. For example, a single DIMM board or expansion board 70 may be employed in a system 80 in accordance with the present invention as well as larger numbers of expansion boards 70. The number of expansion boards 70 that may function in system 80 is partially a function of the access speeds required and the signal conformity.
  • An exemplar multiplexing switch 90 has multiple inputs 92(a), 92(b), 92(c), and 92(d) to provide independent data lines for each level of an exemplar module 10 populated upon the respective memory expansion board 70. Thus, with a 1:4 switch 90, there will be 18 iterations of multiplexing switch 90, one for each of the 18 four-high module 10's populating memory expansion board 70(1). Thus, the system 80 shown in FIG. 9 presents a total of 288 memory devices. It should be noted that system 80 may be employed with ICs of any package type and need not be limited to DDR or DDRII or even CSP.
  • The data line of each level of the constituent CSPs of each module 10 is connected to one input 92 of a corresponding exemplar multiplexing switch 90. In response to the CS signal 88 from decode logic 86 on a DIMM expansion board 70, multiplexing switch 90 connects the appropriate one of the DQ signals 94 to one of the four levels of a module 10 on that memory expansion board 70. This switching of the data bus through multiplexing switch 90 may, in some systems, required further control signal connections as those of skill in the art will recognize to accomodate the data latency of one or more clocks cycles, CAS latency, and burst length, for example. In a preferred mode, expansion board 70 may keep all the constituent devices of the modules 10 as if each constituent device of the modules 10 were the target, instead of having to switch terminations each time a different CS is chosen. In some applications it may be preferred to terminate the end of the data line past the last DIMM expansion board 70. Other features may enable improvements to the efficiency of system 80 such as creating more CS banks by decoding the chip select lines.
  • In the system 80, the capacitive load presented to chipset 82 would be approximately the combination of the input capacitance of switching multiplexer 90 times the number of DIMM slots plus one DRAM device load plus one times the output capacitance of the multiplexing switch 90. In large systems, this will reduce capacitive loading by a notable amount, thus allowing more DIMM slots at higher speeds and/or more densely populated DIMMs. Memory access system 80 provides an opportunity to improve high speed memory performance and allows use of memory expansion configurations that might not otherwise be available due to capacitive loading in conventional DIMM systems.
  • Although the present invention has been described in detail, it will be apparent to those skilled in the art that the invention may be embodied in a variety of specific forms and that various changes, substitutions and alterations can be made without departing from the spirit and scope of the invention. The described embodiments are only illustrative and not restrictive and the scope of the invention is, therefore, indicated by the following claims.

Claims (25)

1. A memory access system comprising:
a memory expansion board;
a high-density circuit module comprised of first and second integrated circuits, the high-density circuit module being mounted on the memory expansion board;
a switching multiplexer mounted on the memory expansion board, the switching multiplexer for switching data lines between the first and second integrated circuits; and
a decode logic circuit for decoding chip selection signals from a control circuit and providing a switching multiplexer control signal.
2. A memory access system comprising:
a high-density circuit module comprised of plural integrated circuits;
a switch for connecting a datapath to one of the plural integrated circuits of the high-density circuit module;
a decode logic for generating a control signal that causes the switch to connect the datapath to one of the plural integrated circuits in response to a combination signal comprised of a clock signal and a chip select signal.
3. The memory access system of claim 2 in which the plural integrated circuits of the high-density circuit module number four.
4. The memory access system of claim 2 in which the plural integrated circuit of the high-density circuit module number two.
5. A memory access system comprising:
plural memory expansion boards each populated with plural high-density circuit modules, each of which plural high-density circuit modules being comprised of plural integrated circuits;
plural multiplexers mounted upon each of the plural memory expansion boards, the plural multiplexers for making connections between a datapath and single ones of the plural integrated circuits comprising the high-density circuit modules;
decode logic on each of the plural memory expansion boards, the decode logic for generating a control signal in response to a combination signal comprised of a clock signal and a chip select signal, the control signal causing at least one of the plural multiplexers to connect a particular datapath to a particular one of the plural integrated circuits.
6. The memory access system of claim 5 in which the multiplexers are FET multiplexers.
7. The memory access system of claim 5 in which the plural high-density circuit modules are comprised of four integrated circuits.
8. The memory access system of claim 5 in which the plural high-density circuit modules are comprised from two integrated circuits.
9. The memory access system of claim 7 in which the four integrated circuits are CSPs.
10. The memory access system of claim 8 in which the two integrated circuits are CSPs.
11. A memory access system comprising:
a memory board having a board memory signal data connection that provides a connection for memory signals between a plurality of integrated circuits mounted on the memory board and memory control circuitry;
a high-density circuit module comprised of first, second, third, and fourth individual integrated circuits, the high-density circuit module being mounted on the memory board;
a switching multiplexer mounted on the memory board, the switching multiplexer having a set of plural input data connections, individual ones of the plural input data connections connected to provide individual data connections between each of the first, second, third, and fourth individual integrated circuits and the switching multiplexer; and
a decode logic circuit for decoding chip selection signals from a control circuit and providing a switching multiplexer control signal.
12. The memory access system of claim 11 in which the switching multiplexer further comprises an output data connection connected to the board signal memory data connection.
13. The memory access system of claim 12 in which the switching multiplexer provides selective individual connection between the board signal memory data connection and the first, second, third, and fourth individual integrated circuits.
14. The memory access system of claim 13 in which the individual connection between the board signal memory data connection and the first, second, third, and fourth individual integrated circuits occurs in response to the switching multiplexer control signal from the decode logic circuit.
15. The memory access system of claim 11 in which the decode logic circuit is mounted on the memory board.
16. A memory access system comprising:
a high-density circuit module comprised of stacked plural individual integrated circuits;
a switch for individually connecting a datapath to one of the plural individual integrated circuits of the high-density circuit module at a time; and
a decode logic for generating a control signal that causes the switch to connect the datapath to one of the plural individual integrated circuits at a time.
17. The memory access system of claim 16 in which the control signal is generated from a clock signal and a chip select signal.
18. The memory access system of claim 16 in which the stacked plural integrated circuits of the high-density circuit module number four.
19. The memory access system of claim 16 in which the stacked plural integrated circuit of the high-density circuit module number two.
20. A memory access system comprising:
X memory expansion boards each populated with Y high-density circuit modules, each of which Y high-density circuit modules being comprised of Z individual integrated circuits;
plural multiplexers mounted upon each of the X memory expansion boards, the plural multiplexers each for selectively making connections between a datapath and single ones of the Z integrated circuits comprising each of the Y high-density circuit modules;
decode logic on each of the plural memory expansion boards, the decode logic for generating a control signal in response to a combination signal comprised of a clock signal and a chip select signal, the control signal causing at least one of the plural multiplexers to connect a particular datapath to a particular one of the Z integrated circuits.
21. The memory access system of claim 20 in which the multiplexers are FET multiplexers.
22. The memory access system of claim 20 in which Z equals 4.
23. The memory access system of claim 20 in which Z equals 2.
24. The memory access system of claim 22 in which the four integrated circuits are CSPs.
25. The memory access system of claim 23 in which the two integrated circuits are CSPs.
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Families Citing this family (107)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5484959A (en) * 1992-12-11 1996-01-16 Staktek Corporation High density lead-on-package fabrication method and apparatus
US5915167A (en) * 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory
US6551857B2 (en) * 1997-04-04 2003-04-22 Elm Technology Corporation Three dimensional structure integrated circuits
JP2004524973A (en) * 2001-02-28 2004-08-19 デイトン・システムズ・グループ・インコーポレーテッド Dome molding system
US6956284B2 (en) * 2001-10-26 2005-10-18 Staktek Group L.P. Integrated circuit stacking system and method
US7053478B2 (en) * 2001-10-26 2006-05-30 Staktek Group L.P. Pitch change and chip scale stacking system
US20030234443A1 (en) * 2001-10-26 2003-12-25 Staktek Group, L.P. Low profile stacking system and method
US7371609B2 (en) * 2001-10-26 2008-05-13 Staktek Group L.P. Stacked module systems and methods
US20060255446A1 (en) 2001-10-26 2006-11-16 Staktek Group, L.P. Stacked modules and method
US6576992B1 (en) * 2001-10-26 2003-06-10 Staktek Group L.P. Chip scale stacking system and method
US6940729B2 (en) * 2001-10-26 2005-09-06 Staktek Group L.P. Integrated circuit stacking system and method
US7026708B2 (en) * 2001-10-26 2006-04-11 Staktek Group L.P. Low profile chip scale stacking system and method
US7202555B2 (en) * 2001-10-26 2007-04-10 Staktek Group L.P. Pitch change and chip scale stacking system and method
US7656678B2 (en) 2001-10-26 2010-02-02 Entorian Technologies, Lp Stacked module systems
US20050009234A1 (en) * 2001-10-26 2005-01-13 Staktek Group, L.P. Stacked module systems and methods for CSP packages
US6914324B2 (en) * 2001-10-26 2005-07-05 Staktek Group L.P. Memory expansion and chip scale stacking system and method
US20040195666A1 (en) * 2001-10-26 2004-10-07 Julian Partridge Stacked module systems and methods
US7485951B2 (en) * 2001-10-26 2009-02-03 Entorian Technologies, Lp Modularized die stacking system and method
US20040245615A1 (en) * 2003-06-03 2004-12-09 Staktek Group, L.P. Point to point memory expansion system and method
US7081373B2 (en) * 2001-12-14 2006-07-25 Staktek Group, L.P. CSP chip stack with flex circuit
US6639309B2 (en) 2002-03-28 2003-10-28 Sandisk Corporation Memory package with a controller on one side of a printed circuit board and memory on another side of the circuit board
US20050021470A1 (en) * 2002-06-25 2005-01-27 Bose Corporation Intelligent music track selection
US20030236582A1 (en) * 2002-06-25 2003-12-25 Lee Zamir Selection of items based on user reactions
WO2004015764A2 (en) * 2002-08-08 2004-02-19 Leedy Glenn J Vertical system integration
US7542304B2 (en) * 2003-09-15 2009-06-02 Entorian Technologies, Lp Memory expansion and integrated circuit stacking system and method
US20050056921A1 (en) * 2003-09-15 2005-03-17 Staktek Group L.P. Stacked module systems and methods
US7612443B1 (en) * 2003-09-04 2009-11-03 University Of Notre Dame Du Lac Inter-chip communication
US20050150813A1 (en) * 2003-10-29 2005-07-14 Tessera, Inc. Foldover packages and manufacturing and test methods therefor
JP2005150154A (en) * 2003-11-11 2005-06-09 Sharp Corp Semiconductor module and its mounting method
US8250295B2 (en) 2004-01-05 2012-08-21 Smart Modular Technologies, Inc. Multi-rank memory module that emulates a memory module having a different number of ranks
US8111132B2 (en) * 2004-01-06 2012-02-07 Bose Corporation Remote controlling
US7111080B2 (en) * 2004-03-01 2006-09-19 Cisco Technology, Inc. Distributing an electronic signal in a stackable device
US7916574B1 (en) 2004-03-05 2011-03-29 Netlist, Inc. Circuit providing load isolation and memory domain translation for memory module
US7289386B2 (en) 2004-03-05 2007-10-30 Netlist, Inc. Memory module decoder
US7532537B2 (en) * 2004-03-05 2009-05-12 Netlist, Inc. Memory module with a circuit providing load isolation and memory domain translation
EP2675022B1 (en) * 2004-07-13 2014-09-03 Panduit Corporation Communications connector with flexible printed circuit board
CN100587951C (en) * 2004-07-19 2010-02-03 Nxp股份有限公司 Electronic device comprising integrated circuit and capacitance element
US20060033187A1 (en) * 2004-08-12 2006-02-16 Staktek Group, L.P. Rugged CSP module system and method
US7602618B2 (en) * 2004-08-25 2009-10-13 Micron Technology, Inc. Methods and apparatuses for transferring heat from stacked microfeature devices
US20060043558A1 (en) * 2004-09-01 2006-03-02 Staktek Group L.P. Stacked integrated circuit cascade signaling system and method
US7606040B2 (en) * 2004-09-03 2009-10-20 Entorian Technologies, Lp Memory module system and method
US7760513B2 (en) 2004-09-03 2010-07-20 Entorian Technologies Lp Modified core for circuit module system and method
US7446410B2 (en) * 2004-09-03 2008-11-04 Entorian Technologies, Lp Circuit module with thermal casing systems
US7606049B2 (en) * 2004-09-03 2009-10-20 Entorian Technologies, Lp Module thermal management system and method
US7468893B2 (en) * 2004-09-03 2008-12-23 Entorian Technologies, Lp Thin module system and method
US20060053345A1 (en) * 2004-09-03 2006-03-09 Staktek Group L.P. Thin module system and method
US7579687B2 (en) * 2004-09-03 2009-08-25 Entorian Technologies, Lp Circuit module turbulence enhancement systems and methods
US7542297B2 (en) * 2004-09-03 2009-06-02 Entorian Technologies, Lp Optimized mounting area circuit module system and method
US20060050492A1 (en) * 2004-09-03 2006-03-09 Staktek Group, L.P. Thin module system and method
US7606050B2 (en) * 2004-09-03 2009-10-20 Entorian Technologies, Lp Compact module system and method
US7324352B2 (en) * 2004-09-03 2008-01-29 Staktek Group L.P. High capacity thin module system and method
US7443023B2 (en) * 2004-09-03 2008-10-28 Entorian Technologies, Lp High capacity thin module system
US20060049513A1 (en) * 2004-09-03 2006-03-09 Staktek Group L.P. Thin module system and method with thermal management
US7423885B2 (en) 2004-09-03 2008-09-09 Entorian Technologies, Lp Die module system
US20060055024A1 (en) * 2004-09-14 2006-03-16 Staktek Group, L.P. Adapted leaded integrated circuit module
US20060072297A1 (en) * 2004-10-01 2006-04-06 Staktek Group L.P. Circuit Module Access System and Method
WO2006088270A1 (en) * 2005-02-15 2006-08-24 Unisemicon Co., Ltd. Stacked package and method of fabricating the same
US20060118936A1 (en) * 2004-12-03 2006-06-08 Staktek Group L.P. Circuit module component mounting system and method
US7172454B2 (en) * 2004-12-30 2007-02-06 Nokia Corporation Electronic component assembly
US7249955B2 (en) * 2004-12-30 2007-07-31 Intel Corporation Connection of package, board, and flex cable
US7309914B2 (en) * 2005-01-20 2007-12-18 Staktek Group L.P. Inverted CSP stacking system and method
US20060175693A1 (en) * 2005-02-04 2006-08-10 Staktek Group, L.P. Systems, methods, and apparatus for generating ball-out matrix configuration output for a flex circuit
US20060244114A1 (en) * 2005-04-28 2006-11-02 Staktek Group L.P. Systems, methods, and apparatus for connecting a set of contacts on an integrated circuit to a flex circuit via a contact beam
US20060250780A1 (en) * 2005-05-06 2006-11-09 Staktek Group L.P. System component interposer
US20060255459A1 (en) * 2005-05-11 2006-11-16 Simon Muff Stacked semiconductor memory device
US20060261449A1 (en) * 2005-05-18 2006-11-23 Staktek Group L.P. Memory module system and method
US20060277355A1 (en) * 2005-06-01 2006-12-07 Mark Ellsberry Capacity-expanding memory device
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US8359187B2 (en) * 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US7609567B2 (en) * 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
KR101303518B1 (en) 2005-09-02 2013-09-03 구글 인코포레이티드 Methods and apparatus of stacking drams
US7492325B1 (en) 2005-10-03 2009-02-17 Ball Aerospace & Technologies Corp. Modular electronic architecture
JP4799157B2 (en) 2005-12-06 2011-10-26 エルピーダメモリ株式会社 Stacked semiconductor device
US7511969B2 (en) * 2006-02-02 2009-03-31 Entorian Technologies, Lp Composite core circuit module system and method
EP2458505B1 (en) * 2006-02-09 2014-10-08 Google, Inc. Memory circuit system and method
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US7289327B2 (en) * 2006-02-27 2007-10-30 Stakick Group L.P. Active cooling methods and apparatus for modules
US7265719B1 (en) 2006-05-11 2007-09-04 Ball Aerospace & Technologies Corp. Packaging technique for antenna systems
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US7888185B2 (en) * 2006-08-17 2011-02-15 Micron Technology, Inc. Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device
TWI378747B (en) * 2006-08-18 2012-12-01 Ind Tech Res Inst Flexible electronic assembly
US20110090413A1 (en) * 2006-08-18 2011-04-21 Industrial Technology Research Institute 3-dimensional image display
US7425758B2 (en) * 2006-08-28 2008-09-16 Micron Technology, Inc. Metal core foldover package structures
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US7417310B2 (en) 2006-11-02 2008-08-26 Entorian Technologies, Lp Circuit module having force resistant construction
US7629538B2 (en) * 2006-11-10 2009-12-08 The Boeing Company Stripline flex circuit
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US7344410B1 (en) 2006-12-19 2008-03-18 International Business Machines Corporation Blade server expansion
KR100829614B1 (en) * 2006-12-29 2008-05-14 삼성전자주식회사 Stacked semiconductor package and method of manufacturing the same
US20080235440A1 (en) * 2007-03-22 2008-09-25 Le Trung V Memory device
US20090013260A1 (en) * 2007-07-06 2009-01-08 Martin Keith D Intelligent music track selection in a networked environment
JP4588060B2 (en) * 2007-09-19 2010-11-24 スパンション エルエルシー Semiconductor device and manufacturing method thereof
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
WO2010144624A1 (en) 2009-06-09 2010-12-16 Google Inc. Programming of dimm termination resistance values
US8417870B2 (en) * 2009-07-16 2013-04-09 Netlist, Inc. System and method of increasing addressable memory space on a memory board
US8516185B2 (en) 2009-07-16 2013-08-20 Netlist, Inc. System and method utilizing distributed byte-wise buffers on a memory module
US8688887B2 (en) * 2009-12-22 2014-04-01 International Business Machines Corporation Computer peripheral expansion apparatus
WO2011161857A1 (en) * 2010-06-22 2011-12-29 パナソニック株式会社 Display device
KR101796116B1 (en) 2010-10-20 2017-11-10 삼성전자 주식회사 Semiconductor device, memory module and memory system having the same and operating method thereof
CN102157401B (en) * 2011-01-30 2013-05-15 南通富士通微电子股份有限公司 High-density SIP (system in package) method of chip
US9324583B2 (en) 2011-01-30 2016-04-26 Nantong Fujitsu Microelectronics Co., Ltd. Packaging method
US20140094070A1 (en) * 2012-03-23 2014-04-03 Winchester Electronics Corporation Electrical socket assembly and method of manufacturing same
US9620473B1 (en) 2013-01-18 2017-04-11 University Of Notre Dame Du Lac Quilt packaging system with interdigitated interconnecting nodules for inter-chip alignment
US9820376B2 (en) * 2013-05-28 2017-11-14 Tatsuta Electric Wire & Cable Co., Ltd. Shape-retaining film, and shape-retaining-type flexible circuit board provided with same shape-retaining film

Citations (95)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3436604A (en) * 1966-04-25 1969-04-01 Texas Instruments Inc Complex integrated circuit array and method for fabricating same
US3654394A (en) * 1969-07-08 1972-04-04 Gordon Eng Co Field effect transistor switch, particularly for multiplexing
US3727064A (en) * 1971-03-17 1973-04-10 Monsanto Co Opto-isolator devices and method for the fabrication thereof
US4079511A (en) * 1976-07-30 1978-03-21 Amp Incorporated Method for packaging hermetically sealed integrated circuit chips on lead frames
US4437235A (en) * 1980-12-29 1984-03-20 Honeywell Information Systems Inc. Integrated circuit package
US4513368A (en) * 1981-05-22 1985-04-23 Data General Corporation Digital data processing system having object-based logical memory addressing and self-structuring modular memory
US4587596A (en) * 1984-04-09 1986-05-06 Amp Incorporated High density mother/daughter circuit board connector
US4645944A (en) * 1983-09-05 1987-02-24 Matsushita Electric Industrial Co., Ltd. MOS register for selecting among various data inputs
US4722691A (en) * 1986-02-03 1988-02-02 General Motors Corporation Header assembly for a printed circuit board
US4733461A (en) * 1984-12-28 1988-03-29 Micro Co., Ltd. Method of stacking printed circuit boards
US4821007A (en) * 1987-02-06 1989-04-11 Tektronix, Inc. Strip line circuit component and method of manufacture
US4823234A (en) * 1985-08-16 1989-04-18 Dai-Ichi Seiko Co., Ltd. Semiconductor device and its manufacture
US4833568A (en) * 1988-01-29 1989-05-23 Berhold G Mark Three-dimensional circuit component assembly and method corresponding thereto
US4891789A (en) * 1988-03-03 1990-01-02 Bull Hn Information Systems, Inc. Surface mounted multilayer memory printed circuit board
US4911643A (en) * 1988-10-11 1990-03-27 Beta Phase, Inc. High density and high signal integrity connector
US4983533A (en) * 1987-10-28 1991-01-08 Irvine Sensors Corporation High-density electronic modules - process and product
US4985703A (en) * 1988-02-03 1991-01-15 Nec Corporation Analog multiplexer
US5012323A (en) * 1989-11-20 1991-04-30 Micron Technology, Inc. Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe
US5016138A (en) * 1987-10-27 1991-05-14 Woodman John K Three dimensional integrated circuit package
US5081067A (en) * 1989-02-10 1992-01-14 Fujitsu Limited Ceramic package type semiconductor device and method of assembling the same
US5099393A (en) * 1991-03-25 1992-03-24 International Business Machines Corporation Electronic package for high density applications
US5104820A (en) * 1989-07-07 1992-04-14 Irvine Sensors Corporation Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting
US5117282A (en) * 1990-10-29 1992-05-26 Harris Corporation Stacked configuration for integrated circuit devices
US5198888A (en) * 1987-12-28 1993-03-30 Hitachi, Ltd. Semiconductor stacked device
US5198965A (en) * 1991-12-18 1993-03-30 International Business Machines Corporation Free form packaging of specific functions within a computer system
US5214307A (en) * 1991-07-08 1993-05-25 Micron Technology, Inc. Lead frame for semiconductor devices having improved adhesive bond line control
US5276418A (en) * 1988-11-16 1994-01-04 Motorola, Inc. Flexible substrate electronic assembly
US5279029A (en) * 1990-08-01 1994-01-18 Staktek Corporation Ultra high density integrated circuit packages method
US5281852A (en) * 1991-12-10 1994-01-25 Normington Peter J C Semiconductor device including stacked die
US5289062A (en) * 1991-03-18 1994-02-22 Quality Semiconductor, Inc. Fast transmission gate switch
US5311401A (en) * 1991-07-09 1994-05-10 Hughes Aircraft Company Stacked chip assembly and manufacturing method therefor
US5313097A (en) * 1992-11-16 1994-05-17 International Business Machines, Corp. High density memory module
US5386341A (en) * 1993-11-01 1995-01-31 Motorola, Inc. Flexible substrate folded in a U-shape with a rigidizer plate located in the notch of the U-shape
US5394010A (en) * 1991-03-13 1995-02-28 Kabushiki Kaisha Toshiba Semiconductor assembly having laminated semiconductor devices
US5394303A (en) * 1992-09-11 1995-02-28 Kabushiki Kaisha Toshiba Semiconductor device
US5397916A (en) * 1991-12-10 1995-03-14 Normington; Peter J. C. Semiconductor device including stacked die
US5402006A (en) * 1992-11-10 1995-03-28 Texas Instruments Incorporated Semiconductor device with enhanced adhesion between heat spreader and leads and plastic mold compound
US5484959A (en) * 1992-12-11 1996-01-16 Staktek Corporation High density lead-on-package fabrication method and apparatus
US5493476A (en) * 1994-03-07 1996-02-20 Staktek Corporation Bus communication system for stacked high density integrated circuit packages with bifurcated distal lead ends
US5499160A (en) * 1990-08-01 1996-03-12 Staktek Corporation High density integrated circuit module with snap-on rail assemblies
US5502333A (en) * 1994-03-30 1996-03-26 International Business Machines Corporation Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit
US5514907A (en) * 1995-03-21 1996-05-07 Simple Technology Incorporated Apparatus for stacking semiconductor chips
US5592364A (en) * 1995-01-24 1997-01-07 Staktek Corporation High density integrated circuit module with complex electrical interconnect rails
US5594275A (en) * 1993-11-18 1997-01-14 Samsung Electronics Co., Ltd. J-leaded semiconductor package having a plurality of stacked ball grid array packages
US5612570A (en) * 1995-04-13 1997-03-18 Dense-Pac Microsystems, Inc. Chip stack and method of making same
US5729894A (en) * 1992-07-21 1998-03-24 Lsi Logic Corporation Method of assembling ball bump grid array semiconductor packages
US5744827A (en) * 1995-11-28 1998-04-28 Samsung Electronics Co., Ltd. Three dimensional stack package device having exposed coupling lead portions and vertical interconnection elements
US5751553A (en) * 1992-09-16 1998-05-12 Clayton; James E. Thin multichip module including a connector frame socket having first and second apertures
US5869353A (en) * 1997-11-17 1999-02-09 Dense-Pac Microsystems, Inc. Modular panel stacking process
US5895970A (en) * 1997-05-02 1999-04-20 Nec Corporation Semiconductor package having semiconductor element, mounting structure of semiconductor package mounted on circuit board, and method of assembling semiconductor package
US5899705A (en) * 1997-11-20 1999-05-04 Akram; Salman Stacked leads-over chip multi-chip module
US6014316A (en) * 1997-06-13 2000-01-11 Irvine Sensors Corporation IC stack utilizing BGA contacts
US6025642A (en) * 1995-08-17 2000-02-15 Staktek Corporation Ultra high density integrated circuit packages
US6028352A (en) * 1997-06-13 2000-02-22 Irvine Sensors Corporation IC stack utilizing secondary leadframes
US6028365A (en) * 1998-03-30 2000-02-22 Micron Technology, Inc. Integrated circuit package and method of fabrication
US6034878A (en) * 1996-12-16 2000-03-07 Hitachi, Ltd. Source-clock-synchronized memory system and memory unit
US6040624A (en) * 1997-10-02 2000-03-21 Motorola, Inc. Semiconductor device package and method
US6057903A (en) * 1998-08-18 2000-05-02 International Business Machines Corporation Liquid crystal display device employing a guard plane between a layer for measuring touch position and common electrode layer
US6172874B1 (en) * 1998-04-06 2001-01-09 Silicon Graphics, Inc. System for stacking of integrated circuit packages
US6178093B1 (en) * 1996-06-28 2001-01-23 International Business Machines Corporation Information handling system with circuit assembly having holes filled with filler material
US6187652B1 (en) * 1998-09-14 2001-02-13 Fujitsu Limited Method of fabrication of multiple-layer high density substrate
US6205654B1 (en) * 1992-12-11 2001-03-27 Staktek Group L.P. Method of manufacturing a surface mount package
US6208521B1 (en) * 1997-05-19 2001-03-27 Nitto Denko Corporation Film carrier and laminate type mounting structure using same
US6222737B1 (en) * 1999-04-23 2001-04-24 Dense-Pac Microsystems, Inc. Universal package and method of forming the same
US6336262B1 (en) * 1996-10-31 2002-01-08 International Business Machines Corporation Process of forming a capacitor with multi-level interconnection technology
US20020006032A1 (en) * 2000-05-23 2002-01-17 Chris Karabatsos Low-profile registered DIMM
US6351029B1 (en) * 1999-05-05 2002-02-26 Harlan R. Isaak Stackable flex circuit chip package and method of making same
US20020030995A1 (en) * 2000-08-07 2002-03-14 Masao Shoji Headlight
US6368896B2 (en) * 1997-10-31 2002-04-09 Micron Technology, Inc. Method of wafer level chip scale packaging
US6376769B1 (en) * 1999-05-18 2002-04-23 Amerasia International Technology, Inc. High-density electronic package, and method for making same
US20020048849A1 (en) * 1999-05-05 2002-04-25 Isaak Harlan R. Stackable flex circuit IC package and method of making same
US20030000708A1 (en) * 1999-04-30 2003-01-02 Coone Malcolm G. FAC tool flexible assembly and method
US6509639B1 (en) * 2001-07-27 2003-01-21 Charles W. C. Lin Three-dimensional stacked semiconductor package
US20030016710A1 (en) * 2001-07-19 2003-01-23 Satoshi Komoto Semiconductor laser device including light receiving element for receiving monitoring laser beam
US6528870B2 (en) * 2000-01-28 2003-03-04 Kabushiki Kaisha Toshiba Semiconductor device having a plurality of stacked wiring boards
US20030045025A1 (en) * 2000-01-26 2003-03-06 Coyle Anthony L. Method of fabricating a molded package for micromechanical devices
US20030049886A1 (en) * 2001-09-07 2003-03-13 Salmon Peter C. Electronic system modules and method of fabrication
US6552910B1 (en) * 2000-06-28 2003-04-22 Micron Technology, Inc. Stacked-die assemblies with a plurality of microelectronic devices and methods of manufacture
US6677670B2 (en) * 2000-04-25 2004-01-13 Seiko Epson Corporation Semiconductor device
US6683377B1 (en) * 2000-05-30 2004-01-27 Amkor Technology, Inc. Multi-stacked memory package
US20040021211A1 (en) * 2002-08-05 2004-02-05 Tessera, Inc. Microelectronic adaptors, assemblies and methods
US6690584B2 (en) * 2000-08-14 2004-02-10 Fujitsu Limited Information-processing device having a crossbar-board connected to back panels on different sides
US20040031972A1 (en) * 2001-10-09 2004-02-19 Tessera, Inc. Stacked packages
US6699730B2 (en) * 1996-12-13 2004-03-02 Tessers, Inc. Stacked microelectronic assembly and method therefor
US20040045159A1 (en) * 1996-12-13 2004-03-11 Tessera, Inc. Electrical connection with inwardly deformable contacts
US6707684B1 (en) * 2001-04-02 2004-03-16 Advanced Micro Devices, Inc. Method and apparatus for direct connection between two integrated circuits via a connector
US6709893B2 (en) * 1998-05-11 2004-03-23 Micron Technology, Inc. Interconnections for a semiconductor device and method for forming same
US20040065963A1 (en) * 2002-09-17 2004-04-08 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield
US20040075991A1 (en) * 1999-08-11 2004-04-22 Tessera. Inc. Vapor phase connection techniques
US20050018495A1 (en) * 2004-01-29 2005-01-27 Netlist, Inc. Arrangement of integrated circuits in a memory module
US6849949B1 (en) * 1999-09-27 2005-02-01 Samsung Electronics Co., Ltd. Thin stacked package
US20050035440A1 (en) * 2001-08-22 2005-02-17 Tessera, Inc. Stacked chip assembly with stiffening layer
US20050040508A1 (en) * 2003-08-22 2005-02-24 Jong-Joo Lee Area array type package stack and manufacturing method thereof
US6876074B2 (en) * 2001-10-10 2005-04-05 Samsung Electronics Co., Ltd. Stack package using flexible double wiring substrate
US6884653B2 (en) * 2001-03-21 2005-04-26 Micron Technology, Inc. Folded interposer

Family Cites Families (180)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3411122A (en) 1966-01-13 1968-11-12 Ibm Electrical resistance element and method of fabricating
US3772776A (en) 1969-12-03 1973-11-20 Thomas & Betts Corp Method of interconnecting memory plane boards
US3746934A (en) 1971-05-06 1973-07-17 Siemens Ag Stack arrangement of semiconductor chips
US3766439A (en) 1972-01-12 1973-10-16 Gen Electric Electronic module using flexible printed circuit board with heat sink means
US3765439A (en) 1972-03-16 1973-10-16 Jolger Machine Co Self cleaning sealed concrete pump valve
US3806767A (en) 1973-03-15 1974-04-23 Tek Wave Inc Interboard connector
US3983547A (en) * 1974-06-27 1976-09-28 International Business Machines - Ibm Three-dimensional bubble device
US4103318A (en) 1977-05-06 1978-07-25 Ford Motor Company Electronic multichip module
US4288841A (en) 1979-09-20 1981-09-08 Bell Telephone Laboratories, Incorporated Double cavity semiconductor chip carrier
US4381421A (en) 1980-07-01 1983-04-26 Tektronix, Inc. Electromagnetic shield for electronic equipment
US4398235A (en) 1980-09-11 1983-08-09 General Motors Corporation Vertical integrated circuit package integration
JPH0315340B2 (en) * 1981-04-30 1991-02-28 Hitachi Seisakusho Kk
US4406508A (en) 1981-07-02 1983-09-27 Thomas & Betts Corporation Dual-in-line package assembly
US4420794A (en) 1981-09-10 1983-12-13 Research, Incorporated Integrated circuit switch
US4712129A (en) 1983-12-12 1987-12-08 Texas Instruments Incorporated Integrated circuit device with textured bar cover
KR890004820B1 (en) 1984-03-28 1989-11-27 제이.에이취.그래디 Stacked double density memory module using industry standard memory chips
JPH0535418B2 (en) 1985-02-12 1993-05-26 Fuji Photo Film Co Ltd
US4696525A (en) 1985-12-13 1987-09-29 Amp Incorporated Socket for stacking integrated circuit packages
JPS62162891U (en) 1986-04-03 1987-10-16
US4763188A (en) 1986-08-08 1988-08-09 Thomas Johnson Packaging system for multiple semiconductor devices
US4839717A (en) * 1986-12-19 1989-06-13 Fairchild Semiconductor Corporation Ceramic package for high frequency semiconductor devices
US5159535A (en) 1987-03-11 1992-10-27 International Business Machines Corporation Method and apparatus for mounting a flexible film semiconductor chip carrier on a circuitized substrate
US4862249A (en) 1987-04-17 1989-08-29 Xoc Devices, Inc. Packaging system for stacking integrated circuits
IT1214254B (en) 1987-09-23 1990-01-10 Sgs Microelettonica S P A A semiconductor device made of plastic or ceramic container with "chips" fixed on both sides of the central island of the "frame".
US4956694A (en) 1988-11-04 1990-09-11 Dense-Pac Microsystems, Inc. Integrated circuit chip stacking
DE69006609D1 (en) * 1989-03-15 1994-03-24 Ngk Insulators Ltd Ceramic lid for sealing a semiconductor element and method for sealing a semiconductor element in a ceramic package.
JP2647194B2 (en) 1989-04-17 1997-08-27 住友電気工業株式会社 Sealing method of semiconductor package
US4953060A (en) 1989-05-05 1990-08-28 Ncr Corporation Stackable integrated circuit chip package with improved heat removal
US5057903A (en) 1989-07-17 1991-10-15 Microelectronics And Computer Technology Corporation Thermal heat sink encapsulated integrated circuit
US5200362A (en) 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US5068708A (en) 1989-10-02 1991-11-26 Advanced Micro Devices, Inc. Ground plane for plastic encapsulated integrated circuit die packages
US5229641A (en) 1989-11-25 1993-07-20 Hitachi Maxell, Ltd. Semiconductor card and manufacturing method therefor
US5041902A (en) * 1989-12-14 1991-08-20 Motorola, Inc. Molded electronic package with compression structures
JPH03227541A (en) 1990-02-01 1991-10-08 Hitachi Ltd Semiconductor device
US5083697A (en) * 1990-02-14 1992-01-28 Difrancesco Louis Particle-enhanced joining of metal surfaces
US5041015A (en) 1990-03-30 1991-08-20 Cal Flex, Inc. Electrical jumper assembly
US5345205A (en) 1990-04-05 1994-09-06 General Electric Company Compact high density interconnected microwave system
US5261068A (en) 1990-05-25 1993-11-09 Dell Usa L.P. Dual path memory retrieval system for an interleaved dynamic RAM memory unit
US5050039A (en) 1990-06-26 1991-09-17 Digital Equipment Corporation Multiple circuit chip mounting and cooling arrangement
US5446620A (en) 1990-08-01 1995-08-29 Staktek Corporation Ultra high density integrated circuit packages
US5377077A (en) 1990-08-01 1994-12-27 Staktek Corporation Ultra high density integrated circuit packages method and apparatus
US5475920A (en) 1990-08-01 1995-12-19 Burns; Carmen D. Method of assembling ultra high density integrated circuit packages
US5148265A (en) * 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
JP3242101B2 (en) 1990-10-05 2001-12-25 三菱電機株式会社 The semiconductor integrated circuit
JPH04162556A (en) 1990-10-25 1992-06-08 Mitsubishi Electric Corp Lead frame and its manufacturing
US5138434A (en) * 1991-01-22 1992-08-11 Micron Technology, Inc. Packaging for semiconductor logic devices
US5289346A (en) 1991-02-26 1994-02-22 Microelectronics And Computer Technology Corporation Peripheral to area adapter with protective bumper for an integrated circuit chip
US5219794A (en) * 1991-03-14 1993-06-15 Hitachi, Ltd. Semiconductor integrated circuit device and method of fabricating same
US5158912A (en) 1991-04-09 1992-10-27 Digital Equipment Corporation Integral heatsink semiconductor package
US5138430A (en) 1991-06-06 1992-08-11 International Business Machines Corporation High performance versatile thermally enhanced IC chip mounting
JPH0513666A (en) 1991-06-29 1993-01-22 Sony Corp Complex semiconductor device
US5252857A (en) 1991-08-05 1993-10-12 International Business Machines Corporation Stacked DCA memory chips
US5448450A (en) 1991-08-15 1995-09-05 Staktek Corporation Lead-on-chip integrated circuit apparatus
JP2967621B2 (en) * 1991-08-27 1999-10-25 日本電気株式会社 Method of manufacturing a package for a semiconductor device
US5168926A (en) 1991-09-25 1992-12-08 Intel Corporation Heat sink design integrating interface material
IT1252136B (en) * 1991-11-29 1995-06-05 St Microelectronics Srl semiconductor device structure with metal heatsink and plastic body, with means for an electrical connection to the high reliability sink '
US5241454A (en) 1992-01-22 1993-08-31 International Business Machines Corporation Mutlilayered flexible circuit package
US5262927A (en) 1992-02-07 1993-11-16 Lsi Logic Corporation Partially-molded, PCB chip carrier package
US5224023A (en) 1992-02-10 1993-06-29 Smith Gary W Foldable electronic assembly module
US5243133A (en) 1992-02-18 1993-09-07 International Business Machines, Inc. Ceramic chip carrier with lead frame or edge clip
US5509198A (en) * 1992-02-24 1996-04-23 Nsk Ltd. Preloading method for preload-adjustable rolling bearing and manufacture of the same
US5222014A (en) 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
US5229916A (en) * 1992-03-04 1993-07-20 International Business Machines Corporation Chip edge interconnect overlay element
US5259770A (en) 1992-03-19 1993-11-09 Amp Incorporated Impedance controlled elastomeric connector
US5438224A (en) * 1992-04-23 1995-08-01 Motorola, Inc. Integrated circuit package having a face-to-face IC chip arrangement
US5361228A (en) * 1992-04-30 1994-11-01 Fuji Photo Film Co., Ltd. IC memory card system having a common data and address bus
MY120226A (en) * 1992-05-25 2005-09-30 Hitachi Ulsi Eng Corp Thin type semiconductor device, module structure using the device and method of mounting the device on board.
US5247423A (en) 1992-05-26 1993-09-21 Motorola, Inc. Stacking three dimensional leadless multi-chip module and method for making the same
DE69325770T2 (en) * 1992-06-02 1999-11-18 Hewlett Packard Co A method of computer-aided design for multi-layer technologies compounds
US5343366A (en) 1992-06-24 1994-08-30 International Business Machines Corporation Packages for stacked integrated circuit chip cubes
US5702985A (en) 1992-06-26 1997-12-30 Staktek Corporation Hermetically sealed ceramic integrated circuit heat dissipating package fabrication method
US5804870A (en) * 1992-06-26 1998-09-08 Staktek Corporation Hermetically sealed integrated circuit lead-on package configuration
US5432630A (en) 1992-09-11 1995-07-11 Motorola, Inc. Optical bus with optical transceiver modules and method of manufacture
US5375041A (en) 1992-12-02 1994-12-20 Intel Corporation Ra-tab array bump tab tape based I.C. package
US5347428A (en) 1992-12-03 1994-09-13 Irvine Sensors Corporation Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip
US5801437A (en) 1993-03-29 1998-09-01 Staktek Corporation Three-dimensional warp-resistant integrated circuit module method and apparatus
US5644161A (en) 1993-03-29 1997-07-01 Staktek Corporation Ultra-high density warp-resistant memory module
US5428190A (en) 1993-07-02 1995-06-27 Sheldahl, Inc. Rigid-flex board with anisotropic interconnect and method of manufacture
US5384690A (en) * 1993-07-27 1995-01-24 International Business Machines Corporation Flex laminate package for a parallel processor
US5396573A (en) 1993-08-03 1995-03-07 International Business Machines Corporation Pluggable connectors for connecting large numbers of electrical and/or optical cables to a module through a seal
US5337388A (en) 1993-08-03 1994-08-09 International Business Machines Corporation Matrix of pluggable connectors for connecting large numbers of clustered electrical and/or opticcal cables to a module
US5523619A (en) 1993-11-03 1996-06-04 International Business Machines Corporation High density memory structure
US5499656A (en) * 1993-12-23 1996-03-19 Hughes Aircraft Company Integrated storage and transfer system and method for spacecraft propulsion systems
US5477082A (en) 1994-01-11 1995-12-19 Exponential Technology, Inc. Bi-planar multi-chip module
US5541812A (en) 1995-05-22 1996-07-30 Burns; Carmen D. Bus communication system for stacked high density integrated circuit packages having an intermediate lead frame
US5448511A (en) 1994-06-01 1995-09-05 Storage Technology Corporation Memory stack with an integrated interconnect and mounting structure
US5523695A (en) * 1994-08-26 1996-06-04 Vlsi Technology, Inc. Universal test socket for exposing the active surface of an integrated circuit in a die-down package
KR970005644B1 (en) * 1994-09-03 1997-04-18 김광호 Multi-block erase and verify device and method of non-volatile semiconductor memory device
JP2570628B2 (en) 1994-09-21 1997-01-08 日本電気株式会社 Semiconductor package and a method of manufacturing the same
JP2606177B2 (en) * 1995-04-26 1997-04-30 日本電気株式会社 Printed wiring board
DE19516272A1 (en) * 1995-05-08 1996-11-14 Hermann Leguin Primary element scanner for determining deflection of scanning pin or similar
US5657537A (en) * 1995-05-30 1997-08-19 General Electric Company Method for fabricating a stack of two dimensional circuit modules
US5922061A (en) * 1995-10-20 1999-07-13 Iq Systems Methods and apparatus for implementing high speed data communications
SG45122A1 (en) * 1995-10-28 1998-01-16 Inst Of Microelectronics Low cost and highly reliable chip-sized package
JPH09139559A (en) * 1995-11-13 1997-05-27 Minolta Co Ltd Connection structure of circuit board
US6013948A (en) * 1995-11-27 2000-01-11 Micron Technology, Inc. Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US5646446A (en) * 1995-12-22 1997-07-08 Fairchild Space And Defense Corporation Three-dimensional flexible assembly of integrated circuits
JPH09260568A (en) 1996-03-27 1997-10-03 Mitsubishi Electric Corp Semiconductor device and its manufacture
US5789815A (en) * 1996-04-23 1998-08-04 Motorola, Inc. Three dimensional semiconductor package having flexible appendages
US5778522A (en) 1996-05-20 1998-07-14 Staktek Corporation Method of manufacturing a high density integrated circuit module with complex electrical interconnect rails having electrical interconnect strain relief
DE19626126C2 (en) * 1996-06-28 1998-04-16 Fraunhofer Ges Forschung A method of forming a spatial arrangement and spatial chip Chipanordung
US5729896A (en) * 1996-10-31 1998-03-24 International Business Machines Corporation Method for attaching a flip chip on flexible circuit carrier using chip with metallic cap on solder
JP3695893B2 (en) * 1996-12-03 2005-09-14 沖電気工業株式会社 Semiconductor device and a manufacturing method and mounting method thereof
US6121676A (en) 1996-12-13 2000-09-19 Tessera, Inc. Stacked microelectronic assembly and method therefor
US7149095B2 (en) * 1996-12-13 2006-12-12 Tessera, Inc. Stacked microelectronic assemblies
US5917709A (en) * 1997-06-16 1999-06-29 Eastman Kodak Company Multiple circuit board assembly having an interconnect mechanism that includes a flex connector
US5986209A (en) * 1997-07-09 1999-11-16 Micron Technology, Inc. Package stack via bottom leaded plastic (BLP) packaging
US6234820B1 (en) * 1997-07-21 2001-05-22 Rambus Inc. Method and apparatus for joining printed circuit boards
JPH1197619A (en) * 1997-07-25 1999-04-09 Oki Electric Ind Co Ltd Semiconductor device, manufacture thereof and mounting thereof
US5949657A (en) 1997-12-01 1999-09-07 Karabatsos; Chris Bottom or top jumpered foldable electronic assembly
US5953215A (en) 1997-12-01 1999-09-14 Karabatsos; Chris Apparatus and method for improving computer memory speed and capacity
US6266252B1 (en) * 1997-12-01 2001-07-24 Chris Karabatsos Apparatus and method for terminating a computer memory bus
DE19754874A1 (en) * 1997-12-10 1999-06-24 Siemens Ag Converting substrate with edge contacts into ball grid array
US6186106B1 (en) * 1997-12-29 2001-02-13 Visteon Global Technologies, Inc. Apparatus for routing electrical signals in an engine
US5926369A (en) 1998-01-22 1999-07-20 International Business Machines Corporation Vertically integrated multi-chip circuit package with heat-sink support
US6233650B1 (en) * 1998-04-01 2001-05-15 Intel Corporation Using FET switches for large memory arrays
US6072233A (en) 1998-05-04 2000-06-06 Micron Technology, Inc. Stackable ball grid array package
US6300679B1 (en) * 1998-06-01 2001-10-09 Semiconductor Components Industries, Llc Flexible substrate for packaging a semiconductor component
US6300687B1 (en) * 1998-06-26 2001-10-09 International Business Machines Corporation Micro-flex technology in semiconductor packages
JP3842444B2 (en) * 1998-07-24 2006-11-08 富士通株式会社 A method of manufacturing a semiconductor device
DE19833713C1 (en) * 1998-07-27 2000-05-04 Siemens Ag Laminate or stacked package arrangement based on at least two integrated circuits
JP2000068444A (en) * 1998-08-26 2000-03-03 Mitsubishi Electric Corp Semiconductor device
DE69938582T2 (en) * 1998-09-09 2009-06-04 Seiko Epson Corp. Semiconductor device, its manufacturing, circuit board and electronic apparatus
JP2000111715A (en) * 1998-10-01 2000-04-21 Canon Inc Reflecting optical device and image pickup device using the device
US6239485B1 (en) * 1998-11-13 2001-05-29 Fujitsu Limited Reduced cross-talk noise high density signal interposer with power and ground wrap
US6410827B1 (en) * 1998-12-02 2002-06-25 E. I. Du Pont De Nemours And Company Geranylgernayl pyrophosphate synthases
US6360935B1 (en) * 1999-01-26 2002-03-26 Board Of Regents Of The University Of Texas System Apparatus and method for assessing solderability
US6206654B1 (en) * 1999-04-15 2001-03-27 Dlm Plastics Corporation Air mattress inflation apparatus
US6262660B1 (en) * 1999-04-30 2001-07-17 Erica Marmon Segale Child proximity transmitter
JP2000353767A (en) * 1999-05-14 2000-12-19 Universal Instr Corp Board for mounting electronic component, package, mounting method, and method for housing integrated circuit chip in package
US6446158B1 (en) * 1999-05-17 2002-09-03 Chris Karabatsos Memory system using FET switches to select memory banks
TW409377B (en) * 1999-05-21 2000-10-21 Siliconware Prec Ind Co Ltd Small scale ball grid array package
JP3526788B2 (en) * 1999-07-01 2004-05-17 沖電気工業株式会社 A method of manufacturing a semiconductor device
DE19933265A1 (en) * 1999-07-15 2001-02-01 Siemens Ag TSOP memory chip housing assembly
JP2001053243A (en) * 1999-08-06 2001-02-23 Hitachi Ltd Semiconductor memory device and memory module
US6689634B1 (en) * 1999-09-22 2004-02-10 Texas Instruments Incorporated Modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or LGA) package to increase device reliability
US6572387B2 (en) * 1999-09-24 2003-06-03 Staktek Group, L.P. Flexible circuit connector for stacked chip module
CN1230046C (en) * 1999-10-01 2005-11-30 精工爱普生株式会社 Wiring board, semiconductor device and method of producing, testing and mounting the same
US6724894B1 (en) * 1999-11-05 2004-04-20 Pitney Bowes Inc. Cryptographic device having reduced vulnerability to side-channel attack and method of operating same
US6262895B1 (en) * 2000-01-13 2001-07-17 John A. Forthun Stackable chip package with flex carrier
JP2001203319A (en) * 2000-01-18 2001-07-27 Sony Corp Laminated semiconductor device
JP2001217388A (en) * 2000-02-01 2001-08-10 Sony Corp Electronic device and method for manufacturing the same
US6444921B1 (en) * 2000-02-03 2002-09-03 Fujitsu Limited Reduced stress and zero stress interposers for integrated-circuit chips, multichip substrates, and the like
US6522018B1 (en) * 2000-05-16 2003-02-18 Micron Technology, Inc. Ball grid array chip packages having improved testing and stacking characteristics
US7115986B2 (en) * 2001-05-02 2006-10-03 Micron Technology, Inc. Flexible ball grid array chip scale packages
US6560117B2 (en) * 2000-06-28 2003-05-06 Micron Technology, Inc. Packaged microelectronic die assemblies and methods of manufacture
US6614664B2 (en) * 2000-10-24 2003-09-02 Samsung Electronics Co., Ltd. Memory module having series-connected printed circuit boards
US6392162B1 (en) * 2000-11-10 2002-05-21 Chris Karabatsos Double-sided flexible jumper assembly and method of manufacture
KR100400765B1 (en) * 2000-11-13 2003-10-08 엘지.필립스 엘시디 주식회사 Method for forming thin-film and liquid crystal display device fabricated by the same method
KR100355032B1 (en) * 2001-01-08 2002-10-05 삼성전자 주식회사 High density package memory device, memory module using this device, and control method of this module
US6737891B2 (en) * 2001-02-01 2004-05-18 Chris Karabatsos Tri-directional, high-speed bus switch
AU2002254027A1 (en) * 2001-02-27 2002-09-12 Chippac, Inc. Tape ball grid array semiconductor package structure and assembly process
US6410857B1 (en) * 2001-03-01 2002-06-25 Lockheed Martin Corporation Signal cross-over interconnect for a double-sided circuit card assembly
US6910268B2 (en) * 2001-03-27 2005-06-28 Formfactor, Inc. Method for fabricating an IC interconnect system including an in-street integrated circuit wafer via
US6588095B2 (en) * 2001-04-27 2003-07-08 Hewlett-Packard Development Company, Lp. Method of processing a device by electrophoresis coating
US6532162B2 (en) * 2001-05-26 2003-03-11 Intel Corporation Reference plane of integrated circuit packages
KR100415279B1 (en) * 2001-06-26 2004-01-16 삼성전자주식회사 Chip stack package and manufacturing method thereof
US6627984B2 (en) * 2001-07-24 2003-09-30 Dense-Pac Microsystems, Inc. Chip stack with differing chip package types
KR100429878B1 (en) * 2001-09-10 2004-05-03 삼성전자주식회사 Memory module and printed circuit board for the same
DE10297316T5 (en) * 2001-10-09 2004-12-09 Tessera, Inc., San Jose stacked modules
US6620651B2 (en) * 2001-10-23 2003-09-16 National Starch And Chemical Investment Holding Corporation Adhesive wafers for die attach application
US6940729B2 (en) * 2001-10-26 2005-09-06 Staktek Group L.P. Integrated circuit stacking system and method
US6914324B2 (en) * 2001-10-26 2005-07-05 Staktek Group L.P. Memory expansion and chip scale stacking system and method
US6576992B1 (en) * 2001-10-26 2003-06-10 Staktek Group L.P. Chip scale stacking system and method
AU2002351081A1 (en) * 2001-12-03 2003-06-17 Koninklijke Philips Electronics N.V. Optical storage system, optical storage medium and use of such a medium
US6590282B1 (en) * 2002-04-12 2003-07-08 Industrial Technology Research Institute Stacked semiconductor package formed on a substrate and method for fabrication
US6707148B1 (en) * 2002-05-21 2004-03-16 National Semiconductor Corporation Bumped integrated circuits for optical applications
TW565918B (en) * 2002-07-03 2003-12-11 United Test Ct Inc Semiconductor package with heat sink
US6600222B1 (en) * 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
WO2004017399A1 (en) * 2002-08-16 2004-02-26 Tessera, Inc. Microelectronic packages with self-aligning features
JP4085788B2 (en) * 2002-08-30 2008-05-14 日本電気株式会社 Semiconductor device and manufacturing method thereof, circuit board, electronic apparatus
US7246431B2 (en) * 2002-09-06 2007-07-24 Tessera, Inc. Methods of making microelectronic packages including folded substrates
US7071547B2 (en) * 2002-09-11 2006-07-04 Tessera, Inc. Assemblies having stacked semiconductor chips and methods of making same
US6869825B2 (en) * 2002-12-31 2005-03-22 Intel Corporation Folded BGA package design with shortened communication paths and more electrical routing flexibility
TWI236077B (en) * 2002-12-31 2005-07-11 Unisemicon Co Ltd Stack package and fabricating method thereof
US6879047B1 (en) * 2003-02-19 2005-04-12 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US6841855B2 (en) * 2003-04-28 2005-01-11 Intel Corporation Electronic package having a flexible substrate with ends connected to one another
DE10319984B4 (en) * 2003-05-05 2009-09-03 Qimonda Ag Apparatus for cooling of memory modules
US7455928B2 (en) * 2003-08-18 2008-11-25 General Motors Corporation Diffusion media for use in a PEM fuel cell
KR100575590B1 (en) * 2003-12-17 2006-05-03 삼성전자주식회사 Thermal emission type stack package and modules mounting the same

Patent Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3436604A (en) * 1966-04-25 1969-04-01 Texas Instruments Inc Complex integrated circuit array and method for fabricating same
US3654394A (en) * 1969-07-08 1972-04-04 Gordon Eng Co Field effect transistor switch, particularly for multiplexing
US3727064A (en) * 1971-03-17 1973-04-10 Monsanto Co Opto-isolator devices and method for the fabrication thereof
US4079511A (en) * 1976-07-30 1978-03-21 Amp Incorporated Method for packaging hermetically sealed integrated circuit chips on lead frames
US4437235A (en) * 1980-12-29 1984-03-20 Honeywell Information Systems Inc. Integrated circuit package
US4513368A (en) * 1981-05-22 1985-04-23 Data General Corporation Digital data processing system having object-based logical memory addressing and self-structuring modular memory
US4645944A (en) * 1983-09-05 1987-02-24 Matsushita Electric Industrial Co., Ltd. MOS register for selecting among various data inputs
US4587596A (en) * 1984-04-09 1986-05-06 Amp Incorporated High density mother/daughter circuit board connector
US4733461A (en) * 1984-12-28 1988-03-29 Micro Co., Ltd. Method of stacking printed circuit boards
US4823234A (en) * 1985-08-16 1989-04-18 Dai-Ichi Seiko Co., Ltd. Semiconductor device and its manufacture
US4722691A (en) * 1986-02-03 1988-02-02 General Motors Corporation Header assembly for a printed circuit board
US4821007A (en) * 1987-02-06 1989-04-11 Tektronix, Inc. Strip line circuit component and method of manufacture
US5016138A (en) * 1987-10-27 1991-05-14 Woodman John K Three dimensional integrated circuit package
US4983533A (en) * 1987-10-28 1991-01-08 Irvine Sensors Corporation High-density electronic modules - process and product
US5198888A (en) * 1987-12-28 1993-03-30 Hitachi, Ltd. Semiconductor stacked device
US4833568A (en) * 1988-01-29 1989-05-23 Berhold G Mark Three-dimensional circuit component assembly and method corresponding thereto
US4985703A (en) * 1988-02-03 1991-01-15 Nec Corporation Analog multiplexer
US4891789A (en) * 1988-03-03 1990-01-02 Bull Hn Information Systems, Inc. Surface mounted multilayer memory printed circuit board
US4911643A (en) * 1988-10-11 1990-03-27 Beta Phase, Inc. High density and high signal integrity connector
US5276418A (en) * 1988-11-16 1994-01-04 Motorola, Inc. Flexible substrate electronic assembly
US5081067A (en) * 1989-02-10 1992-01-14 Fujitsu Limited Ceramic package type semiconductor device and method of assembling the same
US5104820A (en) * 1989-07-07 1992-04-14 Irvine Sensors Corporation Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting
US5012323A (en) * 1989-11-20 1991-04-30 Micron Technology, Inc. Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe
US5279029A (en) * 1990-08-01 1994-01-18 Staktek Corporation Ultra high density integrated circuit packages method
US5420751A (en) * 1990-08-01 1995-05-30 Staktek Corporation Ultra high density modular integrated circuit package
US5499160A (en) * 1990-08-01 1996-03-12 Staktek Corporation High density integrated circuit module with snap-on rail assemblies
US5117282A (en) * 1990-10-29 1992-05-26 Harris Corporation Stacked configuration for integrated circuit devices
US5394010A (en) * 1991-03-13 1995-02-28 Kabushiki Kaisha Toshiba Semiconductor assembly having laminated semiconductor devices
US5289062A (en) * 1991-03-18 1994-02-22 Quality Semiconductor, Inc. Fast transmission gate switch
US5099393A (en) * 1991-03-25 1992-03-24 International Business Machines Corporation Electronic package for high density applications
US5214307A (en) * 1991-07-08 1993-05-25 Micron Technology, Inc. Lead frame for semiconductor devices having improved adhesive bond line control
US5311401A (en) * 1991-07-09 1994-05-10 Hughes Aircraft Company Stacked chip assembly and manufacturing method therefor
US5281852A (en) * 1991-12-10 1994-01-25 Normington Peter J C Semiconductor device including stacked die
US5397916A (en) * 1991-12-10 1995-03-14 Normington; Peter J. C. Semiconductor device including stacked die
US5198965A (en) * 1991-12-18 1993-03-30 International Business Machines Corporation Free form packaging of specific functions within a computer system
US5729894A (en) * 1992-07-21 1998-03-24 Lsi Logic Corporation Method of assembling ball bump grid array semiconductor packages
US5394303A (en) * 1992-09-11 1995-02-28 Kabushiki Kaisha Toshiba Semiconductor device
US5751553A (en) * 1992-09-16 1998-05-12 Clayton; James E. Thin multichip module including a connector frame socket having first and second apertures
US5402006A (en) * 1992-11-10 1995-03-28 Texas Instruments Incorporated Semiconductor device with enhanced adhesion between heat spreader and leads and plastic mold compound
US5313097A (en) * 1992-11-16 1994-05-17 International Business Machines, Corp. High density memory module
US5484959A (en) * 1992-12-11 1996-01-16 Staktek Corporation High density lead-on-package fabrication method and apparatus
US5631193A (en) * 1992-12-11 1997-05-20 Staktek Corporation High density lead-on-package fabrication method
US6205654B1 (en) * 1992-12-11 2001-03-27 Staktek Group L.P. Method of manufacturing a surface mount package
US5386341A (en) * 1993-11-01 1995-01-31 Motorola, Inc. Flexible substrate folded in a U-shape with a rigidizer plate located in the notch of the U-shape
US5594275A (en) * 1993-11-18 1997-01-14 Samsung Electronics Co., Ltd. J-leaded semiconductor package having a plurality of stacked ball grid array packages
US5493476A (en) * 1994-03-07 1996-02-20 Staktek Corporation Bus communication system for stacked high density integrated circuit packages with bifurcated distal lead ends
US5502333A (en) * 1994-03-30 1996-03-26 International Business Machines Corporation Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit
US5592364A (en) * 1995-01-24 1997-01-07 Staktek Corporation High density integrated circuit module with complex electrical interconnect rails
US5514907A (en) * 1995-03-21 1996-05-07 Simple Technology Incorporated Apparatus for stacking semiconductor chips
US5612570A (en) * 1995-04-13 1997-03-18 Dense-Pac Microsystems, Inc. Chip stack and method of making same
US6025642A (en) * 1995-08-17 2000-02-15 Staktek Corporation Ultra high density integrated circuit packages
US5744827A (en) * 1995-11-28 1998-04-28 Samsung Electronics Co., Ltd. Three dimensional stack package device having exposed coupling lead portions and vertical interconnection elements
US6178093B1 (en) * 1996-06-28 2001-01-23 International Business Machines Corporation Information handling system with circuit assembly having holes filled with filler material
US6336262B1 (en) * 1996-10-31 2002-01-08 International Business Machines Corporation Process of forming a capacitor with multi-level interconnection technology
US20040045159A1 (en) * 1996-12-13 2004-03-11 Tessera, Inc. Electrical connection with inwardly deformable contacts
US6699730B2 (en) * 1996-12-13 2004-03-02 Tessers, Inc. Stacked microelectronic assembly and method therefor
US6034878A (en) * 1996-12-16 2000-03-07 Hitachi, Ltd. Source-clock-synchronized memory system and memory unit
US5895970A (en) * 1997-05-02 1999-04-20 Nec Corporation Semiconductor package having semiconductor element, mounting structure of semiconductor package mounted on circuit board, and method of assembling semiconductor package
US6208521B1 (en) * 1997-05-19 2001-03-27 Nitto Denko Corporation Film carrier and laminate type mounting structure using same
US6014316A (en) * 1997-06-13 2000-01-11 Irvine Sensors Corporation IC stack utilizing BGA contacts
US6028352A (en) * 1997-06-13 2000-02-22 Irvine Sensors Corporation IC stack utilizing secondary leadframes
US6040624A (en) * 1997-10-02 2000-03-21 Motorola, Inc. Semiconductor device package and method
US6368896B2 (en) * 1997-10-31 2002-04-09 Micron Technology, Inc. Method of wafer level chip scale packaging
US5869353A (en) * 1997-11-17 1999-02-09 Dense-Pac Microsystems, Inc. Modular panel stacking process
US5899705A (en) * 1997-11-20 1999-05-04 Akram; Salman Stacked leads-over chip multi-chip module
US6028365A (en) * 1998-03-30 2000-02-22 Micron Technology, Inc. Integrated circuit package and method of fabrication
US6172874B1 (en) * 1998-04-06 2001-01-09 Silicon Graphics, Inc. System for stacking of integrated circuit packages
US6709893B2 (en) * 1998-05-11 2004-03-23 Micron Technology, Inc. Interconnections for a semiconductor device and method for forming same
US6057903A (en) * 1998-08-18 2000-05-02 International Business Machines Corporation Liquid crystal display device employing a guard plane between a layer for measuring touch position and common electrode layer
US6187652B1 (en) * 1998-09-14 2001-02-13 Fujitsu Limited Method of fabrication of multiple-layer high density substrate
US6360433B1 (en) * 1999-04-23 2002-03-26 Andrew C. Ross Universal package and method of forming the same
US6222737B1 (en) * 1999-04-23 2001-04-24 Dense-Pac Microsystems, Inc. Universal package and method of forming the same
US20030000708A1 (en) * 1999-04-30 2003-01-02 Coone Malcolm G. FAC tool flexible assembly and method
US20020048849A1 (en) * 1999-05-05 2002-04-25 Isaak Harlan R. Stackable flex circuit IC package and method of making same
US6514793B2 (en) * 1999-05-05 2003-02-04 Dpac Technologies Corp. Stackable flex circuit IC package and method of making same
US6351029B1 (en) * 1999-05-05 2002-02-26 Harlan R. Isaak Stackable flex circuit chip package and method of making same
US6376769B1 (en) * 1999-05-18 2002-04-23 Amerasia International Technology, Inc. High-density electronic package, and method for making same
US20040075991A1 (en) * 1999-08-11 2004-04-22 Tessera. Inc. Vapor phase connection techniques
US6849949B1 (en) * 1999-09-27 2005-02-01 Samsung Electronics Co., Ltd. Thin stacked package
US20030045025A1 (en) * 2000-01-26 2003-03-06 Coyle Anthony L. Method of fabricating a molded package for micromechanical devices
US6528870B2 (en) * 2000-01-28 2003-03-04 Kabushiki Kaisha Toshiba Semiconductor device having a plurality of stacked wiring boards
US6677670B2 (en) * 2000-04-25 2004-01-13 Seiko Epson Corporation Semiconductor device
US20020006032A1 (en) * 2000-05-23 2002-01-17 Chris Karabatsos Low-profile registered DIMM
US6683377B1 (en) * 2000-05-30 2004-01-27 Amkor Technology, Inc. Multi-stacked memory package
US6552910B1 (en) * 2000-06-28 2003-04-22 Micron Technology, Inc. Stacked-die assemblies with a plurality of microelectronic devices and methods of manufacture
US20020030995A1 (en) * 2000-08-07 2002-03-14 Masao Shoji Headlight
US6690584B2 (en) * 2000-08-14 2004-02-10 Fujitsu Limited Information-processing device having a crossbar-board connected to back panels on different sides
US6884653B2 (en) * 2001-03-21 2005-04-26 Micron Technology, Inc. Folded interposer
US6707684B1 (en) * 2001-04-02 2004-03-16 Advanced Micro Devices, Inc. Method and apparatus for direct connection between two integrated circuits via a connector
US20030016710A1 (en) * 2001-07-19 2003-01-23 Satoshi Komoto Semiconductor laser device including light receiving element for receiving monitoring laser beam
US6509639B1 (en) * 2001-07-27 2003-01-21 Charles W. C. Lin Three-dimensional stacked semiconductor package
US20050035440A1 (en) * 2001-08-22 2005-02-17 Tessera, Inc. Stacked chip assembly with stiffening layer
US20030049886A1 (en) * 2001-09-07 2003-03-13 Salmon Peter C. Electronic system modules and method of fabrication
US20040031972A1 (en) * 2001-10-09 2004-02-19 Tessera, Inc. Stacked packages
US6876074B2 (en) * 2001-10-10 2005-04-05 Samsung Electronics Co., Ltd. Stack package using flexible double wiring substrate
US20040021211A1 (en) * 2002-08-05 2004-02-05 Tessera, Inc. Microelectronic adaptors, assemblies and methods
US20040065963A1 (en) * 2002-09-17 2004-04-08 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield
US20050040508A1 (en) * 2003-08-22 2005-02-24 Jong-Joo Lee Area array type package stack and manufacturing method thereof
US20050018495A1 (en) * 2004-01-29 2005-01-27 Netlist, Inc. Arrangement of integrated circuits in a memory module

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US6914324B2 (en) 2005-07-05
US7256484B2 (en) 2007-08-14
US20040197956A1 (en) 2004-10-07
US20050062144A1 (en) 2005-03-24
US20050280135A1 (en) 2005-12-22
WO2004109802A1 (en) 2004-12-16
US20040000708A1 (en) 2004-01-01
US7495334B2 (en) 2009-02-24
US20040178496A1 (en) 2004-09-16
US6955945B2 (en) 2005-10-18
AU2003304192A1 (en) 2005-01-04

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