TWI695463B - 具有反向堆積混合式添加結構之穿模柱封裝 - Google Patents

具有反向堆積混合式添加結構之穿模柱封裝 Download PDF

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TWI695463B
TWI695463B TW107126681A TW107126681A TWI695463B TW I695463 B TWI695463 B TW I695463B TW 107126681 A TW107126681 A TW 107126681A TW 107126681 A TW107126681 A TW 107126681A TW I695463 B TWI695463 B TW I695463B
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conductive
redistribution structure
semiconductor device
contacts
semiconductor die
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TW107126681A
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TW201921614A (zh
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辰 Ｈ 游
約翰 Ｆ 凱汀
艾夏克 帕查穆索
馬克 Ｅ 朵杜
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美商美光科技公司
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Abstract

本文中揭示具有電耦合至一重佈結構之一半導體晶粒及位於該重佈結構上方之一模製材料之半導體裝置以及相關聯系統及方法。在一實施例中，一種半導體裝置包含附著至一無基板重佈結構之一第一側之一半導體晶粒及延伸穿過安置於該重佈結構之該第一側上之一模製材料之複數個導電柱。該半導體裝置亦可包含位於該模製材料上且電耦合至該等導電柱之一第二重佈結構。可使用一單一載體且需要僅對一半導體裝置之一單一側之處理來製造該半導體裝置。

Description

具有反向堆積混合式添加結構之穿模柱封裝
本發明大體上係關於半導體裝置。特定而言，本發明係關於具有電耦合至一重佈結構之一半導體晶粒及位於該重佈結構上方之一模製材料之半導體裝置以及相關聯系統及方法。
微電子裝置大體上具有一晶粒(即，一晶片)，其包含具有一高密度之極小組件之積體電路。通常，晶粒包含電耦合至積體電路之一極小接合墊陣列。接合墊係供應電壓、信號等等透過其傳輸至積體電路及自積體電路傳輸之外部電接點。在形成晶粒之後，「封裝」晶粒以將接合墊耦合至可更容易耦合至各種電力供應線、信號線及接地線之一較大電端子陣列。用於封裝晶粒之習知程序包含將晶粒上之接合墊電耦合至引線、球墊或其他類型之電端子之一陣列且囊封晶粒以保護其免受環境因數(例如水分、微粒、靜電及實體衝擊)影響。
不同類型之晶粒可具有大不相同接合墊配置，但應與類似外部裝置相容。因此，既有封裝技術可包含在晶粒上形成一重佈層(RDL)。RDL包含將晶粒接合墊與RDL接合墊連接之線及/或通路，RDL接合墊繼而經配置以與外部裝置之接合墊配合。在一典型封裝程序中，將諸多晶粒安裝於一載體上(即，在一晶圓或面板級處)且在移除載體之前囊封晶粒。接著，翻轉經處理裝置及/或將其附著至一第二載體，使得可使用沈積及微影技術來使一RDL直接形成於晶粒之一正面上。最後，將引線、球墊或其他類型之電端子之一陣列安裝於RDL之接合墊上且分割經處理裝置以形成個別裝置。
上述封裝技術之一缺點在於其需要多個階段來移動經處理裝置(例如翻轉裝置及/或將其附著至一第二載體)。各額外階段增加製造成本及製程期間之損壞風險(即，良率損失)。
根據本發明之一實施例，提供一種半導體裝置，其包括：一重佈結構，其具有一第一側及一第二側，其中該第一側包含數個第一導電接點及數個第二導電接點，其中該等第一導電接點電耦合至該等第二導電接點之對應者，且其中該第二側包括其內無任何導體之一連續絕緣材料層；一半導體晶粒，其定位於該第一側上方且電耦合至該等第一導電接點；一模製材料，其位於該第一側上；及數個導電柱，其等自該第一側至少部分延伸穿過該模製材料且電耦合至該等第二導電接點之對應者。
根據本發明之另一實施例，提供一種製造一半導體裝置之方法，該方法包括：在一載體上形成一重佈結構，其中該重佈結構包含數個第一導電接點及電耦合至該等第一導電接點之對應者之數個第二導電接點；形成具有一第一端部分及一第二端部分之數個導電柱，其中該等第一端部分電耦合至該等第二導電接點之對應者；將一半導體晶粒電耦合至該等第一導電接點；在該重佈結構上形成一模製材料，其中該模製材料至少部分包圍該半導體晶粒及該等導電柱，且其中該等導電柱之至少該等第二端部分自該模製材料暴露；及移除該載體。
根據本發明之另一實施例，提供一種半導體裝置封裝，其包括：一重佈結構，其包含數個第一導電接點及數個第二導電接點，其中該等第一導電接點電耦合至該等第二導電接點之對應者；一半導體晶粒，其位於該重佈結構上方；數個導電構件，其等將該半導體晶粒電耦合至該等第一導電接點；數個導電柱，其等電耦合至該等第二導電接點之對應者；及一模製材料，其位於該重佈結構上且至少部分包圍該半導體晶粒、該等導電構件及該等導電柱，其中暴露該等導電柱之至少一部分以界定複數個封裝接點。
本申請案含有與名稱為「HYBRID ADDITIVE STRUCTURE STACKABLE MEMORY DIE USING WIRE BOND」之John F. Kaeding、Ashok Pachamuthu及Chan H. Yoo之一同時申請美國專利申請案相關之標的。相關申請案(其揭示內容以引用的方式併入本文中)讓與Micron Technology公司且由代理檔案號010829-9217.US00識別。
下文將描述具有電耦合至一重佈結構之一半導體晶粒及位於重佈結構上方之一模製材料之半導體裝置之若干實施例之特定細節。在一些實施例中，一半導體裝置包含附著至一重佈結構之一第一側且由一模製材料囊封之一半導體晶粒。裝置包含自重佈結構上之接點延伸穿過模製材料之數個導電柱。在相關聯方法之特定實施例中，可使用一單一臨時載體及僅對裝置之一單一側之處理來製造一半導體裝置。在以下描述中，討論諸多特定細節以提供本發明之實施例之一透徹及可行描述。然而，熟悉相關技術者將認識到，可在無一或多個特定細節的情況下實踐本發明。在其他例項中，未展示或未詳細描述通常與半導體裝置相關聯之熟知結構或操作以免使本發明之其他態樣不清楚。一般而言，應瞭解，除本文中所揭示之特定實施例之外，各種其他裝置、系統及方法亦可在本發明之範疇內。
如本文中所使用，術語「垂直」、「橫向」、「上」及「下」可係指半導體晶粒總成中之構件鑑於圖中所展示之定向之相對方向或位置。例如，「上」或「最上」可涉及定位成比一構件更靠近一頁之頂部之另一構件。然而，此等術語應被廣義解釋為包含具有其他定向(諸如其中頂部/底部、上方/下方、上面/下面、上/下及左/右可取決於定向而互換之相反或傾斜定向)之半導體裝置。
圖1係繪示根據本發明之一實施例之一半導體裝置100 (「裝置100」)的一橫截面圖。裝置100可包含耦合至一重佈結構130之一半導體晶粒110。半導體晶粒110包含暴露於其之一正面113a處之複數個接合墊112。半導體晶粒110可具有積體電路或組件、資料儲存元件、處理組件及/或製造於半導體基板上之其他構件。例如，半導體晶粒110可包含積體電路記憶體及/或邏輯電路，且可包含各種類型之半導體組件及功能構件，諸如動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、快閃記憶體、其他形式之積體電路記憶體、處理電路、成像組件及/或其他半導體構件。如圖1中所展示，裝置100僅包含一單一半導體晶粒110。然而，在其他實施例中，裝置100可包含任何數目個半導體晶粒。例如，裝置100可包含堆疊於半導體晶粒110上及/或相鄰於半導體晶粒110安置於重佈結構130上之一或多個額外半導體晶粒。
重佈結構130包含具有一第一表面133a及與第一表面133a對置之一第二表面133b之一介電材料132。重佈結構130亦包含介電材料132中及/或介電材料132上之第一接點134及介電材料132中及/或介電材料132上之第二接點136。半導體晶粒110耦合至重佈結構130之第一表面133a，且第一接點134及第二接點136暴露於第一表面133a處。如圖1中所展示，第一接點134可定位於一晶粒附著區域中之第一表面133a上，使得其至少部分位於半導體晶粒110下方。第二接點136可沿周邊與第一接點134隔開(例如，自第一接點134扇出或定位於第一接點134外)，且因此不定位於半導體晶粒110下方。重佈結構130進一步包含延伸於介電材料132內及/或介電材料132上以將第一接點134之個別者電耦合至第二接點136之對應者之複數個導線138 (例如通路及/或跡線)。在特定實施例中，第一接點134、第二接點136及導線138可由諸如銅、鎳、焊料(例如基於SnAg之焊料)、填充有導體之環氧樹脂及/或其他導電材料之一或多個導電材料形成。
在一些實施例中，重佈結構130之介電材料132可包括一適合介電或鈍化材料之一或多個層，且介電材料132使個別第一接點134、第二接點136及相關聯導線138彼此電隔離。重佈結構130進一步包含界定重佈結構130之第二表面133b之介電材料132之一絕緣層131。無電接點或其他導電元件安置於絕緣層131中。因此，裝置100之半導體晶粒110及/或其他組件無法自重佈結構130之第二表面133b電接取且因此無法自裝置100之一最下側接取。
重佈結構130不包含一預成形基板(例如一層疊或有機基板)且因此可被製成極薄的。例如，在一些實施例中，重佈結構130之第一表面133a與第二表面133b之間之一距離D1 小於50 μm。在特定實施例中，距離D1 係約30 μm或小於30 µm。然而，重佈結構130之厚度係不受限的。在其他實施例中，重佈結構130可包含不同構件及/或構件可具有一不同配置。
裝置100進一步包含將半導體晶粒110之接合墊112耦合至重佈結構130之第一接點134之對應者之複數個導電構件115。導電構件115可具有諸如支柱、柱、短軸、凸塊等等之各種適合結構且可由銅、鎳、焊料(例如基於SnAg之焊料)、填充有導體之環氧樹脂及/或其他導電材料製成。在特定實施例中，導電構件115係焊料接頭。在選定實施例中，導電構件115可為銅柱，而在其他實施例中，導電構件115可包含更複雜結構，諸如氮化物上凸塊結構。在一些實施例中，導電構件115具有重佈結構130上方之一高度，使得裝置100包含隙間地形成於半導體晶粒110與重佈結構130之第一表面133a之間之一間隙118。
如圖1中所展示，裝置100亦包含電耦合至重佈結構130之第二接點136之複數個導電柱120。導電柱120沿繪示定向遠離重佈結構130之第一表面133a向上延伸，且其可由銅、鎳、焊料(例如基於SnAg之焊料)、填充有導體之環氧樹脂及/或其他導電材料製成。在所繪示之實施例中，導電柱120向上延伸至半導體晶粒110之一背面113b之標高上方。即，導電柱120可具有大於重佈結構130之第一表面133a上方之半導體晶粒110之一高度之重佈結構130之第一表面133a上方之一高度。在其他實施例中，導電柱120之高度可等於或小於半導體晶粒110之高度。因此，導電柱120之高度可大於重佈結構130之第一表面133a上方之導電構件115之一高度。再者，導電柱120之各者之一終端123 (例如與重佈結構130之第二接點136對置之端)可共同界定複數個第三接點152。第三接點152可暴露於一模製材料150之一上表面151處。
模製材料150可形成於重佈結構130之第一表面133a之至少一部分上方且可至少部分包圍半導體晶粒110及/或導電柱120。在一些實施例中，模製材料150可囊封半導體晶粒110以藉此保護半導體晶粒110免受污染及實體損壞。在特定實施例中，模製材料150至少部分填充半導體晶粒110之正面113a與重佈結構130之第一表面133a之間之間隙118。在此等實施例中，模製材料150可用於加強半導體晶粒110與重佈結構130之間之耦合且有助於防止半導體晶粒110在將外力施加至裝置100時彎曲、翹曲等等。再者，由於重佈結構130不包含一預成形基板，所以模製材料150可用於給予裝置100一所要結構強度。例如，模製材料150可經選擇以防止裝置100在將外力施加至裝置100時彎曲、翹曲等等。因此，在一些實施例中，重佈結構130可被製成極薄的(例如，小於50 µm或小於30 µm)，此係因為重佈結構130無需對裝置100提供很大結構強度。因此，可減小裝置100之總大小(例如高度)。
裝置100可進一步包含安置於第三接點152上之複數個電連接器106。電連接器106可為焊球、導電凸塊、導電支柱、導電環氧樹脂及/或其他適合導電元件且可電耦合至外部電路(圖中未展示)。在一些實施例中，電連接器106在模製材料150之上表面151處之第三接點152上形成一球柵陣列。球柵陣列可為其中電連接器106全部沿周邊與半導體晶粒110隔開(例如，定位於半導體晶粒110外)之一周邊球柵陣列。即，電連接器106不定位於半導體晶粒110上方。在一些實施例(例如下文將參考圖2A及圖2B描述)中，一第二重佈結構可形成於模製材料150之上表面151上且用於將電連接器106分佈成不同配置(例如具有大於周邊球柵陣列實施例之電連接器106之相鄰者之間之間隔之一「扇入」或其他配置)。在其他實施例中，可省略電連接器106且可將第三接點152直接連接至外部裝置或電路。
圖2A係一橫截面圖且圖2B係一俯視圖，其等繪示根據本發明之另一實施例且包含一第二重佈結構之一半導體裝置200 (「裝置200」)。裝置200可包含大體上類似於上文詳細描述之裝置100之構件之構件。例如，在圖2A所繪示之實施例中，裝置200包含具有一上表面233a及一下表面233b之一第一重佈結構230及耦合至第一重佈結構230之上表面233a之一半導體晶粒210。第一重佈結構230可包含經由導電構件215電耦合至半導體晶粒210之接合墊212之第一接點234。第一接點234可經由導線238電耦合至定位於第一接點234外之第二接點236之對應者。另外，裝置200可包含自第一重佈結構230之第二接點236向上延伸之導電柱220。導電柱220可各具有共同界定複數個第三接點252之一上端部分。第三接點252可暴露於一模製材料250之一上表面251處，其中模製材料250安置於第一重佈結構230之上表面233a上方且至少部分包圍半導體晶粒210及/或導電柱220。
裝置200可進一步包含模製材料250之上表面251及第三接點252上方之一第二重佈結構240。第二重佈結構240可具有大體上類似於第一重佈結構230及上文參考圖1所描述之重佈結構130之構件。例如，第二重佈結構240可為包括一或多個導電層(例如導電跡線、線路、通路等等)及一或多個絕緣層之一添加結構。更明確而言，第二重佈結構240可包含鄰接模製材料250之上表面251及第三接點252之一下表面243b及與下表面243b對置之一上表面243a。
第二重佈結構240可具有暴露於下表面243b處之複數個第四接點254a及暴露於上表面243a處之複數個第五接點254b。第四接點254a可電連接至第三接點252之對應者(例如，定位於第三接點252上或第三接點252相鄰處)以提供導電柱220與第二重佈結構240之間之一電耦合。第五接點254b可透過第二重佈結構240中及/或第二重佈結構240上之導電元件電耦合至第四接點254a之對應者。更明確而言，第二重佈結構240之導電元件(例如複數個導電跡線、通路等等)可在第二重佈結構240之一介電材料中、該介電材料上及/或穿過該介電材料延伸以將第四接點254a電耦合至第五接點254b之對應者。如圖2A中所展示，在一些實施例中，第四接點254a之一或多者可相較於至少一些第五接點254b定位外部(例如，更與半導體晶粒210橫向間隔)。在一實施例中，全部第四接點254a可定位於第五接點254b外。複數個電連接器206 (例如焊球、導電凸塊、導電支柱、導電環氧樹脂等等)可安置於第五接點254b上且經組態以電耦合至外部電路(圖中未展示)。
在一些實施例中，導電柱220突出超過模製材料250之上表面251而至第二重佈結構240中。在一些此等實施例中，裝置200可不包含單獨或不同第三接點252及第四接點254a。在其他實施例中，導電柱220可完全延伸穿過模製材料250及第二重佈結構240之介電材料兩者，使得導電柱220之一或多者之上端部分可暴露於第二重佈結構240之上表面243a處以界定一第五接點254b。因此，不同於第一重佈結構230 (其包含沿第一重佈結構230之整個下表面233b之介電材料之一絕緣層231)，第二重佈結構240不包含使下表面243b或上表面243a電隔離之一絕緣層。因此，第二重佈結構240可在兩個表面處電接取。
在一些實施例中，第二重佈結構240具有小於第一重佈結構230之一厚度(界定為上表面233a與下表面233b之間之一距離)之一厚度(界定為上表面243a與下表面243b之間之一距離)。例如，第二重佈結構240可僅包含一個導電及/或絕緣材料層，而第一重佈結構230可包含一個以上導電及/或絕緣材料層。在其他實施例中，第一重佈結構230及第二重佈結構240可具有相同結構，或第二重佈結構240之厚度可大於第一重佈結構230之厚度。
在操作中，第二重佈結構240將導電柱220之第三接點252向內重佈於半導體晶粒210上方以形成第五接點254b之一更寬間隔陣列，使得(例如)可在裝置200上形成一全球柵陣列。更明確而言，圖2B係裝置200之一俯視圖，其示意性地展示第二重佈結構240之上表面243a上之電連接器206之佈局之一實施例。如圖中所展示，電連接器206可大體上排列成列及行以形成一陣列(例如一球柵陣列)。在其他實施例中，第五接點254b可經形成使得電連接器206可具有任何其他適合定位及排列(例如呈偏移列或行、呈一同心圖案、不均勻間隔等等)。第二重佈結構240允許一些第五接點254b定位於半導體晶粒210之一覆蓋區211內(即，在半導體晶粒210上方)。例如，如圖2B中所展示，複數個電連接器206b至少部分定位於覆蓋區211內，而複數個電連接器206a自覆蓋區211向外間隔。因而，第二重佈結構240使導電柱220之周邊第三接點252向內重佈以提供用於將裝置200連接至外部電路之一更寬間隔界面(例如，相較於一周邊陣列，諸如圖1中所展示之實施例)。
圖3A至圖3G係繪示根據本發明之實施例之製造半導體裝置200之一方法中之各種階段的橫截面圖。一般而言，可將一半導體裝置200製造為(例如)一離散裝置或一較大晶圓或面板之部分。在晶圓級或面板級製造中，形成一較大半導體裝置，接著在一最後階段中將其分割以形成複數個個別裝置。為便於解釋及理解，圖3A至圖3G繪示兩個半導體裝置200之製造。然而，熟悉技術者應易於瞭解，可將半導體裝置200之製造拓廣至晶圓及/或面板級(即，包含能夠分割成兩個以上半導體裝置200之更多組件)，同時包含類似於本文中所描述之構件之構件且使用類似於本文中所描述之程序之程序。再者，除下文將提及之差異之外，可使用相同或實質上類似方法來製造一或多個半導體裝置100。
首先參考圖3A，半導體裝置200之製造開始於在附著半導體晶粒210之前形成一重佈結構。提供具有一正面361a及一背面361b之一載體360，且在載體360之正面361a上形成一釋放層362。在釋放層362上形成第一重佈結構230。釋放層362使載體360易於在製造之一後續階段中自第一重佈結構230移除且防止第一重佈結構230與載體360之直接接觸以保護第一重佈結構230免受載體360上之可能污染。在特定實施例中，載體360可為由(例如)矽、絕緣體上矽、化合物半導體(例如氮化鎵)、玻璃或其他適合材料形成之一臨時載體。在某種程度上，載體360對下游處理階段提供機械支撐且亦在下游處理階段期間保護釋放層362之一表面以確保第一重佈結構230可自釋放層362移除。在一些實施例中，可在隨後移除載體360之後重新使用載體360。釋放層362可為一次性膜(例如基於環氧樹脂之材料之一層疊膜)或其他適合材料。
第一重佈結構230係可由一添加堆積程序形成之導電及介電材料之一混合結構。即，將第一重佈結構230添加地直接堆積於載體360及釋放層362而非一預成形層疊或有機基板上。明確而言，藉由諸如濺鍍、物理氣相沈積(PVD)、電鍍、微影等等之半導體晶圓製程來製造第一重佈結構230。重佈結構之一介電材料232可包括一或多個層且可由(例如)聚對二甲苯、聚醯亞胺、低溫化學氣相沈積(CVD)材料(諸如四乙氧基矽烷(TEOS)、氮化矽(Si3 Ni4 )、氧化矽(SiO2 ))及/或其他適合介電、非導電材料形成。尤其形成僅包括介電材料232之第一重佈結構230之下表面233b。因此，介電材料232界定第一重佈結構230之下表面233b，使得第一重佈結構230無法自下表面233b電接取。第一重佈結構230包含諸如圖2A中所展示之第一接點234、第二接點236及導線238之導電部分235，其可由銅、鎳、焊料(例如基於SnAg之焊料)、填充有導體之環氧樹脂及/或其他導電材料製成。在一些實施例中，導電部分235全部由相同導電材料製成。在其他實施例中，第一接點234、第二接點236及/或導線238可包括一或多個導電材料，及/或不同導電部分235可包括不同導電材料。
參考圖3B，半導體裝置200之製造接著在第一重佈結構230之第一接點234上形成導電構件215且在第一重佈結構230之第二接點236上形成導電柱220。導電柱220經形成使得其具有大於導電構件215之一高度之一高度。在一些實施例中，可使導電構件215及導電柱220形成為相同程序之部分。例如，在特定實施例中，可藉由此項技術中熟知之一適合電鍍程序來製造導電構件215及導電柱220。在其他實施例中，可使用其他沈積技術(例如濺鍍沈積)來替代電鍍。在其他實施例中，可由一不同程序及/或在不同時間形成導電構件215及/或導電柱220。例如，導電構件215可包括安置於第一接點234上之焊球或焊料凸塊，而導電柱220電鍍於第二接點236上。再者，導電構件215及導電柱220可具有一圓形、矩形、六邊形、多邊形或其他橫截面形狀且可為單層或多層結構。
轉至圖3C，半導體裝置200之製造接著將半導體晶粒210電耦合至導電構件215。更明確而言，可將半導體晶粒210覆晶接合至第一重佈結構230，使得半導體晶粒210之接合墊212經由導電構件215電耦合至第一重佈結構230之第一接點234之對應者。在一些實施例中，使用焊料或一焊料膏來將接合墊212耦合至導電構件215。在其他實施例中，可使用諸如熱壓接合(例如銅-銅(Cu-Cu)接合)之另一程序來形成接合墊212與導電構件215之間之導電焊料接頭。如圖3C中所展示，可形成延伸超過半導體晶粒210之一上表面213b之一標高之導電柱220。在其他實施例中，可形成具有等於半導體晶粒210之一高度之一高度之導電柱220 (即，導電柱220之上端部分可大體上與半導體晶粒210之上表面213b共面)。
參考圖3D，半導體裝置200之製造接著將模製材料250安置於第一重佈結構230之上表面233a上方及至少部分安置於半導體晶粒210及導電柱220周圍。模製材料250可由樹脂、環氧樹脂、基於聚矽氧之材料、聚醯亞胺及/或此項技術中所使用或已知之其他適合樹脂形成。一旦被沈積，則可藉由UV光、化學硬化劑、熱或此項技術中已知之其他適合固化方法來固化模製材料250。模製材料250可至少部分安置於各半導體晶粒210與第一重佈結構230之上表面233a之間之一間質間隙218中。因此，模製材料250可消除一單獨底膠材料且加強半導體晶粒210與第一重佈結構230之間之耦合。再者，各導電柱220之至少一終端223可暴露於模製材料250之上表面251處。導電柱220之終端223共同界定第三接點252。在一些實施例中，在一步驟中形成模製材料250，使得第一接點252暴露於模製材料250之上表面251處。在其他實施例中，形成模製材料250且接著磨削模製材料250以平坦化上表面251且藉此暴露導電柱220之第三接點252。如圖3D中所進一步展示，在一些實施例中，模製材料250囊封半導體晶粒210，使得半導體晶粒210密封於模製材料250內。
轉至圖3E，半導體裝置200之製造接著形成第二重佈結構240且將電連接器206電耦合至第二重佈結構240。特定而言，在模製材料250之上表面251及導電柱220之第三接點252上方形成第二重佈結構240。可藉由大體上類似於第一重佈結構230之一程序來形成第二重佈結構240。例如，第二重佈結構240可為由一添加堆積程序形成之導電及介電材料之一混合結構。然而，不同於第一重佈結構230，第二重佈結構240不包含一下表面243b上之唯一絕緣層且因此可在上表面243a及下表面243b兩者處電接取。例如，延伸於第二重佈結構240之介電材料中及/或第二重佈結構240之介電材料上之導電部分(例如第四接點254a、導電跡線、通路等等)可將導電柱220之第三接點252電耦合至暴露於第二重佈結構240之上表面243a處之封裝接點254 (例如第五接點254b)之對應者。
電連接器206經組態以將第二重佈結構240之封裝接點254電耦合至外部電路(圖中未展示)。在一些實施例中，電連接器206包括複數個焊球或焊料凸塊。例如，一模板印刷機可將焊料膏之離散區塊沈積至第二重佈結構240之封裝接點254上。接著，可回焊焊料膏以在封裝接點254上形成焊球或焊料凸塊。在其中半導體裝置200僅包含第一重佈結構230之實施例(例如，如同圖1中所展示之實施例)中，可在導電柱220之暴露第三接點252上直接形成電連接器206。
轉至圖3F，半導體裝置200之製造接著使第一重佈結構230與載體360分離。在一些實施例中，釋放層362允許載體360易於經由真空、桿銷或其他適合方法自第一重佈結構230移除以可再次重新使用載體360。在其他實施例中，亦可使用研磨技術或依其他方式移除載體360及釋放層362 (例如背面研磨、乾式蝕刻程序、化學蝕刻程序、化學機械拋光(CMP)等等)來移除載體360及釋放層362。移除載體360及釋放層362暴露第一重佈結構230之電絕緣下表面233b。如圖3F中所進一步展示，可在相鄰半導體裝置200之間提供分割道353以促進半導體裝置200之分割。
圖3G展示彼此分割之後之半導體裝置200。明確而言，可在分割道353 (如圖3F中所繪示)處同時切割第一重佈結構230、模製材料250及第二重佈結構240以使半導體裝置200彼此分離。在其中半導體裝置200僅包含一單一重佈結構230之實施例(例如，如同圖1中所展示之實施例)中，僅在分割道353處切割模製材料250及第一重佈結構230以分割個別半導體裝置(例如半導體裝置100)。一旦被分割，個別半導體裝置200可經由電連接器206附著至外部電路且因此併入至各種系統及/或裝置中。
參考圖3A至圖3G所繪示之方法僅利用一單一載體360且需要僅對半導體裝置200之一單一側(例如上側)進行處理。更明確而言，藉由以下操作來達成單側及單載體處理階段：在安裝半導體晶粒210之前於載體360上形成第一重佈結構230，且形成足夠高以延伸穿過模製材料250且可電耦合至定位於半導體裝置200之一最上側上之封裝接點(例如第二重佈結構240之第三接點252或封裝接點254)之導電柱220。因此，可相較於需要雙側處理及/或多個載體之其他方法而降低製造一半導體裝置(例如本文中所描述之半導體裝置100或200)之成本、時間及複雜性。
上文參考圖1至圖3所描述之半導體裝置之任何者可併入至各種更大及/或更複雜系統之任何者中，圖4中所示意性展示之系統490係該等系統之一代表性實例。系統490可包含一半導體晶粒總成400、一電源492、一驅動器494、一處理器496及/或其他子系統或組件498。半導體晶粒總成400可包含具有大體上類似於上述半導體裝置之構件之構件之半導體裝置。所得系統490可執行各種功能之任何者，諸如記憶體儲存、資料處理及/或其他適合功能。因此，代表性系統490可包含(但不限於)手持裝置(例如行動電話、平板電腦、數位讀取器及數位音訊播放器)、電腦及電器。系統490之組件可收容於一單一單元中或分佈於多個互連單元上(例如，透過一通信網路)。系統490之組件亦可包含遠端裝置及各種電腦可讀媒體之任何者。
可自上文瞭解，本文已為了說明而描述本發明之特定實施例，但可在不背離本發明的情況下作出各種修改。因此，本發明僅受限於隨附申請專利範圍。此外，亦可在其他實施例中組合或消除特定實施例之內文中所描述之新技術之特定態樣。再者，儘管已在該等實施例之內文中描述與新技術之特定實施例相關聯之優點，但其他實施例亦可展現此等優點，但未必需要落入本發明之範疇內之全部實施例展現此等優點。因此，本發明及相關聯技術可涵蓋本文中未明確展示或描述之其他實施例。
100‧‧‧半導體裝置106‧‧‧電連接器110‧‧‧半導體晶粒112‧‧‧接合墊113a‧‧‧正面113b‧‧‧背面115‧‧‧導電構件118‧‧‧間隙120‧‧‧導電柱123‧‧‧終端130‧‧‧重佈結構131‧‧‧絕緣層132‧‧‧介電材料133a‧‧‧第一表面133b‧‧‧第二表面134‧‧‧第一接點136‧‧‧第二接點138‧‧‧導線150‧‧‧模製材料151‧‧‧上表面152‧‧‧第三接點200‧‧‧半導體裝置206‧‧‧電連接器206a‧‧‧電連接器206b‧‧‧電連接器210‧‧‧半導體晶粒211‧‧‧覆蓋區212‧‧‧接合墊213b‧‧‧上表面215‧‧‧導電構件218‧‧‧間隙220‧‧‧導電柱223‧‧‧終端230‧‧‧第一重佈結構231‧‧‧絕緣層232‧‧‧介電材料233a‧‧‧上表面233b‧‧‧下表面234‧‧‧第一接點235‧‧‧導電部分236‧‧‧第二接點238‧‧‧導線240‧‧‧第二重佈結構243a‧‧‧上表面243b‧‧‧下表面250‧‧‧模製材料251‧‧‧上表面252‧‧‧第三接點254‧‧‧封裝接點254a‧‧‧第四接點254b‧‧‧第五接點353‧‧‧分割道360‧‧‧載體361a‧‧‧正面361b‧‧‧背面362‧‧‧釋放層400‧‧‧半導體晶粒總成490‧‧‧系統492‧‧‧電源494‧‧‧驅動器496‧‧‧處理器498‧‧‧其他子系統/組件D1‧‧‧距離
圖1係繪示根據本發明之一實施例之一半導體裝置的一橫截面圖。
圖2A及圖2B分別係繪示根據本發明之一實施例之一半導體裝置的一橫截面圖及一俯視圖。
圖3A至圖3G係繪示根據本發明之一實施例之製造一半導體裝置之各種階段中之一半導體裝置的橫截面圖。
圖4係包含根據本發明之一實施例所組態之一半導體裝置之一系統之一示意圖。
100‧‧‧半導體裝置
106‧‧‧電連接器
110‧‧‧半導體晶粒
112‧‧‧接合墊
113a‧‧‧正面
113b‧‧‧背面
115‧‧‧導電構件
118‧‧‧間隙
120‧‧‧導電柱
123‧‧‧終端
130‧‧‧重佈結構
131‧‧‧絕緣層
132‧‧‧介電材料
133a‧‧‧第一表面
133b‧‧‧第二表面
134‧‧‧第一接點
136‧‧‧第二接點
138‧‧‧導線
150‧‧‧模製材料
151‧‧‧上表面
152‧‧‧第三接點
D1‧‧‧距離

Claims (29)

  1. 一種半導體裝置，其包括：一重佈結構，其具有一第一側及一第二側，其中該第一側包含數個第一導電接點及數個第二導電接點，其中該等第一導電接點電耦合至該等第二導電接點之對應者，且其中該第二側包括其內無任何導體之一連續絕緣材料層，其中該重佈結構不包含一預形成基板；一半導體晶粒，其定位於該第一側上方且電耦合至該等第一導電接點；一模製材料，其位於該第一側上；及數個導電柱，其等自該第一側延伸而至少部分穿過該模製材料且電耦合至該等第二導電接點之對應者。
  2. 如請求項1之半導體裝置，其進一步包括數個導電構件，其中該等導電構件延伸於該半導體晶粒與該重佈結構之該第一側之間且將該半導體晶粒電耦合至該等第一導電接點。
  3. 如請求項1之半導體裝置，其中該等導電柱在該模製材料中延伸至至少高達該半導體晶粒之一後表面之一高度。
  4. 如請求項1之半導體裝置，其中該重佈結構係一第一重佈結構，且該半導體裝置進一步包括該模製材料之至少一部分上之一第二重佈結構。
  5. 如請求項4之半導體裝置，其中該第二重佈結構包含電耦合至該等導電柱之對應者之數個第三導電接點。
  6. 如請求項5之半導體裝置，其中該第二重佈結構包含電耦合至該等第三導電接點之對應者之數個第四導電接點。
  7. 如請求項6之半導體裝置，其中該等第四導電接點之至少一者至少部分定位於該半導體晶粒之一覆蓋區內。
  8. 如請求項6之半導體裝置，其進一步包括安置於該等第四導電接點上之複數個導電構件。
  9. 如請求項8之半導體裝置，其中該等導電構件係焊球及焊料凸塊之至少一者。
  10. 如請求項1之半導體裝置，其中該模製材料填充該半導體晶粒與該重佈結構之該第一側之間之一空間。
  11. 如請求項1之半導體裝置，其中該等導電柱各具有自該模製材料暴露之一端部分且共同界定第三導電接點。
  12. 如請求項11之半導體裝置，其進一步包括安置於該等第三導電接點上之數個導電構件。
  13. 如請求項12之半導體裝置，其中該等導電構件係焊球或焊料凸塊之至少一者。
  14. 如請求項1之半導體裝置，其中該重佈結構之該第一側包含該半導體晶粒下方之一晶粒附著區域，且其中該等第二導電接點位於該晶粒附著區域外。
  15. 如請求項1之半導體裝置，其中該重佈結構之該第一側包含該半導體晶粒下方之一晶粒附著區域，且其中該等第一接點位於該晶粒附著區域中。
  16. 如請求項1之半導體裝置，其中該模製材料至少部分包圍或接觸該等導電柱及該半導體晶粒。
  17. 如請求項1之半導體裝置，其中該半導體晶粒之一正面自該重佈結構之該第一側隔開以定義其間之一間隙，且其中該模製材料至少部分填充該間隙。
  18. 一種製造一半導體裝置之方法，該方法包括：在一載體上形成一重佈結構，其中該重佈結構包含數個第一導電接點及電耦合至該等第一導電接點之對應者之數個第二導電接點，其中該重佈結構不包含一預形成基板； 形成具有一第一端部分及一第二端部分之數個導電柱，其中該等第一端部分電耦合至該等第二導電接點之對應者；將一半導體晶粒電耦合至該等第一導電接點；在該重佈結構上形成一模製材料，其中該模製材料至少部分包圍該半導體晶粒及該等導電柱，且其中該等導電柱之至少該等第二端部分自該模製材料暴露；及移除該載體。
  19. 如請求項18之方法，其中該重佈結構包含一第一側及與該第一側對置之一第二側，其中該第二側面向該載體且包括其內無任何導體之一連續絕緣材料層。
  20. 如請求項18之方法，其進一步包括：形成電耦合至該重佈結構之該等第一導電接點之對應者之數個導電構件，及其中將該半導體晶粒電耦合至該等第一導電接點包括：將該半導體晶粒電耦合至該等導電構件。
  21. 如請求項18之方法，其中該重佈結構係一第一重佈結構，且該方法進一步包括：在該模製材料之至少一部分上形成一第二重佈結構，其中該等導電柱將該第二重佈結構電耦合至該第一重佈結構。
  22. 如請求項21之方法，其中該第二重佈結構包含數個第三導電接點，且該方法進一步包括：將複數個導電構件安置於該等第三導電接點上。
  23. 如請求項18之方法，其中在該重佈結構上形成該模製材料包含形成該模製材料以接觸該半導體晶粒及該等導電柱。
  24. 一種半導體裝置封裝，其包括：一重佈結構，其包含數個第一導電接點及數個第二導電接點，其中該等第一導電接點電耦合至該等第二導電接點之對應者，其中該重佈結構不包含一預形成基板；一半導體晶粒，其位於該重佈結構上方；數個導電構件，其等將該半導體晶粒電耦合至該等第一導電接點；數個導電柱，其等電耦合至該等第二導電接點之對應者；及一模製材料，其位於該重佈結構上且至少部分包圍該半導體晶粒、該等導電構件及該等導電柱，其中暴露該等導電柱之至少一部分以界定複數個封裝接點。
  25. 如請求項24之半導體裝置封裝，其中該等導電柱具有大於該等導電構件之一高度之一高度。
  26. 如請求項24之半導體裝置封裝，其中該半導體晶粒僅可透過該等封裝接點電接取。
  27. 如請求項24之半導體裝置封裝，其中該等封裝接點係第一封裝接點，且該半導體裝置封裝進一步包括至少部分位於該模製材料上且具有電耦合至該等第一封裝接點之對應者之數個第二封裝接點之一第二重佈結構。
  28. 如請求項27之半導體裝置封裝，其進一步包括安置於該等第二封裝接點上之數個焊球。
  29. 如請求項24之半導體裝置封裝，其中該模製材料接觸該半導體晶粒及該等導體柱。
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