CN112802764A - 封装件及其形成方法 - Google Patents

封装件及其形成方法 Download PDF

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Publication number
CN112802764A
CN112802764A CN202011627702.4A CN202011627702A CN112802764A CN 112802764 A CN112802764 A CN 112802764A CN 202011627702 A CN202011627702 A CN 202011627702A CN 112802764 A CN112802764 A CN 112802764A
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Prior art keywords
chip
coupler
layer
package
couplers
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CN202011627702.4A
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CN112802764B (zh
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李维平
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Shanghai Yibu Semiconductor Co ltd
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Shanghai Yibu Semiconductor Co ltd
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Priority to CN202011627702.4A priority Critical patent/CN112802764B/zh
Publication of CN112802764A publication Critical patent/CN112802764A/zh
Priority to KR1020210177222A priority patent/KR20220097240A/ko
Priority to TW110148083A priority patent/TWI810754B/zh
Priority to US17/566,661 priority patent/US20220208733A1/en
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Publication of CN112802764B publication Critical patent/CN112802764B/zh
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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Abstract

本发明公开了一种封装件及其形成方法。一种形成封装件的方法，所述方法包括：在载体的上方放置芯片层，所述芯片层包括多个芯片联接器和正面朝下的多个芯片，其中在所述多个芯片联接器上方的表面具有多个第一凸点；在所述载体的上方对所述芯片层进行模塑处理以形成塑封结构；对所述塑封结构进行减薄处理，以暴露出所述多个第一凸点；在经减薄的塑封结构上方添加金属层；去除所述载体以形成封装件主体，并在所述封装件主体的下方添加重布线层和第二凸点；以及分割所述封装件主体以形成多个所述封装件。

Description

封装件及其形成方法
技术领域
本发明涉及半导体技术领域，尤其涉及一种封装件及其形成方法。
背景技术
目前，半导体集成电路所需的功能越来越多，所需的计算速度越来越快，在这种形势下，业界已经开始在芯片堆叠技术的研发上增加投入，以探索在芯片堆叠技术中更有效的解决方案。然而，传统的晶圆级封装(WLP)技术无法实现芯片的堆叠。而在传统的芯片堆叠技术中，堆叠大多是在最终组装中完成的，并且需要利用硅片通孔(TSV，ThroughSilicon Via)、玻璃基板通孔(TGV，Through Glass Via)、塑封层通孔(TMV，Through MoldVia)或者引线键合(Wire-bond)等技术来实现堆叠芯片间的竖直联接。传统堆叠技术的封装工艺较复杂并且成本较高。
发明内容
本发明实施例提供一种形成封装件的方案，该封装件包含堆叠的多个芯片。
本发明的第一方面提供了一种形成封装件的方法，所述方法包括：在载体的上方放置芯片层，所述芯片层包括多个芯片联接器和正面朝下的多个芯片，其中在所述多个芯片联接器上方的表面具有多个第一凸点；在所述载体的上方对所述芯片层进行模塑处理以形成塑封结构；对所述塑封结构进行减薄处理，以暴露出所述多个第一凸点；在经减薄的塑封结构上方添加金属层；去除所述载体以形成封装件主体，并在所述封装件主体的下方添加重布线层和第二凸点；以及分割所述封装件主体以形成多个所述封装件。
所述多个芯片联接器可以是有源联接器件或无源联接器件。
所述多个芯片联接器可以被设置成在竖直方向上包含至少一个导电通道。
所述封装件可以包括至少一个被分割的芯片联接器、第一芯片和被分割的金属层，其中，所述第一芯片能够通过所述至少一个被分割的芯片联接器和所述重布线层电联接至所述被分割的金属层。
所述多个芯片联接器由一种或多种半导体材料、一种或多种无机材料、一种或多种有机材料和/或一种或多种金属材料形成。
在所述金属层内可以集成如下电子器件中的一种或多种：I/O端口、无源器件、射频天线、电磁干扰屏蔽器件和散热器件。
所述多个芯片联接器可以由如下的一种或多种半导体材料形成：硅、碳化硅、砷化镓和氮化镓。
所述多个芯片联接器可以由如下的一种或多种无机材料形成：玻璃和陶瓷。
所述多个芯片联接器可以由如下的一种或多种封装基板的制程和材料形成：印刷电路基板、塑封基板和柔性电路基板。
所述多个芯片联接器可以由金属基板的制程和材料形成，所述金属基板采用如下的一种或多种金属材料及其合金材料：铜、铝和铁。
在所述金属层的上方可以放置并组装如下电子器件中的一种或多种：集成电路模块、微机电系统、光电器件和无源器件。
本发明的第一方面提供了一种封装件，包括：重布线层，其包括第一侧和第二侧；多个第一凸点，其设置在所述重布线层的第一侧；芯片，其包括正面和背面，所述芯片正面朝下地放置并组装在所述重布线层的第二侧；至少一个芯片联接器，其包括正面和背面，所述至少一个芯片联接器正面朝下地放置并组装在所述重布线层的第二侧上，并且水平地放置在所述至少一个第一芯片的侧面；多个第二凸点，其设置在所述至少一个芯片联接器的上方；以及金属层，其放置并组装在所述封装件的上方并与所述多个第二凸点中的至少一个电联接，其中，所述封装件被模塑处理成塑封结构。
所述至少一个芯片联接器可以是有源联接器件或无源联接器件。
所述至少一个芯片联接器可以被设置成在竖直方向上包含至少一个导电通道。
所述芯片能够通过所述至少一个芯片联接器和所述重布线层电联接至所述金属层。
所述至少一个芯片联接器可以由一种或多种半导体材料、一种或多种无机材料、一种或多种有机材料和/或一种或多种金属材料形成。
在所述金属层内可以集成如下电子器件中的一种或多种：I/O端口、无源器件、射频天线、电磁干扰屏蔽器件和散热器件。
所述至少一个芯片联接器可以由如下的一种或多种半导体材料形成：硅、碳化硅、砷化镓和氮化镓。
所述至少一个芯片联接器可以由如下的一种或多种无机材料形成：玻璃和陶瓷。
所述至少一个芯片联接器可以由如下的一种或多种封装基板的制程和材料形成：印刷电路基板、塑封基板和柔性电路基板。
所述至少一个芯片联接器可以由金属基板的制程和材料形成，所述金属基板采用如下的一种或多种金属材料及其合金材料：铜、铝和铁。
在所述金属层的上方可以放置并组装如下电子器件中的一种或多种：集成电路模块、微机电系统、光电器件和无源器件。
本发明的第二方面提供了一种形成封装件的方法，所述方法包括：在载体的上方放置至少一个第一芯片层，每个所述第一芯片层包括多个第一芯片联接器、多个第二芯片联接器和正面朝下的多个第一芯片；在所述至少一个第一芯片层的上方放置并组装第二芯片层，所述第二芯片层包括正面朝下的多个第二芯片和多个第三芯片联接器，其中在所述多个第三芯片联接器上方的表面具有多个第一凸点；在所述载体的上方对所述至少一个第一芯片层和所述第二芯片层进行模塑处理以形成塑封结构；对所述塑封结构进行减薄处理，以暴露出所述多个第一凸点；在经减薄的塑封结构上方添加金属层；去除所述载体以形成封装件主体，并在所述封装件主体的下方添加重布线层和第二凸点；以及分割所述封装件主体以形成多个所述封装件。
所述多个第一芯片联接器可以是有源联接器件或无源联接器件，所述多个第二芯片联接器是有源联接器件或无源联接器件，并且所述多个第三芯片联接器是有源联接器件或无源联接器件。
所述多个第一芯片联接器、所述多个第二芯片联接器和所述多个第三芯片联接器可以被设置成在竖直方向上包含至少一个导电通道。
在由位于不同第一芯片层中的多个第一芯片联接器形成的第一芯片联接器堆叠中的每个第一芯片联接器在水平方向上的面积可以不同。
由位于不同第一芯片层中的多个第二芯片联接器形成的第二芯片联接器堆叠与堆叠在所述第二堆叠上的第三芯片联接器能够一体成型。
在所述第二芯片联接器堆叠中的每个第二芯片联接器与堆叠在所述第二芯片联接器堆叠上的第三芯片联接器在水平方向上的面积可以相同。
所述封装件可以包括多个第一凸点、至少一个第一芯片、第二芯片、至少一个被分割的第一芯片联接器、至少一个被分割的第二芯片联接器、被分割的第三芯片联接器和被分割的金属层，其中，所述第二芯片能够通过所述至少一个被分割的第一芯片联接器和所述重布线层电联接至所述至少一个第一芯片，或者所述第二芯片能够通过所述至少一个被分割的第一芯片联接器电联接至所述至少一个第一芯片，其中，所述第二芯片能够通过所述至少一个被分割的第一芯片联接器、所述重布线层、所述至少一个被分割的第二芯片联接器、所述被分割的第三芯片联接器和所述多个第一凸点电联接至所述被分割的金属层，其中，所述至少一个第一芯片能够通过所述重布线层、所述至少一个被分割的第二芯片联接器、所述被分割的第三芯片联接器和所述多个第一凸点电联接至所述被分割的金属层。
所述多个第一芯片联接器、所述多个第二芯片联接器和所述多个第三芯片联接器可以由一种或多种半导体材料、一种或多种无机材料、一种或多种有机材料和/或一种或多种金属材料形成。
在所述金属层内可以集成如下电子器件中的一种或多种：I/O端口、无源器件、射频天线、电磁干扰屏蔽器件和散热器件。
所述多个第一芯片联接器、所述多个第二芯片联接器和所述多个第三芯片联接器可以由如下的一种或多种半导体材料形成：硅、碳化硅、砷化镓和氮化镓。
所述多个第一芯片联接器、所述多个第二芯片联接器和所述多个第三芯片联接器可以由如下的一种或多种无机材料形成：玻璃和陶瓷。
所述多个第一芯片联接器、所述多个第二芯片联接器和所述多个第三芯片联接器可以由如下的一种或多种封装基板的制程和材料形成：印刷电路基板、塑封基板和柔性电路基板。
所述多个第一芯片联接器、所述多个第二芯片联接器和所述多个第三芯片联接器可以由金属基板的制程和材料形成，所述金属基板采用如下的一种或多种金属材料及其合金材料：铜、铝和铁。
在所述金属层的上方可以放置并组装如下电子器件中的一种或多种：集成电路模块、微机电系统、光电器件和无源器件。
本发明的第二方面提供了一种封装件，包括：重布线层，其包括第一侧和第二侧；多个第一凸点，其设置在所述重布线层的第一侧；至少一个第一芯片，其包括正面和背面，其中，由所述至少一个第一芯片形成的芯片堆叠正面朝下地放置并组装在所述重布线层的第二侧；至少一个第一芯片联接器，其包括正面和背面，其中，由所述至少一个第一芯片联接器形成的芯片联接器堆叠正面朝下地放置并组装在所述重布线层的第二侧上，并且水平地放置在所述至少一个第一芯片的一侧；跨层芯片联接器，其放置并组装在所述重布线层的第二侧上，并且水平地放置在所述至少一个第一芯片的另一侧；第二芯片，其包括正面和背面，所述第二芯片正面朝下地放置在所述至少一个第一芯片的背面的上方并组装在所述至少一个第一芯片联接器的上方；多个第二凸点，其设置在所述跨层芯片联接器的上方；以及金属层，其放置在所述封装件的上方并与所述多个第二凸点中的至少一个电联接，其中，所述封装件被模塑处理成塑封结构。
所述至少一个第一芯片联接器可以是有源联接器件或无源联接器件，并且所述跨层芯片联接器是有源联接器件或无源联接器件。
所述至少一个第一芯片联接器和所述跨层芯片联接器可以被设置成在竖直方向上包含至少一个导电通道。
在所述芯片联接器堆叠中的每个第一芯片联接器在水平方向上的面积可以不同。
所述第二芯片能够通过所述至少一个第一芯片联接器和所述重布线层电联接至所述至少一个第一芯片，或者所述第二芯片能够通过所述至少一个第一芯片联接器电联接至所述至少一个第一芯片，其中，所述第二芯片能够通过所述至少一个第一芯片联接器、所述重布线层、所述跨层芯片联接器和所述多个第一凸点电联接至所述金属层，其中，所述至少一个第一芯片能够通过所述重布线层、所述跨层芯片联接器和所述多个第一凸点电联接至所述金属层。
所述至少一个第一芯片联接器和所述跨层芯片联接器可以由一种或多种半导体材料、一种或多种无机材料、一种或多种有机材料和/或一种或多种金属材料形成。
在所述金属层内可以集成如下电子器件中的一种或多种：I/O端口、无源器件、射频天线、电磁干扰屏蔽器件和散热器件。
所述至少一个第一芯片联接器和所述跨层芯片联接器可以由如下的一种或多种半导体材料形成：硅、碳化硅、砷化镓和氮化镓。
所述至少一个第一芯片联接器和所述跨层芯片联接器可以由如下的一种或多种无机材料形成：玻璃和陶瓷。
所述至少一个第一芯片联接器和所述跨层芯片联接器可以由如下的一种或多种封装基板的制程和材料形成：印刷电路基板、塑封基板和柔性电路基板。
所述至少一个第一芯片联接器和所述跨层芯片联接器可以由金属基板的制程和材料形成，所述金属基板采用如下的一种或多种材料金属材料及其合金材料：铜、铝和铁。
在所述金属层的上方可以放置并组装如下电子器件中的一种或多种：集成电路模块、微机电系统、光电器件和无源器件。
本发明的第三方面提供了一种形成封装件的方法，所述方法包括：在载体的上方放置至少一个第一芯片层，每个所述第一芯片层包括多个第一芯片联接器、多个第二芯片联接器和正面朝下的多个第一芯片；在所述第一芯片层的上方放置并组装第二芯片层，所述第二芯片层包括正面朝下的多个第二芯片、多个第三芯片联接器和多个第四芯片联接器，其中在所述多个第三芯片联接器和所述多个第四芯片联接器上方的表面具有多个第一凸点；在所述载体的上方对所述至少一个第一芯片层和所述第二芯片层进行模塑处理以形成塑封结构；对所述塑封结构进行减薄处理，以暴露出所述多个第一凸点；在经减薄的塑封结构上方添加金属层；去除所述载体以形成封装件主体，并在所述封装件主体的下方添加重布线层和第二凸点；以及分割所述封装件主体以形成多个所述封装件。
所述多个第一芯片联接器可以是有源联接器件或无源联接器件，所述多个第二芯片联接器可以是有源联接器件或无源联接器件，所述多个第三芯片联接器可以是有源联接器件或无源联接器件，并且所述多个第四芯片联接器可以是有源联接器件或无源联接器件。
所述多个第一芯片联接器、所述多个第二芯片联接器、所述多个第三芯片联接器和所述多个第四芯片联接器可以被设置成在竖直方向上包含至少一个导电通道。
在由位于不同第一芯片层中的多个第一芯片联接器形成的第一芯片联接器堆叠中的每个第一芯片联接器与堆叠在所述第一芯片联接器堆叠上的第三芯片联接器在水平方向上的面积可以不同。
由位于不同第一芯片层中的多个第二芯片联接器形成的第二芯片联接器堆叠与堆叠在所述第二芯片联接器堆叠上的第四芯片联接器能够一体成型。
在所述第二芯片联接器堆叠中的每个第二芯片联接器与堆叠在所述第二芯片联接器堆叠上的第四芯片联接器在水平方向上的面积可以相同。
所述封装件可以包括至少一个第一芯片、第二芯片、至少一个被分割的第一芯片联接器、至少一个被分割的第二芯片联接器、被分割的第三芯片联接器、被分割的第四芯片联接器和被分割的金属层，其中，所述第二芯片能够通过所述至少一个被分割的第一芯片联接器和所述重布线层电联接至所述第一芯片，其中，所述第二芯片能够通过所述至少一个被分割的第一芯片联接器、所述重布线层、所述至少一个被分割的第二芯片联接器和所述被分割的第四芯片联接器电联接至所述被分割的金属层，其中，所述被分割的金属层能够通过所述被分割的第三芯片联接器、所述至少一个被分割的第一芯片联接器和所述重布线层电联接至所述至少一个第一芯片。
所述多个第一芯片联接器、所述多个第二芯片联接器、所述多个第三芯片联接器和所述多个第四芯片联接器可以由一种或多种半导体材料、一种或多种无机材料、一种或多种有机材料和/或一种或多种金属材料形成。
在所述金属层内可以集成如下电子器件中的一种或多种：I/O端口、无源器件、射频天线、电磁干扰屏蔽器件和散热器件。
所述多个第一芯片联接器、所述多个第二芯片联接器、所述多个第三芯片联接器和所述多个第四芯片联接器可以由如下的一种或多种半导体材料形成：硅、碳化硅、砷化镓和氮化镓。
所述多个第一芯片联接器、所述多个第二芯片联接器、所述多个第三芯片联接器和所述多个第四芯片联接器可以由如下的一种或多种无机材料形成：玻璃和陶瓷。
所述多个第一芯片联接器、所述多个第二芯片联接器、所述多个第三芯片联接器和所述多个第四芯片联接器可以由如下的一种或多种封装基板的制程和材料形成：印刷电路基板、塑封基板和柔性电路基板。
所述多个第一芯片联接器、所述多个第二芯片联接器、所述多个第三芯片联接器和所述多个第四芯片联接器可以由金属基板的制程和材料形成，所述金属基板采用如下的一种或多种金属材料及其合金材料：铜、铝和铁。
在所述金属层的上方可以放置并组装如下电子器件中的一种或多种：集成电路模块、微机电系统、光电器件和无源器件。
本发明的第三方面提供了一种封装件，包括：重布线层，其包括第一侧和第二侧；多个第一凸点，其设置在所述重布线层的第一侧；至少一个第一芯片，其包括正面和背面，其中，由所述至少一个第一芯片形成的芯片堆叠正面朝下地放置并组装在所述重布线层的第二侧；至少一个第一芯片联接器，其包括正面和背面，其中，由所述至少一个第一芯片联接器形成的芯片联接器堆叠正面朝下地放置并组装在所述重布线层的第二侧上，并且水平地放置在所述至少一个第一芯片的一侧；跨层芯片联接器，其放置并组装在所述重布线层的第二侧上，并且水平地放置在所述至少一个第一芯片的另一侧；第二芯片，其包括正面和背面，所述第二芯片正面朝下地放置在所述至少一个第一芯片的背面的上方并组装在所述至少一个第一芯片联接器的上方；第二芯片联接器，其放置并组装在所述至少一个第一芯片联接器的上方；多个第二凸点，其设置在所述第二芯片联接器和所述跨层芯片联接器的上方；以及金属层，其放置并组装在所述封装件的上方并与所述多个第二凸点中的至少一个电联接，其中，所述封装件被模塑处理成塑封结构。
所述至少一个第一芯片联接器可以是有源联接器件或无源联接器件，所述跨层芯片联接器可以是有源联接器件或无源联接器件，并且所述第二芯片联接器可以是有源联接器件或无源联接器件。
所述至少一个第一芯片联接器、所述第二芯片联接器和所述跨层芯片联接器可以被设置成在竖直方向上包含至少一个导电通道。
在所述芯片联接器堆叠中的每个第一芯片联接器与所述芯片联接器堆叠上方的第二芯片联接器在水平方向上的面积可以不同。
所述第二芯片能够通过所述至少一个第一芯片联接器和所述重布线层电联接至所述至少一个第一芯片，其中，所述第二芯片能够通过所述至少一个第一芯片联接器和所述重布线层、所述跨层芯片联接器电联接至所述金属层，其中，所述金属层能够通过所述第二芯片联接器、所述至少一个第一芯片联接器和所述重布线层电联接至所述至少一个第一芯片。
所述至少一个第一芯片联接器、所述第二芯片联接器和所述跨层芯片联接器由一种或多种半导体材料、一种或多种无机材料、一种或多种有机材料和/或一种或多种金属材料形成。
在所述金属层内可以集成如下电子器件中的一种或多种：I/O端口、无源器件、射频天线、电磁干扰屏蔽器件和散热器件。
所述至少一个第一芯片联接器、所述第二芯片联接器和所述跨层芯片联接器可以由如下的一种或多种半导体材料形成：硅、碳化硅、砷化镓和氮化镓。
所述至少一个第一芯片联接器、所述第二芯片联接器和所述跨层芯片联接器可以由如下的一种或多种无机材料形成：玻璃和陶瓷。
所述至少一个第一芯片联接器、所述第二芯片联接器和所述跨层芯片联接器可以由如下的一种或多种封装基板的制程和材料形成：印刷电路基板、塑封基板和柔性电路基板。
所述至少一个第一芯片联接器、所述第二芯片联接器和所述跨层芯片联接器可以由金属基板的制程和材料形成，所述金属基板采用如下的一种或多种金属材料及其合金材料：铜、铝和铁。
在所述金属层的上方可以放置并组装如下电子器件中的一种或多种：集成电路模块、微机电系统、光电器件和无源器件。
本发明的实施例利用芯片联接器和一站式的晶圆级扇出或板级扇出封装工艺实现芯片的堆叠，无需在功能芯片中使用TSV等垂直联接芯片的技术。因此，降低了三维多层芯片封装的复杂度和制造成本。
本发明的实施例还利用在封装件上方的金属层来实现与其他封装件的联接和堆叠，或者利用金属层为封装件集成和添加具有其它功能的电子器件。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其它目的、特征和优点能够更明显易懂，以下特举本发明的具体实施方式。
附图说明
通过参考附图阅读下文的详细描述，本发明示例性实施方式的上述以及其他目的、特征和优点将变得易于理解。在附图中，以示例性而非限制性的方式示出了本发明的若干实施方式，其中：
在附图中，相同或对应的标号表示相同或对应的部分。
图1示出了根据本发明实施例的形成封装件的方法的流程图。
图2至5示出了形成根据本发明第一实施例的封装件的过程的剖面示意图。
图6至9示出了形成根据本发明第二实施例的封装件的过程的剖面示意图。
图10至13示出了形成根据本发明第三实施例的封装件的过程的剖面示意图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”、“在…上方”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。另外，在本文中，术语“组装”是指在各个电子器件之间实现电路联接。术语“芯片”可以指各种类型的芯片，例如逻辑芯片、储存芯片等。
图1示出了根据本发明实施例的形成封装件的方法的流程图。在该方法中包括如下四个步骤：
步骤100：在载体上放置并组装芯片层。
步骤200：对芯片层进行模塑处理以形成塑封结构。
步骤300：对塑封结构进行减薄处理并且在塑封结构上方添加金属层。
步骤400：去除载体以形成封装件主体，添加重布线层和凸点，并且分割封装件主体以形成封装件。
在一些实施例中，载体是表面平整度很高的部件，可以将至少一个芯片层堆叠在载体上。载体可以是晶圆。载体也可以是由任意材料形成的板状部件。例如，板状部件可以是金属板。在一些实施例中，板状部件可以具有任意形状，例如圆形、矩形等。
在对芯片层进行模塑处理后，可以在载体上形成塑封结构。在一些实施例中，用于模塑处理的材料可以包括添加或没有添加硅基或玻璃填料的环氧树脂、有机聚合物或其它化合物为原料的固体或者液体塑封材料。
在一些实施例中，去除载体、添加重布线层和凸点以及分割封装件主体的步骤是晶圆级封装(WLP)和板级扇出封装中已知的步骤。
下面将基于上述方法并参照各个附图说明本发明的各个实施例。
图2至4示出了形成根据本发明第一实施例的封装件的过程的剖面示意图。
图2示出了针对封装结构实施步骤100和步骤200的剖面示意图。
如图2所示，载体100上放置有一个芯片层。芯片层包括多个芯片11和多个芯片联接器15。在一些实施例中，多个芯片11和多个芯片联接器15可以彼此间隔地布置在载体100上。芯片包括正面和背面。在本领域中，具有例如凸点的表面被认为是正面。在一些实施例中，芯片11是正面朝下放置的。
多个芯片联接器15的上方表面可以设置有多个第一凸点14。在一些实施例中，多个第一凸点14可以是金属柱的形式(例如铜柱)。
在本文中，芯片联接器可以用于电联接不同的电子器件，所述电子器件例如包括芯片、重布线层和其他芯片联接器等各种器件；芯片联接器所联接的电子器件通常不与芯片联接器处于相同的芯片层中。在一些实施例中，芯片联接器可以是有源联接器件或无源联接器件。在一些实施例中，芯片联接器在竖直方向上可以具有若干导电通道。导电通道可以联接芯片联接器的上表面和下表面。例如，如图2所示，芯片联接器15可以包含多个通孔12，可以在通孔中填充导电介质形成导电通道。在其他实施例中，也可以通过其他方式形成联接芯片联接器的上表面和下表面的导电通道。在一些实施例中，芯片联接器的上表面和下表面上都可以设置导电线路，从而在一个表面上使得在不同的导电通道之间、在组装至芯片联接器的凸点之间以及在导电通道与凸点之间形成电联接。在下文中将在各个实施例中省略对导电通道的描述。
在本文中，芯片联接器可以由硅、碳化硅、砷化镓、氮化镓以及其他半导体材料形成；芯片联接器可以由玻璃、陶瓷和其他无机材料形成；芯片联接器可以由印刷电路基板(PCB)、塑封基板(EMC)、柔性电路基板、金属基板材料以及其他封装基板的制程和材料形成；金属基板可以采用铜、铝和铁等金属材料及其合金材料。
如图2所示，在载体100上的芯片层已被模塑处理，从而形成了塑封结构16。
图3示出了针对封装结构实施步骤300的剖面示意图。
如图3所示，可以对塑封结构16进行减薄处理，以暴露出多个第一凸点14。然后，在塑封结构16上添加金属层17而使多个第一凸点14与金属层17电联接。在一些实施例中，金属层可以包括多个金属线路，多个金属线路中的至少一个金属线路连接多个第一凸点14中的至少一个第一凸点14。
在本文中，通过在塑封结构上添加金属层，使得可以在金属层内添加各种功能器件(即，具有特定功能的电子器件)。功能器件可以例如是I/O端口、无源器件、射频天线、电磁干扰(EMI)屏蔽器件和散热器件等。在一些实施例中，还可以将某些功能器件组装在金属层的上部。例如，可以将集成电路模块、微机电系统(MEMS)、光电器件、无源器件等电子器件作为组装在金属层的上部的功能器件。
图4示出了针对封装结构实施步骤400的剖面示意图。
如图4所示，可以去除载体100以形成封装件主体。然后，将重布线层18和第二凸点19添加到封装件主体的下方。最后，沿图4中示出的虚线分割封装件主体以形成如图5所示的封装件。请注意，图4所示出的虚线仅仅是示意性的，并且对封装件主体的分割操作也并不仅沿着图4所示出的虚线。
图5示出了根据本发明第一实施例的封装件的剖面示意图。
如图5所示，封装件可以包括一个芯片11和两个被分割的芯片联接器15。可以在封装件的上方放置并组装附加的电子器件150。如上所述，也可以将附加的电子器件150集成到金属层17中。在另一些实施例中，封装结构也可以按其他方式进行分割。例如，封装件可以形成为包含一个芯片11和一个芯片联接器15。
在某些实施例中，形成上述封装件的过程还可以是先去除载体100，然后添加重布线层18和多个第二凸点19。最后，减薄塑封结构16并添加金属层17，从而形成待被分割的封装件主体。
图6至9示出了形成根据本发明第二实施例的封装件的过程的剖面示意图。
图6示出了针对封装结构实施步骤100和步骤200的剖面示意图。
如图6所示，在载体200上放置了三个芯片层。第一芯片层包括多个第一芯片21和多个第一芯片联接器24。第二芯片层包括多个第二芯片22和多个第二芯片联接器25。第三芯片层包括多个第三芯片23。此外，在载体200上还放置有多个跨层芯片联接器201。在跨层芯片联接器201的上方设置有多个第一凸点202。在一些实施例中，多个第一凸点202可以是金属柱的形式(例如铜柱)。
在本文中，跨层芯片联接器在竖直方向上的高度可以与封装件中的所有芯片层的高度相近或一致。例如，如图6所示，跨层芯片联接器201的高度可以与三个芯片层的高度相似或一致。
在本文中，跨层芯片联接器可以是一个完整的芯片联接器，即，跨层芯片联接器可以一体成型。也可以通过将多个芯片联接器堆叠在一起并组装而形成跨层芯片联接器。在剖面示意图中，跨层芯片联接器在水平方向上的宽度可以从上到下是一致的，也可以是不一致的。
在一些实施例中，在放置和组装三个芯片层时，可以首先将多个第一芯片21、多个第一芯片联接器24和多个跨层芯片连接器201放置在载体200上，然后将多个第二芯片22和多个第二芯片联接器25放置并组装在第一芯片11和多个第一芯片联接器24上，最后将多个第三芯片23放置并组装在多个第二芯片22和多个第二芯片联接器25上。在一些实施例中，第一芯片21、第二芯片22和第三芯片23是正面朝下放置的。
在一些实施例中，如图6至9所示的封装结构可以仅包含两个芯片层。例如，可以去掉第一芯片层，只保留第二芯片层和第三芯片层。
在一些实施例中，如图6至9所示的封装结构可以包含多个其他芯片层。多个其他芯片层中的每一层都包含多个芯片和多个其他芯片联接器。所述多个其他芯片联接器可以堆叠并组装在第一芯片联接器24的下方，并且所述多个芯片可以堆叠并组装在第一芯片21的下方。在一些实施例中，在由多层其他芯片联接器、第一芯片联接器24和第二芯片联接器25形成的堆叠中，每层芯片联接器在水平方向上的面积可以不完全相同。例如，在所述堆叠中，任一层中的芯片联接器在水平方向上的面积可以比在该芯片联接器下方的芯片联接器在水平方向上的面积小或大。例如，由各个芯片层中的芯片联接器所形成的堆叠可以具有阶梯形、金字塔形、倒阶梯形或倒金字塔形等。在一些实施例中，由各个芯片层中的芯片联接器所形成的堆叠也可以是一体成型的。
如图6所示，在载体200上的第一芯片层、第二芯片层和第三芯片层已被模塑处理，从而形成了塑封结构26。
在本文中，在不同的芯片层之间还可以设置粘合点(adhesive dot)(例如，图6-9中的粘合点203)。粘合点用于隔离和固定不同的芯片层。在一些实施例中，粘合点由非导电介质制成。在下文中，将省略对粘合点的描述。
图7示出了针对封装结构实施步骤300的剖面示意图。
如图7所示，可以对塑封结构26进行减薄处理，以暴露出多个第一凸点202。然后，在塑封结构26上添加金属层27而使多个第一凸点202与金属层27电联接。在一些实施例中，金属层可以包括多个金属线路，多个金属线路中的至少一个金属线路连接多个第一凸点202中的至少一个第一凸点。
图8示出了针对封装结构实施步骤400的剖面示意图。
如图8所示，可以去除载体200以形成封装件主体。然后，将重布线层28和第二凸点29添加到封装件主体的下方。最后，沿图8中示出的虚线分割封装件主体以形成如图9所示的封装件。请注意，图8所示出的虚线仅仅是示意性的，并且对封装件主体的分割操作也并不仅沿着图8所示出的虚线。
图9示出了根据本发明第二实施例的封装件的剖面示意图。
如图9所示，封装件可以包括第一芯片21、第二芯片22、第三芯片23、被分割的第一芯片联接器24、被分割的跨层芯片联接器201和被分割的第二芯片联接器25。可以在封装件的上方放置并组装附加的电子器件250。如上所述，也可以将附加的电子器件250集成到金属层27中。在另一些实施例中，封装结构也可以按其他方式进行分割。
在另一些实施例中，形成上述封装件的过程还可以是先去除载体200，然后添加重布线层28和多个第二凸点29。最后，减薄塑封结构26并添加金属层27，从而形成待被分割的封装件主体。
图10至13示出了形成根据本发明第三实施例的封装件的过程的剖面示意图。
图10示出了针对封装结构实施步骤100和步骤200的剖面示意图。
如图10所示，在载体300上放置了两个芯片层。第一芯片层包括多个第一芯片31和多个第一芯片联接器33。第二芯片层包括多个第二芯片32和多个第二芯片联接器34。此外，在载体300上还放置有多个跨层芯片联接器301。在跨层芯片联接器301和和多个第二芯片联接器34的上方设置有多个第一凸点302。在一些实施例中，多个第一凸点302可以是金属柱的形式(例如铜柱)。在第一芯片31和第二芯片32之间可以设置粘合点303。
在本文中，跨层芯片联接器在竖直方向上的高度可以与封装件中的所有芯片层的高度相近或一致。例如，如图10所示，跨层芯片联接器301的高度可以与两个芯片层的高度相似或一致。
在一些实施例中，在放置和组装两个芯片层时，可以首先将多个第一芯片31、多个第一芯片联接器33和多个跨层芯片连接器301放置在载体300上，然后将多个第二芯片32和多个第二芯片联接器35放置并组装在第一芯片31和多个第一芯片联接器33上。在一些实施例中，第一芯片31和第二芯片32是正面朝下放置的。
在一些实施例中，如图10至13所示的封装结构可以包含多个其他芯片层。多个其他芯片层中的每一层都包含多个芯片和多个其他芯片联接器。所述多个其他芯片联接器可以堆叠并组装在第一芯片联接器33的下方，并且所述多个芯片可以堆叠并组装在第一芯片31的下方。在一些实施例中，在由多层其他芯片联接器、第一芯片联接器33和第二芯片联接器34形成的堆叠中，每层芯片联接器在水平方向上的面积可以不完全相同。例如，在所述堆叠中，任一层中的芯片联接器在水平方向上的面积可以比在该芯片联接器下方的芯片联接器在水平方向上的面积小或大。例如，由各个芯片层中的芯片联接器所形成的堆叠可以具有阶梯形、金字塔形、倒阶梯形或倒金字塔形等。在一些实施例中，由各个芯片层中的芯片联接器所形成的堆叠也可以是一体成型的。
如图10所示，在载体300上的第一芯片层和第二芯片层已被模塑处理，从而形成了塑封结构36。
图11示出了针对封装结构实施步骤300的剖面示意图。
如图11所示，可以对塑封结构36进行减薄处理，以暴露出多个第一凸点302。然后，在塑封结构36上添加金属层37而使多个第一凸点302与金属层37电联接。在一些实施例中，金属层可以包括多个金属线路，多个金属线路中的至少一个金属线路连接多个第一凸点302中的至少一个第一凸点。
图12示出了针对封装结构实施步骤400的剖面示意图。
如图12所示，可以去除载体300以形成封装件主体。然后，将重布线层38和第二凸点39添加到封装件主体的下方。最后，沿图12中示出的虚线分割封装件主体以形成如图13所示的封装件。请注意，图12所示出的虚线仅仅是示意性的，并且对封装件主体的分割操作也并不仅沿着图12所示出的虚线。
图13示出了根据本发明第二实施例的封装件的剖面示意图。
如图13所示，封装件可以包括第一芯片31、第二芯片32、被分割的第一芯片联接器33、被分割的跨层芯片联接器301和被分割的第二芯片联接器34。可以在封装件的上方放置并组装附加的电子器件350。如上所述，也可以将附加的电子器件350集成到金属层37中。在另一些实施例中，封装结构也可以按其他方式进行分割。
在另一些实施例中，形成上述封装件的过程还可以是先去除载体300，然后添加重布线层38和多个第二凸点39。最后，减薄塑封结构36并添加金属层37，从而形成待被分割的封装件主体。
在本文中，在不改变该封装件中的各部件之间的联接关系的前提下，各个芯片和芯片联接器的称谓可以并非如上所定义的。例如，可以将第一芯片、第二芯片或第三芯片的称谓彼此交换，可以将第一芯片联接器、第二芯片联接器、第三芯片联接器和第四芯片联接器的称谓彼此交换，并且也可以将第一凸点和第二凸点的称谓彼此交换。
在本发明的各个实施例中，在封装件中的各个芯片不仅可以利用芯片联接器、重布线层和/或金属层彼此互联，还可以利用芯片联接器、金属层、重布线层和/或凸点联接到封装件外部的各种电路结构和电子器件。
如本领域技术人员所公知的，凸点可以由导电材料或焊料制成，导电材料包括Cu、Ni、Au、Ag等或其它合金材料，也可以包括其他材料。在一些实施例中，凸点可以是焊盘或为柱形形状(例如铜柱)，也可以具有其他可能的形式。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的各个方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (38)

1.一种形成封装件的方法，所述方法包括：
在载体的上方放置芯片层，所述芯片层包括多个芯片联接器和正面朝下的多个芯片，其中在所述多个芯片联接器上方的表面具有多个第一凸点；
在所述载体的上方对所述芯片层进行模塑处理以形成塑封结构；
对所述塑封结构进行减薄处理，以暴露出所述多个第一凸点；
在经减薄的塑封结构上方添加金属层；
去除所述载体以形成封装件主体，并在所述封装件主体的下方添加重布线层和第二凸点；和
分割所述封装件主体以形成多个所述封装件。
2.根据权利要求1所述的方法，其中，所述多个芯片联接器是有源联接器件或无源联接器件，并且其中，所述多个芯片联接器被设置成在竖直方向上包含至少一个导电通道。
3.根据权利要求1所述的方法，其中，所述封装件包括至少一个被分割的芯片联接器、第一芯片和被分割的金属层，其中，所述第一芯片能够通过所述至少一个被分割的芯片联接器和所述重布线层电联接至所述被分割的金属层。
4.根据权利要求1所述的方法，其中，所述多个芯片联接器由一种或多种半导体材料、一种或多种无机材料、一种或多种有机材料和/或一种或多种金属材料形成。
5.根据权利要求1所述的方法，其中，在所述金属层内集成如下电子器件中的一种或多种：I/O端口、无源器件、射频天线、电磁干扰屏蔽器件和散热器件；和/或其中，在所述金属层的上方放置并组装如下电子器件中的一种或多种：集成电路模块、微机电系统、光电器件和无源器件。
6.一种封装件，包括：
重布线层，其包括第一侧和第二侧；
多个第一凸点，其设置在所述重布线层的第一侧；
芯片，其包括正面和背面，所述芯片正面朝下地放置并组装在所述重布线层的第二侧；
至少一个芯片联接器，其包括正面和背面，所述至少一个芯片联接器正面朝下地放置并组装在所述重布线层的第二侧上，并且水平地放置在所述至少一个第一芯片的侧面；
多个第二凸点，其设置在所述至少一个芯片联接器的上方；和
金属层，其放置并组装在所述封装件的上方并与所述多个第二凸点中的至少一个电联接，
其中，所述封装件被模塑处理成塑封结构。
7.根据权利要求6所述的封装件，其中，所述至少一个芯片联接器是有源联接器件或无源联接器件，并且其中，所述至少一个芯片联接器被设置成在竖直方向上包含至少一个导电通道。
8.根据权利要求6所述的封装件，其中，所述芯片能够通过所述至少一个芯片联接器和所述重布线层电联接至所述金属层。
9.根据权利要求6所述的封装件，其中，所述至少一个芯片联接器由一种或多种半导体材料、一种或多种无机材料、一种或多种有机材料和/或一种或多种金属材料形成。
10.根据权利要求6所述的封装件，其中，在所述金属层内集成如下电子器件中的一种或多种：I/O端口、无源器件、射频天线、电磁干扰屏蔽器件和散热器件；和/或其中，在所述金属层的上方放置并组装如下电子器件中的一种或多种：集成电路模块、微机电系统、光电器件和无源器件。
11.一种形成封装件的方法，所述方法包括：
在载体的上方放置至少一个第一芯片层，每个所述第一芯片层包括多个第一芯片联接器、多个第二芯片联接器和正面朝下的多个第一芯片；
在所述至少一个第一芯片层的上方放置并组装第二芯片层，所述第二芯片层包括正面朝下的多个第二芯片和多个第三芯片联接器，其中在所述多个第三芯片联接器上方的表面具有多个第一凸点；
在所述载体的上方对所述至少一个第一芯片层和所述第二芯片层进行模塑处理以形成塑封结构；
对所述塑封结构进行减薄处理，以暴露出所述多个第一凸点；
在经减薄的塑封结构上方添加金属层；
去除所述载体以形成封装件主体，并在所述封装件主体的下方添加重布线层和第二凸点；和
分割所述封装件主体以形成多个所述封装件。
12.根据权利要求11所述的方法，其中，所述多个第一芯片联接器是有源联接器件或无源联接器件，所述多个第二芯片联接器是有源联接器件或无源联接器件，并且所述多个第三芯片联接器是有源联接器件或无源联接器件，并且其中，所述多个第一芯片联接器、所述多个第二芯片联接器和所述多个第三芯片联接器被设置成在竖直方向上包含至少一个导电通道。
13.根据权利要求11所述的方法，其中，在由位于不同第一芯片层中的多个第一芯片联接器形成的第一芯片联接器堆叠中的每个第一芯片联接器在水平方向上的面积不同。
14.根据权利要求11所述的方法，其中，由位于不同第一芯片层中的多个第二芯片联接器形成的第二芯片联接器堆叠与堆叠在所述第二堆叠上的第三芯片联接器能够一体成型。
15.根据权利要求11所述的方法，其中，在所述第二芯片联接器堆叠中的每个第二芯片联接器与堆叠在所述第二芯片联接器堆叠上的第三芯片联接器在水平方向上的面积相同。
16.根据权利要求11所述的方法，其中，所述封装件包括多个第一凸点、至少一个第一芯片、第二芯片、至少一个被分割的第一芯片联接器、至少一个被分割的第二芯片联接器、被分割的第三芯片联接器和被分割的金属层，
其中，所述第二芯片能够通过所述至少一个被分割的第一芯片联接器和所述重布线层电联接至所述至少一个第一芯片，或者所述第二芯片能够通过所述至少一个被分割的第一芯片联接器电联接至所述至少一个第一芯片，
其中，所述第二芯片能够通过所述至少一个被分割的第一芯片联接器、所述重布线层、所述至少一个被分割的第二芯片联接器、所述被分割的第三芯片联接器和所述多个第一凸点电联接至所述被分割的金属层，
其中，所述至少一个第一芯片能够通过所述重布线层、所述至少一个被分割的第二芯片联接器、所述被分割的第三芯片联接器和所述多个第一凸点电联接至所述被分割的金属层。
17.根据权利要求11所述的方法，其中，所述多个第一芯片联接器、所述多个第二芯片联接器和所述多个第三芯片联接器由一种或多种半导体材料、一种或多种无机材料、一种或多种有机材料和/或一种或多种金属材料形成。
18.根据权利要求11所述的方法，其中，在所述金属层内集成如下电子器件中的一种或多种：I/O端口、无源器件、射频天线、电磁干扰屏蔽器件和散热器件；和/或其中，在所述金属层的上方放置并组装如下电子器件中的一种或多种：集成电路模块、微机电系统、光电器件和无源器件。
19.一种封装件，包括：
重布线层，其包括第一侧和第二侧；
多个第一凸点，其设置在所述重布线层的第一侧；
至少一个第一芯片，其包括正面和背面，其中，由所述至少一个第一芯片形成的芯片堆叠正面朝下地放置并组装在所述重布线层的第二侧；
至少一个第一芯片联接器，其包括正面和背面，其中，由所述至少一个第一芯片联接器形成的芯片联接器堆叠正面朝下地放置并组装在所述重布线层的第二侧上，并且水平地放置在所述至少一个第一芯片的一侧；
跨层芯片联接器，其放置并组装在所述重布线层的第二侧上，并且水平地放置在所述至少一个第一芯片的另一侧；
第二芯片，其包括正面和背面，所述第二芯片正面朝下地放置在所述至少一个第一芯片的背面的上方并组装在所述至少一个第一芯片联接器的上方；
多个第二凸点，其设置在所述跨层芯片联接器的上方；和
金属层，其放置在所述封装件的上方并与所述多个第二凸点中的至少一个电联接，
其中，所述封装件被模塑处理成塑封结构。
20.根据权利要求19所述的封装件，其中，所述至少一个第一芯片联接器是有源联接器件或无源联接器件，并且所述跨层芯片联接器是有源联接器件或无源联接器件，并且其中，所述至少一个第一芯片联接器和所述跨层芯片联接器被设置成在竖直方向上包含至少一个导电通道。
21.根据权利要求19所述的封装件，其中，在所述芯片联接器堆叠中的每个第一芯片联接器在水平方向上的面积不同。
22.根据权利要求19所述的封装件，其中，所述第二芯片能够通过所述至少一个第一芯片联接器和所述重布线层电联接至所述至少一个第一芯片，或者所述第二芯片能够通过所述至少一个第一芯片联接器电联接至所述至少一个第一芯片，
其中，所述第二芯片能够通过所述至少一个第一芯片联接器、所述重布线层、所述跨层芯片联接器和所述多个第一凸点电联接至所述金属层，
其中，所述至少一个第一芯片能够通过所述重布线层、所述跨层芯片联接器和所述多个第一凸点电联接至所述金属层。
23.根据权利要求19所述的封装件，其中，所述至少一个第一芯片联接器和所述跨层芯片联接器由一种或多种半导体材料、一种或多种无机材料、一种或多种有机材料和/或一种或多种金属材料形成。
24.根据权利要求19所述的封装件，其中，在所述金属层内集成如下电子器件中的一种或多种：I/O端口、无源器件、射频天线、电磁干扰屏蔽器件和散热器件；和/或其中，在所述金属层的上方放置并组装如下电子器件中的一种或多种：集成电路模块、微机电系统、光电器件和无源器件。
25.一种形成封装件的方法，所述方法包括：
在载体的上方放置至少一个第一芯片层，每个所述第一芯片层包括多个第一芯片联接器、多个第二芯片联接器和正面朝下的多个第一芯片；
在所述第一芯片层的上方放置并组装第二芯片层，所述第二芯片层包括正面朝下的多个第二芯片、多个第三芯片联接器和多个第四芯片联接器，其中在所述多个第三芯片联接器和所述多个第四芯片联接器上方的表面具有多个第一凸点；
在所述载体的上方对所述至少一个第一芯片层和所述第二芯片层进行模塑处理以形成塑封结构；
对所述塑封结构进行减薄处理，以暴露出所述多个第一凸点；
在经减薄的塑封结构上方添加金属层；
去除所述载体以形成封装件主体，并在所述封装件主体的下方添加重布线层和第二凸点；和
分割所述封装件主体以形成多个所述封装件。
26.根据权利要求25所述的方法，其中，所述多个第一芯片联接器是有源联接器件或无源联接器件，所述多个第二芯片联接器是有源联接器件或无源联接器件，所述多个第三芯片联接器是有源联接器件或无源联接器件，并且所述多个第四芯片联接器是有源联接器件或无源联接器件，并且其中，所述多个第一芯片联接器、所述多个第二芯片联接器、所述多个第三芯片联接器和所述多个第四芯片联接器被设置成在竖直方向上包含至少一个导电通道。
27.根据权利要求25所述的方法，其中，在由位于不同第一芯片层中的多个第一芯片联接器形成的第一芯片联接器堆叠中的每个第一芯片联接器与堆叠在所述第一芯片联接器堆叠上的第三芯片联接器在水平方向上的面积不同。
28.根据权利要求25所述的方法，其中，由位于不同第一芯片层中的多个第二芯片联接器形成的第二芯片联接器堆叠与堆叠在所述第二芯片联接器堆叠上的第四芯片联接器能够一体成型。
29.根据权利要求28所述的方法，其中，在所述第二芯片联接器堆叠中的每个第二芯片联接器与堆叠在所述第二芯片联接器堆叠上的第四芯片联接器在水平方向上的面积相同。
30.根据权利要求25所述的方法，其中，所述封装件包括至少一个第一芯片、第二芯片、至少一个被分割的第一芯片联接器、至少一个被分割的第二芯片联接器、被分割的第三芯片联接器、被分割的第四芯片联接器和被分割的金属层，
其中，所述第二芯片能够通过所述至少一个被分割的第一芯片联接器和所述重布线层电联接至所述第一芯片，
其中，所述第二芯片能够通过所述至少一个被分割的第一芯片联接器、所述重布线层、所述至少一个被分割的第二芯片联接器和所述被分割的第四芯片联接器电联接至所述被分割的金属层，
其中，所述被分割的金属层能够通过所述被分割的第三芯片联接器、所述至少一个被分割的第一芯片联接器和所述重布线层电联接至所述至少一个第一芯片。
31.根据权利要求25所述的方法，其中，所述多个第一芯片联接器、所述多个第二芯片联接器、所述多个第三芯片联接器和所述多个第四芯片联接器由一种或多种半导体材料、一种或多种无机材料、一种或多种有机材料和/或一种或多种金属材料形成。
32.根据权利要求25所述的方法，其中，在所述金属层内集成如下电子器件中的一种或多种：I/O端口、无源器件、射频天线、电磁干扰屏蔽器件和散热器件；和/或其中，在所述金属层的上方放置并组装如下电子器件中的一种或多种：集成电路模块、微机电系统、光电器件和无源器件。
33.一种封装件，包括：
重布线层，其包括第一侧和第二侧；
多个第一凸点，其设置在所述重布线层的第一侧；
至少一个第一芯片，其包括正面和背面，其中，由所述至少一个第一芯片形成的芯片堆叠正面朝下地放置并组装在所述重布线层的第二侧；
至少一个第一芯片联接器，其包括正面和背面，其中，由所述至少一个第一芯片联接器形成的芯片联接器堆叠正面朝下地放置并组装在所述重布线层的第二侧上，并且水平地放置在所述至少一个第一芯片的一侧；
跨层芯片联接器，其放置并组装在所述重布线层的第二侧上，并且水平地放置在所述至少一个第一芯片的另一侧；
第二芯片，其包括正面和背面，所述第二芯片正面朝下地放置在所述至少一个第一芯片的背面的上方并组装在所述至少一个第一芯片联接器的上方；
第二芯片联接器，其放置并组装在所述至少一个第一芯片联接器的上方；
多个第二凸点，其设置在所述第二芯片联接器和所述跨层芯片联接器的上方；和
金属层，其放置并组装在所述封装件的上方并与所述多个第二凸点中的至少一个电联接，
其中，所述封装件被模塑处理成塑封结构。
34.根据权利要求33所述的封装件，其中，所述至少一个第一芯片联接器是有源联接器件或无源联接器件，所述跨层芯片联接器是有源联接器件或无源联接器件，并且所述第二芯片联接器是有源联接器件或无源联接器件，并且其中，所述至少一个第一芯片联接器、所述第二芯片联接器和所述跨层芯片联接器被设置成在竖直方向上包含至少一个导电通道。
35.根据权利要求33所述的封装件，其中，在所述芯片联接器堆叠中的每个第一芯片联接器与所述芯片联接器堆叠上方的第二芯片联接器在水平方向上的面积不同。
36.根据权利要求33所述的封装件，其中，所述第二芯片能够通过所述至少一个第一芯片联接器和所述重布线层电联接至所述至少一个第一芯片，
其中，所述第二芯片能够通过所述至少一个第一芯片联接器和所述重布线层、所述跨层芯片联接器电联接至所述金属层，
其中，所述金属层能够通过所述第二芯片联接器、所述至少一个第一芯片联接器和所述重布线层电联接至所述至少一个第一芯片。
37.根据权利要求33所述的封装件，其中，所述至少一个第一芯片联接器、所述第二芯片联接器和所述跨层芯片联接器由一种或多种半导体材料、一种或多种无机材料、一种或多种有机材料和/或一种或多种金属材料形成。
38.根据权利要求33所述的封装件，其中，在所述金属层内集成如下电子器件中的一种或多种：I/O端口、无源器件、射频天线、电磁干扰屏蔽器件和散热器件；和/或其中，在所述金属层的上方放置并组装如下电子器件中的一种或多种：集成电路模块、微机电系统、光电器件和无源器件。
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