TWI810754B - 封裝件及其形成方法 - Google Patents

封裝件及其形成方法 Download PDF

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Publication number
TWI810754B
TWI810754B TW110148083A TW110148083A TWI810754B TW I810754 B TWI810754 B TW I810754B TW 110148083 A TW110148083 A TW 110148083A TW 110148083 A TW110148083 A TW 110148083A TW I810754 B TWI810754 B TW I810754B
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Taiwan
Prior art keywords
die
coupler
wafer
layer
couplers
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TW110148083A
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English (en)
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TW202228215A (zh
Inventor
維平 李
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大陸商上海易卜半導體有限公司
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Publication of TW202228215A publication Critical patent/TW202228215A/zh
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Abstract

本發明公開了一種封裝件及其形成方法。一種形成封裝件的方法，所述方法包括：在載體的上方放置晶片層，所述晶片層包括多個晶片聯接器和正面朝下的多個晶片，其中在所述多個晶片聯接器上方的表面具有多個第一凸點；在所述載體的上方對所述晶片層進行模塑處理以形成塑封結構；對所述塑封結構進行減薄處理，以暴露出所述多個第一凸點；在經減薄的塑封結構上方添加金屬層；去除所述載體以形成封裝件主體，並在所述封裝件主體的下方添加重佈線層和第二凸點；以及分割所述封裝件主體以形成多個所述封裝件。

Description

封裝件及其形成方法
本發明涉及半導體技術領域，尤其涉及一種封裝件及其形成方法。
目前，半導體積體電路所需的功能越來越多，所需的計算速度越來越快，在這種形勢下，業界已經開始在晶片堆疊技術的研發上增加投入，以探索在晶片堆疊技術中更有效的解決方案。然而，傳統的晶圓級封裝(WLP)技術無法實現晶片的堆疊。而在傳統的晶片堆疊技術中，堆疊大多是在最終組裝中完成的，並且需要利用矽片通孔(TSV，Through Silicon Via)、玻璃基板通孔(TGV，Through Glass Via)、塑封層通孔(TMV，Through Mold Via)或者引線鍵合(Wire-bond)等技術來實現堆疊晶片間的豎直聯接。傳統堆疊技術的封裝工藝較複雜並且成本較高。
本發明實施例提供一種形成封裝件的方案，該封裝件包含堆疊的多個晶片。
本發明的第一方面提供了一種形成封裝件的方法，所述方法包括：在載體的上方放置晶片層，所述晶片層包括多個晶片聯接器和正面朝下的多個晶片，其中在所述多個晶片聯接器上方的表面具有多個第一凸點；在所述載體的上方對所述晶片層進行模塑處理以形成塑封結構；對所述塑封結構進行減薄處理，以暴露出所述多個第一凸點；在經減薄的塑封結構上方添加金屬層；去除 所述載體以形成封裝件主體，並在所述封裝件主體的下方添加重佈線層和第二凸點；以及分割所述封裝件主體以形成多個所述封裝件。
所述多個晶片聯接器可以是有源聯接器件或無源聯接器件。
所述多個晶片聯接器可以被設置成在豎直方向上包含至少一個導電通道。
所述封裝件可以包括至少一個被分割的晶片聯接器、晶片和被分割的金屬層，其中，所述晶片能夠通過所述至少一個被分割的晶片聯接器和所述重佈線層電聯接至所述被分割的金屬層。
所述多個晶片聯接器由一種或多種半導體材料、一種或多種無機材料、一種或多種有機材料和/或一種或多種金屬材料形成。
在所述金屬層內可以集成如下電子器件中的一種或多種：I/O埠、無源器件、射頻天線、電磁干擾遮罩器件和散熱器件。
所述多個晶片聯接器可以由如下的一種或多種半導體材料形成：矽、碳化矽、砷化鎵和氮化鎵。
所述多個晶片聯接器可以由如下的一種或多種無機材料形成：玻璃和陶瓷。
所述多個晶片聯接器可以由如下的一種或多種封裝基板的制程和材料形成：印刷電路基板、塑封基板和柔性電路基板。
所述多個晶片聯接器可以由金屬基板的制程和材料形成，所述金屬基板採用如下的一種或多種金屬材料及其合金材料：銅、鋁和鐵。
在所述金屬層的上方可以放置並組裝如下電子器件中的一種或多種：積體電路模組、微機電系統、光電器件和無源器件。
本發明的第一方面提供了一種封裝件，包括：重佈線層，其包括第一側和第二側；多個第一凸點，其設置在所述重佈線層的第一側；晶片，其包括正面和背面，所述晶片正面朝下地放置並組裝在所述重佈線層的第二側；至少一個晶片聯接器，其放置並組裝在所述重佈線層的第二側上，並且水平地放置在所述至少一個第一晶片的側面；多個第二凸點，其設置在所述至少一個晶片聯接器的上方；以及金屬層，其放置並組裝在所述封裝件的上方並與所述多個第二凸點中的至少一個電聯接，其中，所述封裝件被模塑處理成塑封結構。
所述至少一個晶片聯接器可以是有源聯接器件或無源聯接器件。
所述至少一個晶片聯接器可以被設置成在豎直方向上包含至少一個導電通道。
所述晶片能夠通過所述至少一個晶片聯接器和所述重佈線層電聯接至所述金屬層。
所述至少一個晶片聯接器可以由一種或多種半導體材料、一種或多種無機材料、一種或多種有機材料和/或一種或多種金屬材料形成。
在所述金屬層內可以集成如下電子器件中的一種或多種：I/O埠、無源器件、射頻天線、電磁干擾遮罩器件和散熱器件。
所述至少一個晶片聯接器可以由如下的一種或多種半導體材料形成：矽、碳化矽、砷化鎵和氮化鎵。
所述至少一個晶片聯接器可以由如下的一種或多種無機材料形成：玻璃和陶瓷。
所述至少一個晶片聯接器可以由如下的一種或多種封裝基板的制程和材料形成：印刷電路基板、塑封基板和柔性電路基板。
所述至少一個晶片聯接器可以由金屬基板的制程和材料形成，所述金屬基板採用如下的一種或多種金屬材料及其合金材料：銅、鋁和鐵。
在所述金屬層的上方可以放置並組裝如下電子器件中的一種或多種：積體電路模組、微機電系統、光電器件和無源器件。
本發明的第二方面提供了一種形成封裝件的方法，所述方法包括：在載體的上方放置至少一個第一晶片層，每個所述第一晶片層包括多個第一晶片聯接器、多個第二晶片聯接器和正面朝下的多個第一晶片；在所述至少一個第一晶片層的上方放置並組裝第二晶片層，所述第二晶片層包括正面朝下的多個第二晶片和多個第三晶片聯接器，其中在所述多個第三晶片聯接器上方的表面具有多個第一凸點；在所述載體的上方對所述至少一個第一晶片層和所述第二晶片層進行模塑處理以形成塑封結構；對所述塑封結構進行減薄處理，以暴露出所述多個第一凸點；在經減薄的塑封結構上方添加金屬層；去除所述載體以形成封裝件主體，並在所述封裝件主體的下方添加重佈線層和第二凸點；以及分割所述封裝件主體以形成多個所述封裝件。
所述多個第一晶片聯接器可以是有源聯接器件或無源聯接器件，所述多個第二晶片聯接器是有源聯接器件或無源聯接器件，並且所述多個第三晶片聯接器是有源聯接器件或無源聯接器件。
所述多個第一晶片聯接器、所述多個第二晶片聯接器和所述多個第三晶片聯接器可以被設置成在豎直方向上包含至少一個導電通道。
在由位於不同第一晶片層中的多個第一晶片聯接器形成的第一晶片聯接器堆疊中的每個第一晶片聯接器在水平方向上的面積可以不同。
由位於不同第一晶片層中的多個第二晶片聯接器形成的第二晶片聯接器堆疊與堆疊在所述第二堆疊上的第三晶片聯接器能夠一體成型。
在所述第二晶片聯接器堆疊中的每個第二晶片聯接器與堆疊在所述第二晶片聯接器堆疊上的第三晶片聯接器在水平方向上的面積可以相同。
所述封裝件可以包括多個第一凸點、至少一個第一晶片、第二晶片、至少一個被分割的第一晶片聯接器、至少一個被分割的第二晶片聯接器、被分割的第三晶片聯接器和被分割的金屬層，其中，所述第二晶片能夠通過所述至少一個被分割的第一晶片聯接器和所述重佈線層電聯接至所述至少一個第一晶片，或者所述第二晶片能夠通過所述至少一個被分割的第一晶片聯接器電聯接至所述至少一個第一晶片，其中，所述第二晶片能夠通過所述至少一個被分割的第一晶片聯接器、所述重佈線層、所述至少一個被分割的第二晶片聯接器、所述被分割的第三晶片聯接器和所述多個第一凸點電聯接至所述被分割的金屬層，其中，所述至少一個第一晶片能夠通過所述重佈線層、所述至少一個被分割的第二晶片聯接器、所述被分割的第三晶片聯接器和所述多個第一凸點電聯接至所述被分割的金屬層。
所述多個第一晶片聯接器、所述多個第二晶片聯接器和所述多個第三晶片聯接器可以由一種或多種半導體材料、一種或多種無機材料、一種或多種有機材料和/或一種或多種金屬材料形成。
在所述金屬層內可以集成如下電子器件中的一種或多種：I/O埠、無源器件、射頻天線、電磁干擾遮罩器件和散熱器件。
所述多個第一晶片聯接器、所述多個第二晶片聯接器和所述多個第三晶片聯接器可以由如下的一種或多種半導體材料形成：矽、碳化矽、砷化鎵和氮化鎵。
所述多個第一晶片聯接器、所述多個第二晶片聯接器和所述多個第三晶片聯接器可以由如下的一種或多種無機材料形成：玻璃和陶瓷。
所述多個第一晶片聯接器、所述多個第二晶片聯接器和所述多個第三晶片聯接器可以由如下的一種或多種封裝基板的制程和材料形成：印刷電路基板、塑封基板和柔性電路基板。
所述多個第一晶片聯接器、所述多個第二晶片聯接器和所述多個第三晶片聯接器可以由金屬基板的制程和材料形成，所述金屬基板採用如下的一種或多種金屬材料及其合金材料：銅、鋁和鐵。
在所述金屬層的上方可以放置並組裝如下電子器件中的一種或多種：積體電路模組、微機電系統、光電器件和無源器件。
本發明的第二方面提供了一種封裝件，包括：重佈線層，其包括第一側和第二側；多個第一凸點，其設置在所述重佈線層的第一側；至少一個第一晶片，其包括正面和背面，其中，由所述至少一個第一晶片形成的晶片堆疊正面朝下地放置並組裝在所述重佈線層的第二側；至少一個第一晶片聯接器，其中，由所述至少一個第一晶片聯接器形成的晶片聯接器堆疊放置並組裝在所述重佈線層的第二側上，並且水平地放置在所述至少一個第一晶片的一側；跨層晶片聯接器，其放置並組裝在所述重佈線層的第二側上，並且水平地放置在所述至少一個第一晶片的另一側；第二晶片，其包括正面和背面，所述第二晶片正面朝下地放置在所述至少一個第一晶片的背面的上方並組裝在所述至少一 個第一晶片聯接器的上方；多個第二凸點，其設置在所述跨層晶片聯接器的上方；以及金屬層，其放置在所述封裝件的上方並與所述多個第二凸點中的至少一個電聯接，其中，所述封裝件被模塑處理成塑封結構。
所述至少一個第一晶片聯接器可以是有源聯接器件或無源聯接器件，並且所述跨層晶片聯接器是有源聯接器件或無源聯接器件。
所述至少一個第一晶片聯接器和所述跨層晶片聯接器可以被設置成在豎直方向上包含至少一個導電通道。
在所述晶片聯接器堆疊中的每個第一晶片聯接器在水平方向上的面積可以不同。
所述第二晶片能夠通過所述至少一個第一晶片聯接器和所述重佈線層電聯接至所述至少一個第一晶片，或者所述第二晶片能夠通過所述至少一個第一晶片聯接器電聯接至所述至少一個第一晶片，其中，所述第二晶片能夠通過所述至少一個第一晶片聯接器、所述重佈線層、所述跨層晶片聯接器和所述多個第一凸點電聯接至所述金屬層，其中，所述至少一個第一晶片能夠通過所述重佈線層、所述跨層晶片聯接器和所述多個第一凸點電聯接至所述金屬層。
所述至少一個第一晶片聯接器和所述跨層晶片聯接器可以由一種或多種半導體材料、一種或多種無機材料、一種或多種有機材料和/或一種或多種金屬材料形成。
在所述金屬層內可以集成如下電子器件中的一種或多種：I/O埠、無源器件、射頻天線、電磁干擾遮罩器件和散熱器件。
所述至少一個第一晶片聯接器和所述跨層晶片聯接器可以由如下的一種或多種半導體材料形成：矽、碳化矽、砷化鎵和氮化鎵。
所述至少一個第一晶片聯接器和所述跨層晶片聯接器可以由如下的一種或多種無機材料形成：玻璃和陶瓷。
所述至少一個第一晶片聯接器和所述跨層晶片聯接器可以由如下的一種或多種封裝基板的制程和材料形成：印刷電路基板、塑封基板和柔性電路基板。
所述至少一個第一晶片聯接器和所述跨層晶片聯接器可以由金屬基板的制程和材料形成，所述金屬基板採用如下的一種或多種材料金屬材料及其合金材料：銅、鋁和鐵。
在所述金屬層的上方可以放置並組裝如下電子器件中的一種或多種：積體電路模組、微機電系統、光電器件和無源器件。
本發明的第三方面提供了一種形成封裝件的方法，所述方法包括：在載體的上方放置至少一個第一晶片層，每個所述第一晶片層包括多個第一晶片聯接器、多個第二晶片聯接器和正面朝下的多個第一晶片；在所述第一晶片層的上方放置並組裝第二晶片層，所述第二晶片層包括正面朝下的多個第二晶片、多個第三晶片聯接器和多個第四晶片聯接器，其中在所述多個第三晶片聯接器和所述多個第四晶片聯接器上方的表面具有多個第一凸點；在所述載體的上方對所述至少一個第一晶片層和所述第二晶片層進行模塑處理以形成塑封結構；對所述塑封結構進行減薄處理，以暴露出所述多個第一凸點；在經減薄的塑封結構上方添加金屬層；去除所述載體以形成封裝件主體，並在所述封裝件主體的下方添加重佈線層和第二凸點；以及分割所述封裝件主體以形成多個所述封裝件。
所述多個第一晶片聯接器可以是有源聯接器件或無源聯接器件，所述多個第二晶片聯接器可以是有源聯接器件或無源聯接器件，所述多個第三晶片聯接器可以是有源聯接器件或無源聯接器件，並且所述多個第四晶片聯接器可以是有源聯接器件或無源聯接器件。
所述多個第一晶片聯接器、所述多個第二晶片聯接器、所述多個第三晶片聯接器和所述多個第四晶片聯接器可以被設置成在豎直方向上包含至少一個導電通道。
在由位於不同第一晶片層中的多個第一晶片聯接器形成的第一晶片聯接器堆疊中的每個第一晶片聯接器與堆疊在所述第一晶片聯接器堆疊上的第三晶片聯接器在水平方向上的面積可以不同。
由位於不同第一晶片層中的多個第二晶片聯接器形成的第二晶片聯接器堆疊與堆疊在所述第二晶片聯接器堆疊上的第四晶片聯接器能夠一體成型。
在所述第二晶片聯接器堆疊中的每個第二晶片聯接器與堆疊在所述第二晶片聯接器堆疊上的第四晶片聯接器在水平方向上的面積可以相同。
所述封裝件可以包括至少一個第一晶片、第二晶片、至少一個被分割的第一晶片聯接器、至少一個被分割的第二晶片聯接器、被分割的第三晶片聯接器、被分割的第四晶片聯接器和被分割的金屬層，其中，所述第二晶片能夠通過所述至少一個被分割的第一晶片聯接器和所述重佈線層電聯接至所述第一晶片，其中，所述第二晶片能夠通過所述至少一個被分割的第一晶片聯接器、所述重佈線層、所述至少一個被分割的第二晶片聯接器和所述被分割的第四晶片聯接器電聯接至所述被分割的金屬層，其中，所述被分割的金屬層能夠通過 所述被分割的第三晶片聯接器、所述至少一個被分割的第一晶片聯接器和所述重佈線層電聯接至所述至少一個第一晶片。
所述多個第一晶片聯接器、所述多個第二晶片聯接器、所述多個第三晶片聯接器和所述多個第四晶片聯接器可以由一種或多種半導體材料、一種或多種無機材料、一種或多種有機材料和/或一種或多種金屬材料形成。
在所述金屬層內可以集成如下電子器件中的一種或多種：I/O埠、無源器件、射頻天線、電磁干擾遮罩器件和散熱器件。
所述多個第一晶片聯接器、所述多個第二晶片聯接器、所述多個第三晶片聯接器和所述多個第四晶片聯接器可以由如下的一種或多種半導體材料形成：矽、碳化矽、砷化鎵和氮化鎵。
所述多個第一晶片聯接器、所述多個第二晶片聯接器、所述多個第三晶片聯接器和所述多個第四晶片聯接器可以由如下的一種或多種無機材料形成：玻璃和陶瓷。
所述多個第一晶片聯接器、所述多個第二晶片聯接器、所述多個第三晶片聯接器和所述多個第四晶片聯接器可以由如下的一種或多種封裝基板的制程和材料形成：印刷電路基板、塑封基板和柔性電路基板。
所述多個第一晶片聯接器、所述多個第二晶片聯接器、所述多個第三晶片聯接器和所述多個第四晶片聯接器可以由金屬基板的制程和材料形成，所述金屬基板採用如下的一種或多種金屬材料及其合金材料：銅、鋁和鐵。
在所述金屬層的上方可以放置並組裝如下電子器件中的一種或多種：積體電路模組、微機電系統、光電器件和無源器件。
本發明的第三方面提供了一種封裝件，包括：重佈線層，其包括第一側和第二側；多個第一凸點，其設置在所述重佈線層的第一側；至少一個第一晶片，其中，由所述至少一個第一晶片形成的晶片堆疊放置並組裝在所述重佈線層的第二側；至少一個第一晶片聯接器，其包括正面和背面，其中，由所述至少一個第一晶片聯接器形成的晶片聯接器堆疊正面朝下地放置並組裝在所述重佈線層的第二側上，並且水平地放置在所述至少一個第一晶片的一側；跨層晶片聯接器，其放置並組裝在所述重佈線層的第二側上，並且水平地放置在所述至少一個第一晶片的另一側；第二晶片，其包括正面和背面，所述第二晶片正面朝下地放置在所述至少一個第一晶片的背面的上方並組裝在所述至少一個第一晶片聯接器的上方；第二晶片聯接器，其放置並組裝在所述至少一個第一晶片聯接器的上方；多個第二凸點，其設置在所述第二晶片聯接器和所述跨層晶片聯接器的上方；以及金屬層，其放置並組裝在所述封裝件的上方並與所述多個第二凸點中的至少一個電聯接，其中，所述封裝件被模塑處理成塑封結構。
所述至少一個第一晶片聯接器可以是有源聯接器件或無源聯接器件，所述跨層晶片聯接器可以是有源聯接器件或無源聯接器件，並且所述第二晶片聯接器可以是有源聯接器件或無源聯接器件。
所述至少一個第一晶片聯接器、所述第二晶片聯接器和所述跨層晶片聯接器可以被設置成在豎直方向上包含至少一個導電通道。
在所述晶片聯接器堆疊中的每個第一晶片聯接器與所述晶片聯接器堆疊上方的第二晶片聯接器在水平方向上的面積可以不同。
所述第二晶片能夠通過所述至少一個第一晶片聯接器和所述重佈線層電聯接至所述至少一個第一晶片，其中，所述第二晶片能夠通過所述至少一個第一晶片聯接器和所述重佈線層、所述跨層晶片聯接器電聯接至所述金屬層，其中，所述金屬層能夠通過所述第二晶片聯接器、所述至少一個第一晶片聯接器和所述重佈線層電聯接至所述至少一個第一晶片。
所述至少一個第一晶片聯接器、所述第二晶片聯接器和所述跨層晶片聯接器由一種或多種半導體材料、一種或多種無機材料、一種或多種有機材料和/或一種或多種金屬材料形成。
在所述金屬層內可以集成如下電子器件中的一種或多種：I/O埠、無源器件、射頻天線、電磁干擾遮罩器件和散熱器件。
所述至少一個第一晶片聯接器、所述第二晶片聯接器和所述跨層晶片聯接器可以由如下的一種或多種半導體材料形成：矽、碳化矽、砷化鎵和氮化鎵。
所述至少一個第一晶片聯接器、所述第二晶片聯接器和所述跨層晶片聯接器可以由如下的一種或多種無機材料形成：玻璃和陶瓷。
所述至少一個第一晶片聯接器、所述第二晶片聯接器和所述跨層晶片聯接器可以由如下的一種或多種封裝基板的制程和材料形成：印刷電路基板、塑封基板和柔性電路基板。
所述至少一個第一晶片聯接器、所述第二晶片聯接器和所述跨層晶片聯接器可以由金屬基板的制程和材料形成，所述金屬基板採用如下的一種或多種金屬材料及其合金材料：銅、鋁和鐵。
在所述金屬層的上方可以放置並組裝如下電子器件中的一種或多種：積體電路模組、微機電系統、光電器件和無源器件。
本發明的實施例利用晶片聯接器和一站式的晶圓級扇出或板級扇出封裝工藝實現晶片的堆疊，無需在功能晶片中使用TSV等垂直聯接晶片的技術。因此，降低了三維多層晶片封裝的複雜度和製造成本。
本發明的實施例還利用在封裝件上方的金屬層來實現與其他封裝件的聯接和堆疊，或者利用金屬層為封裝件集成和添加具有其它功能的電子器件。
上述說明僅是本發明技術方案的概述，為了能夠更清楚瞭解本發明的技術手段，而可依照說明書的內容予以實施，並且為了讓本發明的上述和其它目的、特徵和優點能夠更明顯易懂，以下特舉本發明的具體實施方式。
步驟100:在載體上放置並組裝晶片層
步驟200:對晶片層進行模塑處理，以形成塑封結構
步驟300:對塑封結構進行減薄處理並且在塑封結構上方添加金屬層
步驟400:去除載體以形成封裝件主體，添加重佈線層和凸點，並且分割封裝件主體以形成封裝件
100:載體
11:晶片
12:通孔
14:第一凸點
15:聯接器
150:電子器件
16:塑封結構
17:金屬層
18:重佈線層
19:第二凸點
200:載體
201:跨層晶片聯接器
202:第一凸點
203:黏合點
21:第一晶片
22:第二晶片
23:第三晶片
24:第一晶片聯接器
25:第二晶片聯接器
250:電子器件
26:塑封結構
27:金屬層
28:重佈線層
29:第二凸點
300:載體
301:跨層晶片聯接器
302:第一凸點
303:黏合點
31:第一晶片
32:第二晶片
33:第一晶片聯接器
34、35:第二晶片聯接器
350:電子器件
36:塑封結構
37:金屬層
38:重佈線層
39:第二凸點
通過參考附圖閱讀下文的詳細描述，本發明示例性實施方式的上述以及其他目的、特徵和優點將變得易於理解。在附圖中，以示例性而非限制性的方式示出了本發明的若干實施方式，其中：
在附圖中，相同或對應的標號表示相同或對應的部分。
[圖1]示出了根據本發明實施例的形成封裝件的方法的流程圖。
[圖2至5]示出了形成根據本發明第一實施例的封裝件的過程的剖面示意圖。
[圖6至9]示出了形成根據本發明第二實施例的封裝件的過程的剖面示意圖。
[圖10至13]示出了形成根據本發明第三實施例的封裝件的過程的剖面示意圖。
以下公開內容提供了許多用於實現本發明的不同特徵的不同實施例或實例。下面描述了元件和佈置的具體實例以簡化本發明。當然，這些僅僅是實例，而不旨在限制本發明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接觸形成的實施例，並且也可以包括在第一部件和第二部件之間可以形成額外的部件，從而使得第一部件和第二部件可以不直接接觸的實施例。此外，本發明可在各個實施例中重複參考標號和/或字元。該重複是為了簡單和清楚的目的，並且其本身不指示所討論的各個實施例和/或配置之間的關係。
而且，為便於描述，在此可以使用諸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”、“在…上方”等空間相對術語，以描述如圖所示的一個元件或部件與另一個(或另一些)原件或部件的關係。除了圖中所示的方位外，空間相對術語旨在包括器件在使用或操作中的不同方位。器件可以以其它方式定向(旋轉90度或在其它方位上)，而本文使用的空間相對描述符可以同樣地作出相應的解釋。另外，在本文中，術語“組裝”是指在各個電子器件之間實現電路聯接。術語“晶片”可以指各種類型的晶片，例如邏輯晶片、儲存晶片等。
圖1示出了根據本發明實施例的形成封裝件的方法的流程圖。在該方法中包括如下四個步驟：
步驟100：在載體上放置並組裝晶片層。
步驟200：對晶片層進行模塑處理以形成塑封結構。
步驟300：對塑封結構進行減薄處理並且在塑封結構上方添加金屬層。
步驟400：去除載體以形成封裝件主體，添加重佈線層和凸點，並且分割封裝件主體以形成封裝件。
在一些實施例中，載體是表面平整度很高的部件，可以將至少一個晶片層堆疊在載體上。載體可以是晶圓。載體也可以是由任意材料形成的板狀部件。例如，板狀部件可以是金屬板。在一些實施例中，板狀部件可以具有任意形狀，例如圓形、矩形等。
在對晶片層進行模塑處理後，可以在載體上形成塑封結構。在一些實施例中，用於模塑處理的材料可以包括添加或沒有添加矽基或玻璃填料的環氧樹脂、有機聚合物或其它化合物為原料的固體或者液體塑封材料。
在一些實施例中，去除載體、添加重佈線層和凸點以及分割封裝件主體的步驟是晶圓級封裝(WLP)和板級扇出封裝中已知的步驟。
下面將基於上述方法並參照各個附圖說明本發明的各個實施例。
圖2至4示出了形成根據本發明第一實施例的封裝件的過程的剖面示意圖。
圖2示出了針對封裝結構實施步驟100和步驟200的剖面示意圖。
如圖2所示，載體100上放置有一個晶片層。晶片層包括多個晶片11和多個晶片聯接器15。在一些實施例中，多個晶片11和多個晶片聯接器15可以彼此間隔地佈置在載體100上。晶片包括正面和背面。在本領域中，具有例如凸點的表面被認為是正面。在一些實施例中，晶片11是正面朝下放置的。
多個晶片聯接器15的上方表面可以設置有多個第一凸點14。在一些實施例中，多個第一凸點14可以是金屬柱的形式(例如銅柱)。
在本文中，晶片聯接器可以用於電聯接不同的電子器件，所述電子器件例如包括晶片、重佈線層和其他晶片聯接器等各種器件；晶片聯接器所聯接的電子器件通常不與晶片聯接器處於相同的晶片層中。在一些實施例中，晶片聯接器可以是有源聯接器件或無源聯接器件。在一些實施例中，晶片聯接器在豎直方向上可以具有若干導電通道。導電通道可以聯接晶片聯接器的上表面和下表面。例如，如圖2所示，晶片聯接器15可以包含多個通孔12，可以在通孔中填充導電介質形成導電通道。在其他實施例中，也可以通過其他方式形成聯接晶片聯接器的上表面和下表面的導電通道。在一些實施例中，晶片聯接器的上表面和下表面上都可以設置導電線路，從而在一個表面上使得在不同的導電通道之間、在組裝至晶片聯接器的凸點之間以及在導電通道與凸點之間形成電聯接。在下文中將在各個實施例中省略對導電通道的描述。
在本文中，晶片聯接器可以由矽、碳化矽、砷化鎵、氮化鎵以及其他半導體材料形成；晶片聯接器可以由玻璃、陶瓷和其他無機材料形成；晶片聯接器可以由印刷電路基板(PCB)、塑封基板(EMC)、柔性電路基板、金屬基板材料以及其他封裝基板的制程和材料形成；金屬基板可以採用銅、鋁和鐵等金屬材料及其合金材料。
如圖2所示，在載體100上的晶片層已被模塑處理，從而形成了塑封結構16。
圖3示出了針對封裝結構實施步驟300的剖面示意圖。
如圖3所示，可以對塑封結構16進行減薄處理，以暴露出多個第一凸點14。然後，在塑封結構16上添加金屬層17而使多個第一凸點14與金屬層17電聯接。在一些實施例中，金屬層可以包括多個金屬線路，多個金屬線路中的至少一個金屬線路連接多個第一凸點14中的至少一個第一凸點14。在本文中，通過在塑封結構上添加金屬層，使得可以在金屬層內添加各種功能器件(即，具有特定功能的電子器件)。功能器件可以例如是I/O埠、無源器件、射頻天線、電磁干擾(EMI)遮罩器件和散熱器件等。在一些實施例中，還可以將某些功能器件組裝在金屬層的上部。例如，可以將積體電路模組、微機電系統(MEMS)、光電器件、無源器件等電子器件作為組裝在金屬層的上部的功能器件。
圖4示出了針對封裝結構實施步驟400的剖面示意圖。
如圖4所示，可以去除載體100以形成封裝件主體。然後，將重佈線層18和第二凸點19添加到封裝件主體的下方。最後，沿圖4中示出的虛線分割封裝件主體以形成如圖5所示的封裝件。請注意，圖4所示出的虛線僅僅是示意性的，並且對封裝件主體的分割操作也並不僅沿著圖4所示出的虛線。
圖5示出了根據本發明第一實施例的封裝件的剖面示意圖。
如圖5所示，封裝件可以包括一個晶片11和兩個被分割的晶片聯接器15。可以在封裝件的上方放置並組裝附加的電子器件150。如上所述，也可以將附加的電子器件150集成到金屬層17中。在另一些實施例中，封裝結構也可以按其他方式進行分割。例如，封裝件可以形成為包含一個晶片11和一個晶片聯接器15。
在某些實施例中，形成上述封裝件的過程還可以是先去除載體100，然後添加重佈線層18和多個第二凸點19。最後，減薄塑封結構16並添加金屬層17，從而形成待被分割的封裝件主體。
圖6至9示出了形成根據本發明第二實施例的封裝件的過程的剖面示意圖。
圖6示出了針對封裝結構實施步驟100和步驟200的剖面示意圖。如圖6所示，在載體200上放置了三個晶片層。第一晶片層包括多個第一晶片21和多個第一晶片聯接器24。第二晶片層包括多個第二晶片22和多個第二晶片聯接器25。第三晶片層包括多個第三晶片23。此外，在載體200上還放置有多個跨層晶片聯接器201。在跨層晶片聯接器201的上方設置有多個第一凸點202。在一些實施例中，多個第一凸點202可以是金屬柱的形式(例如銅柱)。
在本文中，跨層晶片聯接器在豎直方向上的高度可以與封裝件中的所有晶片層的高度相近或一致。例如，如圖6所示，跨層晶片聯接器201的高度可以與三個晶片層的高度相似或一致。
在本文中，跨層晶片聯接器可以是一個完整的晶片聯接器，即，跨層晶片聯接器可以一體成型。也可以通過將多個晶片聯接器堆疊在一起並組裝而形成跨層晶片聯接器。在剖面示意圖中，跨層晶片聯接器在水平方向上的寬度可以從上到下是一致的，也可以是不一致的。
在一些實施例中，在放置和組裝三個晶片層時，可以首先將多個第一晶片21、多個第一晶片聯接器24和多個跨層晶片連接器201放置在載體200上，然後將多個第二晶片22和多個第二晶片聯接器25放置並組裝在第一 晶片11和多個第一晶片聯接器24上，最後將多個第三晶片23放置並組裝在多個第二晶片22和多個第二晶片聯接器25上。在一些實施例中，第一晶片21、第二晶片22和第三晶片23是正面朝下放置的。
在一些實施例中，如圖6至9所示的封裝結構可以僅包含兩個晶片層。例如，可以去掉第一晶片層，只保留第二晶片層和第三晶片層。
在一些實施例中，如圖6至9所示的封裝結構可以包含多個其他晶片層。多個其他晶片層中的每一層都包含多個晶片和多個其他晶片聯接器。所述多個其他晶片聯接器可以堆疊並組裝在第一晶片聯接器24的下方，並且所述多個晶片可以堆疊並組裝在第一晶片21的下方。在一些實施例中，在由多層其他晶片聯接器、第一晶片聯接器24和第二晶片聯接器25形成的堆疊中，每層晶片聯接器在水平方向上的面積可以不完全相同。例如，在所述堆疊中，任一層中的晶片聯接器在水平方向上的面積可以比在該晶片聯接器下方的晶片聯接器在水平方向上的面積小或大。例如，由各個晶片層中的晶片聯接器所形成的堆疊可以具有階梯形、金字塔形、倒階梯形或倒金字塔形等。在一些實施例中，由各個晶片層中的晶片聯接器所形成的堆疊也可以是一體成型的。
如圖6所示，在載體200上的第一晶片層、第二晶片層和第三晶片層已被模塑處理，從而形成了塑封結構26。
在本文中，在不同的晶片層之間還可以設置黏合點(adhesive dot)(例如，圖6-9中的黏合點203)。黏合點用於隔離和固定不同的晶片層。在一些實施例中，黏合點由非導電介質製成。在下文中，將省略對黏合點的描述。
圖7示出了針對封裝結構實施步驟300的剖面示意圖。
如圖7所示，可以對塑封結構26進行減薄處理，以暴露出多個第一凸點202。然後，在塑封結構26上添加金屬層27而使多個第一凸點202與金屬層27電聯接。在一些實施例中，金屬層可以包括多個金屬線路，多個金屬線路中的至少一個金屬線路連接多個第一凸點202中的至少一個第一凸點。
圖8示出了針對封裝結構實施步驟400的剖面示意圖。
如圖8所示，可以去除載體200以形成封裝件主體。然後，將重佈線層28和第二凸點29添加到封裝件主體的下方。最後，沿圖8中示出的虛線分割封裝件主體以形成如圖9所示的封裝件。請注意，圖8所示出的虛線僅僅是示意性的，並且對封裝件主體的分割操作也並不僅沿著圖8所示出的虛線。
圖9示出了根據本發明第二實施例的封裝件的剖面示意圖。
如圖9所示，封裝件可以包括第一晶片21、第二晶片22、第三晶片23、被分割的第一晶片聯接器24、被分割的跨層晶片聯接器201和被分割的第二晶片聯接器25。可以在封裝件的上方放置並組裝附加的電子器件250。如上所述，也可以將附加的電子器件250集成到金屬層27中。在另一些實施例中，封裝結構也可以按其他方式進行分割。
在另一些實施例中，形成上述封裝件的過程還可以是先去除載體200，然後添加重佈線層28和多個第二凸點29。最後，減薄塑封結構26並添加金屬層27，從而形成待被分割的封裝件主體。
圖10至13示出了形成根據本發明第三實施例的封裝件的過程的剖面示意圖。
圖10示出了針對封裝結構實施步驟100和步驟200的剖面示意圖。
如圖10所示，在載體300上放置了兩個晶片層。第一晶片層包括多個第一晶片31和多個第一晶片聯接器33。第二晶片層包括多個第二晶片32和多個第二晶片聯接器34。此外，在載體300上還放置有多個跨層晶片聯接器301。在跨層晶片聯接器301和和多個第二晶片聯接器34的上方設置有多個第一凸點302。在一些實施例中，多個第一凸點302可以是金屬柱的形式(例如銅柱)。在第一晶片31和第二晶片32之間可以設置黏合點303。
在本文中，跨層晶片聯接器在豎直方向上的高度可以與封裝件中的所有晶片層的高度相近或一致。例如，如圖10所示，跨層晶片聯接器301的高度可以與兩個晶片層的高度相似或一致。
在一些實施例中，在放置和組裝兩個晶片層時，可以首先將多個第一晶片31、多個第一晶片聯接器33和多個跨層晶片連接器301放置在載體300上，然後將多個第二晶片32和多個第二晶片聯接器35放置並組裝在第一晶片31和多個第一晶片聯接器33上。在一些實施例中，第一晶片31和第二晶片32是正面朝下放置的。
在一些實施例中，如圖10至13所示的封裝結構可以包含多個其他晶片層。多個其他晶片層中的每一層都包含多個晶片和多個其他晶片聯接器。所述多個其他晶片聯接器可以堆疊並組裝在第一晶片聯接器33的下方，並且所述多個晶片可以堆疊並組裝在第一晶片31的下方。在一些實施例中，在由多層其他晶片聯接器、第一晶片聯接器33和第二晶片聯接器34形成的堆疊中，每層晶片聯接器在水平方向上的面積可以不完全相同。例如，在所述堆疊中，任一層中的晶片聯接器在水平方向上的面積可以比在該晶片聯接器下方的晶片聯接器在水平方向上的面積小或大。例如，由各個晶片層中的 晶片聯接器所形成的堆疊可以具有階梯形、金字塔形、倒階梯形或倒金字塔形等。在一些實施例中，由各個晶片層中的晶片聯接器所形成的堆疊也可以是一體成型的。
如圖10所示，在載體300上的第一晶片層和第二晶片層已被模塑處理，從而形成了塑封結構36。
圖11示出了針對封裝結構實施步驟300的剖面示意圖。
如圖11所示，可以對塑封結構36進行減薄處理，以暴露出多個第一凸點302。然後，在塑封結構36上添加金屬層37而使多個第一凸點302與金屬層37電聯接。在一些實施例中，金屬層可以包括多個金屬線路，多個金屬線路中的至少一個金屬線路連接多個第一凸點302中的至少一個第一凸點。
圖12示出了針對封裝結構實施步驟400的剖面示意圖。
如圖12所示，可以去除載體300以形成封裝件主體。然後，將重佈線層38和第二凸點39添加到封裝件主體的下方。最後，沿圖12中示出的虛線分割封裝件主體以形成如圖13所示的封裝件。請注意，圖12所示出的虛線僅僅是示意性的，並且對封裝件主體的分割操作也並不僅沿著圖12所示出的虛線。
圖13示出了根據本發明第二實施例的封裝件的剖面示意圖。
如圖13所示，封裝件可以包括第一晶片31、第二晶片32、被分割的第一晶片聯接器33、被分割的跨層晶片聯接器301和被分割的第二晶片聯接器34。可以在封裝件的上方放置並組裝附加的電子器件350。如上所述，也可以將附加的電子器件350集成到金屬層37中。在另一些實施例中，封裝結構也可以按其他方式進行分割。
在另一些實施例中，形成上述封裝件的過程還可以是先去除載體300，然後添加重佈線層38和多個第二凸點39。最後，減薄塑封結構36並添加金屬層37，從而形成待被分割的封裝件主體。
在本文中，在不改變該封裝件中的各部件之間的聯接關係的前提下，各個晶片和晶片聯接器的稱謂可以並非如上所定義的。例如，可以將第一晶片、第二晶片或第三晶片的稱謂彼此交換，可以將第一晶片聯接器、第二晶片聯接器、第三晶片聯接器和第四晶片聯接器的稱謂彼此交換，並且也可以將第一凸點和第二凸點的稱謂彼此交換。
在本發明的各個實施例中，在封裝件中的各個晶片不僅可以利用晶片聯接器、重佈線層和/或金屬層彼此互聯，還可以利用晶片聯接器、金屬層、重佈線層和/或凸點聯接到封裝件外部的各種電路結構和電子器件。
如本領域技術人員所公知的，凸點可以由導電材料或焊料製成，導電材料包括Cu、Ni、Au、Ag等或其它合金材料，也可以包括其他材料。在一些實施例中，凸點可以是焊盤或為柱形形狀(例如銅柱)，也可以具有其他可能的形式。
上面概述了若干實施例的特徵，使得本領域人員可以更好地理解本發明的各個方面。本領域人員應該理解，它們可以容易地使用本發明作為基礎來設計或修改用於實施與本文所介紹實施例相同的目的和/或實現相同優勢的其它工藝和結構。本領域技術人員也應該意識到，這種等同構造並不背離本發明的精神和範圍，並且在不背離本發明的精神和範圍的情況下，本文中它們可以做出多種變化、替換以及改變。
步驟100:在載體上放置並組裝晶片層
步驟200:對晶片層進行模塑處理，以形成塑封結構
步驟300:對塑封結構進行減薄處理並且在塑封結構上方添加金屬層
步驟400:去除載體以形成封裝件主體，添加重佈線層和凸點，並且分割封裝件主體以形成封裝件

Claims (38)

  1. 一種形成封裝件的方法，所述方法包括：在載體的上方放置晶片層，所述晶片層包括多個晶片聯接器和正面朝下的多個晶片，其中在所述多個晶片聯接器上方的表面具有多個第一凸點；在所述載體的上方對所述晶片層進行模塑處理以形成塑封結構；對所述塑封結構進行減薄處理，以暴露出所述多個第一凸點；在經減薄的塑封結構上方添加金屬層；去除所述載體以形成封裝件主體，並在所述封裝件主體的下方添加重佈線層和第二凸點；和分割所述封裝件主體以形成多個所述封裝件。
  2. 如請求項1所述的方法，其中，所述多個晶片聯接器是有源聯接器件或無源聯接器件，並且其中，所述多個晶片聯接器被設置成在豎直方向上包含至少一個導電通道。
  3. 如請求項1所述的方法，其中，所述封裝件包括至少一個被分割的晶片聯接器、晶片和被分割的金屬層，其中，所述晶片能夠通過所述至少一個被分割的晶片聯接器和所述重佈線層電聯接至所述被分割的金屬層。
  4. 如請求項1所述的方法，其中，所述多個晶片聯接器由一種或多種半導體材料、一種或多種無機材料、一種或多種有機材料和/或一種或多種金屬材料形成。
  5. 如請求項1所述的方法，其中，在所述金屬層內集成如下電子器件中的一種或多種：I/O埠、無源器件、射頻天線、電磁干擾遮罩器件和散熱 器件；和/或其中，在所述金屬層的上方放置並組裝如下電子器件中的一種或多種：積體電路模組、微機電系統、光電器件和無源器件。
  6. 一種封裝件，包括：重佈線層，其包括第一側和第二側；多個第一凸點，其設置在所述重佈線層的第一側；晶片，其包括正面和背面，所述晶片正面朝下地放置並組裝在所述重佈線層的第二側；至少一個晶片聯接器，其放置並組裝在所述重佈線層的第二側上，並且水平地放置在所述至少一個第一晶片的側面；多個第二凸點，其設置在所述至少一個晶片聯接器的上方；和金屬層，其放置並組裝在所述封裝件的上方並與所述多個第二凸點中的至少一個電聯接，其中，所述封裝件包括被模塑處理成塑封結構的部分。
  7. 如請求項6所述的封裝件，其中，所述至少一個晶片聯接器是有源聯接器件或無源聯接器件，並且其中，所述至少一個晶片聯接器被設置成在豎直方向上包含至少一個導電通道。
  8. 如請求項6所述的封裝件，其中，所述晶片能夠通過所述至少一個晶片聯接器和所述重佈線層電聯接至所述金屬層。
  9. 如請求項6所述的封裝件，其中，所述至少一個晶片聯接器由一種或多種半導體材料、一種或多種無機材料、一種或多種有機材料和/或一種或多種金屬材料形成。
  10. 如請求項6所述的封裝件，其中，在所述金屬層內集成如下電子器件中的一種或多種：I/O埠、無源器件、射頻天線、電磁干擾遮罩器件和散熱器件；和/或其中，在所述金屬層的上方放置並組裝如下電子器件中的一種或多種：積體電路模組、微機電系統、光電器件和無源器件。
  11. 一種形成封裝件的方法，所述方法包括：在載體的上方放置至少一個第一晶片層，每個所述第一晶片層包括多個第一晶片聯接器、多個第二晶片聯接器和正面朝下的多個第一晶片；在所述至少一個第一晶片層的上方放置並組裝第二晶片層，所述第二晶片層包括正面朝下的多個第二晶片和多個第三晶片聯接器，其中在所述多個第三晶片聯接器上方的表面具有多個第一凸點；在所述載體的上方對所述至少一個第一晶片層和所述第二晶片層進行模塑處理以形成塑封結構；對所述塑封結構進行減薄處理，以暴露出所述多個第一凸點；在經減薄的塑封結構上方添加金屬層；去除所述載體以形成封裝件主體，並在所述封裝件主體的下方添加重佈線層和第二凸點；和分割所述封裝件主體以形成多個所述封裝件。
  12. 如請求項11所述的方法，其中，所述多個第一晶片聯接器是有源聯接器件或無源聯接器件，所述多個第二晶片聯接器是有源聯接器件或無源聯接器件，並且所述多個第三晶片聯接器是有源聯接器件或無源聯接器件，並且其中，所述多個第一晶片聯接器、所述多個第二晶片聯接器和所述多個第三晶片聯接器被設置成在豎直方向上包含至少一個導電通道。
  13. 如請求項11所述的方法，其中，在由位於不同第一晶片層中的多個第一晶片聯接器形成的第一晶片聯接器堆疊中的每個第一晶片聯接器在水平方向上的面積不同。
  14. 如請求項11所述的方法，其中，由位於不同第一晶片層中的多個第二晶片聯接器形成的第二晶片聯接器堆疊與堆疊在所述第二堆疊上的第三晶片聯接器能夠一體成型。
  15. 如請求項11所述的方法，其中，在所述第二晶片聯接器堆疊中的每個第二晶片聯接器與堆疊在所述第二晶片聯接器堆疊上的第三晶片聯接器在水平方向上的面積相同。
  16. 如請求項11所述的方法，其中，所述封裝件包括多個第一凸點、至少一個第一晶片、第二晶片、至少一個被分割的第一晶片聯接器、至少一個被分割的第二晶片聯接器、被分割的第三晶片聯接器和被分割的金屬層，其中，所述第二晶片能夠通過所述至少一個被分割的第一晶片聯接器和所述重佈線層電聯接至所述至少一個第一晶片，或者所述第二晶片能夠通過所述至少一個被分割的第一晶片聯接器電聯接至所述至少一個第一晶片，其中，所述第二晶片能夠通過所述至少一個被分割的第一晶片聯接器、所述重佈線層、所述至少一個被分割的第二晶片聯接器、所述被分割的第三晶片聯接器和所述多個第一凸點電聯接至所述被分割的金屬層，其中，所述至少一個第一晶片能夠通過所述重佈線層、所述至少一個被分割的第二晶片聯接器、所述被分割的第三晶片聯接器和所述多個第一凸點電聯接至所述被分割的金屬層。
  17. 如請求項11所述的方法，其中，所述多個第一晶片聯接器、所述多個第二晶片聯接器和所述多個第三晶片聯接器由一種或多種半導體材料、一種或多種無機材料、一種或多種有機材料和/或一種或多種金屬材料形成。
  18. 如請求項11所述的方法，其中，在所述金屬層內集成如下電子器件中的一種或多種：I/O埠、無源器件、射頻天線、電磁干擾遮罩器件和散熱器件；和/或其中，在所述金屬層的上方放置並組裝如下電子器件中的一種或多種：積體電路模組、微機電系統、光電器件和無源器件。
  19. 一種封裝件，包括：重佈線層，其包括第一側和第二側；多個第一凸點，其設置在所述重佈線層的第一側；至少一個第一晶片，其包括正面和背面，其中，由所述至少一個第一晶片形成的晶片堆疊正面朝下地放置並組裝在所述重佈線層的第二側；至少一個第一晶片聯接器，其中，由所述至少一個第一晶片聯接器形成的晶片聯接器堆疊放置並組裝在所述重佈線層的第二側上，並且水平地放置在所述至少一個第一晶片的一側；跨層晶片聯接器，其放置並組裝在所述重佈線層的第二側上，並且水平地放置在所述至少一個第一晶片的另一側；第二晶片，其包括正面和背面，所述第二晶片正面朝下地放置在所述至少一個第一晶片的背面的上方並組裝在所述至少一個第一晶片聯接器的上方；多個第二凸點，其設置在所述跨層晶片聯接器的上方；和金屬層，其放置在所述封裝件的上方並與所述多個第二凸點中的至少一個電聯接， 其中，所述封裝件包括被模塑處理成塑封結構的部分。
  20. 如請求項19所述的封裝件，其中，所述至少一個第一晶片聯接器是有源聯接器件或無源聯接器件，並且所述跨層晶片聯接器是有源聯接器件或無源聯接器件，並且其中，所述至少一個第一晶片聯接器和所述跨層晶片聯接器被設置成在豎直方向上包含至少一個導電通道。
  21. 如請求項19所述的封裝件，其中，在所述晶片聯接器堆疊中的每個第一晶片聯接器在水平方向上的面積不同。
  22. 如請求項19所述的封裝件，其中，所述第二晶片能夠通過所述至少一個第一晶片聯接器和所述重佈線層電聯接至所述至少一個第一晶片，或者所述第二晶片能夠通過所述至少一個第一晶片聯接器電聯接至所述至少一個第一晶片，其中，所述第二晶片能夠通過所述至少一個第一晶片聯接器、所述重佈線層、所述跨層晶片聯接器和所述多個第一凸點電聯接至所述金屬層，其中，所述至少一個第一晶片能夠通過所述重佈線層、所述跨層晶片聯接器和所述多個第一凸點電聯接至所述金屬層。
  23. 如請求項19所述的封裝件，其中，所述至少一個第一晶片聯接器和所述跨層晶片聯接器由一種或多種半導體材料、一種或多種無機材料、一種或多種有機材料和/或一種或多種金屬材料形成。
  24. 如請求項19所述的封裝件，其中，在所述金屬層內集成如下電子器件中的一種或多種：I/O埠、無源器件、射頻天線、電磁干擾遮罩器件和散熱器件；和/或其中，在所述金屬層的上方放置並組裝如下電子器件中的一種或多種：積體電路模組、微機電系統、光電器件和無源器件。
  25. 一種形成封裝件的方法，所述方法包括：在載體的上方放置至少一個第一晶片層，每個所述第一晶片層包括多個第一晶片聯接器、多個第二晶片聯接器和正面朝下的多個第一晶片；在所述第一晶片層的上方放置並組裝第二晶片層，所述第二晶片層包括正面朝下的多個第二晶片、多個第三晶片聯接器和多個第四晶片聯接器，其中在所述多個第三晶片聯接器和所述多個第四晶片聯接器上方的表面具有多個第一凸點；在所述載體的上方對所述至少一個第一晶片層和所述第二晶片層進行模塑處理以形成塑封結構；對所述塑封結構進行減薄處理，以暴露出所述多個第一凸點；在經減薄的塑封結構上方添加金屬層；去除所述載體以形成封裝件主體，並在所述封裝件主體的下方添加重佈線層和第二凸點；和分割所述封裝件主體以形成多個所述封裝件。
  26. 如請求項25所述的方法，其中，所述多個第一晶片聯接器是有源聯接器件或無源聯接器件，所述多個第二晶片聯接器是有源聯接器件或無源聯接器件，所述多個第三晶片聯接器是有源聯接器件或無源聯接器件，並且所述多個第四晶片聯接器是有源聯接器件或無源聯接器件，並且其中，所述多個第一晶片聯接器、所述多個第二晶片聯接器、所述多個第三晶片聯接器和所述多個第四晶片聯接器被設置成在豎直方向上包含至少一個導電通道。
  27. 如請求項25所述的方法，其中，在由位於不同第一晶片層中的多個第一晶片聯接器形成的第一晶片聯接器堆疊中的每個第一晶片聯接器與 堆疊在所述第一晶片聯接器堆疊上的第三晶片聯接器在水平方向上的面積不同。
  28. 如請求項25所述的方法，其中，由位於不同第一晶片層中的多個第二晶片聯接器形成的第二晶片聯接器堆疊與堆疊在所述第二晶片聯接器堆疊上的第四晶片聯接器能夠一體成型。
  29. 如請求項28所述的方法，其中，在所述第二晶片聯接器堆疊中的每個第二晶片聯接器與堆疊在所述第二晶片聯接器堆疊上的第四晶片聯接器在水平方向上的面積相同。
  30. 如請求項25所述的方法，其中，所述封裝件包括至少一個第一晶片、第二晶片、至少一個被分割的第一晶片聯接器、至少一個被分割的第二晶片聯接器、被分割的第三晶片聯接器、被分割的第四晶片聯接器和被分割的金屬層，其中，所述第二晶片能夠通過所述至少一個被分割的第一晶片聯接器和所述重佈線層電聯接至所述第一晶片，其中，所述第二晶片能夠通過所述至少一個被分割的第一晶片聯接器、所述重佈線層、所述至少一個被分割的第二晶片聯接器和所述被分割的第四晶片聯接器電聯接至所述被分割的金屬層，其中，所述被分割的金屬層能夠通過所述被分割的第三晶片聯接器、所述至少一個被分割的第一晶片聯接器和所述重佈線層電聯接至所述至少一個第一晶片。
  31. 如請求項25所述的方法，其中，所述多個第一晶片聯接器、所述多個第二晶片聯接器、所述多個第三晶片聯接器和所述多個第四晶片聯接器 由一種或多種半導體材料、一種或多種無機材料、一種或多種有機材料和/或一種或多種金屬材料形成。
  32. 如請求項25所述的方法，其中，在所述金屬層內集成如下電子器件中的一種或多種：I/O埠、無源器件、射頻天線、電磁干擾遮罩器件和散熱器件；和/或其中，在所述金屬層的上方放置並組裝如下電子器件中的一種或多種：積體電路模組、微機電系統、光電器件和無源器件。
  33. 一種封裝件，包括：重佈線層，其包括第一側和第二側；多個第一凸點，其設置在所述重佈線層的第一側；至少一個第一晶片，其包括正面和背面，其中，由所述至少一個第一晶片形成的晶片堆疊正面朝下地放置並組裝在所述重佈線層的第二側；至少一個第一晶片聯接器，其中，由所述至少一個第一晶片聯接器形成的晶片聯接器堆疊放置並組裝在所述重佈線層的第二側上，並且水平地放置在所述至少一個第一晶片的一側；跨層晶片聯接器，其放置並組裝在所述重佈線層的第二側上，並且水平地放置在所述至少一個第一晶片的另一側；第二晶片，其包括正面和背面，所述第二晶片正面朝下地放置在所述至少一個第一晶片的背面的上方並組裝在所述至少一個第一晶片聯接器的上方；第二晶片聯接器，其放置並組裝在所述至少一個第一晶片聯接器的上方；多個第二凸點，其設置在所述第二晶片聯接器和所述跨層晶片聯接器的上方；和 金屬層，其放置並組裝在所述封裝件的上方並與所述多個第二凸點中的至少一個電聯接，其中，所述封裝件包括被模塑處理成塑封結構的部分。
  34. 如請求項33所述的封裝件，其中，所述至少一個第一晶片聯接器是有源聯接器件或無源聯接器件，所述跨層晶片聯接器是有源聯接器件或無源聯接器件，並且所述第二晶片聯接器是有源聯接器件或無源聯接器件，並且其中，所述至少一個第一晶片聯接器、所述第二晶片聯接器和所述跨層晶片聯接器被設置成在豎直方向上包含至少一個導電通道。
  35. 如請求項33所述的封裝件，其中，在所述晶片聯接器堆疊中的每個第一晶片聯接器與所述晶片聯接器堆疊上方的第二晶片聯接器在水平方向上的面積不同。
  36. 如請求項33所述的封裝件，其中，所述第二晶片能夠通過所述至少一個第一晶片聯接器和所述重佈線層電聯接至所述至少一個第一晶片，其中，所述第二晶片能夠通過所述至少一個第一晶片聯接器和所述重佈線層、所述跨層晶片聯接器電聯接至所述金屬層，其中，所述金屬層能夠通過所述第二晶片聯接器、所述至少一個第一晶片聯接器和所述重佈線層電聯接至所述至少一個第一晶片。
  37. 如請求項33所述的封裝件，其中，所述至少一個第一晶片聯接器、所述第二晶片聯接器和所述跨層晶片聯接器由一種或多種半導體材料、一種或多種無機材料、一種或多種有機材料和/或一種或多種金屬材料形成。
  38. 如請求項33所述的封裝件，其中，在所述金屬層內集成如下電子器件中的一種或多種：I/O埠、無源器件、射頻天線、電磁干擾遮罩器件和 散熱器件；和/或其中，在所述金屬層的上方放置並組裝如下電子器件中的一種或多種：積體電路模組、微機電系統、光電器件和無源器件。
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