CN110391219A - 扇出型半导体封装件 - Google Patents
扇出型半导体封装件 Download PDFInfo
- Publication number
- CN110391219A CN110391219A CN201811548772.3A CN201811548772A CN110391219A CN 110391219 A CN110391219 A CN 110391219A CN 201811548772 A CN201811548772 A CN 201811548772A CN 110391219 A CN110391219 A CN 110391219A
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- layer
- semiconductor chip
- fan
- wiring layer
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Abstract
本发明提供一种扇出型半导体封装件。所述扇出型半导体封装件包括:芯构件,具有第一通孔并包括布线层;第一半导体芯片,设置在所述第一通孔中并具有形成在所述第一半导体芯片的下侧上的第一连接焊盘;第一包封剂,覆盖所述芯构件和所述第一半导体芯片;连接构件,设置在所述芯构件和所述第一半导体芯片的下方并包括重新分布层;第一堆叠芯片,设置在所述第一包封剂上并通过第一连接导体电连接到所述布线层;以及第二包封剂,设置在所述第一包封剂上并覆盖所述第一堆叠芯片。所述第一半导体芯片包括DRAM和/或控制器,所述第一堆叠芯片包括堆叠型NAND闪存,并且所述第一半导体芯片的第一连接焊盘通过所述重新分布层电连接到所述布线层。
Description
本申请要求于2018年4月18日在韩国知识产权局提交的第10-2018-0045020号韩国专利申请的优先权的权益,该韩国专利申请的公开内容通过引用全部包含于此。
技术领域
本公开涉及一种半导体封装件,更具体地,涉及一种电连接结构可延伸到其中设置有半导体芯片的区域的外部的扇出型半导体封装件。
背景技术
固态硬盘(SSD)是使用NAND闪存存储信息的装置,比硬盘驱动器(HDD)快,并且可减小尺寸和重量,且具有较低的故障率,产热少且噪声小。近年来,随着SSD容量增大,SSD已替代或补充HDD,并且已经应用到上网本和平板电脑。
同时,根据这种小尺寸产品的应用要求,半导体芯片的尺寸正持续减小,并且在形成半导体封装件时为电信号的连接而提出的半导体封装技术中的一种是扇出型封装。在扇出型封装应用到其的传统的层叠封装(POP)型封装结构的情况下,分开制造下封装件和上封装件以形成整个封装件,在这种情况下,产品的厚度相当大且还可能发生信号损耗。
发明内容
本公开的一方面可提供一种能够同时执行各种功能、纤薄化且具有低的信号损耗的扇出型半导体封装件。
本公开的一方面可将堆叠型NAND闪存直接安装在DRAM和/或控制器被封装在其中的下封装件上,并且可使用连接导体将NAND闪存连接到下封装件的芯构件的布线层和连接构件的重新分布层,从而执行重新分布。
根据本公开的一方面,一种扇出型半导体封装件可包括:芯构件,具有第一通孔并包括一个或更多个布线层;第一半导体芯片,设置在所述第一通孔中并具有形成在所述第一半导体芯片的下侧上的第一连接焊盘;第一包封剂,覆盖所述芯构件的至少一部分和所述第一半导体芯片的至少一部分;连接构件,设置在所述芯构件和所述第一半导体芯片的下方并包括一个或更多个重新分布层;第一堆叠芯片,设置在所述第一包封剂上并通过第一连接导体电连接到所述芯构件的所述一个或更多个布线层;以及第二包封剂,设置在所述第一包封剂上并覆盖所述第一堆叠芯片的至少一部分。所述第一半导体芯片可包括DRAM和控制器中的至少一者,所述第一堆叠芯片可包括堆叠型NAND闪存,并且所述第一半导体芯片的所述第一连接焊盘可通过所述连接构件的所述一个或更多个重新分布层电连接到所述芯构件的所述一个或更多个布线层。
根据本公开的另一方面,一种扇出型半导体封装件可包括:芯构件,具有彼此分开的第一通孔和第二通孔,并包括一个或更多个布线层;第一半导体芯片,设置在所述第一通孔中并具有形成在所述第一半导体芯片的下侧上的第一连接焊盘;第二半导体芯片,设置在所述第二通孔中并具有形成在所述第二半导体芯片的下侧上的第二连接焊盘;第一包封剂,覆盖所述芯构件的至少一部分、所述第一半导体芯片的至少一部分和所述第二半导体芯片的至少一部分;连接构件,设置在所述芯构件、所述第一半导体芯片和所述第二半导体芯片的下方并包括一个或更多个重新分布层;第一堆叠芯片,设置在所述第一包封剂上并通过第一连接导体电连接到所述芯构件的所述一个或更多个布线层;第二堆叠芯片,设置在所述第一包封剂上并通过第二连接导体电连接到所述芯构件的所述一个或更多个布线层;以及第二包封剂,设置在所述第一包封剂上并覆盖所述第一堆叠芯片的至少一部分和所述第二堆叠芯片的至少一部分。所述第一连接焊盘和所述第二连接焊盘可通过所述连接构件的所述一个或更多个重新分布层分别电连接到所述芯构件的所述一个或更多个布线层。
附图说明
通过下面结合附图进行的详细描述,本公开的以上和其他方面、特征和其他优点将被更清楚地理解,在附图中:
图1是示出电子装置系统的示例的示意性框图;
图2是示出电子装置的示例的示意性透视图;
图3A和图3B是示出扇入型半导体封装件在被封装之前和封装之后的状态的示意性截面图;
图4是示出扇入型半导体封装件的封装工艺的示意性截面图;
图5是示出扇入型半导体封装件安装在球栅阵列(BGA)基板上并且最终安装在电子装置的主板上的情况的示意性截面图;
图6是示出扇入型半导体封装件嵌入在BGA基板中并且最终安装在电子装置的主板上的情况的示意性截面图;
图7是示出扇出型半导体封装件的示意性截面图;
图8是示出扇出型半导体封装件安装在电子装置的主板上的情况的示意性截面图;
图9是示出扇出型半导体封装件的示例的示意性截面图;
图10是沿着图9的扇出型半导体封装件的I-I′线截取的示意性平面图;
图11是示出扇出型半导体封装件的另一示例的示意性截面图;
图12是示出扇出型半导体封装件的另一示例的示意性截面图;以及
图13是示出扇出型半导体封装件的另一示例的示意性截面图。
具体实施方式
现将在下文中参照附图详细地描述本公开的示例性实施例。
电子装置
图1是示出电子装置系统的示例的示意性框图。
参照图1,电子装置1000可将主板1010容纳在其中。主板1010可包括物理连接或者电连接到其的芯片相关组件1020、网络相关组件1030、其他组件1040等。这些组件可通过各种信号线1090连接到以下将描述的其他组件。
芯片相关组件1020可包括:存储芯片,诸如易失性存储器(例如,动态随机存取存储器(DRAM))、非易失性存储器(例如,只读存储器(ROM))、闪存等;应用处理器芯片,诸如中央处理器(例如,中央处理单元(CPU))、图形处理器(例如,图形处理单元(GPU))、数字信号处理器、密码处理器、微处理器、微控制器等;以及逻辑芯片,诸如模拟数字转换器(ADC)、专用集成电路(ASIC)等。然而,芯片相关组件1020不限于此,而是还可包括其他类型的芯片相关组件。此外,芯片相关组件1020可彼此组合。
网络相关组件1030可包括被指定为根据诸如以下的协议操作的组件:无线保真(Wi-Fi)(电工电子工程师协会(IEEE)802.11族等)、全球微波接入互操作性(WiMAX)(IEEE802.16族等)、IEEE 802.20、长期演进(LTE)、演进数据最优化(Ev-DO)、高速分组接入+(HSPA+)、高速下行链路分组接入+(HSDPA+)、高速上行链路分组接入+(HSUPA+)、增强型数据GSM环境(EDGE)、全球移动通信系统(GSM)、全球定位系统(GPS)、通用分组无线业务(GPRS)、码分多址(CDMA)、时分多址(TDMA)、数字增强型无绳电信(DECT)、蓝牙、3G协议、4G协议和5G协议以及在上述协议之后指定的任意其他无线协议和有线协议。然而,网络相关组件1030不限于此,而是还可包括被指定为根据各种其他无线标准或协议或者有线标准或协议操作的组件。此外,网络相关组件1030可与上述芯片相关组件1020一起彼此组合。
其他组件1040可包括高频电感器、铁氧体电感器、功率电感器、铁氧体磁珠、低温共烧陶瓷(LTCC)、电磁干扰(EMI)滤波器、多层陶瓷电容器(MLCC)等。然而,其他组件1040不限于此,而是还可包括用于各种其他目的的无源组件等。此外,其他组件1040可与上述芯片相关组件1020或网络相关组件1030一起彼此组合。
根据电子装置1000的类型,电子装置1000可包括可物理连接和/或电连接到主板1010或者可不物理连接和/或电连接到主板1010的其他组件。这些其他组件可包括例如相机1050、天线1060、显示器1070、电池1080、音频编解码器(未示出)、视频编解码器(未示出)、功率放大器(未示出)、指南针(未示出)、加速计(未示出)、陀螺仪(未示出)、扬声器(未示出)、大容量存储单元(例如,硬盘驱动器)(未示出)、光盘(CD)驱动器(未示出)、数字通用光盘(DVD)驱动器(未示出)等。然而,这些其他组件不限于此,而是还可根据电子装置1000的类型等而包括用于各种目的的其他组件。
电子装置1000可以是智能电话、个人数字助理(PDA)、数字摄像机、数码相机、网络系统、计算机、监视器、平板个人计算机(PC)、膝上型PC、上网本PC、电视机、视频游戏机、智能手表、汽车组件等。然而,电子装置1000不限于此,而可以是处理数据的任意其他电子装置。
图2是示出电子装置的示例的示意性透视图。
参照图2,半导体封装件可在如上所述的各种电子装置1000中用于各种目的。例如,母板1110可容纳在智能电话1100的主体1101中,并且各种组件1120可物理连接或者电连接到母板1110。另外,可物理连接和/或电连接到母板1110或者可不物理连接和/或电连接到母板1110的其他组件(诸如,相机模块1130)可容纳在主体1101中。各种组件1120中的一些可以是芯片相关组件,例如,半导体封装件1121,但不限于此。电子装置不必然地局限于智能电话1100,而可以是如上所述的其他电子装置。
半导体封装件
通常,半导体芯片中集成了大量的微电子电路。然而,半导体芯片本身可能无法用作成品的半导体产品,并且可能由于外部的物理冲击或者化学冲击而损坏。因此,半导体芯片本身可能不被使用,而半导体芯片可被封装并且在封装的状态下在电子装置等中使用。
这里,就电连接而言,由于半导体芯片和电子装置的主板之间的电路宽度存在差异,因此需要半导体封装。详细地,半导体芯片的连接焊盘的尺寸和半导体芯片的连接焊盘之间的间距非常细小,而在电子装置中使用的主板的组件安装焊盘的尺寸和主板的组件安装焊盘之间的间距显著大于半导体芯片的连接焊盘的尺寸和半导体芯片的连接焊盘之间的间距。因此,可能难以将半导体芯片直接安装在主板上,并且需要用于缓解半导体芯片和主板之间的电路宽度的差异的封装技术。
通过封装技术制造的半导体封装件可根据其结构和目的而分为扇入型半导体封装件和扇出型半导体封装件。
在下文中,将参照附图更详细地描述扇入型半导体封装件和扇出型半导体封装件。
扇入型半导体封装件
图3A和图3B是示出扇入型半导体封装件在被封装之前和封装之后的状态的示意性截面图。
图4是示出扇入型半导体封装件的封装工艺的示意性截面图。
参照附图,半导体芯片2220可以是例如处于裸态的集成电路(IC),并且包括:主体2221,包括硅(Si)、锗(Ge)、砷化镓(GaAs)等;连接焊盘2222,形成在主体2221的一个表面上,并且包括诸如铝(Al)等的导电材料;以及诸如氧化物膜、氮化物膜等的钝化层2223,形成在主体2221的一个表面上并且覆盖连接焊盘2222的至少部分。在这种情况下,由于连接焊盘2222非常小,因此难以将集成电路(IC)安装在中等尺寸等级的印刷电路板(PCB)以及电子装置的主板等上。
因此,根据半导体芯片2220的尺寸,可在半导体芯片2220上形成连接构件2240,以使连接焊盘2222重新分布。连接构件2240可通过如下步骤形成:使用诸如光可成像介电(PID)树脂的绝缘材料在半导体芯片2220上形成绝缘层2241,形成使连接焊盘2222敞开的通路孔2243h,然后形成布线图案2242和过孔2243。然后,可形成保护连接构件2240的钝化层2250,可形成开口2251,并且可形成凸块下金属层2260等。也就是说,可通过一系列工艺制造包括例如半导体芯片2220、连接构件2240、钝化层2250和凸块下金属层2260的扇入型半导体封装件2200。
如上所述,扇入型半导体封装件可具有半导体芯片的所有的连接焊盘(例如,输入/输出(I/O)端子)设置在半导体芯片的内部的封装件形式,可具有优异的电特性,并且可按照低成本生产。因此,安装在智能电话中的许多元件已经按照扇入型半导体封装件形式来制造。详细地,安装在智能电话中的许多元件已经被开发为在具有紧凑的尺寸的同时实现快速的信号传输。
然而,在扇入型半导体封装件中,由于所有的I/O端子需要设置在半导体芯片的内部,因此扇入型半导体封装件具有大的空间局限性。因此,难以将此结构应用于具有大量的I/O端子的半导体芯片或者具有紧凑尺寸的半导体芯片。另外,由于上述缺点,可能无法在电子装置的主板上直接安装和使用扇入型半导体封装件。原因在于:即使半导体芯片的I/O端子的尺寸和半导体芯片的I/O端子之间的间距通过重新分布工艺被增大,半导体芯片的I/O端子的尺寸和半导体芯片的I/O端子之间的间距仍不足以将扇入型半导体封装件直接安装在电子装置的主板上。
图5是示出扇入型半导体封装件安装在BGA基板上并且最终安装在电子装置的主板上的情况的示意性截面图。
图6是示出扇入型半导体封装件嵌在BGA基板中并且最终安装在电子装置的主板上的情况的示意性截面图。
参照图5,在扇入型半导体封装件2200中,半导体芯片2220的连接焊盘2222(即,I/O端子)可通过BGA基板2301重新分布,并且在扇入型半导体封装件2200安装在BGA基板2301上的状态下,扇入型半导体封装件2200可最终安装在电子装置的主板2500上。在这种情况下,焊球2270等可通过底部填充树脂2280等固定,并且半导体芯片2220的外侧可利用模制材料2290等覆盖。可选地,参照图6,扇入型半导体封装件2200可嵌在单独的BGA基板2302中,在扇入型半导体封装件2200嵌在BGA基板2302中的状态下,半导体芯片2220的连接焊盘2222(即,I/O端子)可通过BGA基板2302重新分布,并且扇入型半导体封装件2200可最终安装在电子装置的主板2500上。
如上所述,可能难以在电子装置的主板上直接安装和使用扇入型半导体封装件。因此,扇入型半导体封装件可安装在单独的BGA基板上然后通过封装工艺安装在电子装置的主板上,或者可在扇入型半导体封装件嵌入在BGA基板中的状态下在电子装置的主板上安装和使用扇入型半导体封装件。
扇出型半导体封装件
图7是示出扇出型半导体封装件的示意性截面图。
参照图7,在扇出型半导体封装件2100中,例如,半导体芯片2120的外侧可通过包封剂2130保护,并且半导体芯片2120的连接焊盘2122可通过连接构件2140重新分布到半导体芯片2120的外部。在这种情况下,钝化层2150还可形成在连接构件2140上,并且凸块下金属层2160还可形成在钝化层2150的开口中。焊球2170还可形成在凸块下金属层2160上。半导体芯片2120可以是包括主体2121、连接焊盘2122、钝化层(未示出)等的集成电路(IC)。连接构件2140可包括:绝缘层2141;重新分布层2142,形成在绝缘层2141上;以及过孔2143,使连接焊盘2122和重新分布层2142彼此电连接。
如上所述,扇出型半导体封装件可具有半导体芯片的I/O端子通过形成在半导体芯片上的连接构件重新分布并且设置在半导体芯片的外部的形式。如上所述,在扇入型半导体封装件中,半导体芯片的所有的I/O端子需要设置在半导体芯片的内部。因此,当半导体芯片的尺寸减小时,球的尺寸和节距需要减小,使得在扇入型半导体封装件中可能无法使用标准化的球布局。另一方面,如上所述,扇出型半导体封装件具有半导体芯片的I/O端子通过形成在半导体芯片上的连接构件重新分布并且设置在半导体芯片的外部的形式。因此,即使在半导体芯片的尺寸减小的情况下,在扇出型半导体封装件中仍可按照原样使用标准化的球布局,使得扇出型半导体封装件可在不使用单独的BGA基板的情况下安装在电子装置的主板上,如下所述。
图8是示出扇出型半导体封装件安装在电子装置的主板上的情况的示意性截面图。
参照图8,扇出型半导体封装件2100可通过焊球2170等安装在电子装置的主板2500上。也就是说,如上所述,扇出型半导体封装件2100包括连接构件2140,连接构件2140形成在半导体芯片2120上并且能够使连接焊盘2122重新分布到半导体芯片2120的尺寸的外部的扇出区域,使得可在扇出型半导体封装件2100中按照原样使用标准化的球布局。结果,扇出型半导体封装件2100可在不使用单独的BGA基板等的情况下安装在电子装置的主板2500上。
如上所述,由于扇出型半导体封装件可在不使用单独的BGA基板的情况下安装在电子装置的主板上,因此扇出型半导体封装件可按照比使用BGA基板的扇入型半导体封装件的厚度小的厚度实现。因此,扇出型半导体封装件可被小型化和纤薄化。另外,扇出型半导体封装件具有优异的热特性和电特性,使得其特别适合于移动产品。因此,扇出型半导体封装件可按照比使用印刷电路板(PCB)的普通的层叠封装(POP)型的形式更紧凑的形式实现,并且可解决由于翘曲现象的发生而引起的问题。
同时,扇出型半导体封装指的是如上所述的用于将半导体芯片安装在电子装置的主板等上并且保护半导体芯片免受外部冲击的影响的封装技术,并且是与诸如BGA基板的印刷电路板(PCB)等(具有与扇出型半导体封装件的规格、用途等不同的规格、用途等,并且具有嵌在其中的扇入型半导体封装件)的概念不同的概念。
在下文中,将参照附图描述能够同时执行各种功能、纤薄化且具有低的信号损耗的扇出型半导体封装件。
图9是示出扇出型半导体封装件的示例的示意性截面图。
图10是沿着图9的扇出型半导体封装件的I-I′线截取的示意性平面图。
参照附图,根据示例性实施例的扇出型半导体封装件100A可包括:芯构件110,具有彼此分开第一通孔110HA和第二通孔110HB且包括一个或更多个布线层112a、112b和112c;第一半导体芯片120A,设置在第一通孔110HA中并具有形成在其下侧上的第一连接焊盘120PA;第二半导体芯片120B,设置在第二通孔110HB中并具有形成在其下侧上的第二连接焊盘120PB;第一包封剂130,覆盖芯构件110的至少一部分、第一半导体芯片120A的至少一部分和第二半导体芯片120B的至少一部分;连接构件140,设置在芯构件110、第一半导体芯片120A和第二半导体芯片120B的下方并包括一个或更多个重新分布层142;第一堆叠芯片180A,设置在第一包封剂130上并通过第一连接导体180WA电连接到芯构件110的一个或更多个布线层112a、112b和112c;第二堆叠芯片180B,设置在第一包封剂130上并通过第二连接导体180WB电连接到芯构件110的一个或更多个布线层112a、112b和112c;第二包封剂190,设置在第一包封剂130上并覆盖第一堆叠芯片180A的至少一部分和第二堆叠芯片180B的至少一部分。此外,扇出型半导体封装件100A可包括:钝化层150,设置在连接构件140的下方并具有使连接构件140的重新分布层142的最下方重新分布层的至少一部分暴露的开口151;多个凸块下金属部160,设置在钝化层150的开口151上并连接到暴露的最下方重新分布层;以及多个电连接结构170,设置在钝化层150的下方并连接到多个凸块下金属部160。第一连接焊盘120PA和第二连接焊盘120PB可通过连接构件140的一个或更多个重新分布层142分别电连接到芯构件110的一个或更多个布线层112a、112b和112c。第一半导体芯片120A可包括DRAM,第二半导体芯片120B可包括控制器,第一堆叠芯片180A和第二堆叠芯片180B中的每个可包括堆叠型NAND闪存。
通常,SSD可实现为通过如下步骤制造的层叠型封装件:将DRAM和/或控制器安装在第一中介基板上以形成下封装件,将NAND闪存安装在第二中介基板上以形成上封装件,使用焊球等将上封装件和下封装件彼此连接。然而,在这种情况下,由于主要使用中介基板,因此封装件的厚度非常大。具体地,由于下封装件和上封装件分开制造,然后堆叠来形成整个封装件,因此对减小封装件的整体厚度存在限制。另外,由于下封装件和上封装件之间的信号距离非常大,因此可能发生信号特性方面的损耗。
另一方面,在根据示例性实施例的扇出型半导体封装件100A中,可用作DRAM和/或控制器的第一半导体芯片120A和第二半导体芯片120B可与具有一个或更多个布线层112a、112b和112c的芯构件110一起利用第一包封剂130包封,可用作NAND闪存的第一堆叠芯片180A和第二堆叠芯片180B可在不使用中介体的情况下直接安装在第一包封剂130的上表面上,并且第一堆叠芯片180A和第二堆叠芯片180B可使用诸如接合线的连接导体180WA和180WB电连接到芯构件110的布线层112a、112b和112c。因此,整个扇出型半导体封装件100A的厚度可显著减小并且第一半导体芯片120A和第二半导体芯片120B与第一堆叠芯片180A和第二堆叠芯片180B之间的信号传输路径可由于减小的厚度而显著缩短。结果,可显著降低信号特性方面的损耗。也就是说,根据示例性实施例,可提供能够同时执行各种功能、薄型化并具有低的信号损耗的扇出型半导体封装件100A,其可有效地应用于诸如SSD的产品。
将在下文中更详细地描述包括在根据示例性实施例的扇出型半导体封装件100A中的各个组件。
芯构件110可包括使第一半导体芯片120A的第一连接焊盘120PA和第二半导体芯片120B的第二连接焊盘120PB和/或第一堆叠芯片180A和第二堆叠芯片180B的连接焊盘(未示出)重新分布的一个或更多个布线层112a、112b和112c。因此,可减少连接构件140的层数。另外,芯构件110可根据芯构件110的绝缘层的特定材料保持扇出型半导体封装件100A的刚性,并用于确保第一包封剂130的厚度的均匀性。根据示例性实施例的扇出型半导体封装件100A的上部和下部可通过芯构件110彼此电连接。芯构件110可具有彼此分开的第一通孔110HA和第二通孔110HB。第一半导体芯片120A和第二半导体芯片120B可设置在第一通孔110HA和第二通孔110HB中,以与芯构件110分开预定距离。第一半导体芯片120A的侧表面和第二半导体芯片120B的侧表面可被芯构件110包围。然而,这样的形式仅是示例并且可进行各种修改以具有其他形式,并且芯构件110可根据这样的形式而执行另一功能。
芯构件110可包括:第一绝缘层111a,与连接构件140接触;第一布线层112a,与连接构件140接触并嵌在第一绝缘层111a中;第二布线层112b,设置在第一绝缘层111a的与第一绝缘层111a的嵌有第一布线层112a的一个表面背对的另一表面上;第二绝缘层111b,设置在第一绝缘层111a上并覆盖第二布线层112b;第三布线层112c,设置在第二绝缘层111b上。另外,芯构件110可包括穿透第一绝缘层111a并使第一布线层112a和第二布线层112b彼此电连接的第一连接过孔层113a以及穿透第二绝缘层111b并使第二布线层112b和第三布线层112c彼此电连接的第二连接过孔层113b。当第一布线层112a嵌在第一绝缘层111a中时,可显著减小由于第一布线层112a的厚度而产生的台阶,因此连接构件140的绝缘距离可变得恒定。因此,连接构件140的高密度布线设计可以是容易的。第一布线层112a的下表面和第一绝缘层111a的下表面之间可具有台阶。在这种情况下,第一绝缘层111a可防止第一包封剂130渗入第一布线层112a的下表面,从而解决缺陷问题。
第一绝缘层111a和第二绝缘层111b中的每个的材料不受具体限制。例如,绝缘材料可用作第一缘层111a和第二绝缘层111b的材料。在这种情况下,绝缘材料可以是诸如环氧树脂的热固性树脂、诸如聚酰亚胺树脂的热塑性树脂、包括热固性树脂或热塑性树脂及无机填料和/或诸如玻璃布(或玻璃织物)的芯材料的绝缘材料(例如,半固化片、ABF(Ajinomoto Build up Film)、FR-4、双马来酰亚胺三嗪(BT))等。作为第一绝缘层111a和第二绝缘层111b的材料,可使用ABF。
第一布线层112a、第二布线层112b和第三布线层112c可用于使第一半导体芯片120A的第一连接焊盘120PA和第二半导体芯片120B的第二连接焊盘120PB和/或第一堆叠芯片180A和第二堆叠芯片180B的连接焊盘(未示出)重新分布,并且可用于为连接过孔层113a和113b提供焊盘图案,以使扇出型半导体封装件100A的上部和下部彼此连接。布线层112a、112b和112c中的每个的材料可以是诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金的导电材料。第一布线层112a、第二布线层112b和第三布线层112c可根据相应层的设计执行各种功能。例如,第一布线层112a、第二布线层112b和第三布线层112c可包括接地(GND)图案、电力(PWR)图案、信号(S)图案等。这里,信号(S)图案可包括除接地(GND)图案、电力(PWR)图案等之外的各种信号图案(诸如数据信号图案等)。另外,第一布线层112a、第二布线层112b和第三布线层112c可包括过孔焊盘、布线焊盘、电连接结构焊盘等。例如,设置在最上部上的第三布线层112c可包括连接到第一堆叠芯片180A的第一连接导体180WA和第二堆叠芯片180B的第二连接导体180WB的焊盘图案,并且在第一连接导体180WA和第二连接导体180WB是接合线的情况下,第三布线层112c的焊盘图案可以是布线焊盘。此时,第三布线层112c的布线焊盘的至少部分可通过形成在第一包封剂130中的开口131暴露,并且暴露的部分可连接到上述接合线。同时,如果需要,表面处理层(未示出)可形成在暴露的第三布线层112c的布线焊盘的表面上。表面处理层(未示出)不受具体限制,只要其在现有技术中是已知的即可,但可通过例如电镀金、无电镀金、有机可焊性保护层(OSP)或无电镀锡、无电镀银、无电镀镍/取代镀金、直接浸金(DIG)镀覆、热风整平(HASL)等形成。
第一连接过孔层113a和第二连接过孔层113b可使形成在不同层上的布线层112a、112b和112c彼此电连接,从而在芯构件110中形成电路径。第一连接过孔层113a和第二连接过孔层113b中的每个的材料可以是导电材料。第一连接过孔层113a和第二连接过孔层113b中的每个的连接过孔可利用导电材料完全填充,或者也可沿着通路孔中的每个的壁形成导电材料。另外,连接过孔中的每个可具有锥形形状。同时,当形成用于第一连接过孔层113a的通路孔时,第一布线层112a的焊盘图案的一部分可用作止挡件。因此,在工艺方面,第一连接过孔层113a可具有其上表面的宽度大于其下表面的宽度的锥形形状。在这种情况下,第一连接过孔层113a可与第二布线层112b的焊盘图案一体形成。相似地,在工艺方面,第二连接过孔层113b也可具有其上表面的宽度大于其下表面的宽度的锥形形状。在这种情况下,第二连接过孔层113b可与第三布线层112c的焊盘图案一体形成。
第一半导体芯片120A可以是按照在单个芯片中集成数量为数百至数百万或更多的元件而设置的集成电路(IC)。在这种情况下,构成第一半导体芯片120A的集成电路可以是例如易失性存储器(诸如DRAM)。第一半导体芯片120A可在有效晶圆的基础上形成。在这种情况下,主体的基体材料可以是硅(Si)、锗(Ge)、砷化镓(GaAs)等。主体上可形成各种电路。第一连接焊盘120PA可使第一半导体芯片120A电连接到其他组件,可使用诸如铝(Al)等的导电材料作为第一连接焊盘120PA中的每个的材料,而不具有任何具体的限制。其上设置有第一连接焊盘120PA的表面可以是有效表面,背对的表面可以是无效表面。使第一连接焊盘120PA暴露的钝化层(未示出)可形成在主体上,并且可以是氧化物层、氮化物层等,或者是氧化物层和氮化物层的双层。可在其他需要的位置进一步设置绝缘膜(未示出)等,并且还可在有效表面上形成重新分布层(未示出)。
第二半导体芯片120B也可以是按照在单个芯片中集成数量为数百至数百万或更多的元件而设置的集成电路(IC)。此时,构成第二半导体芯片120B的集成电路可以是例如控制器。第二半导体芯片120B也可在有效晶圆的基础上形成。细节如上所述。如果需要,芯构件110可仅具有第一通孔110HA,仅第一半导体芯片120A或仅第二半导体芯片120B可设置在第一通孔110HA中,并且第一半导体芯片120A和第二半导体芯片120B也可同时设置在第一通孔110HA中。
第一包封剂130可保护芯构件110、第一半导体芯片120A和第二半导体芯片120B等。第一包封剂130的包封形式不受具体限制,并且可以是第一包封剂130包围芯构件110的至少一部分、第一半导体芯片120A的至少一部分和第二半导体芯片120B等的至少一部分的形式。例如,第一包封剂130可覆盖芯构件110、第一半导体芯片120A、第二半导体芯片120B并且可填充第一通孔110HA和第二通孔110HB中的每个的至少一部分。第一包封剂130的具体材料没有具体限制。例如,绝缘材料可用作第一包封剂130的具体材料。在这种情况下,绝缘材料可以是包括无机填料和绝缘树脂(诸如环氧树脂的热固性树脂、诸如聚酰亚胺树脂的热塑性树脂)的材料,例如,诸如无机填料的增强材料浸在热固性树脂或热塑性树脂中的材料(诸如ABF、FR-4、BT等)。可选地,环氧塑封料(EMC)、PID等可用作绝缘材料。可选地,热固性树脂或热塑性树脂与无机填料一起浸在诸如玻璃布(或玻璃织物)的芯材料中的半固化片也可用作绝缘材料。
连接构件140可使第一半导体芯片120A的第一连接焊盘120PA和第二半导体芯片120B的第二连接焊盘120PB和/或第一堆叠芯片180A和第二堆叠芯片180B的连接焊盘(未示出)重新分布,并且可使它们彼此电连接。具有各种功能的数十到数百万个连接焊盘可通过连接构件140重新分布,并且可根据功能通过电连接结构170物理地和/或电连接到外部。连接构件140可包括绝缘层141、设置在绝缘层141上的重新分布层142以及穿透绝缘层141并使重新分布层142彼此连接的连接过孔143。在根据示例性实施例的扇出型半导体封装件100A中,连接构件140可包括多个层,但是也可包括单个层。
绝缘层141中的每个的材料可以是绝缘材料。在这种情况下,除了如上所述的绝缘材料之外,诸如PID树脂的光敏绝缘材料也可用作绝缘材料。也就是说,绝缘层141可以是光敏绝缘层。当绝缘层141具有光敏性质时,绝缘层141可形成为具有较小的厚度,并且可更容易实现连接过孔143的精细节距。绝缘层141可以是包括绝缘树脂和无机填料的光敏绝缘层。当绝缘层141是多层时,绝缘层141的材料可彼此相同,并且如果需要,也可以彼此不同。当绝缘层141是多层时,绝缘层141可根据工艺彼此形成为一体,使得它们之间的边界也可以不明显。
重新分布层142可大体用于使连接焊盘重新分布。重新分布层142中的每个的材料可以是诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金的导电材料。重新分布层142可根据相应层的设计执行各种功能。例如,重新分布层142可包括接地(GND)图案、电力(PWR)图案、信号(S)图案等。这里,信号(S)图案可包括除接地(GND)图案、电力(PWR)图案等之外的各种信号图案(诸如数据信号图案等)。另外,重新分布层142可包括过孔焊盘、电连接结构焊盘等。如果需要,表面处理层(未示出)可形成在一些重新分布层142的通过钝化层150的开口151暴露的表面上。表面处理层(未示出)可通过例如电镀金、无电镀金、有机可焊性保护层(OSP)或无电镀锡、无电镀银、无电镀镍/取代镀金、直接浸金(DIG)镀覆、热风整平(HASL)等形成,但不限于此。同时,芯构件110的布线层112a、112b和112c的厚度可大于连接构件140的重新分布层142的厚度。由于芯构件110的厚度可等于或大于第一半导体芯片120A和第二半导体芯片120B的厚度,因此形成在芯构件110上的布线层112a、112b和112c也可根据芯构件110的规格而以大尺寸形成。另一方面,为了连接构件140的纤薄化,连接构件140的重新分布层142可以以比芯构件110的布线层112a、112b和112c的尺寸相对小的尺寸形成。
连接过孔143可使形成在不同层上的重新分布层142、连接焊盘120PA和120PB等彼此电连接,从而在扇出型半导体封装件100A中形成电路径。连接过孔143中的每个的材料可以是诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金的导电材料。连接过孔143中的每个可利用导电材料完全填充,或者导电材料也可沿着通路孔中的每个的壁形成。另外,各个连接过孔143可具有在彼此相同方向上的锥形形状。
钝化层150可另外被构造为保护连接构件140免受外部的物理或化学损坏。钝化层150可具有使连接构件140的重新分布层142的最下方重新分布层的至少部分暴露的开口151。形成在钝化层150中的开口151的数量可以是数十至数百万。弹性模量比连接构件140的绝缘层141的弹性模量大的材料可用作钝化层150的材料。例如,不包括玻璃布(或玻璃织物)但包括无机填料和绝缘树脂的ABF等可用作钝化层150的材料。当ABF等用作钝化层150的材料时,包括在钝化层150中的无机填料的重量百分比可大于包括在连接构件140的绝缘层141中的无机填料的重量百分比。在这种条件下,可改善可靠性。当ABF等用作钝化层150的材料时,钝化层150可以是包括无机填料的非光敏绝缘层,并且可在改善可靠性方面是有效的,但不限于此。
凸块下金属部160可具有另外的构造并且可改善电连接结构170的连接可靠性,以改善扇出型半导体封装件100A的板级可靠性。凸块下金属部160可连接到连接构件140的通过钝化层150的开口151暴露的重新分布层142。凸块下金属部160可使用诸如金属的已知的导电材料通过已知的金属化方法形成在钝化层150的开口151中,但不限于此。
电连接结构170可被另外构造为使扇出型半导体封装件100A物理连接和/或电连接到外部。例如,扇出型半导体封装件100A可通过电连接结构170安装在电子装置的主板上。电连接结构170中的每个可利用低熔点金属(例如,锡(Sn)或包括锡(Sn)的合金材料)形成,更具体地,可利用焊料等形成。然而,这仅是示例,并且电连接结构170中的每个的材料不具体局限于此。电连接结构170中的每个可以是焊盘、焊球、引脚等。电连接结构170可形成为多层结构或单层结构。当电连接结构170形成为多层结构时,电连接结构170可包括铜(Cu)柱和焊料。当电连接结构170形成为单层结构时,电连接结构170可包括锡-银焊料或铜(Cu)。然而,电连接结构170不限于此。
电连接结构170的数量、间距、设置形式等不受具体地限制,而是本领域技术人员可根据设计细节进行充分地修改。例如,电连接结构170可根据连接焊盘的数量按照数十至数百万的数量设置,或者可按照数十至数百万或更多或者数十至数百万或更少的数量设置。当电连接结构170为焊球时,电连接结构170可覆盖凸块下金属部160的延伸到钝化层150的下表面上的侧表面,并且连接可靠性可以是更优异的。电连接结构170中的至少一个可设置在扇出区域中。扇出区域是除了设置有第一半导体芯片120A和第二半导体芯片120B的区域之外的区域。扇出型封装件可具有比扇入型封装件的可靠性更优异的可靠性,可实现多个I/O端子,并且可易于执行3D互连。此外,与球栅阵列(BGA)封装件、栅格阵列(LGA)封装件等相比,扇出型封装件可被制造为具有小的厚度,并且可具有价格竞争力。
第一堆叠芯片180A和第二堆叠芯片180B中的每个可通过以3D形式堆叠多个集成电路来实现。此时,构成第一堆叠芯片180A和第二堆叠芯片180B中的每个的集成电路可以是闪存。更具体地,第一堆叠芯片180A和第二堆叠芯片180B中的每个可以是3D形状的堆叠型NAND闪存。第一堆叠芯片180A和第二堆叠芯片180B的各个堆叠存储器的连接焊盘(未示出)可通过连接导体180WA和180WB连接到芯构件110的第三布线层112c的焊盘图案,可通过芯构件110的布线层112a、112b和112c电连接到连接构件140的重新分布层142,并且可电连接到第一半导体芯片120A和第二半导体芯片120B的连接焊盘120PA和120PB或电连接结构170。连接导体180WA和180WB可以是诸如金属线的已知的接合线。第一堆叠芯片180A可设置在第一半导体芯片120A上并在第一堆叠芯片180A堆叠在第一半导体芯片120A上所沿的竖直方向上与第一半导体芯片120A重叠,第二堆叠芯片180B可设置在第二半导体芯片120B上并在第二堆叠芯片180B堆叠在第二半导体芯片120B上所沿的竖直方向上与第二半导体芯片120B重叠。第一半导体芯片120A的第一连接焊盘120PA中的至少一个可通过连接构件140的重新分布层142电连接到电连接结构170中的至少一个,并且第一半导体芯片120A的第一连接焊盘120PA中的至少另一个可通过连接构件140的重新分布层142以及芯构件110的布线层112a、112b和112c电连接到第一堆叠芯片180A。相似地,第二半导体芯片120B的第二连接焊盘120PB中的至少一个可通过连接构件140的重新分布层142电连接到电连接结构170中的至少一个,并且第二半导体芯片120B的第二连接焊盘120PB中的至少另一个可通过连接构件140的重新分布层142以及芯构件110的布线层112a、112b和112c电连接到第二堆叠芯片180B。
第二包封剂190可保护第一堆叠芯片180A和第二堆叠芯片180B。第二包封剂190的包封形式不受具体限制,但可以是第二包封剂190包围第一堆叠芯片180A的至少一部分和第二堆叠芯片180B的至少一部分的形式。例如,第二包封剂190可覆盖第一堆叠芯片180A和第二堆叠芯片180B,使得第一堆叠芯片180A和第二堆叠芯片180B完全嵌入。第二包封剂190的具体材料没有具体限制。例如,可使用绝缘材料作为第二包封剂190的具体材料。在这种情况下,绝缘材料可以是包括无机填料和绝缘树脂(诸如环氧树脂的热固性树脂、诸如聚酰亚胺树脂的热塑性树脂)的材料,例如,诸如无机填料的增强材料浸在热固性树脂或热塑性树脂中的树脂(诸如ABF、FR-4、BT)等。另外,环氧塑封料、PID等也可用作绝缘材料,并且热固性树脂或热塑性树脂与无机填料一起浸在诸如玻璃布的芯材料中的半固化片也可用作绝缘材料。
同时,虽然在附图中未示出,但是单独的无源组件可被设置为与通孔110HA和110HB中的半导体芯片120A和120B一起并排。可选地,单独的无源元件也可安装在钝化层150的下表面上。另外,为了电磁屏蔽和热辐射效果,金属层可设置在通孔110HA和110HB的壁上。
图11是示出扇出型半导体封装件的另一示例的示意性截面图。
参照附图,根据本公开中的另一示例性实施例的扇出型半导体封装件100B还可包括设置在第一包封剂130上的背侧重新分布层132、穿透第一包封剂130的至少一部分并使背侧重新分布层132和芯构件110的第三布线层112c彼此电连接的背侧过孔133以及设置在第一包封剂130上并覆盖背侧重新分布层132的至少部分的覆盖层195。此时,第一堆叠芯片180A和第二堆叠芯片180B可设置在覆盖层195上,并且可分别通过第一连接导体180WA和第二连接导体180WB电连接到背侧重新分布层132。更具体地,第一堆叠芯片180A和第二堆叠芯片180B中的每个可安装在覆盖层195的上表面上,第一连接导体180WA和第二连接导体180WB中的每个可包括接合线,背侧重新分布层132可包括布线焊盘,覆盖层195可具有使布线焊盘的至少一部分暴露的开口197,并且接合线可连接到暴露的布线焊盘。
背侧重新分布层132可用于使第一半导体芯片120A和第二半导体芯片120B的连接焊盘120PA和120PB以及第一堆叠芯片180A和第二堆叠芯片180B的连接焊盘(未示出)重新分布,诸如(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金的导电材料可用作背侧重新分布层132的材料。背侧重新分布层132可根据设计执行各种功能。例如,背侧重新分布层132可包括接地(GND)图案、电力(PWR)图案、信号(S)图案等。这里,信号(S)图案可包括除接地(GND)图案、电力(PWR)图案等之外的各种信号图案(诸如数据信号图案等)。另外,背侧重新分布层132可包括过孔焊盘、布线焊盘、电连接结构焊盘等。背侧重新分布层132的部分可通过形成在覆盖层195中的开口197暴露,并且暴露的背侧重新分布层132可连接到如上所述的接合线。也就是说,暴露的背侧重新分布层可包括连接到布线的布线焊盘。同时,如果需要,表面处理层(未示出)可形成在暴露的背侧重新分布层132的表面上。表面处理层(未示出)可通过例如电镀金、无电镀金、OSP或无电镀锡、无电镀银、无电镀镍/取代镀金、DIG镀覆、HASL等形成。
背侧过孔133可使形成在不同层上的背侧重新分布层132、第三布线层112c等彼此电连接,从而在扇出型半导体封装件100B中形成电路径。背侧过孔133的材料可以是诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金的导电材料。背侧过孔133中的每个可利用导电材料完全填充,或者导电材料可沿着通路孔中的每个的壁形成。另外,背侧过孔133可具有在与连接构件140的连接过孔143相反的方向上的锥形形状。其他内容与上面描述的其他内容重复,因此省略其详细描述。
图12是示出扇出型半导体封装件的另一示例的示意性截面图。
图13是示出扇出型半导体封装件的另一示例的示意性截面图。
参照附图,在根据本公开中的另一示例性实施例的扇出型半导体封装件100C和100D中,与上面描述的扇出型半导体封装件100A和100B不同,芯构件110可包括:第一绝缘层111a;第一布线层112a和第二布线层112b,分别设置在第一绝缘层111a的背对的表面上;第二绝缘层111b,设置在第一绝缘层111的下表面上并覆盖第一布线层112a;第三布线层112c,设置在第二绝缘层111b的下表面上;第三绝缘层111c,设置在第一绝缘层111a的上表面上并覆盖第二布线层112b;第四布线层112d,设置在第三绝缘层111c的上表面上。由于芯构件110可包括更多数量的布线层112a、112b、112c和112d,因此可进一步简化连接构件140。因此,可抑制根据在形成连接构件140的工艺中发生的缺陷而导致良率的下降。同时,第一布线层112a、第二布线层112b、第三布线层112c和第四布线层112d可通过分别穿过第一绝缘层111a的第一连接过孔层113a、穿过第二绝缘层111b的第二连接过孔层113b和穿过第三绝缘层111c的第三连接过孔层113c彼此电连接。
第一绝缘层111a可具有比第二绝缘层111b的厚度和第三绝缘层111c的厚度大的厚度。第一绝缘层111a可基本上相对厚,以保持刚性,可引入第二绝缘层111b和第三绝缘层111c,以形成更多数量的布线层112c和112d。第一绝缘层111a可包括与第二绝缘层111b和第三绝缘层111c的绝缘材料不同的绝缘材料。例如,第一绝缘层111a可以是例如包括芯材料、无机填料和绝缘树脂的半固化片,第二绝缘层111b和第三绝缘层111c可以是包括无机填料和绝缘树脂的ABF或光敏绝缘膜。然而,第一绝缘层111a以及第二绝缘层111b和第三绝缘层111c的材料不限于此。
芯构件110的第三布线层112c可以以突出形式设置在第二绝缘层111b上,从而与连接构件140接触。芯构件110的第一布线层112a和第二布线层112b可设置在第一半导体芯片120A的有效表面和无效表面之间。芯构件110可以以与第一半导体芯片120A的厚度对应的厚度形成。因此,形成在芯构件110中的第一布线层112a和第二布线层112b可设置在第一半导体芯片120A的有效表面和无效表面之间的高度上。芯构件110的第一布线层112a、第二布线层112b、第三布线层112c和第四布线层112d的厚度可大于连接构件140的重新分布层142的厚度。由于芯构件110的厚度可等于或大于第一半导体芯片120A的厚度,因此布线层112a、112b、112c和112d也可以以较大的尺寸形成。另一方面,为了纤薄化,连接构件140的重新分布层142可以以相对小的尺寸形成。其他内容与上面描述的其他内容重复,因此省略其详细描述。
这里,与附图的截面相关的下侧、下部、下表面等用于指朝向扇出型半导体封装件的安装表面的方向,而上侧、上部、上表面等用于指与该方向相反的方向。然而,这些方向是为了便于说明而定义的,权利要求不被如上所述定义的方向具体限制。
在说明书中,组件与另一组件的“连接”的含义包括通过粘合层的间接连接以及两个组件之间的直接连接。另外,“电连接”意味着包括物理连接和物理断开的概念。可理解的是,当利用“第一”和“第二”来提及元件时,该元件不由此受限。它们可仅用于将元件与其他元件相区分的目的,并且可不限制元件的顺序或重要性。在一些情况下,在不脱离本公开的范围的情况下,第一组件可被称为第二组件并且第二组件也可类似地被称为第一组件。
在此使用的术语“示例性实施例”不指同一示例性实施例,而是被提供来突出与另一示例性实施例的特征或特性不同的特定的特征或特性。然而,在此提供的示例性实施例被认为为能够通过彼此全部组合或部分组合来实现。例如,除非在其中提供了相反或相矛盾的描述,否则特定的示例性实施例中描述的一个元件即使其在另一示例性实施例中没有被描述,也可被理解为与另一示例性实施例相关的描述。
在此使用的术语仅用于描述示例性实施例,而非限制本公开。在这种情况下,除非上下文中另外解释,否则单数形式包括复数形式。
如上面所阐述的,根据本公开中的示例性实施例,可提供一种能够同时执行各种功能、纤薄化且具有低的信号损耗的扇出型半导体封装件。
尽管上面已经示出并描述了示例性实施例,但是对于本领域技术人员将明显的是,可在不脱离本发明的由所附权利要求限定的范围的情况下做出修改和改变。
Claims (16)
1.一种扇出型半导体封装件,所述扇出型半导体封装件包括:
芯构件,具有第一通孔并包括一个或更多个布线层;
第一半导体芯片,设置在所述第一通孔中并具有形成在所述第一半导体芯片的下侧上的第一连接焊盘;
第一包封剂,覆盖所述芯构件的至少一部分和所述第一半导体芯片的至少一部分;
连接构件,设置在所述芯构件和所述第一半导体芯片的下方并包括一个或更多个重新分布层;
第一堆叠芯片,设置在所述第一包封剂上并通过第一连接导体电连接到所述芯构件的所述一个或更多个布线层;以及
第二包封剂,设置在所述第一包封剂上并覆盖所述第一堆叠芯片的至少一部分,
其中,所述第一半导体芯片包括动态随机存取存储器和控制器中的至少一者,
所述第一堆叠芯片包括堆叠型NAND闪存,并且
所述第一半导体芯片的所述第一连接焊盘通过所述连接构件的所述一个或更多个重新分布层电连接到所述芯构件的所述一个或更多个布线层。
2.根据权利要求1所述的扇出型半导体封装件,其中,所述第一堆叠芯片安装在所述第一包封剂的上表面上,
所述第一连接导体包括接合线,
所述一个或更多个布线层中的最上方布线层包括布线焊盘,
所述第一包封剂具有使所述布线焊盘的至少一部分暴露的开口,并且
所述接合线连接到暴露的所述布线焊盘。
3.根据权利要求1所述的扇出型半导体封装件,所述扇出型半导体封装件还包括:
背侧重新分布层,设置在所述第一包封剂上;
背侧过孔,穿透所述第一包封剂的至少一部分并使所述背侧重新分布层和所述一个或更多个布线层的最上方布线层彼此电连接;以及
覆盖层,设置在所述第一包封剂上并覆盖所述背侧重新分布层的至少一部分,
其中,所述第一堆叠芯片设置在所述覆盖层上并通过所述第一连接导体电连接到所述背侧重新分布层。
4.根据权利要求3所述的扇出型半导体封装件,其中,所述第一堆叠芯片安装在所述覆盖层的上表面上,
所述第一连接导体包括接合线,
所述背侧重新分布层包括布线焊盘,
所述覆盖层具有使所述布线焊盘的至少一部分暴露的开口,并且
所述接合线连接到暴露的所述布线焊盘。
5.根据权利要求1所述的扇出型半导体封装件,其中,所述芯构件还具有与所述第一通孔分开的第二通孔,
具有第二连接焊盘的第二半导体芯片设置在所述第二通孔中,
通过第二连接导体电连接到所述芯构件的所述一个或更多个布线层的第二堆叠芯片设置在所述第一包封剂上,
所述第一半导体芯片包括动态随机存取存储器,
所述第二半导体芯片包括控制器,并且
所述第二堆叠芯片包括堆叠型NAND闪存。
6.根据权利要求5所述的扇出型半导体封装件,其中,所述第一堆叠芯片在所述第一堆叠芯片和所述第一半导体芯片的堆叠方向上与所述第一半导体芯片重叠,
所述第二堆叠芯片在所述第二堆叠芯片和所述第二半导体芯片的堆叠方向上与所述第二半导体芯片重叠,并且
所述第一堆叠芯片和所述第二堆叠芯片设置为彼此并列。
7.根据权利要求1所述的扇出型半导体封装件,其中,所述芯构件包括:
第一绝缘层;
第一布线层,与所述连接构件接触并嵌在所述第一绝缘层中;
第二布线层,设置在所述第一绝缘层的与所述第一绝缘层的嵌有所述第一布线层的一个表面背对的另一表面上;以及
第一连接过孔层,穿透所述第一绝缘层并使所述第一布线层和所述第二布线层彼此电连接。
8.根据权利要求7所述的扇出型半导体封装件,其中,所述芯构件还包括:
第二绝缘层,设置在所述第一绝缘层上并覆盖所述第二布线层;
第三布线层,设置在所述第二绝缘层上;以及
第二连接过孔层,穿透所述第二绝缘层并使所述第二布线层和所述第三布线层彼此电连接。
9.根据权利要求7所述的扇出型半导体封装件,其中,所述第一绝缘层的下表面和所述第一布线层的下表面之间具有台阶。
10.根据权利要求1所述的扇出型半导体封装件,其中,所述芯构件包括:
第一绝缘层;
第一布线层和第二布线层,设置在所述第一绝缘层的背对的表面上;以及
第一连接过孔层,穿透所述第一绝缘层并使所述第一布线层和所述第二布线层彼此电连接。
11.根据权利要求10所述的扇出型半导体封装件,其中,所述芯构件还包括:
第二绝缘层,设置在所述第一绝缘层的下表面上并覆盖所述第一布线层;
第三布线层,设置在所述第二绝缘层的下表面上;
第二连接过孔层,穿透所述第二绝缘层并使所述第一布线层和所述第三布线层彼此电连接;
第三绝缘层,设置在所述第一绝缘层的上表面上并覆盖所述第二布线层;
第四布线层,设置在所述第三绝缘层的上表面上;以及
第三连接过孔层,穿透所述第三绝缘层并使所述第二布线层与所述第四布线层彼此电连接。
12.根据权利要求11所述的扇出型半导体封装件,其中,所述第一绝缘层的厚度大于所述第二绝缘层的厚度和所述第三绝缘层的厚度。
13.根据权利要求1所述的扇出型半导体封装件,所述扇出型半导体封装件还包括:
钝化层,设置在所述连接构件的下方并具有使所述连接构件的所述重新分布层的最下方重新分布层的至少一部分暴露的开口;
多个凸块下金属部,设置在所述钝化层的所述开口上并连接到暴露的所述最下方重新分布层;以及
多个电连接结构,设置在所述钝化层的下方并连接到所述多个凸块下金属部。
14.根据权利要求13所述的扇出型半导体封装件,其中,所述第一半导体芯片的所述第一连接焊盘中的至少一个通过所述连接构件的所述重新分布层电连接到所述电连接结构中的至少一个,并且
所述第一半导体芯片的所述第一连接焊盘中的至少另一个通过所述连接构件的所述一个或更多个重新分布层和所述芯构件的所述一个或更多个布线层电连接到所述第一堆叠芯片。
15.一种扇出型半导体封装件,所述扇出型半导体封装件包括:
芯构件,具有彼此分开的第一通孔和第二通孔,并包括一个或更多个布线层;
第一半导体芯片,设置在所述第一通孔中并具有形成在所述第一半导体芯片的下侧上的第一连接焊盘;
第二半导体芯片,设置在所述第二通孔中并具有形成在所述第二半导体芯片的下侧上的第二连接焊盘;
第一包封剂,覆盖所述芯构件的至少一部分、所述第一半导体芯片的至少一部分和所述第二半导体芯片的至少一部分;
连接构件,设置在所述芯构件、所述第一半导体芯片和所述第二半导体芯片的下方并包括一个或更多个重新分布层;
第一堆叠芯片,设置在所述第一包封剂上并通过第一连接导体电连接到所述芯构件的所述一个或更多个布线层;
第二堆叠芯片,设置在所述第一包封剂上并通过第二连接导体电连接到所述芯构件的所述一个或更多个布线层;以及
第二包封剂,设置在所述第一包封剂上并覆盖所述第一堆叠芯片的至少一部分和所述第二堆叠芯片的至少一部分,
其中,所述第一连接焊盘和所述第二连接焊盘通过所述连接构件的所述一个或更多个重新分布层分别电连接到所述芯构件的所述一个或更多个布线层。
16.根据权利要求15所述的扇出型半导体封装件,其中,所述第一半导体芯片包括动态随机存取存储器,
所述第二半导体芯片包括控制器,
所述第一堆叠芯片包括堆叠型NAND闪存,并且
所述第二堆叠芯片包括堆叠型NAND闪存。
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