CN107665852A - 使用含金属层以减小封装件形成中的载体冲击 - Google Patents

使用含金属层以减小封装件形成中的载体冲击 Download PDF

Info

Publication number
CN107665852A
CN107665852A CN201710519676.5A CN201710519676A CN107665852A CN 107665852 A CN107665852 A CN 107665852A CN 201710519676 A CN201710519676 A CN 201710519676A CN 107665852 A CN107665852 A CN 107665852A
Authority
CN
China
Prior art keywords
dielectric layer
metal
layer
radiation
unsticking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710519676.5A
Other languages
English (en)
Other versions
CN107665852B (zh
Inventor
郑心圃
刘献文
林仪柔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN107665852A publication Critical patent/CN107665852A/zh
Application granted granted Critical
Publication of CN107665852B publication Critical patent/CN107665852B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H01L2221/68386—Separation by peeling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种方法包括在辐射可脱粘涂层上方形成介电层。辐射可脱粘涂层位于载体上方，并且辐射可脱粘涂层包括在其中的金属颗粒。在介电层上方形成金属柱。器件管芯附接至介电层。在包封材料中包封器件管芯和金属柱。多个再分布线形成在包封材料的第一侧上并且电连接至器件管芯和金属柱。通过对辐射可脱粘涂层上投射辐射源以分解辐射可脱粘涂层从而脱粘载体。在包封材料的第二侧上形成电连接件。电连接件电连接至金属柱。本发明实施例涉及一种形成半导体器件的方法。

Description

使用含金属层以减小封装件形成中的载体冲击
技术领域
本发明实施例涉及一种形成半导体器件的方法，更具体地，涉及使用含金属层以减小封装件形成中的载体冲击。
背景技术
随着半导体技术的发展，半导体芯片/管芯变得越来越小。同时，更多功能需要集成至半导体管芯内。因此，半导体管芯需要将越来越多的I/O焊盘封装至更小的区域内，并且因此I/O焊盘的密度随着时间增加。结果，半导体管芯的封装变得更加困难，这会对封装产量产生不利影响。
传统的封装技术可以划分为两类。在第一类中，晶圆上的管芯在它们被切割之前封装。这种封装技术具有一些有利的特征，诸如更大的生产量和更低的成本。此外，需要较少的底部填充物或模塑料。然而，这种封装技术还具有一些缺陷。由于管芯的尺寸正变得越来越小，并且相应的封装件可能仅为多输入型封装件，其中，每个管芯的I/O焊盘限制于直接位于相应的管芯的表面上方的区域。由于管芯的面积有限，I/O焊盘的数量由于I/O焊盘的间距的限制而受到限制。如果焊盘的间距减小，则可能发生焊料桥接。此外，在固定的球尺寸需求下，焊球必须具有特定尺寸，这进而限制可以封装在管芯表面上的焊球的数量。
在另一类封装中，在封装管芯之前从晶圆切割管芯。这种封装技术的有利特征在于可能形成输出型封装件，这意味着管芯上的I/O焊盘可以被重新分布至比管芯更大的区域，并且因此可以增加封装在管芯表面上的I/O焊盘的数量。该封装技术的另一有利特征是“已知良好管芯”被封装，以及丢弃有缺陷管芯，并且因此成本和精力不会浪费在缺陷管芯上。
发明内容
根据本发明的一些实施例，提供了一种形成半导体器件的方法，包括：在辐射可脱粘涂层上方形成介电层，其中，所述辐射可脱粘涂层位于载体上方，并且所述辐射可脱粘涂层中包括金属颗粒；在所述介电层上方形成金属柱；将器件管芯附接在所述介电层上方；将所述器件管芯和所述金属柱包封在包封材料中；在所述包封材料的第一侧上形成多条再分布线，其中，所述多条再分布线电连接至所述器件管芯和所述金属柱；通过在所述辐射可脱粘涂层上投射辐射源以分解所述辐射可脱粘涂层来脱粘所述载体；以及在所述包封材料的第二侧上形成电连接件，其中，所述电连接件电连接至所述金属柱。
根据本发明的另一些实施例，还提供了一种形成半导体器件的方法，包括：在载体上方形成毯式金属层；在所述毯式金属层上方形成介电层；在所述介电层上方形成金属柱；将器件管芯附接至所述介电层上；将所述器件管芯和所述金属柱包封在包封材料中；在所述包封材料的第一侧上形成多条第一再分布线，其中，所述多条第一再分布线位于所述器件管芯和所述金属柱上方并且电连接至所述器件管芯和所述金属柱；将所述载体从所述毯式金属层脱粘；以及去除所述毯式金属层。
根据本发明的又一些实施例，还提供了一种形成半导体器件的方法，包括：在辐射可脱粘涂层上方施加牺牲层，其中，所述辐射可脱粘涂层位于载体上方，并且所述辐射可脱粘涂层中包括金属颗粒；在所述牺牲层上方形成金属层；在所述金属层上方形成第一介电层，所述第一介电层下面的所述金属层未被图案化；图案化所述第一介电层以形成开口，所述金属层的部分通过所述开口暴露；形成多条第一再分布线，所述多条第一再分布线包括：迹线部分，具有接触所述第一介电层的顶面的底面；以及通孔部分，位于所述开口中；在所述多条第一再分布线上方形成第二介电层；在所述第二介电层上方形成金属柱，其中，所述金属柱通过所述第二介电层中的开口电连接至所述多条第一再分布线；将器件管芯附接在所述第二介电层上；将所述器件管芯和所述金属柱包封在包封材料中；通过分解所述辐射可脱粘涂层将所述载体从所述牺牲层脱粘；以及去除所述牺牲层。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的实施例。应该强调的是，根据工业中的标准实践，对各种部件没有按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或缩小。
图1至图11示出了根据一些实施例的在封装件的形成中的中间阶段的截面图。
图12至图18示出了根据一些实施例的在封装件的形成中的中间阶段的截面图。
图19至图23示出了根据一些实施例的在封装件的形成中的中间阶段的截面图。
图24示出了根据一些实施例的光热转换(LTHC)涂层的一部分的放大图。
图25示出了根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在...下面”、“在...下方”、“下部”、“在...上面”、“上部”等的空间相对术语，以便于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而在此使用的空间相对描述符可以同样地作相应的解释。
根据各个示例性实施例提供了堆叠封装(PoP)结构和形成该封装件的方法。讨论实施例的变型。贯穿各个视图和说明性实施例，相同的参考标号用于指定相同的元件。
图1至图11示出了根据一些实施例的在形成PoP封装件中的中间阶段的截面图。在如图25所示的工艺流程200中也示意性地示出了图1至图11中示出的步骤。
图1示出了载体10和层12。载体10可以是玻璃载体、陶瓷载体等。载体10可具有圆形的顶视图形状并且可具有硅晶圆的顶视图形状和尺寸。例如，载体10可以具有8英寸的直径、12英寸的直径等。层12形成在载体10上方，并且可以是可以被分解并且因此在热辐射下脱粘的辐射可脱粘膜/涂层。根据一些实施例，层12是由光热转换(LTHC)材料形成，层12可以与载体10一起从将在随后步骤中形成的上面的结构被去除。层12是载体10上的涂层。对应的步骤示出为图25中所示的工艺流程中的步骤202。因此，层12在下文中被称为LTHC涂层。根据本发明的一些实施例，LTHC涂层12包括炭黑(碳颗粒)、溶剂、硅填料、和/或环氧树脂。
图1示出了包括LTHC涂层12的一部分的区域11。在图24中示出了区域11的示意性放大图。根据一些实施例，LTHC涂层12包括在基材料6中分布的并且示出为金属颗粒8的金属粉末。基材料6可以包括溶剂、硅填料、和环氧树脂。金属颗粒8可以由具有高热导率的铝、铜、钨、镍等形成。金属颗粒8可以由基本上纯金属形成(例如，具有大于约95％或更高的重量百分比)，并且不由氧化物、碳化物、氮化物等形成。金属颗粒8可以具有在约10％和约60％之间的体积百分比，但是更多或更少的金属颗粒8可以并入LTHC涂层12中。根据一些实施例，金属颗粒8具有足够大的体积百分比以使它们在整个LTHC涂层12中基本上连续地互连以用于有效热传递，而不形成离散的岛。
根据一些实施例，将金属粉末形式的金属颗粒8混合至如图24中所示的基材料6的现有LTHC材料中，以生成涂覆在载体10上的新的LTHC材料。
在PoP封装件(例如，图11中的封装件70)的形成中，具有多个热工艺。由于不同部位的材料差异和温度变化，载体10的不同区域可以具有不同的温度。另外，可以由玻璃形成的载体10具有高热膨胀系数(CTE)，并且响应于温度的变化显著地膨胀或缩小。载体10的不同部位的温度差异因此可以导致载体10上的热冲击，导致碎裂或破裂。有利地，通过将金属颗粒8并入LTHC涂层12，LTHC涂层12的热导率得以改善，并且可以帮助在周围散热以实现载体10的更均匀的热分布。载体10遭受的热冲击得以减小。此外，当金属颗粒8互连时，散热能力显著地改善。根据其他实施例，金属颗粒8形成为离散的颗粒和/或形成通过基材料6彼此分离的离散的岛的颗粒群。
根据可选实施例，LTHC涂层12不包括金属颗粒。根据这些实施例的LTHC涂层12可以包括炭黑、硅颗粒、溶剂、环氧树脂，以及可以或可以不包括金属氧化物颗粒。
参照回图1，在LTHC涂层12上形成层14。对应的步骤还示出为图25中所示的工艺流程中的步骤202。根据一些实施例，层14是牺牲层，并且可以称为牺牲层14。根据本发明的一些实施例，层14由聚合物形成，该聚合物也可以是诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的光敏材料。因此，可以通过曝光和显影图案化层14。牺牲层14是未被图案化的毯式层，并且具有平坦的顶面。
接下来，在毯式沉积步骤中，也可以是牺牲层的金属层16形成在牺牲层14上方。对应的步骤示出为图25中所示的工艺流程中的步骤204。根据本发明的一些实施例，金属层16具有复合结构，复合结构可以包括钛层16A和钛层16A上方的铜层16B。根据一些其它实施例，金属层16由可以包括铝、铜、铝铜、钛、或它们的合金的单一同质材料形成。类似于含金属的LTHC涂层12，在封装工艺中金属层16也具有再分布热量的功能。为了提高效率，金属层16的厚度T1可以足够大以获得满意的热量再分布能力。厚度T1可以大于用于镀敷的传统晶种层的厚度。根据一些实施例，厚度T1大于约0.5μm。可以使用例如物理汽相沉积(PVD)形成金属层16。
图2示出了介电层18和再分布线(RDL)20的形成。首先在金属层16上方形成介电层18。介电层18可以由与介电层14的材料不同或相同的材料形成。根据一些实施例，介电层18由诸如可以是PBO或聚酰亚胺的聚合物的有机材料形成。根据可选的实施例，介电层18由无机材料形成，例如，诸如氮化硅的氮化物、诸如氧化硅的氧化物、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺硼磷硅酸盐玻璃(BPSG)等形成。介电层18被图案化以形成开口(由RDL20占据)，通过开口暴露下面的金属层16。
接下来，形成RDL 20。对应的步骤示出为图25中所示的工艺流程中的步骤206。形成工艺包括形成毯式晶种层(未示出)、在晶种层上方形成图案化的掩模(未示出)、并且执行金属镀敷以形成RDL 20。晶种层包括在介电层18上方的部分和延伸至介电层18中的开口中以接触金属层16的部分。图案化的掩模层可以由光刻胶形成。根据一些实施例，晶种层包括钛层和钛层上方的铜层。根据可选实施例，晶种层包括单一铜层或单一铜合金层。可以使用，例如，PVD形成晶种层。在RDL 20的形成中，金属层16不用作晶种层。可以使用，例如，化学镀执行镀敷。镀敷的材料可以包括铜或铜合金。在镀敷之后，图案化的掩模被去除。在蚀刻步骤中，晶种层的之前由去除的图案化的掩模覆盖的部分被去除，留下如图2中的RDL20。RDL 20包括在介电层18中的通孔部分20A，和在介电层18上方的迹线部分20B。
参照图3，形成介电层24并且然后介电层24被图案化。对应的步骤示出为图25中所示的工艺流程中的步骤208。介电层24可以(或可以不)是由从用于形成介电层114和/或18的相同候选材料的组中所选择的材料形成的，并且可以由聚合物或无机材料形成。然后，图案化介电层24，并且暴露出RDL 20的一些部分。由于图案化，形成开口26。
图4示出了金属柱28的形成。对应的步骤示出为图25中所示的工艺流程中的步骤210。参照图4，金属晶种层33被形成并且延伸至开口26(图3)中。可以由光刻胶形成的图案化的掩模32形成在金属晶种层33上方并且被图案化，从而暴露晶种层33的一些部分。然后执行镀敷步骤以形成金属柱28。镀敷之后，图案化的掩模32被去除，接着去除晶种层33的由图案化的掩模32之前覆盖的部分。贯穿说明书，晶种层33的剩余部分被认为是金属柱28的部分。
图5示出了介电层24上方的器件管芯34的附接。对应的步骤示出为图25中所示的工艺流程中的步骤212。器件管芯34可以通过管芯附接膜36粘附至介电层24。管芯贴附膜36的边缘与相应的器件管芯34的对应边缘具有共同边界(垂直地对准)。管芯贴附膜36是粘合膜。尽管示出了一个器件管芯34，但是在该步骤中放置了与器件管芯34相同的多个器件管芯。多个放置的器件管芯可以布置为包括多行和多列的矩阵。器件管芯34可以包括半导体衬底，该半导体衬底的背面(面朝下的表面)与对应下面的管芯附接膜36物理接触。器件管芯34进一步包括在半导体衬底的正面(面朝上的表面)处的集成电路器件(诸如包括晶体管的有源器件，未示出)。器件管芯34可以是逻辑管芯，诸如中央处理单元(CPU)管芯、图形处理单元(GPU)管芯、移动应用管芯等。根据一些示例性实施例，器件管芯34包括连接至集成电路器件的金属支柱38，和覆盖和/或环绕金属支柱38的介电层40。根据一些实施例，金属支柱38可以是铜支柱。介电层40可以由诸如聚酰亚胺或PBO的聚合物形成。
如图6所示，接下来，执行包封，将器件管芯34包封在包封材料42中。对应的步骤示出为图25中所示的工艺流程中的步骤214。包封材料42可以是模塑料、模制底部填充物、环氧树脂和/或树脂。包封材料42填充相邻的金属柱28之间的间隙以及金属柱28和器件管芯34之间的间隙。包封材料42的顶面高于金属柱28的顶端。
接下来，执行诸如化学机械抛光(CMP)或机械研磨的平坦化步骤以薄化包封材料42，直到暴露金属柱28和金属支柱38。图6中示出得到的结构。由于平坦化，金属柱28的顶端与包封材料42的顶面和金属支柱38的顶面基本齐平(共面)。
参考图7，在包封材料42、金属柱28和金属支柱38上方形成一个或多个介电层46和相应的RDL 48。对应的步骤示出为图25中所示的工艺流程中的步骤216。根据本发明的一些实施例，介电层46由诸如PBO、聚酰亚胺等的聚合物形成。根据本发明的可选实施例，介电层46由诸如氮化硅、氧化硅、氮氧化硅等的无机介电材料形成。
RDL 48形成在介电层46中以电连接至金属支柱38和金属柱28。RDL 48也可以互连金属支柱38和金属柱28。RDL 48可以包括金属迹线(金属线)和位于金属迹线下面并且连接至金属迹线的通孔。根据本发明的一些实施例，通过镀敷工艺形成RDL 48，其中，每个RDL48均包括晶种层(未示出)和位于晶种层上方的镀敷的金属材料。RDL 48的每层的形成可以与RDL 20的形成相似。
图8示出了根据本发明的一些示例性实施例的凸块下金属(UBM)50和电连接件52的形成。电连接件52电连接至RDL 48、金属支柱38、和/或金属柱28。形成工艺可以包括在RDL 48上方形成顶部介电层47，并且然后图案化顶部介电层47以暴露RDL 48的金属焊盘。然后，形成UBM 50以延伸至顶部介电层47内。焊料球可以放置在UBM 50上方，并且然后回流以形成焊料区域52。根据本发明的可选实施例，电连接件52的形成包括执行镀敷步骤以在RDL 48上方形成焊料区域并且然后回流焊料区域。电连接件52还可以包括金属支柱或者金属支柱和焊帽，其也可以通过镀敷来形成。
又如图8所示，无源器件54(也表示多个无源器件)又接合至RDL 48。接合的无源器件(诸如无源器件54)可以包括电容器、电阻器、电感器等，并且可以是其中没有形成诸如晶体管和二极管的有源器件的离散器件。贯穿说明书，包括介电层14、金属层16、器件管芯34、金属柱28、包封材料42、RDL 48、介电层46、以及上面的部件的组合结构称为封装件56，其可以是复合晶圆。
接下来，封装件56从载体10脱粘。对应的步骤示出为图25中所示的工艺流程中的步骤218。根据一些示例性脱粘工艺，例如，通过穿过载体10对LTHC涂层12投射可以是激光或UV光的辐射53执行脱粘。由光或激光生成的热量导致LTHC涂层12分解，并且因此载体10从封装件56分离。图9中示出得到的结构。因此暴露介电层14。
然后，例如，在蚀刻步骤或机械研磨步骤中去除介电层14。对应的步骤示出为图25中所示的工艺流程中的步骤220。根据一些实施例，暴露的金属层16被完全地去除以暴露出RDL 20的通孔。在图25所示的工艺流程中还将相应的步骤示出为步骤220。还可以通过蚀刻或机械研磨执行金属层16的去除。根据可选实施例，代替完全地去除金属层16，在蚀刻步骤中图案化金属层16(使用诸如光刻胶的图案化掩模层，未示出)。金属层16的剩余部分形成包括金属迹线和金属焊盘的附加的RDL层。
图10示出了介电层14和金属层16(图9)被去除之后的结构。接下来，封装件60被接合至封装件56，因此形成如图11中所示的PoP封装件70。对应的步骤示出为图25中所示的工艺流程中的步骤222。虽然示出了一个封装件60，但是可以具有与封装件60相同的多个封装件接合至下面的封装件56。通过焊料区域62执行接合，该焊料区域使RDL 20连接至上面的封装件60中的金属焊盘。根据本发明的一些实施例，封装件60包括器件管芯64，该器件管芯64可以是诸如闪速存储器管芯、静态随机存取存储器(SRAM)管芯、动态随机存取存储器(DRAM)管芯等的存储器管芯。根据一些示例性实施例，存储器管芯也可以接合至封装件衬底66。
在将封装件60接合至封装件56之后，底部填充物68设置在封装件60和封装件56之间的间隙内。在随后的步骤中，如图11中所示的封装件被锯切成多个封装件，并且在图11中还示出了得到的PoP封装件70中的一个。复合晶圆56被锯开成多个封装件56'。封装件60和封装件56'也分别称为PoP封装件的顶部封装件和底部封装件。根据可选实施例，首先执行锯切以分离复合晶圆56，并且然后，从复合晶圆56锯切的封装件56'接合至顶部封装件60以形成PoP封装件70。
图12至图18和图19至图23示出了根据本发明的一些实施例的PoP封装件的形成中的中间阶段的截面图。除非另有说明，否则这些实施例中的组件的材料和形成方法与相同组件基本上相同，在图1至图11中示出的实施例中，相同组件由相同的参考标号表示。因此，关于图12至图23中示出的组件的形成工艺和材料的细节可以在图1至图11中示出的实施例的讨论中找到。
图12至图18中示出的实施例类似于图1至图11中示出的实施例，除了不形成金属层16(图1)和RDL 20(图11)以外。参照图12，在载体10上方形成LTHC涂层12。在图24中示出了LTHC涂层12的一部分，其中，金属颗粒8并入LTHC涂层12中。因此，在封装的随后热工艺中，LTHC涂层12的热导率被提高以减小载体10的热冲击。接下来，在LTHC涂层12上方形成介电层14'。根据一些实施例，介电层14'是毯式层。
图13示出了金属柱28的形成，其中，该形成工艺包括沉积金属晶种层(未示出)、形成诸如图案化的光刻胶的图案化的掩模(未示出)、镀金属柱28、去除图案化的掩模、以及蚀刻晶种层的由于图案化的掩模的去除暴露出的部分。接下来，如图14所示，器件管芯34通过管芯附接膜36附接至器件管芯14'。
图15示出了金属柱28和器件管芯34在包封材料42中的包封，接着进行平坦化步骤以露出金属支柱38和金属柱28。在随后的工艺中，如图16中所示，形成介电层46、RDL 48、UBM 50和电连接件52。无源器件54还接合至RDL 48。因此，形成可以是复合晶圆的封装件56。
接下来，例如，通过使用激光或UV光53以分解LTHC涂层12来将封装件56从载体10脱粘。图17中示出了相对于图16的取向上下倒置的所得到的结构。
在形成如图17中示出的结构之后，在介电层14'中形成开口(图18中由焊料区域62占据)。例如，可以使用激光钻孔图案化介电层14'以去除介电层14'的与金属柱28重叠的部分，从而通过开口暴露金属柱28。
接下来，如图18中所示，封装件60通过焊料区域62接合至金属柱28，其中，焊料区域62延伸至介电层14'中的开口中。还分配底部填充物68。相似地，可以在接合封装件60之前或之后锯切复合晶圆56。
图19至图23示出了根据可选实施例的在形成PoP封装件中的中间阶段的截面图。图19至图23中示出的实施例类似于图1至图11中示出的实施例，除了不形成如图11中示出的RDL 20，而形成如图1中所示的金属层16。
参照图19，形成LTHC涂层12，接下来依次地形成层14、金属层16、和介电层18'。根据一些实施例，LTHC涂层12包括如图24中示出的金属颗粒8，或可以没有金属颗粒。LTHC涂层12和金属层16均具有再分布/散热的功能以减小载体10遭受的热冲击。
如图20所示，形成金属柱28，接下来附接器件管芯34，以及将器件管芯34和金属柱28包封在包封材料42中。在已经形成金属柱28时，介电层18'保持未被图案化，并且保持为毯式层。图21示出了介电层46、RDL 48、UBM 50和电连接件52的形成。另外，接合无源器件54。然后，所得到的复合晶圆56通过LTHC涂层12的分解与载体10脱粘，其中，通过激光或UV光53执行LTHC涂层12的分解。图22中示出了得到的复合晶圆56。
接下来，例如，通过蚀刻和/或机械研磨去除如图22中所示的介电层14和金属层16。图23中示出得到的结构。随后的工艺步骤类似于参照图18所论述的工艺步骤，并且不在此赘述。所得到的结构基本上与图18中示出的结构相同。
本发明的实施例具有一些有利的特征。在根据本发明的实施例的封装工艺中，具有多个热工艺，诸如聚合物层的固化和包封材料的固化。热工艺导致玻璃载体的加热和冷却，由于不均匀的温度分布，该玻璃载体遭受碎裂和破裂。通过将金属颗粒并入LTHC涂层和/或在LTHC涂层上方形成金属层，由于LTHC涂层的增加的热导率和/或金属层的添加的热导率，可以减小整个载体10上的温度差。
根据本发明的一些实施例，一种方法包括在辐射可脱粘涂层上方形成介电层。辐射可脱粘涂层位于载体上方，并且辐射可脱粘涂层包括位于其中的金属颗粒。在介电层上方形成金属柱。器件管芯附接至介电层。在包封材料中包封器件管芯和金属柱。多条再分布线形成在包封材料的第一侧上并且电连接至器件管芯和金属柱。通过对辐射可脱粘涂层投射辐射源以分解辐射可脱粘涂层从而脱粘载体。在包封材料的第二侧上形成电连接件。电连接件电连接至金属柱。
根据本发明的一些实施例，一种方法包括在载体上方形成毯式金属层，在毯式金属层上方形成介电层，在介电层上方形成金属柱，将器件管芯附接至介电层上，在包封材料中包封器件管芯和金属柱，以及在包封材料的第一侧上形成多条第一再分布线。多条第一再分布线位于器件管芯和金属柱上方并且电连接至器件管芯和金属柱。该方法还包括将载体从毯式金属层脱粘，并且去除毯式金属层。
根据本发明的一些实施例，一种方法包括在辐射可脱粘涂层上方施加牺牲层，辐射可脱粘涂层位于载体上方，并且辐射可脱粘涂层具有在其中的金属颗粒。方法还包括在牺牲层上方形成金属层；在金属层上方形成第一介电层，其中，第一介电层下面的金属层是未被图案化的；图案化第一介电层以形成开口，其中，通过开口暴露金属层的部分；以及形成多条第一再分布线，该多条第一再分布线包括具有接触第一介电层的顶面的底面的迹线部分和位于开口中的通孔部分。该方法包括在多条第一再分布线上方形成第二介电层，并且在第二介电层上方形成金属柱。金属柱通过第二介电层中的开口电连接至多条第一再分布线。该方法还包括在第二介电层上附接器件管芯，将器件管芯和金属柱包封在包封材料中，通过分解辐射可脱粘涂层将载体从牺牲层脱粘，以及去除牺牲层。
根据本发明的一些实施例，提供了一种形成半导体器件的方法，包括：在辐射可脱粘涂层上方形成介电层，其中，所述辐射可脱粘涂层位于载体上方，并且所述辐射可脱粘涂层中包括金属颗粒；在所述介电层上方形成金属柱；将器件管芯附接在所述介电层上方；将所述器件管芯和所述金属柱包封在包封材料中；在所述包封材料的第一侧上形成多条再分布线，其中，所述多条再分布线电连接至所述器件管芯和所述金属柱；通过在所述辐射可脱粘涂层上投射辐射源以分解所述辐射可脱粘涂层来脱粘所述载体；以及在所述包封材料的第二侧上形成电连接件，其中，所述电连接件电连接至所述金属柱。
在上述方法中，所述金属颗粒包括铝、铜、钨、镍、或它们的组合。
在上述方法中，还包括将所述金属颗粒混合至所述辐射可脱粘涂层中。
在上述方法中，还包括：在所述载体上方形成毯式金属层，其中，在所述毯式金属层上方形成所述介电层；以及在执行所述包封之后，去除所述毯式金属层。
在上述方法中，所述毯式金属层被完全地去除。
在上述方法中，还包括：图案化所述介电层以形成开口，其中，所述毯式金属层通过所述开口暴露；形成延伸至所述开口中以接触所述毯式金属层的晶种层；以及执行镀敷以形成再分布线。
在上述方法中，还包括，其中，在形成所述金属柱之后，所述介电层保持未被图案化。
在上述方法中，在形成所述金属柱之后，所述介电层保持未被图案化。
根据本发明的另一些实施例，还提供了一种形成半导体器件的方法，包括：在载体上方形成毯式金属层；在所述毯式金属层上方形成介电层；在所述介电层上方形成金属柱；将器件管芯附接至所述介电层上；将所述器件管芯和所述金属柱包封在包封材料中；在所述包封材料的第一侧上形成多条第一再分布线，其中，所述多条第一再分布线位于所述器件管芯和所述金属柱上方并且电连接至所述器件管芯和所述金属柱；将所述载体从所述毯式金属层脱粘；以及去除所述毯式金属层。
在上述方法中，所述毯式金属层被完全地去除。
在上述方法中，还包括形成多条第二再分布线，所述金属柱位于所述多条第二再分布线上方并且电连接至所述多条第二再分布线，其中，所述多条第二再分布线包括：迹线部分，具有接触所述介电层的顶面的底面；以及通孔部分，延伸至所述介电层中以物理地接触所述毯式金属层，所述金属柱位于所述多条第二再分布线上方并且电连接至所述多条第二再分布线，其中，在去除所述毯式金属层之后，暴露所述多条第二再分布线的所述通孔部分。
在上述方法中，形成所述多条第二再分布线而无需将所述毯式金属层用作晶种层。
在上述方法中，在形成所述金属柱之后，所述介电层保持未被图案化，并且所述方法还包括：在去除所述毯式金属层之后，图案化所述介电层以形成开口，所述金属柱通过所述开口暴露。
在上述方法中，还包括：通过焊料区域将封装件接合至所述金属柱，其中，所述焊料区域延伸至所述开口中以结合所述金属柱。
在上述方法中，还包括：在辐射可脱粘涂层上方施加牺牲层，其中，所述辐射可脱粘涂层位于所述载体上方，并且所述辐射可脱粘涂层中包括金属颗粒，并且脱粘所述载体包括分解所述辐射可脱粘涂层。
根据本发明的又一些实施例，还提供了一种形成半导体器件的方法，包括：在辐射可脱粘涂层上方施加牺牲层，其中，所述辐射可脱粘涂层位于载体上方，并且所述辐射可脱粘涂层中包括金属颗粒；在所述牺牲层上方形成金属层；在所述金属层上方形成第一介电层，所述第一介电层下面的所述金属层未被图案化；图案化所述第一介电层以形成开口，所述金属层的部分通过所述开口暴露；形成多条第一再分布线，所述多条第一再分布线包括：迹线部分，具有接触所述第一介电层的顶面的底面；以及通孔部分，位于所述开口中；在所述多条第一再分布线上方形成第二介电层；在所述第二介电层上方形成金属柱，其中，所述金属柱通过所述第二介电层中的开口电连接至所述多条第一再分布线；将器件管芯附接在所述第二介电层上；将所述器件管芯和所述金属柱包封在包封材料中；通过分解所述辐射可脱粘涂层将所述载体从所述牺牲层脱粘；以及去除所述牺牲层。
在上述方法中，还包括：去除所述金属层。
在上述方法中，去除所述金属层的整体。
在上述方法中，还包括：去除所述牺牲层。
在上述方法中，还包括：形成电连接至所述器件管芯和所述金属柱的多条第二再分布线，其中，所述多条第一再分布线和所述多条第二再分布线位于所述包封材料的相对两侧上。
上面概述了若干实施例的部件、使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围、并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成半导体器件的方法，包括：
在辐射可脱粘涂层上方形成介电层，其中，所述辐射可脱粘涂层位于载体上方，并且所述辐射可脱粘涂层中包括金属颗粒；
在所述介电层上方形成金属柱；
将器件管芯附接在所述介电层上方；
将所述器件管芯和所述金属柱包封在包封材料中；
在所述包封材料的第一侧上形成多条再分布线，其中，所述多条再分布线电连接至所述器件管芯和所述金属柱；
通过在所述辐射可脱粘涂层上投射辐射源以分解所述辐射可脱粘涂层来脱粘所述载体；以及
在所述包封材料的第二侧上形成电连接件，其中，所述电连接件电连接至所述金属柱。
2.根据权利要求1所述的方法，其中，所述金属颗粒包括铝、铜、钨、镍、或它们的组合。
3.根据权利要求1所述的方法，还包括将所述金属颗粒混合至所述辐射可脱粘涂层中。
4.根据权利要求1所述的方法，还包括：
在所述载体上方形成毯式金属层，其中，在所述毯式金属层上方形成所述介电层；以及
在执行所述包封之后，去除所述毯式金属层。
5.根据权利要求4所述的方法，其中，所述毯式金属层被完全地去除。
6.根据权利要求4所述的方法，还包括：
图案化所述介电层以形成开口，其中，所述毯式金属层通过所述开口暴露；
形成延伸至所述开口中以接触所述毯式金属层的晶种层；以及
执行镀敷以形成再分布线。
7.根据权利要求4所述的方法，还包括，其中，在形成所述金属柱之后，所述介电层保持未被图案化。
8.根据权利要求1所述的方法，其中，在形成所述金属柱之后，所述介电层保持未被图案化。
9.一种形成半导体器件的方法，包括：
在载体上方形成毯式金属层；
在所述毯式金属层上方形成介电层；
在所述介电层上方形成金属柱；
将器件管芯附接至所述介电层上；
将所述器件管芯和所述金属柱包封在包封材料中；
在所述包封材料的第一侧上形成多条第一再分布线，其中，所述多条第一再分布线位于所述器件管芯和所述金属柱上方并且电连接至所述器件管芯和所述金属柱；
将所述载体从所述毯式金属层脱粘；以及
去除所述毯式金属层。
10.一种形成半导体器件的方法，包括：
在辐射可脱粘涂层上方施加牺牲层，其中，所述辐射可脱粘涂层位于载体上方，并且所述辐射可脱粘涂层中包括金属颗粒；
在所述牺牲层上方形成金属层；
在所述金属层上方形成第一介电层，所述第一介电层下面的所述金属层未被图案化；
图案化所述第一介电层以形成开口，所述金属层的部分通过所述开口暴露；
形成多条第一再分布线，所述多条第一再分布线包括：
迹线部分，具有接触所述第一介电层的顶面的底面；以及
通孔部分，位于所述开口中；
在所述多条第一再分布线上方形成第二介电层；
在所述第二介电层上方形成金属柱，其中，所述金属柱通过所述第二介电层中的开口电连接至所述多条第一再分布线；
将器件管芯附接在所述第二介电层上；
将所述器件管芯和所述金属柱包封在包封材料中；
通过分解所述辐射可脱粘涂层将所述载体从所述牺牲层脱粘；以及去除所述牺牲层。
CN201710519676.5A 2016-07-29 2017-06-30 形成半导体器件的方法 Active CN107665852B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/223,862 US10083949B2 (en) 2016-07-29 2016-07-29 Using metal-containing layer to reduce carrier shock in package formation
US15/223,862 2016-07-29

Publications (2)

Publication Number Publication Date
CN107665852A true CN107665852A (zh) 2018-02-06
CN107665852B CN107665852B (zh) 2020-06-05

Family

ID=61012245

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710519676.5A Active CN107665852B (zh) 2016-07-29 2017-06-30 形成半导体器件的方法

Country Status (3)

Country Link
US (2) US10083949B2 (zh)
CN (1) CN107665852B (zh)
TW (1) TWI640055B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110391219A (zh) * 2018-04-18 2019-10-29 三星电机株式会社 扇出型半导体封装件
CN113053757A (zh) * 2020-03-19 2021-06-29 台湾积体电路制造股份有限公司 封装件及其形成方法
CN113410144A (zh) * 2018-04-30 2021-09-17 台湾积体电路制造股份有限公司 半导体器件及其形成方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9935080B2 (en) * 2016-04-29 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Three-layer Package-on-Package structure and method forming same
US10269589B2 (en) * 2017-06-30 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a release film as isolation film in package
US11610855B2 (en) * 2017-11-29 2023-03-21 Pep Innovation Pte. Ltd. Chip packaging method and package structure
US11011502B2 (en) * 2018-01-19 2021-05-18 Nepes Co., Ltd. Semiconductor package
US10886231B2 (en) 2018-06-29 2021-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming RDLS and structure formed thereof
KR102540829B1 (ko) * 2018-10-05 2023-06-08 삼성전자주식회사 반도체 패키지, 반도체 패키지 제조방법 및 재배선 구조체 제조방법
KR20210152721A (ko) * 2020-06-09 2021-12-16 삼성전자주식회사 반도체 패키지

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140252646A1 (en) * 2013-03-06 2014-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect Structure for Package-on-Package Devices

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7156527B2 (en) * 2003-03-06 2007-01-02 3M Innovative Properties Company Lamina comprising cube corner elements and retroreflective sheeting
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
US9985150B2 (en) 2010-04-07 2018-05-29 Shimadzu Corporation Radiation detector and method of manufacturing the same
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
JP5949193B2 (ja) 2012-06-12 2016-07-06 富士通株式会社 電子装置の製造方法
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US8653626B2 (en) 2012-07-18 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures including a capacitor and methods of forming the same
US20140024264A1 (en) * 2012-07-18 2014-01-23 Hsuan-Ho CHUNG Portable electronic device
CN103811358A (zh) * 2012-11-13 2014-05-21 矽品精密工业股份有限公司 半导体封装件的制法
TWI500090B (zh) * 2012-11-13 2015-09-11 矽品精密工業股份有限公司 半導體封裝件之製法
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US9368438B2 (en) 2012-12-28 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package (PoP) bonding structures
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9461025B2 (en) 2013-03-12 2016-10-04 Taiwan Semiconductor Manfacturing Company, Ltd. Electric magnetic shielding structure in packages
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9583420B2 (en) * 2015-01-23 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufactures
US9735134B2 (en) * 2014-03-12 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with through-vias having tapered ends
JP6287627B2 (ja) 2014-06-25 2018-03-07 住友金属鉱山株式会社 光熱変換層、ドナーシート
US9754928B2 (en) * 2014-07-17 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. SMD, IPD, and/or wire mount in a package
US9812337B2 (en) 2014-12-03 2017-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package pad and methods of forming
US9659805B2 (en) * 2015-04-17 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and methods forming the same
US9685411B2 (en) * 2015-09-18 2017-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit dies having alignment marks and methods of forming same
US9646946B2 (en) * 2015-10-07 2017-05-09 Invensas Corporation Fan-out wafer-level packaging using metal foil lamination
US9735131B2 (en) * 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US9773757B2 (en) * 2016-01-19 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaged semiconductor devices, and semiconductor device packaging methods
US9761522B2 (en) * 2016-01-29 2017-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Wireless charging package with chip integrated in coil center
US9691708B1 (en) * 2016-07-20 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140252646A1 (en) * 2013-03-06 2014-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect Structure for Package-on-Package Devices

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110391219A (zh) * 2018-04-18 2019-10-29 三星电机株式会社 扇出型半导体封装件
CN110391219B (zh) * 2018-04-18 2022-12-20 三星电机株式会社 扇出型半导体封装件
CN113410144A (zh) * 2018-04-30 2021-09-17 台湾积体电路制造股份有限公司 半导体器件及其形成方法
CN113410144B (zh) * 2018-04-30 2024-01-30 台湾积体电路制造股份有限公司 半导体器件及其形成方法
CN113053757A (zh) * 2020-03-19 2021-06-29 台湾积体电路制造股份有限公司 封装件及其形成方法
CN113053757B (zh) * 2020-03-19 2024-05-24 台湾积体电路制造股份有限公司 封装件及其形成方法

Also Published As

Publication number Publication date
US20180033782A1 (en) 2018-02-01
US10083949B2 (en) 2018-09-25
US20190027469A1 (en) 2019-01-24
TW201804557A (zh) 2018-02-01
US10354988B2 (en) 2019-07-16
TWI640055B (zh) 2018-11-01
CN107665852B (zh) 2020-06-05

Similar Documents

Publication Publication Date Title
CN107665852A (zh) 使用含金属层以减小封装件形成中的载体冲击
US11637084B2 (en) Semiconductor package having a through intervia through the molding compound and fan-out redistribution layers disposed over the respective die of the stacked fan-out system-in-package
US11069656B2 (en) Three-layer package-on-package structure and method forming same
US10879162B2 (en) Integrated fan-out packages
US9972581B1 (en) Routing design of dummy metal cap and redistribution line
US10170457B2 (en) COWOS structures and method of forming the same
CN105225967B (zh) 封装半导体器件的方法和封装的半导体器件
CN109216207A (zh) 封装件及其形成方法
TW202125657A (zh) 製造半導體封裝的方法以及半導體封裝
CN109309013A (zh) Lthc在形成封装件中作为电荷阻挡层、封装件及其形成方法
TW202002192A (zh) 晶片封裝件
TWI590416B (zh) 封裝及形成封裝的方法
TWI805170B (zh) 包含散熱塊的積體扇出型封裝與其製造方法
TWI802210B (zh) 封裝結構及其製造方法
US11495506B2 (en) Semiconductor package with separate electric and thermal paths
US11955455B2 (en) Embedded stress absorber in package
TWI825917B (zh) 用於三維積體電路電源分配的方法及半導體裝置
US20230395519A1 (en) Semiconductor package with substrate recess and methods for forming the same
US20230386988A1 (en) Semiconductor package with variable pillar height and methods for forming the same
US20240071849A1 (en) Semiconductor package and method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant