CN109309013A - Lthc在形成封装件中作为电荷阻挡层、封装件及其形成方法 - Google Patents

Lthc在形成封装件中作为电荷阻挡层、封装件及其形成方法 Download PDF

Info

Publication number
CN109309013A
CN109309013A CN201810836178.8A CN201810836178A CN109309013A CN 109309013 A CN109309013 A CN 109309013A CN 201810836178 A CN201810836178 A CN 201810836178A CN 109309013 A CN109309013 A CN 109309013A
Authority
CN
China
Prior art keywords
coating material
buffer layer
layer
polymer buffer
packaging part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201810836178.8A
Other languages
English (en)
Other versions
CN109309013B (zh
Inventor
赖怡仁
林忠仪
郑锡圭
陈承先
刘国洲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN109309013A publication Critical patent/CN109309013A/zh
Application granted granted Critical
Publication of CN109309013B publication Critical patent/CN109309013B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60Protection against electrostatic charges or discharges, e.g. Faraday shields
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20Structure, shape, material or disposition of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68331Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0231Manufacturing methods of the redistribution layers
    • H01L2224/02311Additive methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0231Manufacturing methods of the redistribution layers
    • H01L2224/02319Manufacturing methods of the redistribution layers by using a preform
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0233Structure of the redistribution layers
    • H01L2224/02331Multilayer structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02372Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02375Top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02379Fan-out arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02381Side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0618Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181On opposite sides of the body
    • H01L2224/06182On opposite sides of the body with specially adapted redistribution layers [RDL]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13024Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/274Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2743Manufacturing methods by blanket deposition of the material of the layer connector in solid form
    • H01L2224/27436Lamination of a preform, e.g. foil, sheet or layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92142Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/0651Wire or wire-like electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

一种方法包括在载体上方形成释放膜,在释放膜上方形成聚合物缓冲层,在聚合物缓冲层上形成金属柱,将金属柱密封在密封材料中,对密封材料实施平坦化以暴露金属柱,在密封材料和金属柱上方形成再分布结构,以及分解释放膜的第一部分。分解后留下释放膜的第二部分。在聚合物缓冲层中形成开口以暴露金属柱。本发明的实施例还提供了LTHC在形成封装件中作为电荷阻挡层、封装件及其形成方法。

Description

LTHC在形成封装件中作为电荷阻挡层、封装件及其形成方法
技术领域
本发明的实施例一般地涉及半导体技术领域,更具体地,涉及LTHC在形成封装件中作为电荷阻挡层、封装件及其形成方法。
背景技术
随着半导体技术的发展,半导体芯片/管芯变得越来越小。同时,需要将更多功能集成到半导体管芯中。因此,半导体管芯需要具有封装到更小的面积中的越来越多数量的I/O焊盘,并且I/O焊盘的密度随着时间快速增加。结果,封装半导体管芯变得更加困难,这对封装件的产量有不利影响。
传统的封装技术可以分成两类。在第一类中,晶圆上的管芯被切割之前,对其进行封装。这种封装技术具有一些有利的特征,例如更大的产量和更低的成本。此外,需要较少的底部填充物或模塑料。但是,这种封装技术也存在缺点。由于管芯的尺寸变得越来越小,并且相应的封装件只能是扇入型封装件,其中,每个管芯的I/O焊盘受限于直接位于相应管芯的表面上方的区域。通过有限的管芯面积中,I/O焊盘的数量由于I/O焊盘的间距的限制而受到限制。如果要减小焊盘的间距,则可能出现焊桥。此外,在固定焊球尺寸的要求下,焊球必须具有一定的尺寸,这转而限制了可以封装在管芯表面上的焊球的数量。
在另一类封装中,在封装管芯之前,从晶圆上切割该管芯。这种封装技术的有利特征是可能形成扇出封装件,这意味着可以将管芯上的I/O焊盘重新分配到比管芯更大的面积,并且因此可以增加封装在管芯表面上的I/O焊盘的数量。这种封装技术的另一个有利特征是封装了“已知良好的管芯”,并且丢弃了有缺陷的管芯,并且因此不会在有缺陷的管芯上浪费成本和精力。
发明内容
根据本发明的一方面,提供了一种用于形成封装件的方法,包括:在载体上方形成释放膜;在所述释放膜上方形成聚合物缓冲层;在所述聚合物缓冲层上形成金属柱;将所述金属柱密封在密封材料中;对所述密封材料实施平坦化以暴露所述金属柱;在所述密封材料和所述金属柱上方形成再分布结构;分解所述释放膜的第一部分,其中,在所述分解之后留下所述释放膜的第二部分;以及在所述聚合物缓冲层中形成开口以暴露所述金属柱。
根据本发明的另一方面,提供了一种用于形成封装件的方法,包括:在载体上涂覆光热转换(LTHC)涂层材料;在所述光热转换涂层材料上方形成聚合物缓冲层;形成与所述聚合物缓冲层接触的金属晶种层;在所述金属晶种层上方形成图案化光刻胶,其中,通过所述图案化光刻胶中的开口暴露所述金属晶种层的部分;在所述金属晶种层上方镀敷金属柱;去除所述图案化光刻胶;蚀刻所述金属晶种层以暴露所述聚合物缓冲层;将激光束投射在所述光热转换涂层材料上,其中,所述激光束的工作范围覆盖所述光热转换涂层材料的第一部分,并且所述光热转换涂层材料的第二部分不在所述工作范围内;剥离所述载体;以及形成穿透所述光热转换涂层材料的第二部分的焊料区域。
根据本发明的又一方面,提供了一种封装件包括:密封材料;通孔,所述通孔穿透所述密封材料;聚合物缓冲层,所述聚合物缓冲层与所述通孔和所述密封材料接触;光热转换(LTHC)涂层材料,所述光热转换涂层材料与所述聚合物缓冲层接触;以及焊料区域,所述焊料区域穿透所述光热转换涂层材料和所述聚合物缓冲层。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳地理解本发明的各个方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或减小。
图1至图18A示出了根据一些实施例的形成封装件的中间阶段的截面图。
图18B示出了根据一些实施例的封装件的截面图。
图19A和图19B分别示出了根据一些实施例的封装件中的释放膜的部分的顶视图和截面图。
图19C示出了根据一些实施例的释放膜的部分的放大视图。
图20A和图20B示意性地示出了激光扫描之前和之后的释放膜的部分。
图21示出了根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开内容提供了用于实现本发明的不同特征的许多不同实施例或实例。下面描述了组件和布置的特定实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身并不指示所讨论的各个实施例和/或配置之间的关系。
此外,为了便于描述,在本文中可以使用诸如“在...之下”、“在...下面”、“下部”、“在...之上”、“上部”等的空间相对术语来描述如图中所示的一个元件或部件与另一个(另一些)元件或部件的关系。除了图中所示的取向之外,空间相对术语旨在包含在使用或操作中的器件的不同取向。装置可以以其他方式定向(旋转90度或在其他方位上),并且在本文中使用的空间相对描述符同样可以作出相应地解释。
根据各种示例性实施例提供了一种集成扇出(InFO)封装件及其形成方法。根据一些实施例示出了形成InFO封装件的中间阶段。讨论了一些实施例的一些变型。在各种视图和示例性实施例中,相同的参考标号用于表示相同的元件。
图1至图18A示出根据一些实施例的形成封装件的中间阶段的截面图。在图21中示出的工艺流程400中还示意性地示出了图1至图18A中示出的步骤。
参考图1,提供了载体20,并且将释放膜22涂覆在载体20上。相应的步骤在图21所示的工艺流程中被示为步骤402。载体20由透明材料形成,并且可以是玻璃载体、陶瓷载体、有机载体等。载体20可以具有圆形顶视图形状,并且可以具有硅晶圆的尺寸。例如,载体20可以具有8英寸直径、12英寸直径等。释放膜22与载体20的顶面物理接触。释放膜22可以由光热转换(LTHC)涂层材料形成。释放膜22可以通过涂覆施加到载体20上。根据本发明的一些实施例,LTHC涂层材料能够在光/辐射(例如,激光)的热量下分解,并且因此可以从形成在其上的结构释放载体20。根据本发明的一些实施例,LTHC涂层材料22包括炭黑(具有黑色的碳颗粒)、溶剂、硅填充物和/或环氧树脂。环氧树脂可以包括丙烯酸或其他聚合物,例如聚酰亚胺。如果聚酰亚胺包含在LTHC涂层材料中,则该聚酰亚胺与用于光刻的典型聚酰亚胺不同,因为它不再是光敏的,并且不能通过照相曝光和显影被去除。根据本发明的一些示例性实施例,LTHC涂层材料22的厚度T1可以大于约1μm,并且可以在约1μm与约2.5μm之间的范围内。在随后的段落中详细讨论了厚度T1。应该认识到,在本发明的整个说明书中所引用的值是实例,并且可以改变为不同的值。LTHC涂层材料22可以以可流动的形式进行涂覆,并且然后诸如在紫外(UV)光下固化。LTHC涂层材料22是均匀材料,并且整个LTHC涂层材料22的顶部和底部具有相同的组分。
根据一些实施例,也如图1所示,聚合物缓冲层23形成在LTHC涂层材料22上。在图21所示的工艺流程中将相应的步骤还示出为步骤402。根据一些实施例,聚合物缓冲层23由聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)或其他可应用的聚合物形成。
图2至图4示出了金属柱32的形成。在图21中所示的工艺流程中将相应的步骤示出为步骤404。在整个说明书中,因为金属柱32穿过随后分配的密封材料,所以金属柱32可选地称为通孔32。
参考图2,例如通过物理汽相沉积(PVD)形成金属晶种层24。金属晶种层24可以与聚合物缓冲层23物理接触。根据本发明的一些实施例,金属晶种层24包括钛层和位于钛层上方的铜层。根据本发明的可选实施例,金属晶种层24包括接触LTHC涂层22的铜层。
还如图2所示,在金属晶种层24上方形成光刻胶26。然后使用光刻掩模(未示出)对光刻胶26实施曝光。在随后的显影之后,在光刻胶26中形成开口28。通过开口28暴露金属晶种层24的一些部分。
接下来,如图3所示,通过在开口28中镀敷金属材料来形成金属柱32。因为金属柱32将穿过随后形成在最终封装件中的密封材料(其可以是模塑料),所以金属柱32可选地称为通孔或模制通孔。镀敷金属材料可以是铜或铜合金。金属柱32的顶面低于光刻胶26的顶面,使得由开口28限定金属柱32的形状。金属柱32可以具有基本垂直并且笔直的边缘。可选地,金属柱32可以在横截面视图中具有沙漏形状,其中金属柱32的中间部分比相应的顶部部分和底部部分更窄。
在随后的步骤中,光刻胶26被去除,并且因此金属晶种层24的下面部分被暴露。然后在蚀刻步骤中(例如,在各向异性或各向同性蚀刻步骤中)去除金属晶种层24的暴露部分。因此剩余晶种层24的边缘与金属柱32的相应重叠部分具有共端点(co-terminus,又称共端部)。在图4中示出所得金属柱32。在整个说明书中,金属晶种层24的剩余部分被认为是金属柱32的部分,并且没有单独示出该金属晶种层24的剩余部分。金属柱32的顶视形状(top-view shape)包括但不限于圆形、矩形、六边形、八边形等。在形成金属柱32之后,暴露聚合物缓冲层23。
图5示出了器件管芯36的放置/附接。在如图21中所示的工艺流程中将相应的步骤示出为步骤406。器件管芯36通过管芯附接膜(DAF)38附接到聚合物缓冲层23,其中,该DAF38是在器件管芯36放置在聚合物缓冲层23上之前,预先附接在器件管芯36上的粘附膜。因此,在附接至聚合物缓冲层23之前,DAF 38和器件管芯36组合为集成件。器件管芯36可以包括半导体衬底,该半导体衬底具有与DAF 38物理接触的后表面(朝下的表面)。器件管芯36可以包括位于半导体衬底的前表面(朝上的表面)的集成电路器件(例如,包括诸如晶体管(未示出)的有源器件)。根据本发明的一些实施例,器件管芯36是逻辑管芯,其中,该逻辑管芯可以是中央处理单元(CPU)管芯、图形处理单元(GPU)管芯、移动应用管芯、微控制单元(MCU)管芯、输入-输出(IO)管芯、基带(BB)管芯或应用处理(AP)管芯。由于载体20处于晶圆层级,所以虽然示出了一个器件管芯36,但是多个相同的器件管芯36被放置在聚合物缓冲层23上方,并且可以被分配为包括多行和多列的阵列。
根据一些示例性实施例,金属柱42(例如,铜柱)预先形成为器件管芯36的部分,并且金属柱42电耦合至器件管芯36中的集成电路器件,诸如晶体管(未示出)。根据本发明的一些实施例,诸如聚合物的电介质材料填充相邻金属柱42之间的间隙以形成顶部介电层44。顶部介电层44还可以包括覆盖和保护金属柱42的部分。根据本发明的一些实施例,聚合物层44可以由PBO或聚酰亚胺形成。
接下来,如图6所示,器件管芯36和金属柱32被密封在密封材料48中。在如图21中所示的工艺流程中将相应的步骤示出为步骤408。密封材料48填充相邻通孔32之间的间隙以及通孔32与器件管芯36之间的间隙。密封材料48可以包括模塑料、模制底部填充物、环氧树脂和/或树脂。密封材料48的顶面高于金属柱42的顶端。当密封材料48由模塑料形成时,密封材料48可以包括基材(其可以是聚合物、树脂、环氧树脂等)以及基材中的填充物颗粒(未示出,参考图19C)。填充物颗粒可以是SiO2、Al2O3、硅石等的介电颗粒,并且可以具有球形。此外,球形填充物颗粒可以具有多种不同的直径。还如图19C中示意性所示,模塑料中的填充物颗粒和基材可以与聚合物缓冲层23物理接触。
在随后的步骤中,如图7所示,实施诸如化学机械抛光(CMP)步骤或机械研磨步骤的平坦化步骤以使密封材料48和介电层44变薄,直到通孔32和金属柱42全部暴露。在图21所示的工艺流程中将相应的步骤还示出为步骤408。由于平坦化工艺,通孔32的顶端与金属柱42的顶面基本齐平(共面),并且基本上与密封材料48的顶面共面。
图8至图12示出了正面再分布结构的形成。图8和图9示出了第一层再分布线(RDL)和相应介电层的形成。参考图8,形成介电层50。在如图21中所示的工艺流程中相应的步骤示出为步骤410。根据本发明的一些实施例,介电层50由诸如PBO、聚酰亚胺等的聚合物形成。形成方法包括以可流动形式涂覆介电层50,并且然后固化介电层50。根据本发明的可选实施例,介电层50由无机介电材料形成,例如氮化硅、氧化硅等。形成方法可以包括化学汽相沉积(CVD)、原子层沉积(ALD)、等离子体增强的化学汽相沉积(PECVD)或其他可应用的沉积方法。然后诸如通过光刻工艺形成开口52。根据一些实施例,其中介电层50由诸如PBO或聚酰亚胺的光敏材料形成,开口52的形成包括使用光刻掩模(未示出)的曝光和显影步骤。通过开口52暴露通孔32和金属柱42。
接下来,参考图9,在介电层50上方形成RDL 54。在如图21中所示的工艺流程中相应的步骤示出为步骤412。RDL 54包括:通孔54A,形成在介电层50中以连接至金属柱42和通孔32、以及介电层50上方的金属迹线(金属线)54B。根据本发明的一些实施例,在镀敷工艺中形成RDL 54(包括54A和54B),这包括沉积金属晶种层(未示出)、在金属晶种层上方形成并图案化光刻胶(未示出)、以及在金属晶种层上方镀敷诸如铜和/或铝的金属材料。金属晶种层和镀敷金属材料可以由相同材料或不同材料形成。然后去除图案化的光刻胶,随后蚀刻先前由图案化的光刻胶覆盖的金属晶种层的部分。虽然未示出,但是从开口52生长的RDL54的部分的顶面可以凹陷至比直接覆盖介电层50的RDL 54的部分更低。
参考图10,根据本发明的一些实施例,在图9所示的结构上方形成介电层60,随后在介电层60中形成开口。因此通过开口暴露RDL 54的一些部分。可以使用从与形成介电层50相同的候选材料中选择的材料来形成介电层60,其中,介电层60可以包括PBO、聚酰亚胺、BCB或其他有机或无机材料。然后形成RDL 58。在如图21中所示的工艺流程中将相应的步骤示出为步骤414。RDL 58还包括延伸到介电层60的开口中以接触RDL 54的通孔部分、以及直接位于介电层60上方的金属线部分。RDL 58的形成可以与RDL 54的形成相同,RDL 58的形成包括形成晶种层、形成图案化掩模、镀敷RDL 58、以及然后去除图案化掩模和并去除晶种层的不期望部分。
图11示出了在介电层60和RDL 58上方形成的介电层62和RDL 64。在如图21中所示的工艺流程中将相应的步骤示出为步骤416。可以由从与形成介电层50和60相同的候选材料的组中选择的材料来形成介电层62。RDL 64也可以由金属或包括铝、铜、钨或它们的合金的金属合金形成。可以理解的是,尽管在示出的示例性实施例中,形成了三层RDL(54、58和64),但是封装件可以具有任何数量的RDL层,例如一层、两层或多于三层。
图12示出了根据一些示例性实施例的介电层66、凸块下金属(UBM)68和电连接器70的形成。可以由从与形成介电层50、60、62和66同一组的候选材料中选择的材料来形成介电层66。例如,介电层66可以使用PBO、聚酰亚胺或BCB形成。在介电层66中形成开口以暴露下层金属焊盘,该下层金属焊盘在示出的示例性实施例中是RDL 64的部分。根据本发明的一些实施例,UBM 68被形成为延伸到介电层66的开口中以接触RDL 64中的金属焊盘。UBM68可以由镍、铜、钛或它们的多层形成。根据一些示例性实施例,UBM 68包括钛层和位于钛层上方的铜层。
然后形成电连接器70。在如图21中所示的工艺流程中相应的步骤示出为步骤418。电连接器70的形成可以包括将焊球放置在UBM 68的暴露部分上,然后回流焊球,并且因此电连接器70是焊料区域。根据本发明的可选实施例,电连接器70的形成包括实施镀敷步骤以在UBM 68上方形成焊料层,以及然后回流焊料层。电连接器70还可以包括也可以通过镀敷形成的非焊料金属柱、或者位于非焊料金属柱上方的金属柱和焊帽。在整个说明书中,包括释放膜22和上层结构的组合的结构被称为封装件100,该封装件100是包括多个器件管芯36的复合晶圆(并且以下也称为复合晶圆100)。
接下来,参考图13,将复合晶圆100放置在附接到框架76的带74上。根据本发明的一些实施例,电连接器70与带74接触。接下来,将光78(或其他类型的载热辐射源)投射在LTHC涂层材料22上,并且光78穿透透明载体20。根据本发明的一些示例性实施例,光78是激光束,光78可以在LTHC涂层材料22上来回扫描,其中对LTHC涂层材料22的未扫描部分实施每次扫描。在随后的讨论中,为了简单起见,辐射78被称为激光束78,但是辐射78可以是其他类型的辐射。
图20A示出了在实施激光扫描之前的区域79(在图13中示出)。在LTHC涂层材料22中,炭黑颗粒122A散布在基材122B中,根据一些实施例,炭黑颗粒122A可以是丙烯酸。炭黑颗粒122A不形成连续的导电路径,因为炭黑颗粒122A被基材122B彼此隔离。
图20B示出了在实施激光扫描期间和之后的区域79(图13)的放大视图。LTHC涂层材料22包括位于激光束78的工作范围内的部分22A。LTHC涂层材料22的部分22B在激光束78的工作范围之外。激光束78的工作范围是其中激光束78的能量足以分解LTHC涂层材料22的范围。在工作范围之外,激光束78已经在工作范围内被吸收或阻挡,或者即使激光束78可能会超出工作范围,激光束78的能量也不足以分解LTHC涂层材料22。因此,在激光束扫描期间,响应于由曝光引入的热量,LTHC涂层材料22的部分22A(其中的基材122B)被分解,并且部分22B没有被分解。
根据本发明的一些实施例,如图20B所示,激光束78被聚焦到层级81。层级81位于载体20与LTHC涂层材料22之间的界面之下。激光78的工作范围包括高于聚焦层级81的深度ΔD的范围以及低于聚焦层级81的深度ΔD的范围。根据一些实施例,深度ΔD可以为约0.5μm。可以理解的是,工作范围受各种因素影响,包括但不限于激光束的能级、扫描速度、LTHC涂层材料22的能量吸收率等。根据本发明的一些实施例,调节聚焦层级81以允许工作范围的顶部到达LTHC涂层材料22和载体20之间的界面,并且工作范围的底部高于LTHC涂层材料22的底面。
在激光扫描期间,电荷(诸如由e符号表示的电子)被诱发,并且被捕获在炭黑颗粒122A中。此外,激光扫描引起炭黑颗粒122A的膨胀,并且因此隔离的炭黑颗粒122A互相连接,以产生连续的导电路径。
由于曝光(例如激光扫描),载体20可以从LTHC涂层材料22剥离,并且因此复合晶圆100从载体20去粘结(debond,又称脱粘)(拆卸)。在如图21所示的工艺流程中相应的步骤示出为步骤420。在图14中示出所得到的复合晶圆100。在曝光期间,LTHC涂层材料22的部分22A(图20B)被分解。LTHC涂层材料22的部分22B没有被分解,并且因此在载体20已经剥离之后,该部分22B保持不变。根据本发明的一些实施例,LTHC涂层材料22在分解之前的总厚度T1(图13)在约1.5μm至约2.5μm之间的范围内。根据一些示例性实施例,LTHC涂层材料22的剩余部分22B的厚度T2(图14)可以在约0.5μm至约1.5μm之间的范围内。此外,LTHC涂层材料22的未分解部分的厚度T2与总厚度T1的比率可以在约0.4与约0.7之间的范围内。此外,未分解部分的厚度T2可以大于碳黑颗粒122A的直径Dia(图20A和图20B)的5倍,以确保部分22B具有足够的厚度以充当有效的介电阻挡层。
在载体20的剥离期间,由于载体20上的摩擦,可能产生大量的静电荷。静电荷可以与激光扫描中产生的电荷复合,并且通过由膨胀的炭黑颗粒122A形成的导电路径进行传导。如果LTHC涂层材料22的部分22B不存在,则部分22A(因此连续的导电路径)将延伸到聚合物缓冲层23。大量的电荷可以穿过聚合物缓冲层23并且被传导到通孔32。通过通孔32和RDL 54、58等,电荷可以被传导到器件管芯36中,并且损坏器件管芯36中的器件和细金属线。这被称为电过应力(EOS)。
根据本发明的一些实施例,部分地由于部分22B中的炭黑颗粒122A不形成连续路径,所以部分22B用作介电阻挡层。介电阻挡层防止电荷到达通孔32。因此,减少了EOS损坏的可能性。从样本晶圆获得的实验结果揭示,通过采用本发明的实施例,大部分EOS损坏被消除,并且EOS损坏可以减少98%。
根据本发明的一些实施例,LTHC涂层材料22的剩余未分解部分22B(图14)可以是毯式层,其中,该毯式层没有暴露下面的聚合物缓冲层23的任何开口。
根据本发明的一些实施例,在剥离载体20之后,去除剩余的LTHC涂层材料22,从而暴露下面的聚合物缓冲层23。在如图21所示的工艺流程中相应的步骤示出为步骤422。例如,可以使用氮气(N2)、氧气(O2)、CF4等的等离子体通过等离子体清洁步骤去除LTHC涂层材料22。在图14中示出了所得的复合晶圆100。
根据本发明的可选实施例,未去除剩余的LTHC涂层材料22。因此图21中的步骤422被示出为虚线以表示该步骤可以实施也可以不实施。LTHC涂层材料22的顶面可以具有满足封装件的制造工艺的规格的共面性。因此,将不实施LTHC涂层材料22的顶面的平坦化。然而,如果在载体20剥离之后,LTHC涂层材料22的粗糙度大于由规格规定的可接受最大粗糙度,并且高粗糙度可能导致产量损失,则可以实施平坦化(例如,化学机械抛光(CMP)或机械研磨)以使LTHC涂层材料22的顶面齐平。平坦化移除LTHC涂层材料22的顶面部分,同时留下未被去除的毯式底部部分。参考图15,在LTHC涂层材料22和聚合物缓冲层23中形成开口72,并且因此暴露通孔32。在如图21所示的工艺流程中相应的步骤示出为步骤424。根据本发明的一些实施例,通过激光钻孔形成开口72,在此期间,直接位于通孔32上方的LTHC涂层材料22的一些部分被激光被烧毁并分解。根据本发明的可选实施例,通过光刻工艺中的蚀刻形成开口72。
根据本发明的一些实施例,在激光钻孔之后暴露钛层24A。如图3所示,钛层24A是金属晶种层24的剩余部分。在随后的步骤中,实施蚀刻步骤以去除钛层。由于钛具有比铜更高的电阻率,所以通过去除钛层,露出具有比钛层低的电阻率的通孔32的铜部分。因此,与通孔32的电连接可以用较低的电阻来建立。根据本发明的一些实施例,通过使用氟化氢(HF)溶液、磷酸或HF和磷酸的混合物的湿法蚀刻来实施钛层的蚀刻。也可以使用干法蚀刻来实施蚀刻。
在蚀刻钛层24A时,LTHC涂层材料22未被蚀刻。因此,选择LTHC涂层材料22的材料和钛层24A的蚀刻剂,使得蚀刻剂能够蚀刻钛层24A的同时,又不会腐蚀LTHC涂层材料22。
复合晶圆100包括彼此相同的多个封装件100’(参见图18A-18B),其中每个封装件100’均包括多个通孔32和一个器件管芯36。LTHC涂层材料22跨越整个晶圆级封装件100。图16示出了将多个封装件200(具有所示的一个封装件200)接合到复合晶圆100上,因此形成多个相同的封装件叠层(PoP)结构/封装件300(图17)。通过焊料区域80实施接合,其中,该焊料区域80将通孔32连接至上层封装件200的金属焊盘206。根据本发明的一些实施例,封装件200包括封装衬底204和器件管芯202,器件管芯202可以是存储器管芯,例如静态随机存取存储器(SRAM)管芯、动态随机存取存储器(DRAM)管芯等。底部填充物208也被置于封装件200与下面的复合晶圆100之间的间隙中,并且被固化。底部填充物208可以与LTHC涂层材料22接触。
根据本发明的可选实施例,不是通过开口72(图15)直接将封装件200接合至复合晶圆100,而是形成背侧RDL(未示出),并且封装件200接合在背侧再分布结构中的背侧RDL上方。因此,背面RDL将包括延伸到LTHC涂层材料22中的通孔(未示出)以及LTHC涂层材料22上方的金属线(未示出)。,由于如果形成这些RDL,这些RDL将位于器件管芯36的背侧上,所以背侧RDL这样命名。为了形成背侧RDL,可以在复合晶圆100下面放置载体而不是带,作为形成背侧RDL的支撑件。因此,在形成背侧RDL期间,电连接器70通过粘合剂膜(未示出)粘附到载体。
接下来,参考图17,实施分割(管芯切割)工艺以将复合晶圆100分离成彼此相同的单个封装件300。当复合晶圆100位于带74上时,可以实施分割。可以使用刀片实施分割,或者可以通过以下步骤实施分割:使用激光束以进行预开槽,从而形成凹槽,并且然后使用刀片通过凹槽进行切开。
图18A示出了分割的封装件300通过焊料区域70接合到封装组件86,从而形成封装件302。在如图21所示的工艺流程中相应的步骤示出为步骤426。根据本发明的一些实施例,封装组件86是封装衬底,其可以是无芯衬底或有芯衬底。根据本发明的其他实施例,封装组件86是印刷电路板或封装件。焊料区域70可以被接合到封装组件86的接合焊盘88。
图18B示出了根据本发明的可选实施例形成的封装件302。除了在剥离载体20之后,去除剩余的LTHC涂层材料22(图14)之外,这些实施例与图18A中所示的实施例类似。因此,如图18B所示,底部填充物208与聚合物缓冲层23接触。
图19A示出了示例性封装件300的一些部分的顶视图,其中示出了通孔32、LTHC涂层材料22和器件管芯36,而为了简单起见未示出其他部件。根据本发明的一些实施例,通过以激光束形式的激光实施LTHC涂层材料22的分解。激光束比封装件300窄,并且需要多个激光束扫描路径来覆盖整个封装件300(并且如图13所示覆盖复合晶圆100)。多个激光束扫描的路径可以彼此略微重叠,以确保LTHC涂层材料22的完全覆盖,而不存在不期望的未被扫描的一些部分。与非重叠部分相比,重叠部分接收双重扫描。根据本发明的一些实施例,双重扫描区域中分解的LTHC涂层材料22的厚度大于单重扫描区域中分解的LTHC涂层材料22的厚度。这导致LTHC涂层材料22的顶面具有比其他部分更凹陷的一些部分。例如,图19A示意性地示出了部分222A和比部分222A更凹陷的部分222B。部分222B和222A具有交替布局,其中部分222A是单重扫描部分,并且部分222B是双重扫描部分。此外,在顶视图中,部分222A和222B可以基本上是直的。
图19B示出了根据本发明的一些示例性实施例的LTHC涂层材料22的截面图。还示出了部分222A和222B。还示出了部分222A的厚度T3A和部分222B的厚度T3B。厚度T3A大于厚度T3B。根据本发明的一些实施例,差值(T3A-T3B)大于约0.1μm,并且可以在约0.1μm至约0.5μm之间的范围内。因此,在封装件300中,LTHC涂层材料22具有交替厚度的部分。部分222A可以具有基本均匀的宽度,并且部分222B可以具有基本均匀的宽度,并且部分222A的宽度可以大于部分222B的宽度。
部分222B(并且还可能部分222A)在横截面视图中可以具有凹陷形状,其中部分222B(或部分222A)的中间部分比部分222B/222A的边缘部分更凹陷。此外,凹陷形状可以是弯曲的。
图19C示出了图17中的区域84的放大视图。如图19C所示,密封材料48包括基材48A和基材48A中的填充颗粒48B。由于密封材料48被密封在聚合物缓冲层23上(如图6所示),并且没有对与聚合物缓冲层23接触的密封材料48的部分实施平坦化,所以与聚合物缓冲层23接触的球形颗粒48B是圆形的,其中圆形表面与聚合物缓冲层23接触。此外,在该界面处没有球形颗粒48B被研磨以具有与所示基材48A的顶面共面的平面表面。作为比较,与介电层50接触的密封材料48的部分已经在图7所示的步骤中被平坦化。因此,与介电层50接触的球形颗粒48B在平坦化期间被部分地切割,并且因此将具有与介电层50接触的基本上平坦的底面(而不是圆形底面)。
在上述示例性实施例中,根据本发明的一些实施例讨论了一些示例性工艺和部件。也可能包含其他部件和工艺。例如,可以包括测试结构以辅助3D封装件或3DIC器件的验证测试。测试结构可以包括诸如测试焊盘,该测试焊盘形成在再分布层中或允许测试3D封装件或3DIC、使用探针和/或探针卡等的衬底上。可以在中间结构以及最终结构上实施验证测试。此外,本文公开的结构和方法可以与测试方法结合使用,其中该测试方法包含已知良好管芯的中间验证以提高产量并降低成本。
本发明的实施例具有一些有利的特征。通过使LTHC涂层材料的厚度比用于分解LTHC涂层材料的激光的工作范围更大,将LTHC涂层材料的未分解的剩余部分用作介电阻挡层以防止电荷排放到InFO封装件的器件管芯中,并且避免了EOS损坏。
根据本发明的一些实施例,一种方法包括在载体上方形成释放膜,在释放膜上方形成聚合物缓冲层,在聚合物缓冲层上形成金属柱,将金属柱密封在密封材料中,对密封材料实施平坦化以暴露金属柱,在密封材料和金属柱上方形成再分布结构,以及分解释放膜的第一部分。分解后留下释放膜的第二部分。在聚合物缓冲层中形成开口以暴露金属柱。在一个实施例中,该方法包括将封装组件接合到金属柱;以及在封装组件与释放膜的第二部分之间分配底部填充物。在一个实施例中,通过将激光束投射在释放膜上来实施分解释放膜的第一部分。在一个实施例中,释放膜包括聚合物基材和炭黑颗粒。在一个实施例中,该方法包括在聚合物缓冲层中形成开口之前去除释放膜的第二部分。在一个实施例中,开口延伸到聚合物缓冲层和释放膜的第二部分两者中。在一个实施方式中,释放膜的第一部分在分解之前具有第一厚度,并且释放膜在分解之后具有第二厚度,并且第一厚度与第二厚度的比率在约0.4至0.7之间的范围内。
在实施例中,用于形成封装件的方法,还包括:将封装组件接合到所述金属柱;以及在所述封装组件与所述释放膜的第二部分之间分配底部填充物。
在实施例中,通过将激光束投射在所述释放膜上来实施分解所述释放膜的第一部分。
在实施例中,所述释放膜包括聚合物基材和炭黑颗粒。
在实施例中,用于形成封装件的方法,还包括在所述聚合物缓冲层中形成开口之前去除所述释放膜的第二部分。
在实施例中,所述开口延伸到所述聚合物缓冲层和所述释放膜的第二部分这两者中。
在实施例中,所述释放膜的第一部分在所述分解之前具有第一厚度,并且所述释放膜在所述分解之后具有第二厚度,并且所述第一厚度与所述第二厚度的比率在约0.4至0.7之间的范围内。
根据本发明的一些实施例,一种方法包括在载体上涂覆LTHC涂层材料;在LTHC涂层材料上方形成聚合物缓冲层;形成与聚合物缓冲层接触的金属晶种层;在金属晶种层上方形成图案化光刻胶,其中金属晶种层的部分通过图案化光刻胶中的开口暴露;在金属晶种层上方镀敷金属柱;去除图案化的光刻胶;蚀刻金属晶种层以暴露聚合物缓冲层;将激光束投射在LTHC涂层材料上,其中激光束的工作范围覆盖LTHC涂层材料的第一部分,并且LTHC涂层材料的第二部分不在工作范围内;剥离载体;以及形成穿透LTHC涂层材料的第二部分的焊料区域。在一个实施例中,在载体剥离之后,LTHC涂层材料的第二部分保持为毯式层,并且毯式层没有暴露聚合物缓冲层的任何开口。在一个实施例中,该方法包括在LTHC涂层材料的第二部分和聚合物缓冲层中形成开口,其中焊料区域延伸到开口中。在一个实施例中,该方法包括去除LTHC涂层材料的第二部分。在一个实施例中,投射激光束包括使激光束扫描穿过整个LTHC涂层材料。在一个实施例中,该方法包括,在载体剥离之后,在LTHC涂层的第二部分上实施平坦化。在一个实施例中,该方法包括,在载体剥离之后并且在形成焊料区域之前,蚀刻金属晶种层的剩余部分的部分。
在实施例中,在剥离所述载体之后,所述光热转换涂层材料的第二部分保持为毯式层,并且所述毯式层没有暴露所述聚合物缓冲层的任何开口。
在实施例中,用于形成封装件的方法还包括:在所述光热转换涂层材料的第二部分和所述聚合物缓冲层中形成开口,其中,所述焊料区域延伸到所述开口中。
在实施例中,用于形成封装件的方法还包括去除所述光热转换涂层材料的第二部分。
在实施例中,投射所述激光束包括使所述激光束扫描穿过所述光热转换涂层材料的全部。
在实施例中,用于形成封装件的方法还包括在所述载体剥离之后,对所述光热转换涂层材料的第二部分实施平坦化。
在实施例中,用于形成封装件的方法还包括在所述载体剥离之后并且在所述焊料区域形成之前,蚀刻所述金属晶种层的剩余部分中的部分。
根据本发明的一些实施例,一种封装件包括密封材料;穿过密封材料的通孔;接触通孔和密封材料的聚合物缓冲层;接触聚合物缓冲层的LTHC涂层材料;以及穿透LTHC涂层材料和聚合物缓冲层的焊料区域。在一个实施例中,LTHC涂层材料被配置为在激光束的加热下分解。在一个实施例中,LTHC涂层材料包含基材和基材中的炭黑颗粒。在一个实施例中,该封装件还包括:器件管芯;以及将器件管芯粘附到聚合物缓冲层的管芯附接膜,其中通过密封材料密封器件管芯和管芯附接膜。在一个实施例中,LTHC涂层材料包括以交替布局分配的多个第一部分和多个第二部分,并且多个第一部分比多个第二部分薄。在一个实施例中,LTHC涂层材料的多个第一部分和多个第二部分是平行条。
在实施例中,所述光热转换涂层材料被配置为在激光束的加热下分解。
在实施例中,所述光热转换涂层材料包含基材和所述基材中的炭黑颗粒。
在实施例中,封装件还包括:器件管芯;以及管芯附接膜,所述管芯附接膜将所述器件管芯粘附到所述聚合物缓冲层,其中,通过所述密封材料密封所述器件管芯和所述管芯附接膜。
在实施例中,所述光热转换涂层材料包括以交替布局分配的多个第一部分和多个第二部分,并且所述多个第一部分比所述多个第二部分薄。
在实施例中,所述光热转换涂层材料的多个第一部分和多个第二部分是平行条。
以上论述了若干实施例的特征,使得本领域的技术人员可以更好地理解本发明的各个方面。本领域技术人员应该理解,他们可以很容易地使用本发明作为基础来设计或更改其他用于达到与本文所介绍实施例相同的目的和/或实现相同优点的工艺和结构。本领域技术人员也应该意识到,这些等效结构并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,可以进行多种变化、替换以及改变。

Claims (10)

1.一种用于形成封装件的方法,包括:
在载体上方形成释放膜;
在所述释放膜上方形成聚合物缓冲层;
在所述聚合物缓冲层上形成金属柱;
将所述金属柱密封在密封材料中;
对所述密封材料实施平坦化以暴露所述金属柱;
在所述密封材料和所述金属柱上方形成再分布结构;
分解所述释放膜的第一部分,其中,在所述分解之后留下所述释放膜的第二部分;以及
在所述聚合物缓冲层中形成开口以暴露所述金属柱。
2.根据权利要求1所述的用于形成封装件的方法,还包括:
将封装组件接合到所述金属柱;以及
在所述封装组件与所述释放膜的第二部分之间分配底部填充物。
3.根据权利要求1所述的用于形成封装件的方法,其中,通过将激光束投射在所述释放膜上来实施分解所述释放膜的第一部分。
4.根据权利要求1所述的用于形成封装件的方法,其中,所述释放膜包括聚合物基材和炭黑颗粒。
5.根据权利要求1所述的用于形成封装件的方法,还包括在所述聚合物缓冲层中形成开口之前去除所述释放膜的第二部分。
6.根据权利要求1所述的用于形成封装件的方法,其中,所述开口延伸到所述聚合物缓冲层和所述释放膜的第二部分这两者中。
7.根据权利要求1所述的用于形成封装件的方法,其中,所述释放膜的第一部分在所述分解之前具有第一厚度,并且所述释放膜在所述分解之后具有第二厚度,并且所述第一厚度与所述第二厚度的比率在约0.4至0.7之间的范围内。
8.一种用于形成封装件的方法,包括:
在载体上涂覆光热转换(LTHC)涂层材料;
在所述光热转换涂层材料上方形成聚合物缓冲层;
形成与所述聚合物缓冲层接触的金属晶种层;
在所述金属晶种层上方形成图案化光刻胶,其中,通过所述图案化光刻胶中的开口暴露所述金属晶种层的部分;
在所述金属晶种层上方镀敷金属柱;
去除所述图案化光刻胶;
蚀刻所述金属晶种层以暴露所述聚合物缓冲层;
将激光束投射在所述光热转换涂层材料上,其中,所述激光束的工作范围覆盖所述光热转换涂层材料的第一部分,并且所述光热转换涂层材料的第二部分不在所述工作范围内;
剥离所述载体;以及
形成穿透所述光热转换涂层材料的第二部分的焊料区域。
9.根据权利要求8所述的用于形成封装件的方法,其中,在剥离所述载体之后,所述光热转换涂层材料的第二部分保持为毯式层,并且所述毯式层没有暴露所述聚合物缓冲层的任何开口。
10.一种封装件包括:
密封材料;
通孔,所述通孔穿透所述密封材料;
聚合物缓冲层,所述聚合物缓冲层与所述通孔和所述密封材料接触;
光热转换(LTHC)涂层材料,所述光热转换涂层材料与所述聚合物缓冲层接触;以及
焊料区域,所述焊料区域穿透所述光热转换涂层材料和所述聚合物缓冲层。
CN201810836178.8A 2017-07-28 2018-07-26 Lthc在形成封装件中作为电荷阻挡层、封装件及其形成方法 Active CN109309013B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201762538192P 2017-07-28 2017-07-28
US62/538,192 2017-07-28
US15/907,409 US10522526B2 (en) 2017-07-28 2018-02-28 LTHC as charging barrier in InFO package formation
US15/907,409 2018-02-28

Publications (2)

Publication Number Publication Date
CN109309013A true CN109309013A (zh) 2019-02-05
CN109309013B CN109309013B (zh) 2020-11-20

Family

ID=65004186

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810836178.8A Active CN109309013B (zh) 2017-07-28 2018-07-26 Lthc在形成封装件中作为电荷阻挡层、封装件及其形成方法

Country Status (5)

Country Link
US (3) US10522526B2 (zh)
KR (1) KR102175610B1 (zh)
CN (1) CN109309013B (zh)
DE (1) DE102018106672A1 (zh)
TW (1) TWI683411B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112687628A (zh) * 2019-10-18 2021-04-20 台湾积体电路制造股份有限公司 半导体器件、半导体器件的制造方法及封装件

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10361122B1 (en) * 2018-04-20 2019-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Processes for reducing leakage and improving adhesion
US10818640B1 (en) * 2019-04-02 2020-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Die stacks and methods forming same
US10950519B2 (en) 2019-05-31 2021-03-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US20220278075A1 (en) * 2019-07-24 2022-09-01 Nantong Tongfu Microelectronics Co., Ltd Packaging structure and formation method thereof
US11410902B2 (en) 2019-09-16 2022-08-09 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US11817426B2 (en) 2021-01-13 2023-11-14 Taiwan Semiconductor Manufacturing Co., Ltd. Package and method of fabricating the same

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101489789A (zh) * 2006-07-14 2009-07-22 3M创新有限公司 层叠式主体以及使用层叠式主体制造薄基底的方法
US20150102502A1 (en) * 2013-09-11 2015-04-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated Fan-Out Structure with Openings in Buffer Layer
CN105225967A (zh) * 2014-06-27 2016-01-06 台湾积体电路制造股份有限公司 封装半导体器件的方法和封装的半导体器件
CN106409810A (zh) * 2015-07-31 2017-02-15 台湾积体电路制造股份有限公司 具有堆叠通孔的再分布线
CN106711115A (zh) * 2015-11-16 2017-05-24 台湾积体电路制造股份有限公司 芯片封装件及其制造方法
CN106711092A (zh) * 2015-11-16 2017-05-24 台湾积体电路制造股份有限公司 集成扇出结构以及形成方法
CN106981475A (zh) * 2016-01-19 2017-07-25 台湾积体电路制造股份有限公司 器件、封装的半导体器件和半导体器件封装方法
US20170213808A1 (en) * 2016-01-25 2017-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Dual-Sided Integrated Fan-Out Package

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002124603A (ja) * 2000-10-18 2002-04-26 Mitsubishi Electric Corp エポキシ樹脂組成物、半導体装置およびレーザマークの視認性の判断方法
US6894399B2 (en) * 2001-04-30 2005-05-17 Intel Corporation Microelectronic device having signal distribution functionality on an interfacial layer thereof
JP4565804B2 (ja) 2002-06-03 2010-10-20 スリーエム イノベイティブ プロパティズ カンパニー 被研削基材を含む積層体、その製造方法並びに積層体を用いた極薄基材の製造方法及びそのための装置
JP3945415B2 (ja) * 2003-02-14 2007-07-18 セイコーエプソン株式会社 半導体装置の製造方法
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
US9305769B2 (en) * 2009-06-30 2016-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Thin wafer handling method
US9985150B2 (en) 2010-04-07 2018-05-29 Shimadzu Corporation Radiation detector and method of manufacturing the same
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
JP2012043953A (ja) * 2010-08-18 2012-03-01 Renesas Electronics Corp 電子部品および電子部品の製造方法
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) * 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
JP6216180B2 (ja) * 2013-08-01 2017-10-18 日東電工株式会社 封止用シート、及び、当該封止用シートを用いた半導体装置の製造方法
US9589900B2 (en) * 2014-02-27 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Metal pad for laser marking
US9666522B2 (en) * 2014-05-29 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment mark design for packages
US9601353B2 (en) * 2014-07-30 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with molding structures and methods of forming the same
US10177115B2 (en) 2014-09-05 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming
US9475272B2 (en) * 2014-10-09 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. De-bonding and cleaning process and system
US10325853B2 (en) * 2014-12-03 2019-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor packages having through package vias
US9589903B2 (en) 2015-03-16 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Eliminate sawing-induced peeling through forming trenches
US10115647B2 (en) * 2015-03-16 2018-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Non-vertical through-via in package
US10522383B2 (en) * 2015-03-25 2019-12-31 International Business Machines Corporation Thermoplastic temporary adhesive for silicon handler with infra-red laser wafer de-bonding
US10090241B2 (en) * 2015-05-29 2018-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. Device, package structure and method of forming the same
US10317965B2 (en) * 2015-09-15 2019-06-11 Intersil Americas LLC Apparatuses and methods for encapsulated devices
US9947570B2 (en) * 2015-12-30 2018-04-17 International Business Machines Corporation Handler bonding and debonding for semiconductor dies
US10269702B2 (en) * 2016-01-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Info coil structure and methods of manufacturing same
US9935009B2 (en) * 2016-03-30 2018-04-03 International Business Machines Corporation IR assisted fan-out wafer level packaging using silicon handler

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101489789A (zh) * 2006-07-14 2009-07-22 3M创新有限公司 层叠式主体以及使用层叠式主体制造薄基底的方法
US20150102502A1 (en) * 2013-09-11 2015-04-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated Fan-Out Structure with Openings in Buffer Layer
CN105225967A (zh) * 2014-06-27 2016-01-06 台湾积体电路制造股份有限公司 封装半导体器件的方法和封装的半导体器件
CN106409810A (zh) * 2015-07-31 2017-02-15 台湾积体电路制造股份有限公司 具有堆叠通孔的再分布线
CN106711115A (zh) * 2015-11-16 2017-05-24 台湾积体电路制造股份有限公司 芯片封装件及其制造方法
CN106711092A (zh) * 2015-11-16 2017-05-24 台湾积体电路制造股份有限公司 集成扇出结构以及形成方法
CN106981475A (zh) * 2016-01-19 2017-07-25 台湾积体电路制造股份有限公司 器件、封装的半导体器件和半导体器件封装方法
US20170213808A1 (en) * 2016-01-25 2017-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Dual-Sided Integrated Fan-Out Package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112687628A (zh) * 2019-10-18 2021-04-20 台湾积体电路制造股份有限公司 半导体器件、半导体器件的制造方法及封装件

Also Published As

Publication number Publication date
TWI683411B (zh) 2020-01-21
KR20190013461A (ko) 2019-02-11
US11437361B2 (en) 2022-09-06
US20220399325A1 (en) 2022-12-15
KR102175610B1 (ko) 2020-11-09
DE102018106672A1 (de) 2019-01-31
US10522526B2 (en) 2019-12-31
US20200006312A1 (en) 2020-01-02
US11923353B2 (en) 2024-03-05
US20190035774A1 (en) 2019-01-31
TW201911519A (zh) 2019-03-16
CN109309013B (zh) 2020-11-20

Similar Documents

Publication Publication Date Title
CN109309013A (zh) Lthc在形成封装件中作为电荷阻挡层、封装件及其形成方法
TWI598997B (zh) 具有堆疊通孔的重佈線
US20210327816A1 (en) InFO-POP structures with TIVs Having Cavities
KR102218926B1 (ko) 패키지 내의 격리막으로서의 릴리스막
CN109216213A (zh) 封装件及其形成方法
CN109801849B (zh) 封装件及其形成方法
CN106257644A (zh) 晶圆级封装件的切割
CN110416095A (zh) 封装件及其形成方法
CN107665852A (zh) 使用含金属层以减小封装件形成中的载体冲击
CN110660686B (zh) 形成rdl的方法和由其形成的结构
US20240136298A1 (en) InFO-POP Structures with TIVs Having Cavities
US11823969B2 (en) Packages with enlarged through-vias in encapsulant
JP2010182904A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant