TW201944560A - 扇出型半導體封裝 - Google Patents
扇出型半導體封裝 Download PDFInfo
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- TW201944560A TW201944560A TW107138245A TW107138245A TW201944560A TW 201944560 A TW201944560 A TW 201944560A TW 107138245 A TW107138245 A TW 107138245A TW 107138245 A TW107138245 A TW 107138245A TW 201944560 A TW201944560 A TW 201944560A
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Abstract
一種扇出型半導體封裝包括核心構件,具有第一貫穿孔且包括配線層;第一半導體晶片,設置於第一貫穿孔中且具有形成於第一半導體晶片的下側上的第一連接墊;第一包封體,覆蓋核心構件及第一半導體晶片;連接構件,設置於核心構件及第一半導體晶片下方且包括重佈線層;第一堆疊晶片,設置於第一包封體上且經由第一連接導體電性連接至配線層;以及第二包封體,設置於第一包封體上且覆蓋第一堆疊晶片。第一半導體晶片包括動態隨機存取記憶體及/或控制器,第一堆疊晶片包括堆疊型反及快閃,且第一半導體晶片的第一連接墊經由重佈線層電性連接至配線層。
Description
本揭露是有關於一種半導體封裝,且更具體而言,有關於一種電性連接結構可朝向設置有半導體晶片的區域之外延伸的扇出型半導體封裝。
[相關申請案的交叉參考]
[相關申請案的交叉參考]
本申請案主張2018年4月18日在韓國智慧財產局中申請的韓國專利申請案第10-2018-0045020號的優先權的權益,所述申請案的揭露內容全文併入本案供參考。
固態驅動機(solid state drive,SSD)是使用反及(NAND)快閃記憶體儲存資訊的裝置,較硬碟驅動機(hard disk drive,HDD)更快,並且可減小尺寸及重量且具有更低的故障率、更少的熱量產生及更少的雜訊。近年來,隨著SSD容量增加,SSD已取代或補充HDD,且已應用於隨身型易網機及平板。
同時,半導體晶片的尺寸根據此種小型化產品的應用要求不斷減小,且當形成半導體封裝時被提出用於連接電性訊號的半導體封裝技術中的一者是扇出型封裝。在應用扇出型封裝的傳統疊層封裝(package on package,POP)型封裝結構的情形中,單獨製造下部封裝及上部封裝以形成完整的封裝,且在此種情形中,產品的厚度是相當大的且可能會進一步出現訊號損耗。
本揭露的態樣可提供一種能夠同時執行各種功能、被薄化且具有低訊號損耗的扇出型半導體封裝。
本揭露的態樣可將堆疊型反及快閃直接安裝在封裝有動態隨機存取記憶體(dynamic random access memory,DRAM)及/或控制器的下部封裝上,且使用連接導體將反及快閃連接至下部封裝的核心構件的配線層以及連接構件的重佈線層以藉此執行重佈線。
根據本揭露的態樣,一種扇出型半導體封裝可包括:核心構件,具有第一貫穿孔且包括一或多個配線層;第一半導體晶片,設置於所述第一貫穿孔中,且具有形成於所述第一半導體晶片的下側上的第一連接墊;第一包封體,覆蓋所述第一半導體晶片及所述核心構件的至少部分;連接構件,設置於所述核心構件及所述第一半導體晶片下方,且包括一或多個重佈線層;第一堆疊晶片,設置於所述第一包封體上且經由第一連接導體電性連接至所述核心構件的所述一或多個配線層;以及第二包封體,設置於所述第一包封體上,且覆蓋所述第一堆疊晶片的至少部分。所述第一半導體晶片可包括動態隨機存取記憶體及控制器中的至少一者,所述第一堆疊晶片可包括堆疊型反及快閃,且所述第一半導體晶片的所述第一連接墊可經由所述連接構件的所述一或多個重佈線層電性連接至所述核心構件的所述一或多個配線層。
根據本揭露的另一態樣,一種扇出型半導體封裝可包括:核心構件,具有彼此間隔開的第一貫穿孔及第二貫穿孔,且包括一或多個配線層;第一半導體晶片,設置於所述第一貫穿孔中,且具有形成於所述第一半導體晶片的下側上的第一連接墊;第二半導體晶片,設置於所述第二貫穿孔中,且具有形成於所述第二半導體晶片的下側上的第二連接墊;第一包封體,覆蓋所述第二半導體晶片、所述第一半導體晶片及所述核心構件的至少部分;連接構件,設置於所述核心構件、所述第一半導體晶片及所述第二半導體晶片的下方,且包括一或多個重佈線層;第一堆疊晶片,設置於所述第一包封體上且經由第一連接導體電性連接至所述核心構件的所述一或多個配線層;第二堆疊晶片,設置於所述第一包封體上且經由第二連接導體電性連接至所述核心構件的所述一或多個配線層;以及第二包封體,設置於所述第一包封體上,且覆蓋所述第二堆疊晶片及所述第一堆疊晶片的至少部分。所述第一連接墊及所述第二連接墊可分別經由所述連接構件的所述一或多個重佈線層電性連接至所述核心構件的所述一或多個配線層。
以下,現在將參照附圖詳細闡述本揭露中的例示性實施例。
電子裝置
電子裝置
圖1為示出電子裝置系統的實例的示意性方塊圖。
參照圖1,電子裝置1000中可容置主板1010。主板1010可包括物理連接至或電性連接至主板1010的晶片相關組件1020、網路相關組件1030、其他組件1040等。該些組件可連接至以下將闡述的其他組件,以形成各種訊號線1090。
晶片相關組件1020可包括:記憶體晶片,例如揮發性記憶體(例如動態隨機存取記憶體(DRAM))、非揮發性記憶體(例如唯讀記憶體(read only memory,ROM))或快閃記憶體等;應用處理器晶片,例如中央處理器(例如,中央處理單元(central processing unit,CPU))、圖形處理器(例如,圖形處理單元(graphics processing unit,GPU))、數位訊號處理器、密碼處理器(cryptographic processor)、微處理器或微控制器等;以及邏輯晶片,例如類比至數位轉換器(analog-to-digital converter,ADC)或應用專用積體電路(application-specific integrated circuit,ASIC)等。然而,晶片相關組件1020並非僅限於此,而是亦可包括其他類型的晶片相關組件。另外,晶片相關組件1020可彼此組合。
網路相關組件1030可包括例如以下協定:無線保真(wireless fidelity,Wi-Fi)(電氣及電子工程師學會(Institute of Electrical And Electronics Engineers,IEEE)802.11家族等)、全球互通微波存取(worldwide interoperability for microwave access,WiMAX)(IEEE 802.16家族等)、IEEE 802.20、長期演進(long term evolution,LTE)、僅支援資料的演進(evolution data only,Ev-DO)、高速封包存取+(high speed packet access +,HSPA+)、高速下行封包存取+(high speed downlink packet access +,HSDPA+)、高速上行封包存取+(high speed uplink packet access +,HSUPA+)、增強型資料GSM環境(enhanced data GSM environment,EDGE)、全球行動通訊系統(global system for mobile communications,GSM)、全球定位系統(global positioning system,GPS)、通用封包無線電服務(general packet radio service,GPRS)、分碼多重存取(code division multiple access,CDMA)、分時多重存取(time division multiple access,TDMA)、數位增強型無線電訊(digital enhanced cordless telecommunications,DECT)、藍芽、3G協定、4G協定、5G協定以及繼上述協定之後指定的任何其他無線協定及有線協定。然而,網路相關組件1030並非僅限於此,而是亦可包括各種其他無線標準或協定或者有線標準或協定。另外,網路相關組件1030可與上文所述的晶片相關組件1020一起彼此組合。
其他組件1040可包括高頻電感器、鐵氧體電感器(ferrite inductor)、功率電感器(power inductor)、鐵氧體珠粒(ferrite beads)、低溫共燒陶瓷(low temperature co-firing ceramic,LTCC)、電磁干擾(electromagnetic interference,EMI)濾波器、多層陶瓷電容器(multilayer ceramic capacitor,MLCC)等。然而,其他組件1040並非僅限於此,而是亦可包括用於各種其他目的的被動組件等。另外,其他組件1040可與上文所述的晶片相關組件1020或網路相關組件1030一起彼此組合。
端視電子裝置1000的類型而定,電子裝置1000可包括可物理連接至及/或電性連接至主板1010或可不物理連接至及/或不電性連接至主板1010的其他組件。該些其他組件可包括例如照相機1050、天線1060、顯示器裝置1070、電池1080、音訊編解碼器(未繪示)、視訊編解碼器(未繪示)、功率放大器(未繪示)、羅盤(未繪示)、加速度計(未繪示)、陀螺儀(未繪示)、揚聲器(未繪示)、大容量儲存單元(例如,硬碟驅動機)(未繪示)、光碟(compact disk,CD)驅動機(未繪示)、數位多功能光碟(digital versatile disk,DVD)驅動機(未繪示)等。然而,該些其他組件並非僅限於此,而是亦可端視電子裝置1000的類型等而包括用於各種目的的其他組件。
電子裝置1000可為智慧型電話、個人數位助理(personal digital assistant,PDA)、數位攝影機、數位照相機(digital still camera)、網路系統、電腦、監視器、平板個人電腦(personal computer,PC)、筆記型個人電腦、隨身型易網機個人電腦(netbook PC)、電視、視訊遊戲機(video game machine)、智慧型手錶或汽車等。然而,電子裝置1000並非僅限於此,而是亦可為處理資料的任何其他電子裝置。
圖2為示出電子裝置的實例的示意性立體圖。
參照圖2,半導體封裝可於上文所述的各種電子裝置1000中用於各種目的。舉例而言,母板1110可容置於智慧型電話1100的本體1101中,且各種組件1120可物理連接至或電性連接至母板1110。另外,可物理連接及/或電性連接至母板1110的其他組件或可不物理連接及/或不電性連接至母板1110的其他組件(例如照相機模組1130)可容置於本體1101中。電子組件1120中的一些電子組件可為晶片相關組件,例如半導體封裝1121,但並非僅限於此。所述電子裝置不必僅限於智慧型電話1100,而是可為如上所述的其他電子裝置。
半導體封裝
半導體封裝
一般而言,在半導體晶片中整合有許多精細的電路。然而,半導體晶片自身可能不能充當已完成的半導體產品,且可能因外部物理或化學影響而受損。因此,半導體晶片可能無法單獨使用,但可以封裝狀態在電子裝置等中封裝並使用。
此處,由於半導體晶片與電子裝置的主板之間存在電性連接方面的電路寬度差異,因而需要半導體封裝。詳言之,半導體晶片的連接墊的尺寸及半導體晶片的各連接墊之間的間隔極為精細,但電子裝置中所使用的主板的組件安裝墊的尺寸及主板的各組件安裝墊之間的間隔顯著大於半導體晶片的連接墊的尺寸及間隔。因此,可能難以將半導體晶片直接安裝於主板上,而需要用於緩衝半導體晶片與主板之間的電路寬度差異的封裝技術。
藉由封裝技術所製造的半導體封裝可端視半導體封裝的結構及目的而分類為扇入型半導體封裝或扇出型半導體封裝。
將在下文中參照圖式更詳細地闡述扇入型半導體封裝及扇出型半導體封裝。
扇入型 半導體封裝
扇入型 半導體封裝
圖3為示出扇入型半導體封裝在封裝前及封裝後的狀態的示意性剖視圖。
圖4為示出扇入型半導體封裝的封裝製程的示意性剖視圖。
參照圖式,半導體晶片2220可例如是處於裸露狀態下的積體電路(integrated circuit,IC),半導體晶片2220包括:本體2221,包含矽(Si)、鍺(Ge)或砷化鎵(GaAs)等;連接墊2222,形成於本體2221的一個表面上且包含例如鋁(Al)等導電材料;以及鈍化層2223,例如氧化物膜、氮化物膜等,形成於本體2221的一個表面上且覆蓋連接墊2222的至少部分。在此種情形中,由於連接墊2222是顯著小的,因此難以將積體電路(IC)安裝於中級印刷電路板(printed circuit board,PCB)上以及電子裝置的主板等上。
因此,可端視半導體晶片2220的尺寸而在半導體晶片2220上形成連接構件2240以對連接墊2222進行重新分佈。連接構件2240可藉由以下步驟來形成:使用例如感光成像介電(photo imagable dielectric,PID)樹脂等絕緣材料在半導體晶片2220上形成絕緣層2241,形成敞露連接墊2222的通孔孔洞2243h,並接著形成配線圖案2242及通孔2243。接著,可形成保護連接構件2240的鈍化層2250,可形成開口2251,且可形成凸塊下金屬層2260等。亦即,可藉由一系列製程來製造包括例如半導體晶片2220、連接構件2240、鈍化層2250及凸塊下金屬層2260的扇入型半導體封裝2200。
如上所述,扇入型半導體封裝可具有半導體晶片的所有連接墊(例如,輸入/輸出(input/output,I/O)端子)皆設置於半導體晶片內的一種封裝形式,且可具有優異的電性質並可以低成本進行生產。因此,已以扇入型半導體封裝的形式製造諸多安裝於智慧型電話中的元件。詳言之,已開發出安裝於智慧型電話中的許多元件以在具有緊湊尺寸的同時實施快速訊號傳輸。
然而,由於扇入型半導體封裝中的所有輸入/輸出端子皆需要設置於半導體晶片內,因此扇入型半導體封裝具有大的空間限制。因此,難以將此結構應用於具有大量輸入/輸出端子的半導體晶片或具有緊湊尺寸的半導體晶片。另外,由於上述缺點,扇入型半導體封裝可能無法在電子裝置的主板上直接安裝並使用。原因在於,即使藉由重佈線製程增大半導體晶片的輸入/輸出端子的尺寸及半導體晶片的各輸入/輸出端子之間的間隔,半導體晶片的輸入/輸出端子的尺寸及半導體晶片的各輸入/輸出端子之間的間隔仍不足以使扇入型半導體封裝直接安裝於電子裝置的主板上。
圖5為示出扇入型半導體封裝安裝於球柵陣列基板上且最終安裝於電子裝置的主板上之情形的示意性剖視圖。
圖6為示出扇入型半導體封裝嵌入球柵陣列基板中且最終安裝於電子裝置的主板上之情形的示意性剖視圖。
參照圖5及圖6,在扇入型半導體封裝2200中,半導體晶片2220的連接墊2222(亦即,輸入/輸出端子)可通過球柵陣列基板2301進行重新分佈,且扇入型半導體封裝2200可在扇入型半導體封裝2200安裝於球柵陣列基板2301上的狀態下最終安裝於電子裝置的主板2500上。在此種情形中,可藉由底部填充樹脂2280等來固定焊球2270等,且半導體晶片2220的外側面可以模製材料2290等覆蓋。或者,扇入型半導體封裝2200可嵌入單獨的球柵陣列基板2302中,半導體晶片2220的連接墊2222(亦即,輸入/輸出端子)可在扇入型半導體封裝2200嵌入中介基板2302中的狀態下,由球柵陣列基板2302重新分佈,且扇入型半導體封裝2200可最終安裝於電子裝置的主板2500上。
如上所述,可能難以在電子裝置的主板上直接安裝及使用扇入型半導體封裝。因此,扇入型半導體封裝可安裝於單獨的球柵陣列基板上,並接著藉由封裝製程安裝於電子裝置的主板上;或者扇入型半導體封裝可在扇入型半導體封裝嵌入球柵陣列基板中的狀態下在電子裝置的主板上安裝及使用。
扇出型 半導體封裝
扇出型 半導體封裝
圖7為示出扇出型半導體封裝的示意性剖視圖。
參照圖7,在扇出型半導體封裝2100中,舉例而言,半導體晶片2120的外側面可由包封體2130保護,且半導體晶片2120的連接墊2122可藉由連接構件2140而朝半導體晶片2120之外進行重新分佈。在此種情形中,可在連接構件2140上進一步形成鈍化層2202,且可在鈍化層2202的開口中進一步形成凸塊下金屬層2160。可在凸塊下金屬層2160上進一步形成焊球2170。半導體晶片2120可為包括本體2121、連接墊2122、鈍化層(未繪示)等的積體電路(IC)。連接構件2140可包括絕緣層2141、形成於絕緣層2241上的重佈線層2142以及將連接墊2122與重佈線層2142彼此電性連接的通孔2143。
如上所述,扇出型半導體封裝可具有一種形式,其中半導體晶片的輸入/輸出端子藉由形成於半導體晶片上的連接構件而朝半導體晶片之外進行重新分佈並朝半導體晶片之外設置。如上所述,在扇入型半導體封裝中,半導體晶片的所有輸入/輸出端子皆需要設置於半導體晶片內。因此,當半導體晶片的尺寸減小時,需減小球的尺寸及間距,進而使得標準化球佈局(standardized ball layout)可能無法在扇入型半導體封裝中使用。另一方面,扇出型半導體封裝具有如上所述的其中半導體晶片的輸入/輸出端子藉由形成於半導體晶片上的連接構件朝半導體晶片之外進行重新分佈並設置的形式。因此,即使在半導體晶片的尺寸減小的情形中,標準化球佈局亦可照樣用於扇出型半導體封裝中,使得扇出型半導體封裝無需使用單獨的球柵陣列基板即可安裝於電子裝置的主板上,如下所述。
圖8為示出扇出型半導體封裝安裝於電子裝置的主板上之情形的示意性剖視圖。
參照圖8,扇出型半導體封裝2100可通過焊球2170等安裝於電子裝置的主板2500上。亦即,如上所述,扇出型半導體封裝2100包括連接構件2140,連接構件2140形成於半導體晶片2120上且能夠將連接墊2122重新分佈至半導體晶片2120的尺寸之外的扇出區域,進而使得標準化球佈局可照樣用於扇出型半導體封裝2100中。因此,扇出型半導體封裝2100無需使用單獨的球柵陣列基板等即可安裝在電子裝置的主板2500上。
如上所述,由於扇出型半導體封裝無需使用單獨的球柵陣列基板即可安裝於電子裝置的主板上,因此扇出型半導體封裝可被實施成具有較使用球柵陣列基板的扇入型半導體封裝的厚度小的厚度。因此,扇出型半導體封裝可小型化及薄化。另外,扇出型半導體封裝具有優異的熱特性及電性特性,使得扇出型半導體封裝尤其適合用於行動產品。因此,扇出型半導體封裝可以較使用印刷電路板(PCB)的一般疊層封裝(POP)型的形式更緊湊的形式實施,且可解決因出現翹曲(warpage)現象而造成的問題。
同時,扇出型半導體封裝是指一種封裝技術,如上所述用於將半導體晶片安裝於電子裝置的主板等上且保護半導體晶片免受外部影響,並且扇出型半導體封裝是與例如球柵陣列基板等印刷電路板(PCB)的概念不同的概念,印刷電路板具有與扇出型半導體封裝的規格、目的等不同的規格、目的等,且有扇入型半導體封裝嵌入其中。
以下將參照圖式闡述能夠同時執行各種功能、被薄化且具有低訊號損耗的扇出型半導體封裝。
圖9為示出扇出型半導體封裝的實例的示意性剖視圖。
圖10為沿圖9所示扇出型半導體封裝的線I-I'截取的示意性平面圖。
參照圖式,根據例示性實施例的扇出型半導體封裝100A可包括:核心構件110,具有彼此間隔開的第一貫穿孔110HA及第二貫穿孔110HB,且包括一或多個配線層112a、配線層112b及配線層112c;第一半導體晶片120A,設置於第一貫穿孔110HA中,且具有形成於其下側上的第一連接墊120PA;第二半導體晶片120B,設置於第二貫穿孔110HB中,且具有形成於其下側上的第二連接墊120PB;第一包封體130,覆蓋第二半導體晶片120B、第一半導體晶片120A及核心構件110的至少部分;連接構件140,設置於核心構件110、第一半導體晶片120A及第二半導體晶片120B的下方,且包括一或多個重佈線層142;第一堆疊晶片180A,設置於第一包封體130上且經由第一連接導體180WA電性連接至核心構件110的一或多個配線層112a、配線層112b及配線層112c;第二堆疊晶片180B,設置於第一包封體130上且經由第二連接導體180WB電性連接至核心構件110的一或多個配線層112a、配線層112b及配線層112c;以及第二包封體190,設置於第一包封體130上,且覆蓋第二堆疊晶片180B及第一堆疊晶片180A的至少部分。另外,扇出型半導體封裝100A可包括:鈍化層150,設置於連接構件140下方且具有暴露連接構件140的重佈線層142中的最下重佈線層的至少部分的開口151;多個凸塊下金屬部分160,設置於鈍化層150的開口151上且連接至被暴露的最下重佈線層;以及多個電性連接結構170,設置於鈍化層150下方且連接至所述多個凸塊下金屬部分160。第一連接墊120PA及第二連接墊120PB可經由連接構件140的一或多個重佈線層142分別電性連接至核心構件110的一或多個配線層112a、配線層112b及配線層112c。第一半導體晶片120A可包括DRAM,第二半導體晶片120B可包括控制器,且第一堆疊晶片180A及第二堆疊晶片180B中的每一者可包括堆疊型反及快閃。
一般而言,SSD可被實施為藉由以下方式製造的疊層封裝型封裝:將DRAM及/或控制器安裝於第一中介基板上以形成下部封裝,將反及快閃安裝於第二中介基板上以形成上部封裝,以及使用焊球等將上部封裝與下部封裝彼此連接。然而,在此種情形中,由於基本上是使用中介基板,因此所述封裝的厚度相當大。尤其是,由於下部封裝及上部封裝是單獨製造然後進行堆疊來形成總體封裝,因此存在減小所述封裝的總體厚度的限制。另外,由於下部封裝與上部封裝之間的訊號距離相當大,因此可能發生特性損耗。
另一方面,在根據例示性實施例的扇出型半導體封裝100A中,適合用作DRAM及/或控制器的第一半導體晶片120A及第二半導體晶片120B可與具有一或多個配線層112a、配線層112b及配線層112c的核心構件110一起使用第一包封體130來包封,適合用作反及快閃的第一堆疊晶片180A及第二堆疊晶片180B可直接安裝於第一包封體130的上表面上而無需使用中介層,且第一堆疊晶片180A及第二堆疊晶片180B可使用連接導體180WA及連接導體180WB(例如接合線)電性連接至核心構件110的配線層112a、配線層112b及配線層112c。因此,總體封裝100A的厚度可顯著減小,且第一半導體晶片120A及第二半導體晶片120B與第一堆疊晶片180A及第二堆疊晶片180B之間的訊號傳輸通路可藉由減小的厚度而顯著縮短。因此,訊號特性的損耗可顯著減少。亦即,根據例示性實施例,可提供能夠同時執行各種功能、被薄化且具有低訊號損耗的扇出型半導體封裝100A,扇出型半導體封裝100A可適用於例如SSD等產品。
以下將更詳細闡述根據例示性實施例的扇出型半導體封裝100A中所包括的各組件。
核心構件110可包括對第一半導體晶片120A及第二半導體晶片120B的連接墊120PA及連接墊120PB及/或第一堆疊晶片180A及第二堆疊晶片180B的連接墊(未繪示)進行重新分佈的一或多個配線層112a、配線層112b及配線層112c。因此,可減少連接構件140的層數。另外,核心構件110可端視核心構件110的絕緣層的特定材料而維持扇出型半導體封裝100A的剛性,且用於確保第一包封體130的厚度均勻性。根據例示性實施例的扇出型半導體封裝100A的上部分及下部分可藉由核心構件110彼此電性連接。核心構件110可具有彼此間隔開的第一貫穿孔110HA及第二貫穿孔110HB。第一半導體晶片120A及第二半導體晶片120B可設置於第一貫穿孔110HA及第二貫穿孔110HB中,以與核心構件110間隔開預定距離。第一半導體晶片120A及第二半導體晶片120B的側表面可被核心構件110環繞。然而,此種形式僅為實例,且可進行各種修改以具有其他形式,並且核心構件110可端視此種形式而執行另一功能。
核心構件110可包括:第一絕緣層111a,其接觸連接構件140;第一配線層112a,其接觸連接構件140且嵌入第一絕緣層111a中;第二配線層112b,其設置於第一絕緣層111a的與第一絕緣層111a的嵌入有第一配線層112a的一個表面相對的另一表面上;第二絕緣層111b,其設置於第一絕緣層111a上且覆蓋第二配線層112b;以及第三配線層112c,其設置於第二絕緣層111b上。另外,核心構件110可包括貫穿第一絕緣層111a並將第一配線層112a與第二配線層112b彼此電性連接的第一連接通孔層113a以及貫穿第二絕緣層111b並將第二配線層112b與第三配線層112c彼此電性連接的第二連接通孔層113b。當第一配線層112a嵌入第一絕緣層111a中時,因第一配線層112a的厚度而產生的台階可顯著地減小,且連接構件140的絕緣距離可因而成為固定。因此,可容易達成連接構件140的高密度配線設計。第一配線層112a的下表面與第一絕緣層111a的下表面之間可具有台階。在此種情形中,第一絕緣層111a可防止第一包封體130滲入第一配線層112a的下表面,進而解決缺陷問題。
第一絕緣層111a及第二絕緣層111b中的每一者的材料無特別限制。舉例而言,可使用絕緣材料作為第一絕緣層111a及第二絕緣層111b的材料。在種情形中,所述絕緣材料可為熱固性樹脂,例如環氧樹脂;熱塑性樹脂,例如聚醯亞胺樹脂;包含熱固性樹脂及熱塑性樹脂以及例如無機填料及/或玻璃布(或玻璃纖維布)等核心材料的絕緣材料,例如預浸體(prepreg)、味之素構成膜(Ajinomoto Build up Film,ABF)、FR-4或雙馬來醯亞胺三嗪(Bismaleimide Triazine,BT)等。可使用ABF作為第一絕緣層111a及第二絕緣層111b的材料。
第一配線層112a、第二配線層112b及第三配線層112c可用於對第一半導體晶片120A及第二半導體晶片120B的連接墊120PA及連接墊120PB及/或第一堆疊晶片180A及第二堆疊晶片180B的連接墊(未繪示)進行重新分佈,且可用於為連接通孔層113a及連接通孔層113b提供接墊圖案,以將封裝100A的上部分及下部分彼此連接。配線層112a、配線層112b及配線層112c中的每一者的材料可為導電材料,例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金。第一配線層112a、第二配線層112b以及第三配線層112c可端視對應層的設計而執行各種功能。舉例而言,第一配線層112a、第二配線層112b以及第三配線層112c可包括接地(GND)圖案、電源(PWR)圖案、訊號(S)圖案等。此處,訊號(S)圖案可包括除了接地(GND)圖案、電源(PWR)圖案等之外的各種訊號,例如資料訊號等。另外,第一配線層112a、第二配線層112b以及第三配線層112c可包括通孔接墊、焊線接墊、電性連接結構接墊等。舉例而言,設置於最上部分上的第三配線層112c可包括與第一堆疊晶片180A及第二堆疊晶片180B的第一連接導體180WA及第二連接導體180WB連接的接墊圖案,且在其中第一連接導體180WA及第二連接導體180WB為接合線的情形中,第三配線層112c的接墊圖案可為焊線接墊。此時,第三配線層112c的焊線接墊的至少部分可經由在第一包封體130中形成的開口131被暴露,且被暴露的部分可連接至上述接合線。同時,若需要,則可在被暴露的第三配線層112c的焊線接墊的表面上形成表面處理層(未繪示)。表面處理層(未繪示)無特別限制,只要其在相關技術中為已知即可,但表面處理層可藉由例如電解鍍金、無電鍍金、有機可焊性保護劑(organic solderability preservative,OSP)或者無電鍍錫、無電鍍銀、無電鍍鎳/置換鍍金、直接浸金(direct immersion gold,DIG)鍍覆或熱空氣焊料均塗(hot air solder leveling,HASL)等而形成。
第一連接通孔層113a及第二連接通孔層113b可將在不同層上形成的配線層112a、配線層112b及配線層112c彼此電性連接,因而在核心構件110中形成電性通路。第一連接通孔層113a及第二連接通孔層113b中的每一者的材料可為導電材料。第一連接通孔層113a及第二連接通孔層113b中的每一者的連接通孔可以導電材料完全填充,或者導電材料亦可沿通孔孔洞中的每一者的壁形成。另外,連接通孔中的每一者可具有錐形形狀。同時,當第一連接通孔層113a的通孔孔洞形成時,第一配線層112a的接墊圖案的一部分可充當終止元件。因此,第一連接通孔層113a可根據製程而具有其上表面的寬度大於其下表面的寬度的錐形形狀。在此種情形中,第一連接通孔層113a可與第二配線層112b的接墊圖案整合於一起。類似地,第二連接通孔層113b亦可根據製程而具有其上表面的寬度大於其下表面的寬度的錐形形狀。在此種情形中,第二連接通孔層113b可與第三配線層112c的接墊圖案整合於一起。
第一半導體晶片121A可為以數百至數百萬個或更多個數量的元件整合於單一晶片中提供的積體電路(IC)。在此種情形中,構成第一半導體晶片120A的積體電路可為例如揮發性記憶體,例如DRAM。第一半導體晶片120A可以主動晶圓為基礎形成。在此種情形中,本體的基礎材料(base material)可為矽(Si)、鍺(Ge)或砷化鎵(GaAs)等。可在本體上形成各種電路。第一連接墊120PA可將第一半導體晶片120A電性連接至其他組件,且可使用例如鋁(Al)等導電材料作為第一連接墊120PA中的每一者的材料而無任何特別限制。上面設置有第一連接墊120PA的表面可為主動面,且相對的表面可為非主動面。可在本體上形成暴露第一連接墊120PA的鈍化層(未繪示),且所述鈍化層可為氧化物膜、氮化物膜等或氧化物層與氮化物層所構成的雙層。可在其他需要的位置上進一步設置絕緣膜(未繪示)等,且亦可在主動面上形成重佈線層(未繪示)。
第二半導體晶片120B亦可為以數百至數百萬個或更多個數量的元件整合於單一晶片中提供的積體電路(IC)。此時,構成第二半導體晶片120B的積體電路可為例如控制器。第二半導體晶片120B亦可以主動晶圓為基礎形成。詳細內容如上所述。若需要,則核心構件110可僅具有第一貫穿孔110HA,可在第一貫穿孔110HA中僅設置第一半導體晶片120A或第二半導體晶片120B,且亦可在第一貫穿孔110HA中同時設置第一半導體晶片120A及第二半導體晶片120B。
第一包封體130可保護核心構件110、第一半導體晶片120A、第二半導體晶片120B等。第一包封體130的包封形式無特別限制,但可為第一包封體130環繞核心構件110、第一半導體晶片120A、第二半導體晶片120B等的至少部分的形式。舉例而言,第一包封體130可覆蓋核心構件110、第一半導體晶片120A、第二半導體晶片120B,且可填充第一貫穿孔110HA及第二貫穿孔110HB中的每一者的至少部分。第一包封體130的特定材料無特別限制。舉例而言,可使用絕緣材料作為第一包封體130的特定材料。在此種情形中,所述絕緣材料可為包含無機填料及絕緣樹脂的材料,舉例而言,為熱固性樹脂,例如環氧樹脂;熱塑性樹脂,例如聚醯亞胺樹脂;具有浸入於熱固性樹脂及熱塑性樹脂中的加強材料(例如無機填料)的樹脂,例如ABF、FR-4或BT等。或者,可使用環氧模製化合物(epoxy molding compound,EMC)或PID等作為所述絕緣材料。或者,亦可使用將熱固性樹脂或熱塑性樹脂與無機填料一起浸入例如玻璃布(或玻璃纖維布)等核心材料中的預浸體作為所述絕緣材料。
連接構件140可對第一半導體晶片120A及第二半導體晶片120B的第一連接墊120PA及第二連接墊120PB及/或第一堆疊晶片180A及第二堆疊晶片180B的連接墊(未繪示)進行重新分佈,且可將所述連接墊彼此電性連接。具有各種功能的數十至數百萬個連接墊122可藉由連接構件140進行重新分佈,且可端視功能而藉由電性連接結構170進行外部物理連接及/或外部電性連接。連接構件140可包括絕緣層141、設置在絕緣層141上的重佈線層142以及貫穿絕緣層141並將各重佈線層142彼此連接的連接通孔143。在根據例示性實施例的扇出型半導體封裝100A中,連接構件140可包括多個層,但亦可包括單個層。
絕緣層141中的每一者的材料可為絕緣材料。在此種情形中,除上述絕緣材料以外,亦可使用例如PID樹脂等感光性絕緣材料作為所述絕緣材料。亦即,絕緣層141可為感光性絕緣層。當絕緣層141具有感光性質時,絕緣層141可被形成為具有較小的厚度,且可更易於達成連接通孔143的精細間距。絕緣層141可為包含絕緣樹脂及無機填料的感光性絕緣層。當絕緣層141為多層時,絕緣層141的材料可為彼此相同,且若需要,則亦可為彼此不同。當絕緣層141為多層時,絕緣層141可端視製程而彼此整合,進而使得各絕緣層之間的邊界亦可為不明顯。
重佈線層142可實質上用於對連接墊122進行重新分佈。重佈線層142中的每一者的材料可為導電材料,例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金。重佈線層142可端視對應層的設計而執行各種功能。舉例而言,重佈線層142可包括接地(GND)圖案、電源(PWR)圖案、訊號(S)圖案等。此處,訊號(S)圖案可包括除了接地(GND)圖案、電源(PWR)圖案等之外的各種訊號,例如資料訊號等。另外,重佈線層142可包括通孔接墊、電性連接結構接墊等。若需要,則可在被鈍化層150的開口151暴露的一些重佈線層142的表面上形成表面處理層(未繪示)。表面處理層(未繪示)可藉由例如電解鍍金、無電鍍金、有機可焊性保護劑(OSP)或者無電鍍錫、無電鍍銀、無電鍍鎳/置換鍍金、直接浸金(DIG)鍍覆或熱空氣焊料均塗(HASL)等而形成,但並非僅限於此。同時,核心構件110的配線層112a、配線層112b及配線層112c的厚度可大於連接構件140的重佈線層142的厚度。由於核心構件110的厚度可等於或大於第一半導體晶片120A及第二半導體晶片120B的厚度,因此形成於核心構件110上的配線層112a、配線層112b及配線層112c亦可端視核心構件110的規格而形成為具有大的尺寸。另一方面,連接構件140的重佈線層142可被形成為具有較核心構件110的配線層112a、配線層112b及配線層112c的尺寸相對更小的尺寸以達成連接構件140的薄度。
連接通孔143可將在不同層上形成的重佈線層142、連接墊120PA及連接墊120PB等彼此電性連接,因而在扇出型半導體封裝100A中形成電性通路。連接通孔143中的每一者的材料可為導電材料,例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金。連接通孔143中的每一者可以導電材料完全填充,或者導電材料亦可沿通孔中的每一者的壁形成。另外,各連接通孔143可在彼此相同的方向上具有錐形形狀。
鈍化層150可另外配置以保護連接構件140免受外部物理或化學損傷。鈍化層150可具有暴露連接構件140的重佈線層142中的最下重佈線層的至少部分的開口151。在鈍化層150中形成的開口151的數目可為數十至數百萬個。可使用彈性模數大於連接構件140的絕緣層141的彈性模數的材料作為鈍化層150的材料。舉例而言,可使用不包含玻璃布(或玻璃纖維布)但包含無機填料及絕緣樹脂的ABF等作為鈍化層150的材料。當使用ABF等作為鈍化層150的材料時,鈍化層150中所包含的無機填料的重量百分比可大於連接構件140的絕緣層141中所包含的無機填料的重量百分比。在此種情況下,可提高可靠性。當使用ABF等作為鈍化層150的材料時,鈍化層150可為包含無機填料的非感光性絕緣層,且可有效地提高可靠性,但並非僅限於此。
凸塊下金屬部分160可具有其他配置且提高電性連接結構170的連接可靠性,以提高扇出型半導體封裝100A的板級可靠性。凸塊下金屬層160可連接至經由鈍化層150的開口151所暴露的連接構件140的重佈線層142。可藉由已知金屬化方法,使用已知導電金屬(例如金屬)在鈍化層150的開口151中形成凸塊下金屬層160,但並非僅限於此。
電性連接結構170可另外配置以外部物理連接及/或外部電性連接扇出型半導體封裝100A。舉例而言,扇出型半導體封裝100A可經由電性連接結構170安裝於電子裝置的主板上。電性連接結構170中的每一者可由低熔點金屬(例如錫(Sn)或包含錫(Sn)的合金材料,更具體而言,焊料等)形成。然而,此僅為實例,且電性連接結構170中的每一者的材料不特別受限於此。電性連接結構170中的每一者可為接腳、球或引腳等。電性連接結構170可形成為多層結構或單層結構。當電性連接結構170形成為多層結構時,電性連接結構170可包含銅(Cu)柱及焊料。當電性連接結構170形成為單層結構時,電性連接結構170可包含錫-銀焊料或銅(Cu)。然而,電性連接結構170並非僅限於此。
電性連接結構170的數目、間隔、設置形式等無特別限制,而是可由熟習此項技術者端視設計特定細節而進行充分地修改。舉例而言,電性連接結構170可根據連接墊的數目而設置為數十至數百萬的數量,或可設置為數十至數百萬或更多的數量或數十至數千或更少的數量。當電性連接結構170為焊球時,電性連接結構170可覆蓋延伸至鈍化層150的下表面上的凸塊下金屬部分160的側表面,且連接可靠性可更加優異。電性連接結構170中的至少一者可設置於扇出區域中。所述扇出區域為除了設置有第一半導體晶片120A的區域之外的區域。扇出型封裝可具有較扇入型封裝的可靠性更大的可靠性,可實施多個輸入/輸出端子,且可易於執行三維內連線(3D interconnection)。另外,相較於球柵陣列(BGA)封裝或接腳柵陣列(land grid array,LGA)封裝等而言,扇出型封裝可被製造成具有小的厚度,且可具有價格競爭力。
第一堆疊晶片180A及第二堆疊晶片180B中的每一者可藉由以3D形式堆疊多個積體電路來實施。此時,構成第一堆疊晶片180A及第二堆疊晶片180B中的每一者的積體電路可為快閃記憶體。更具體而言,第一堆疊晶片180A及第二堆疊晶片180B中的每一者可為3D形狀的堆疊型反及快閃。第一堆疊晶片180A及第二堆疊晶片180B各自的經堆疊記憶體的連接墊(未示出)可經由連接導體180WA及連接導體180WB連接至核心構件110的第三配線層113c的接墊圖案,可經由核心構件110的配線層112a、配線層112b及配線層112c電性連接至連接構件140的重佈線層142,且可電性連接至第一半導體晶片120A及第二半導體晶片120B的連接墊120PA及連接墊120PB或者電性連接結構170。連接導體180WA及連接導體180WB可為已知的接合線,例如金屬線。第一堆疊晶片180A可設置於第一半導體晶片120A上,且在第一堆疊晶片180A堆疊於第一半導體晶片120A上所沿的垂直方向上與第一半導體晶片120A交疊,且第二堆疊晶片180B可設置於第二半導體晶片120B上,且在第二堆疊晶片180B堆疊於第二半導體晶片120B上所沿的垂直方向上與第二半導體晶片120B交疊。第一半導體晶片120A的第一連接墊120PA中的至少一者可經由連接構件140的重佈線層142電性連接至電性連接結構170中的至少一者,且其他第一連接墊120PA可經由連接構件140的重佈線層142以及核心構件110的配線層112a、配線層112b及配線層112c電性連接至第一堆疊晶片180A。類似地,第二半導體晶片120B的第二連接墊120PB中的至少一者可經由連接構件140的重佈線層142電性連接至電性連接結構170中的至少一者,且其他第二連接墊120PB可經由連接構件140的重佈線層142以及核心構件110的配線層112a、配線層112b及配線層112c電性連接至第二堆疊晶片180B。
第二包封體190可保護第一堆疊晶片180A及第二堆疊晶片180B。第二包封體190的包封形式無特別限制,但可為第二包封體190環繞第一堆疊晶片180A及第二堆疊晶片180B的至少部分的形式。舉例而言,第二包封體190可覆蓋第一堆疊晶片180A及第二堆疊晶片180B,以使第一堆疊晶片180A及第二堆疊晶片180B完全嵌入。第二包封體190的特定材料無特別限制。舉例而言,可使用絕緣材料作為第二包封體190的特定材料。在此種情形中,所述絕緣材料可為包含無機填料及絕緣樹脂的材料,舉例而言,為熱固性樹脂,例如環氧樹脂;熱塑性樹脂,例如聚醯亞胺樹脂;具有浸入於熱固性樹脂及熱塑性樹脂中的加強材料(例如無機填料)的樹脂,例如ABF、FR-4或BT等。另外,亦可使用環氧模製化合物或PID等作為所述絕緣材料,且亦可使用其中熱固性樹脂或熱塑性樹脂與無機填料一起浸入例如玻璃布等核心材料中的預浸體。
同時,儘管圖式中未示出,然而可與貫穿孔110HA及貫穿孔110HB中的半導體晶片120A及半導體晶片120B一起設置單獨的被動組件以使其平行。或者,亦可在鈍化層150的下表面上安裝單獨的被動組件。另外,可在貫穿孔110HA及貫穿孔110HB的壁上設置金屬層以達成電磁屏蔽及熱輻射效果。
圖11為示出扇出型半導體封裝的另一實例的示意性剖視圖。
參照圖式,根據本揭露中的另一例示性實施例的扇出型半導體封裝100B可更包括:背側重佈線層132,其設置於第一包封體130上;背側通孔133,其貫穿第一包封體130的至少部分,且將背側重佈線層132與核心構件110的重佈線層112c彼此電性連接;以及覆蓋層195,其設置於第一包封體130上,且覆蓋背側重佈線層132的至少部分。此時,第一堆疊晶片180A及第二堆疊晶片180B可設置於覆蓋層195上,且可分別經由第一連接導體180WA及第二連接導體180WB電性連接至背側重佈線層132。更具體而言,第一堆疊晶片180A及第二堆疊晶片180B中的每一者可安裝於覆蓋層195的上表面上,第一連接導體180WA及第二連接導體180WB中的每一者可包括接合線,背側重佈線層132可包括焊線接墊,覆蓋層195可具有暴露焊線接墊的至少部分的開口197,且接合線可連接至被暴露的焊線接墊。
背側重佈線層132可用於對第一半導體晶片120A及第二半導體晶片120B的連接墊120PA及連接墊120PB以及第一堆疊晶片180A及第二堆疊晶片180B的連接墊(未繪示)進行重新分佈,且可使用例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金等導電材料作為背側重佈線層132的材料。背側重佈線層132可端視設計而執行各種功能。舉例而言,背側重佈線層132可包括接地(GND)圖案、電源(PWR)圖案、訊號(S)圖案等。此處,訊號(S)圖案可包括除了接地(GND)圖案、電源(PWR)圖案等之外的各種訊號,例如資料訊號等。另外,背側重佈線層132可包括通孔接墊、焊線接墊、電性連接結構接墊等。背側重佈線層132的部分可經由在覆蓋層195中形成的開口197而被暴露,且被暴露的背側重佈線層132可連接至上述接合線。亦即,被暴露的背側重佈線層可包括連接至焊線的焊線接墊。同時,若需要,則可在被暴露的重佈線層132的表面上形成表面處理層(未示出)。表面處理層(未示出)可藉由例如電解鍍金、無電鍍金、OSP或者無電鍍錫、無電鍍銀、無電鍍鎳/置換鍍金、DIG鍍覆或HASL等而形成。
背側通孔133可將在不同層上形成的背側重佈線層132、配線層112c等彼此電性連接,因而在扇出型半導體封裝100B中形成電性通路。背側通孔133的材料可為導電材料,例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金。背側通孔133中的每一者可以導電材料完全填充,或者導電材料可沿通孔中的每一者的壁形成。另外,背側通孔133可在與連接構件140的連接通孔143相反的方向上具有錐形形狀。其他內容與上述內容重複,且因此省略其詳細說明。
圖12為示出扇出型半導體封裝的另一實例的示意性剖視圖。
圖13為示出扇出型半導體封裝的另一實例的示意性剖視圖。
參照圖式,與上述扇出型半導體封裝100A及扇出型半導體封裝100B不同,在根據本揭露中的另一例示性實施例的扇出型半導體封裝100C及扇出型半導體封裝100D中,核心構件110可包括第一絕緣層111a;第一配線層112a及第二配線層112b,其分別設置於第一絕緣層111a的相對表面上;第二絕緣層111b,其設置於第一絕緣層111a的下表面上且覆蓋第一配線層112a;第三重佈線層111c,其設置於第二絕緣層111b的下表面上;第三絕緣層111c,其設置於第一絕緣層111a的上表面上且覆蓋第二配線層112b;以及第四配線層112d,其設置於第三絕緣層111c的上表面上。由於核心構件110可包括更大數目的配線層112a、配線層112b、配線層112c及配線層112d,因此連接構件140可被進一步簡化。因此,因形成連接構件140的製程中出現的缺陷而導致的良率下降問題可獲得抑制。同時,第一配線層112a、第二配線層112b、第三配線層112c及第四配線層112d可經由分別貫穿第一絕緣層111a、第二絕緣層111b及第三絕緣層111c的第一連接通孔層113a、第二連接通孔層113b及第三連接通孔層113c而彼此電性連接。
第一絕緣層111a的厚度可大於第二絕緣層111b的厚度及第三絕緣層111c的厚度。第一絕緣層111a基本上可為相對厚的以維持剛性,且第二絕緣層111b及第三絕緣層111c可被引入以形成更大數目的配線層112c及配線層112d。第一絕緣層111a可包含與第二絕緣層111b及第三絕緣層111c的絕緣材料不同的絕緣材料。舉例而言,第一絕緣層111a可例如為包含核心材料、無機填料及絕緣樹脂的預浸體,且第二絕緣層111b及第三絕緣層111c可為包含無機填料及絕緣樹脂的味之素構成膜或感光性絕緣膜。然而,第一絕緣層111a的材料以及第二絕緣層111b及第三絕緣層111c的材料並非僅限於此。
核心構件110的第三配線層112c可以突出的形式設置於第二絕緣層111b上,因而接觸連接構件140。核心構件110的第一配線層112a及第二配線層112b可設置於第一半導體晶片120A的主動面與非主動面之間。核心構件110可被形成為具有與第一半導體晶片120的厚度對應的厚度。因此,形成於核心構件110中的第一配線層112a及第二配線層112b可設置在第一半導體晶片120的主動面與非主動面之間的水平高度上。核心構件110的第一配線層112a、第二配線層112b、第三配線層112c及第四配線層112d的厚度可大於連接構件140的重佈線層142的厚度。由於核心構件110的厚度可等於或大於第一半導體晶片120的厚度,因此亦可形成較大尺寸的配線層112a、配線層112b、配線層112c及配線層112d。另一方面,連接構件140的重佈線層142可被形成為具有相對小的尺寸以達成薄度。其他內容與上述內容重複,且因此省略其詳細說明。
在本文中,下側、下部分、下表面等是用來指代相對於圖式的橫截面的朝向扇出型半導體封裝之安裝表面的方向,而上側、上部分、上表面等是用來指代與所述方向相反的方向。然而,定義該些方向是為了方便闡釋,且本申請專利範圍並不受如上所述所定義的方向特別限制。
在說明書中,組件與另一組件的「連接」的意義包括經由黏合層的間接連接以及在兩個組件之間的直接連接。另外,「電性連接」意為包括物理連接及物理斷接的概念。應理解,當以「第一」及「第二」來指稱元件時,所述元件不不受限於此。使用「第一」及「第二」可能僅用於將所述元件與其他元件區分開的目的,且可不限制所述元件的順序或重要性。在一些情形中,在不背離本揭露的範圍的條件下,第一組件可被稱為第二組件,且第二組件亦可類似地被稱為第一組件。
本文中所使用的用語「例示性實施例」並不指代同一例示性實施例,而是提供來強調與另一例示性實施例的特定特徵或特性不同的特定特徵或特性。然而,本文中所提供的例示性實施例被視為能夠藉由彼此整體組合或部分組合而實施。舉例而言,即使並未在另一例示性實施例中闡述在特定例示性實施例中闡述的一個元件,除非在另一例示性實施例中提供了相反或矛盾的說明,否則所述元件亦可被理解為與另一例示性實施例相關的說明。
本文中所使用的用語僅用於闡述例示性實施例,而非限制本揭露。在此種情形中,除非在上下文中另有解釋,否則單數形式包括複數形式。
如上所述,根據本揭露中的例示性實施例,可提供一種能夠同時執行各種功能、被薄化且具有低訊號損耗的扇出型半導體封裝。
儘管以上已示出並闡述了例示性實施例,然而對於熟習此項技術者而言將顯而易見的是,在不背離由隨附申請專利範圍所界定的本發明的範圍的條件下,可作出修改及變型。
100A、100B、100C、100D、2100‧‧‧扇出型半導體封裝
110‧‧‧核心構件
110HA、110HB‧‧‧貫穿孔
111a‧‧‧第一絕緣層
111b‧‧‧第二絕緣層
111c‧‧‧第三絕緣層
112a、112b、112c、112d‧‧‧配線層
113a、113b、113c‧‧‧連接通孔層
120A、120B‧‧‧半導體晶片
120PA、120PB‧‧‧連接墊
130‧‧‧第一包封體
131、151、197、2251‧‧‧開口
132‧‧‧背側重佈線層
133‧‧‧背側通孔
140、2140、2240‧‧‧連接構件
141、2141、2241‧‧‧絕緣層
142、2142‧‧‧重佈線層
143‧‧‧連接通孔
150、2150、2223、2250‧‧‧鈍化層
160‧‧‧凸塊下金屬部分
170‧‧‧電性連接結構
180A‧‧‧第一堆疊晶片
180B‧‧‧第二堆疊晶片
180WA‧‧‧第一連接導體/連接導體
180WB‧‧‧第二連接導體/連接導體
190‧‧‧第二包封體
195‧‧‧覆蓋層
1000‧‧‧電子裝置
1010、2500‧‧‧主板
1020‧‧‧晶片相關組件
1030‧‧‧網路相關組件
1040‧‧‧組件
1050‧‧‧照相機
1060‧‧‧天線
1070‧‧‧顯示器裝置
1080‧‧‧電池
1090‧‧‧訊號線
1100‧‧‧智慧型電話
1101、2121、2221‧‧‧本體
1110‧‧‧母板
1120‧‧‧組件/電子組件
1121‧‧‧半導體封裝
1130‧‧‧照相機模組
2120、2220‧‧‧半導體晶片
2122、2222‧‧‧連接墊
2130‧‧‧包封體
2143、2243‧‧‧通孔
2160、2260‧‧‧凸塊下金屬層
2170、2270‧‧‧焊球
2200‧‧‧扇入型半導體封裝
2242‧‧‧配線圖案
2243h‧‧‧通孔孔洞
2280‧‧‧底部填充樹脂
2290‧‧‧模製材料
2301、2302‧‧‧球柵陣列基板
I-I'‧‧‧線
結合所附圖式閱讀以下詳細說明,將更清晰地理解本揭露的以上及其他態樣、特徵及其他優點,在所附圖式中:
圖1為示出電子裝置系統的實例的示意性方塊圖。
圖2為示出電子裝置的實例的示意性立體圖。
圖3為示出扇入型半導體封裝在封裝前及封裝後的狀態的示意性剖視圖。
圖4為示出扇入型半導體封裝的封裝製程的示意性剖視圖。
圖5為示出扇入型半導體封裝安裝於球柵陣列(ball grid array,BGA)基板上且最終安裝於電子裝置的主板上之情形的示意性剖視圖。
圖6為示出扇入型半導體封裝嵌入球柵陣列基板中且最終安裝於電子裝置的主板上之情形的示意性剖視圖。
圖7為示出扇出型半導體封裝的示意性剖視圖。
圖8為示出扇出型半導體封裝安裝於電子裝置的主板上之情形的示意性剖視圖。
圖9為示出扇出型半導體封裝的實例的示意性剖視圖。
圖10為沿圖9所示扇出型半導體封裝的線I-I'截取的示意性平面圖。
圖11為示出扇出型半導體封裝的另一實例的示意性剖視圖。
圖12為示出扇出型半導體封裝的另一實例的示意性剖視圖。
圖13為示出扇出型半導體封裝的另一實例的示意性剖視圖。
Claims (16)
- 一種扇出型半導體封裝,包括: 核心構件,具有第一貫穿孔且包括一或多個配線層; 第一半導體晶片,設置於所述第一貫穿孔中,且具有形成於所述第一半導體晶片的下側上的第一連接墊; 第一包封體,覆蓋所述第一半導體晶片和所述核心構件的至少部分; 連接構件,設置於所述核心構件及所述第一半導體晶片下方,且包括一或多個重佈線層; 第一堆疊晶片,設置於所述第一包封體上且經由第一連接導體電性連接至所述核心構件的所述一或多個配線層;以及 第二包封體,設置於所述第一包封體上,且覆蓋所述第一堆疊晶片的至少部分, 其中所述第一半導體晶片包括動態隨機存取記憶體及控制器中的至少一者, 所述第一堆疊晶片包括堆疊型反及快閃(NAND flash),且 所述第一半導體晶片的所述第一連接墊經由所述連接構件的所述一或多個重佈線層電性連接至所述核心構件的所述一或多個配線層。
- 如申請專利範圍第1項所述的扇出型半導體封裝,其中所述第一堆疊晶片安裝在所述第一包封體的上表面上, 所述第一連接導體包括接合線, 所述一或多個配線層中的最上配線層包括焊線接墊, 所述第一包封體具有暴露所述焊線接墊的至少部分的開口,且 所述接合線連接至被暴露的所述焊線接墊。
- 如申請專利範圍第1項所述的扇出型半導體封裝,更包括: 背側重佈線層,設置於所述第一包封體上; 背側通孔,貫穿所述第一包封體的至少部分,且將所述背側重佈線層與所述一或多個配線層中的最上配線層彼此電性連接;以及 覆蓋層,設置於所述第一包封體上且覆蓋所述背側重佈線層的至少部分, 其中所述第一堆疊晶片設置於所述覆蓋層上且經由所述第一連接導體電性連接至所述背側重佈線層。
- 如申請專利範圍第3項所述的扇出型半導體封裝,其中所述第一堆疊晶片安裝在所述覆蓋層的上表面上, 所述第一連接導體包括接合線, 所述背側重佈線層包括焊線接墊, 所述覆蓋層具有暴露所述焊線接墊的至少部分的開口,且 所述接合線連接至被暴露的所述焊線接墊。
- 如申請專利範圍第1項所述的扇出型半導體封裝,其中所述核心構件更具有與所述第一貫穿孔間隔開的第二貫穿孔, 在所述第二貫穿孔中設置有具有第二連接墊的第二半導體晶片, 在所述第一包封體上設置有經由第二連接導體電性連接至所述核心構件的所述一或多個配線層的第二堆疊晶片, 所述第一半導體晶片包括動態隨機存取記憶體, 所述第二半導體晶片包括控制器,且 所述第二堆疊晶片包括堆疊型反及快閃。
- 如申請專利範圍第5項所述的扇出型半導體封裝,其中所述第一堆疊晶片在所述第一堆疊晶片及所述第一半導體晶片的堆疊方向上與所述第一半導體晶片交疊, 所述第二堆疊晶片在所述第二堆疊晶片及所述第二半導體晶片的堆疊方向上與所述第二半導體晶片交疊,且 所述第一堆疊晶片及所述第二堆疊晶片被設置成彼此平行。
- 如申請專利範圍第1項所述的扇出型半導體封裝,其中所述核心構件包括: 第一絕緣層; 第一配線層,接觸所述連接構件且嵌入所述第一絕緣層中; 第二配線層,設置於所述第一絕緣層的與所述第一絕緣層的嵌入有所述第一配線層的一個表面相對的另一表面上;以及 第一連接通孔層,貫穿所述第一絕緣層且將所述第一配線層與所述第二配線層彼此電性連接。
- 如申請專利範圍第7項所述的扇出型半導體封裝,其中所述核心構件更包括: 第二絕緣層,設置於所述第一絕緣層上且覆蓋所述第二配線層; 第三配線層,設置於所述第二絕緣層上;以及 第二連接通孔層,貫穿所述第二絕緣層且將所述第二配線層與所述第三配線層彼此電性連接。
- 如申請專利範圍第7項所述的扇出型半導體封裝,其中所述絕緣層的下表面與所述第一配線層的下表面之間具有台階。
- 如申請專利範圍第1項所述的扇出型半導體封裝,其中所述核心構件包括: 第一絕緣層; 第一配線層及第二配線層,設置於所述第一絕緣層的相對表面上;以及 第一連接通孔層,貫穿所述第一絕緣層且將所述第一配線層與所述第二配線層彼此電性連接。
- 如申請專利範圍第10項所述的扇出型半導體封裝,其中所述核心構件更包括: 第二絕緣層,設置於所述第一絕緣層的下表面上且覆蓋所述第一配線層; 第三配線層,設置於所述第二絕緣層的下表面上; 第二連接通孔層,貫穿所述第二絕緣層且將所述第一配線層與所述第三配線層彼此電性連接; 第三絕緣層,設置於所述第一絕緣層的上表面上且覆蓋所述第二配線層; 第四配線層,設置於所述第三絕緣層的上表面上;以及 第四連接通孔層,貫穿所述第三絕緣層且將所述第二配線層與所述第四配線層彼此電性連接。
- 如申請專利範圍第11項所述的扇出型半導體封裝,其中所述第一絕緣層的厚度大於所述第二絕緣層的厚度及所述第三絕緣層的厚度。
- 如申請專利範圍第1項所述的扇出型半導體封裝,更包括: 鈍化層,設置於所述連接構件下方,且具有暴露所述連接構件的所述重佈線層中的最下重佈線層的至少部分的開口; 多個凸塊下金屬部分,設置於所述鈍化層的所述開口上且連接至被暴露的所述最下重佈線層;以及 多個電性連接結構,設置於所述鈍化層下方且連接至所述多個凸塊下金屬部分。
- 如申請專利範圍第13項所述的扇出型半導體封裝,其中所述第一半導體晶片的所述第一連接墊中的至少一者經由所述連接構件的所述重佈線層電性連接至所述電性連接結構中的至少一者,且 所述第一半導體晶片的其他所述第一連接墊經由所述連接構件的所述一或多個重佈線層以及所述核心構件的所述一或多個配線層電性連接至所述第一堆疊晶片。
- 一種扇出型半導體封裝,包括: 核心構件,具有彼此間隔開的第一貫穿孔及第二貫穿孔,且包括一或多個配線層; 第一半導體晶片,設置於所述第一貫穿孔中,且具有形成於所述第一半導體晶片的下側上的第一連接墊; 第二半導體晶片,設置於所述第二貫穿孔中,且具有形成於所述第二半導體晶片的下側上的第二連接墊; 第一包封體,覆蓋所述第二半導體晶片、所述第一半導體晶片及所述核心構件的至少部分; 連接構件,設置於所述核心構件、所述第一半導體晶片及所述第二半導體晶片的下方,且包括一或多個重佈線層; 第一堆疊晶片,設置於所述第一包封體上且經由第一連接導體電性連接至所述核心構件的所述一或多個配線層; 第二堆疊晶片,設置於所述第一包封體上且經由第二連接導體電性連接至所述核心構件的所述一或多個配線層;以及 第二包封體,設置於所述第一包封體上,且覆蓋所述第二堆疊晶片及所述第一堆疊晶片的至少部分, 其中所述第一連接墊及所述第二連接墊分別經由所述連接構件的所述一或多個重佈線層電性連接至所述核心構件的所述一或多個配線層。
- 如申請專利範圍第15項所述的扇出型半導體封裝,其中所述第一半導體晶片包括動態隨機存取記憶體, 所述第二半導體晶片包括控制器, 所述第一堆疊晶片包括堆疊型反及快閃,且 所述第二堆疊晶片包括堆疊型反及快閃。
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US20200211980A1 (en) * | 2018-12-27 | 2020-07-02 | Powertech Technology Inc. | Fan-out package with warpage reduction and manufacturing method thereof |
US11664350B2 (en) * | 2020-05-20 | 2023-05-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of manufacture |
US11985782B2 (en) * | 2022-04-08 | 2024-05-14 | Western Digital Technologies, Inc. | Enclosure fitting for electronic device |
CN115084093B (zh) * | 2022-08-23 | 2022-12-20 | 深圳市遇贤微电子有限公司 | 芯片封装结构和封装方法 |
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US8354304B2 (en) | 2008-12-05 | 2013-01-15 | Stats Chippac, Ltd. | Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant |
WO2014131152A1 (en) | 2013-02-26 | 2014-09-04 | Sandisk Information Technology (Shanghai) Co., Ltd. | Semiconductor device including alternating stepped semiconductor die stacks |
US9418974B2 (en) | 2014-04-29 | 2016-08-16 | Micron Technology, Inc. | Stacked semiconductor die assemblies with support members and associated systems and methods |
RU2663688C1 (ru) | 2014-09-26 | 2018-08-08 | Интел Корпорейшн | Корпусированная интегральная схема, содержащая соединенный проволочными перемычками многокристальный пакет |
US9627367B2 (en) | 2014-11-21 | 2017-04-18 | Micron Technology, Inc. | Memory devices with controllers under memory packages and associated systems and methods |
US10276467B2 (en) * | 2016-03-25 | 2019-04-30 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
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WO2017209724A1 (en) | 2016-05-31 | 2017-12-07 | Intel Corporation | Microelectronic device stacks having interior window wirebonding |
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US10083949B2 (en) * | 2016-07-29 | 2018-09-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Using metal-containing layer to reduce carrier shock in package formation |
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US10026681B2 (en) * | 2016-09-21 | 2018-07-17 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
TWM537304U (zh) | 2016-11-14 | 2017-02-21 | Jorjin Tech Inc | 3d多晶片模組封裝結構(三) |
TWM537303U (zh) | 2016-11-14 | 2017-02-21 | Jorjin Tech Inc | 3d多晶片模組封裝結構(二) |
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