TWI702699B - 包含有機中介層之半導體封裝 - Google Patents

包含有機中介層之半導體封裝 Download PDF

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TWI702699B
TWI702699B TW107112200A TW107112200A TWI702699B TW I702699 B TWI702699 B TW I702699B TW 107112200 A TW107112200 A TW 107112200A TW 107112200 A TW107112200 A TW 107112200A TW I702699 B TWI702699 B TW I702699B
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semiconductor
semiconductor chip
barrier layer
semiconductor package
interposer
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TW107112200A
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English (en)
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TW201919177A (zh
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明俊佑
黒柳秋久
金暎阿
金恩實
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南韓商三星電子股份有限公司
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Abstract

一種包含有機中介層之半導體封裝包括：第一半導體晶片及第二半導體晶片，分別具有主動面，所述主動面上配置有連接接墊；有機中介層，配置於所述第一半導體晶片的所述主動面及所述第二半導體晶片的所述主動面上，且包括電性連接至所述連接接墊的配線層；障壁層，配置於所述第一半導體晶片的側表面及所述第二半導體晶片的側表面上；以及包封體，包封所述第一半導體晶片的至少部分及所述第二半導體晶片的至少部分。

Description

包含有機中介層之半導體封裝
本申請案主張2017年11月3日在韓國智慧財產局中申請的韓國專利申請案第10-2017-0146194號的優先權的權益，所述申請案的揭露內容以全文引用的方式併入本文中。
本揭露是有關於一種包含有機中介層之半導體封裝。
隨著高頻寬記憶體(high bandwidth memory，HBM)的設定及使用的規範的改善，中介層市場已成長壯大。當前，已主要使用矽作為中介層的材料，但已對玻璃或有機中介層進行開發以增大面積並降低成本。
可藉由執行將例如半導體晶片等晶粒貼合至中介層且對所述晶粒進行模製或包封的封裝製程來製造中介層封裝。此處，當不執行模製製程時，不進行2.5維(2.5 dimension，2.5D)封裝處理，因而使得中介層封裝可能無法連接至球柵陣列(ball grid array，BGA)基板等。因此，藉由所述模製來維持中介層封裝的剛性。然而，當執行模製製程時，中介層封裝可能發生翹曲， 且由於中介層的熱膨脹係數(coefficient of thermal expansion，CTE)與晶粒的包封體的熱膨脹係數之間的失配，晶粒與包封體之間可能發生裂縫。
本揭露的態樣可提供一種能夠藉由在包封體與半導體晶片之間形成應力障壁層來提高可靠性的包含有機中介層之半導體封裝。
根據本揭露的態樣，可提供一種在包封體與半導體晶片之間形成有障壁層的包含有機中介層之半導體封裝。
根據本揭露的態樣，一種半導體封裝可包括：第一半導體晶片及第二半導體晶片，分別具有主動面，所述主動面上配置有連接接墊；有機中介層，配置於所述第一半導體晶片的所述主動面及所述第二半導體晶片的所述主動面上，且包括電性連接至所述連接接墊的配線層；障壁層，配置於所述第一半導體晶片的側表面及所述第二半導體晶片的側表面上；以及包封體，包封所述第一半導體晶片的至少部分及所述第二半導體晶片的至少部分。
100A、100B、100C、2310、2320:半導體封裝
111、112、112a、113:半導體晶片
111B、112B、113B:低熔點金屬
111P、112P、113P:連接接墊
115:連接構件
120、2230:中介層
121:絕緣層
122:配線層
123:通孔
130:鈍化層
140:凸塊下金屬層
150:電性連接結構
160、160a、160b:障壁層
170:底部填充樹脂
180:包封體
210:載體
211:核心層
212、213:金屬層
220:樹脂層
1000:電子裝置
1010、2110:主板
1020:晶片相關組件
1030:網路相關組件
1040:其他組件
1050、1130:照相機模組
1060:天線
1070:顯示器裝置
1080:電池
1090:訊號線
1100:智慧型電話
1101:本體
1110:母板
1120:電子組件
1121:中介層封裝
2210:球柵陣列基板
2220:圖形處理單元
2240:高頻寬記憶體
2250:矽中介層
2260:中介層
P:表面處理層
為讓本揭露的上述及其他樣態、特徵及優點更明顯易懂，配合所附圖式作詳細說明如下：
圖1為示出電子裝置系統的實例的方塊示意圖。
圖2為示出電子裝置的實例的立體示意圖。
圖3為示出三維(three-dimensional，3D)球柵陣列(BGA)封裝安裝於電子裝置的主板上的情形的剖面示意圖。
圖4為示出2.5維矽中介層封裝安裝於主板上的情形的剖面示意圖。
圖5為示出2.5維有機中介層封裝安裝於主板上的情形的剖面示意圖。
圖6為示出包含有機中介層之半導體封裝的實例的剖面示意圖。
圖7A至圖7D為示出形成圖6的包含有機中介層之半導體封裝的製程的實例的示意圖。
圖8為示出包含有機中介層之半導體封裝的另一實例的剖面示意圖。
圖9為示出包含有機中介層之半導體封裝的另一實例的剖面示意圖。
在下文中，將參照所附圖式闡述本揭露中的各例示性實施例。在所附圖式中，為清晰起見，可誇大或縮小各組件的形狀、大小等。
在本文中，下側、下部分、下表面等是用來指代相對於 圖式的橫截面的朝向扇出型半導體封裝之安裝表面的方向，而上側、上部分、上表面等是用來指代與所述方向相反的方向。然而，定義這些方向是為了方便闡釋，且本申請專利範圍並不受如上所述所定義的方向特別限制。
在說明中，組件與另一組件的「連接」的意義包括經由黏合層的間接連接以及在兩個組件之間的直接連接。另外，「電性連接」在概念上包括物理連接及物理斷接(disconnection)。應理解，當以例如「第一」及「第二」等用語來指代元件時，所述元件並不因此受到限制。使用「第一」及「第二」可能僅用於將所述元件與其他元件區分開的目的，並不限制所述元件的順序或重要性。在一些情形中，在不背離本文中所提出的申請專利範圍的範圍的條件下，第一元件可被稱作第二元件。相似地，第二元件亦可被稱作第一元件。
本文中所使用的用語「示例性實施例」並非指稱同一示例性實施例，而是為強調與另一示例性實施例的特定特徵或特性不同的特定特徵或特性而提供。然而，本文中所提供的示例性實施例被視為能夠藉由彼此整體組合或部分組合而實作。舉例而言，即使並未在另一示例性實施例中闡述在特定示例性實施例中闡述的一個元件，除非在另一示例性實施例中提供了相反或矛盾的說明，否則所述元件亦可被理解為與另一示例性實施例相關的說明。
使用本文中所使用的用語僅為了闡述示例性實施例而 非限制本揭露。在此種情形中，除非在上下文中另有解釋，否則單數形式包括複數形式。
電子裝置
圖1為示出電子裝置系統的實例的方塊示意圖。
參照圖1，電子裝置1000中可容置主板1010。主板1010可包括物理連接或電性連接至主板1010的晶片相關組件1020、網路相關組件1030、其他組件1040等。這些組件可連接至以下將闡述的其他組件以形成各種訊號線1090。
晶片相關組件1020可包括：記憶體晶片，例如揮發性記憶體(例如動態隨機存取記憶體(dynamic random access memory，DRAM))、非揮發性記憶體(例如唯讀記憶體(read only memory，ROM))、快閃記憶體等；應用處理器晶片，例如中央處理器(例如：中央處理單元(central processing unit，CPU))、圖形處理器(例如：圖形處理單元(graphics processing unit，GPU))、數位訊號處理器、密碼處理器(cryptographic processor)、微處理器、微控制器等；以及邏輯晶片，例如類比至數位轉換器(analog-to-digital converter，ADC)、應用專用積體電路(application-specific integrated circuit，ASIC)等。然而，晶片相關組件1020並非僅限於此，而是亦可包括其他類型的晶片相關組件。另外，晶片相關組件1020可彼此組合。
網路相關組件1030可包括例如以下協定：無線保真(wireless fidelity，Wi-Fi)(電氣及電子工程師學會(Institute of Electrical And Electronics Engineers，IEEE)802.11家族等)、全球互通微波存取(worldwide interoperability for microwave access，WiMAX)(IEEE 802.16家族等)、IEEE 802.20、長期演進(long term evolution，LTE)、僅支援資料的演進(evolution data only，Ev-DO)、高速封包存取+(high speed packet access +，HSPA+)、高速下行封包存取+(high speed downlink packet access +，HSDPA+)、高速上行封包存取+(high speed uplink packet access +，HSUPA+)、增強型資料GSM環境(enhanced data GSM environment，EDGE)、全球行動通訊系統(global system for mobile communications，GSM)、全球定位系統(global positioning system，GPS)、通用封包無線電服務(general packet radio service，GPRS)、分碼多重存取(code division multiple access，CDMA)、分時多重存取(time division multiple access，TDMA)、數位增強型無線電訊(digital enhanced cordless telecommunications，DECT)、藍芽、3G協定、4G協定及5G協定以及繼上述協定之後指定的任何其他無線協定及有線協定。然而，網路相關組件1030並非僅限於此，而是亦可包括多種其他無線標準或協定或者有線標準或協定。另外，網路相關組件1030可與上文所描述的晶片相關組件1020一起彼此組合。
其他組件1040可包括高頻電感器、鐵氧體電感器(ferrite inductor)、功率電感器(power inductor)、鐵氧體珠粒(ferrite beads)、低溫共燒陶瓷(low temperature co-fired ceramic，LTCC)、 電磁干擾(electromagnetic interference，EMI)濾波器、多層陶瓷電容器(multilayer ceramic capacitor，MLCC)等。然而，其他組件1040並非僅限於此，而是亦可包括用於各種其他目的的被動組件等。另外，其他組件1040可與上文所闡述的晶片相關組件1020或網路相關組件1030一起彼此組合。
視電子裝置1000的類型，電子裝置1000可包括可物理連接至或電性連接至主板1010的其他組件，或可不物理連接至或不電性連接至主板1010的其他組件。這些其他組件可包括例如照相機模組1050、天線1060、顯示器裝置1070、電池1080、音訊編解碼器(圖中未示出)、視訊編解碼器(圖中未示出)、功率放大器(圖中未示出)、羅盤(圖中未示出)、加速度計(圖中未示出)、陀螺儀(圖中未示出)、揚聲器(圖中未示出)、大容量儲存單元(例如硬碟驅動機)(圖中未示出)、光碟(compact disk，CD)驅動機(圖中未示出)、數位多功能光碟(digital versatile disk，DVD)驅動機(圖中未示出)等。然而，這些其他組件並非僅限於此，而是視電子裝置1000的類型等亦可包括各種用途的其他組件。
電子裝置1000可為智慧型電話、個人數位助理(personal digital assistant，PDA)、數位攝影機、數位照相機(digital still camera)、網路系統、電腦、監視器、平板個人電腦(tablet PC)、筆記型個人電腦、隨身型易網機個人電腦(netbook PC)、電視、視訊遊戲機(video game machine)、智慧型手錶或汽車組件等。 然而，電子裝置1000並非僅限於此，而是亦可為處理資料的任何其他電子裝置。
圖2為說明電子裝置的一實例的立體示意圖。
參照圖2，半導體封裝可於上文所述的各種電子裝置1000中用於各種目的。舉例而言，母板1110可容置於智慧型電話1100的本體1101中，且各種電子組件1120可物理連接至或電性連接至母板1110。另外，可物理連接至或電性連接至母板1110或可不物理連接至或不電性連接至母板1110的其他組件(例如照相機模組1130)可容置於本體1101中。電子組件1120中的一些電子組件可為晶片相關組件，且晶片相關組件中的一些晶片相關組件可為中介層封裝1121。所述電子裝置不必僅限於智慧型電話1100，而是可為如上所述的其他電子裝置。
包含有機中介層之半導體封裝
一般而言，半導體晶片中整合了諸多精密的電路。然而，半導體晶片自身不能充當半導體成品，此乃因半導體晶片可能因外部物理性或化學性影響而受損。因此，半導體晶片一般不以被暴露形式來使用，而是封裝於電子裝置等中且在電子裝置等中以封裝狀態使用。
由於半導體晶片與電子裝置的主板之間存在電性連接方面的電路寬度差異，因此亦使用半導體封裝。詳言之，半導體晶片的連接接墊的大小及半導體晶片的連接接墊之間的間隔極為精密，但電子裝置中所使用的主板的組件安裝接墊的大小及主板 的組件安裝接墊之間的間隔顯著大於半導體晶片的連接接墊的大小及間隔。因此，可能難以將半導體晶片直接安裝於主板上，而需要用於緩衝半導體與主板之間的電路寬度差異的封裝技術。
以下將參照圖式更詳細地闡述藉由上述封裝技術而製造的包含有機中介層之半導體封裝。
圖3為示出三維球柵陣列(BGA)封裝安裝於電子裝置的主板上的情形的剖面示意圖。
在半導體晶片中，例如圖形處理單元(GPU)等應用專用積體電路(ASIC)非常昂貴，且因此以高的良率對應用專用積體電路執行封裝非常重要。為此，在安裝半導體晶片之前，製備可對數千至數十萬個連接接墊進行重佈線的球柵陣列(BGA)基板2210等，且藉由表面安裝技術(surface mounting technology，SMT)等將例如圖形處理單元2220等昂貴的半導體晶片安裝並封裝於球柵陣列基板2210上，並然後最終安裝於主板2110上。
同時，在圖形處理單元2220的情形中，需要顯著縮短圖形處理單元2220與例如高頻寬記憶體(HBM)等記憶體之間的訊號通路。為此，以疊層封裝(package-on-package，POP)形式來使用將例如高頻寬記憶體2240等半導體晶片安裝於中介層2230上並然後封裝於中介層2230上且接著堆疊於其中安裝有圖形處理單元2220的封裝上的產品。然而，在此種情形中，裝置的厚度過度增加，且在顯著縮短訊號通路方面存在限制。
圖4為示出2.5維矽中介層封裝安裝於主板上的情形的 剖面示意圖。
作為解決上述問題的方法，可慮及藉由2.5維中介層表面安裝技術並接著將例如圖形處理單元2220等第一半導體晶片與例如高頻寬記憶體2240等第二半導體晶片彼此並排地封裝於矽中介層2250上來製造包含矽中介層之半導體封裝2310。在此種情形中，具有數千至數十萬個連接接墊的圖形處理單元2220及高頻寬記憶體2240可藉由矽中介層2250來進行重佈線，且可經由最短的通路電性連接至彼此。另外，當包含矽中介層之半導體封裝2310又安裝於球柵陣列基板2210等上並在球柵陣列基板2210等上進行重佈線時，包含矽中介層之半導體封裝2310可最終安裝於主板2110上。然而，很難在矽中介層2250中形成矽穿孔(through-silicon via，TSV)，且用於製造矽中介層2250所需要的成本顯著地高，且因此矽中介層2250不利於增大面積並降低成本。
圖5為示出2.5維有機中介層封裝安裝於主板上的情形的剖面示意圖。
作為解決上述問題的方法，可慮及使用有機中介層2260來代替矽中介層2250。舉例而言，可慮及藉由2.5維中介層表面安裝技術並接著將例如圖形處理單元2220等第一半導體晶片與例如高頻寬記憶體2240等第二半導體晶片彼此並排地封裝於有機中介層2260上來製造包含有機中介層之半導體封裝2320。在此種情形中，具有數千至數十萬個連接接墊的圖形處理單元2220及高頻寬記憶體2240可藉由有機中介層2260來進行重佈線，且可經由 最短的通路電性連接至彼此。另外，當包含有機中介層之半導體封裝2320又安裝於球柵陣列基板2210等上並在球柵陣列基板2210等上進行重佈線時，包含有機中介層之半導體封裝2320可最終安裝於主板2110上。另外，有機中介層可有利於增大面積並降低成本。
可藉由執行將晶片(圖形處理單元2220及高頻寬記憶體2240)安裝於有機中介層2260上且接著對所述晶片進行模製或包封的封裝製程來製造包含有機中介層之半導體封裝2320。此處，當不執行模製製程時，不進行封裝處理，因而使得所述封裝可能無法連接至球柵陣列基板2210等。因此，藉由所述模製來維持所述封裝的剛性。然而，當執行模製製程時，所述封裝可能發生翹曲，底部填充樹脂的可填充性可劣化，且由於中介層2260的熱膨脹係數(CTE)與晶片(圖形處理單元2220及高頻寬記憶體2240)的包封體的熱膨脹係數之間的失配，半導體晶片與包封體之間可能發生裂縫，如上所述。
圖6為示出包含有機中介層之半導體封裝的實例的剖面示意圖。
參照圖6，根據本揭露中的示例性實施例的包含有機中介層之半導體封裝100A可包括：半導體晶片111、112及113，分別具有主動面，所述主動面上配置有連接接墊111P、112P及113P；中介層120，配置於半導體晶片111、112及113的主動面上，且包括電性連接至相應連接接墊111P、112P及113P的配線 層122；障壁層160，配置於半導體晶片111、112及113的側表面上；底部填充樹脂170，將半導體晶片111、112及113固定至中介層120上；以及包封體180，包封半導體晶片111、112及113的至少部分。包含有機中介層之半導體封裝100A可更包括：鈍化層130，配置於中介層120的另一表面上；凸塊下金屬層140，形成於鈍化層130的開口中且電性連接至中介層120的配線層122；以及電性連接結構150，配置於凸塊下金屬層140上且藉由凸塊下金屬層140電性連接至中介層120的配線層122。
作為應力障壁層的障壁層160可配置於半導體晶片111、112及113與包封體180之間。障壁層160可由熱膨脹係數大於半導體晶片111、112及113的熱膨脹係數且小於包封體180的熱膨脹係數的材料形成。因此，障壁層160可減小半導體晶片111、112及113的熱膨脹係數與包封體180的熱膨脹係數之間的差異，從而減小應力並防止出現例如翹曲或邊界的裂縫等缺陷。障壁層160亦可由可改善半導體晶片111、112及113與包封體180之間的黏合的材料形成。此外在此種情形中，障壁層160可防止出現例如邊界的裂縫等缺陷。在根據示例性實施例的包含有機中介層之半導體封裝100A中，障壁層160可在相鄰的半導體晶片111、112及113之間沿底部填充樹脂170的側表面延伸，且亦延伸至中介層120上。因此，障壁層160可被配置成障壁層160在相鄰的半導體晶片111、112及113之間直接連接至彼此的形式。另外，可藉由研磨自半導體晶片111、112及113的上表面移除構 成包封體180的材料，以確保散熱特性，因而使得半導體晶片111、112及113的上表面可被暴露至外部，且障壁層160亦可暴露於相同的水平高度上。
以下將更詳細地闡述根據示例性實施例的包含有機中介層之半導體封裝100A中所包括的各個組件。
半導體晶片111、112及113可為將數百至數百萬個或更多數量的元件整合於單一晶片中的積體電路(integrated circuit，IC)。在此種情形中，半導體晶片中的每一者的本體的基材(base material)可為矽(Si)、鍺(Ge)、砷化鎵(GaAs)等。在本體中的每一者上可形成各種電路。半導體晶片111、112及113的連接接墊111P、112P及113P可將半導體晶片111、112及113電性連接至其他組件。連接接墊111P、112P及113P中的每一者的材料可為例如鋁(Al)等導電材料。可在本體中的每一者上形成暴露出連接接墊111P、112P及113P的鈍化層，且所述鈍化層可為氧化物膜、氮化物膜等或氧化物層與氮化物層所構成的雙層。亦可在其他需要的位置進一步配置絕緣層等。可在半導體晶片111、112及113的主動面上進一步形成重佈線層，且低熔點金屬111B、112B及113B亦可分別連接至連接接墊111P、112P及113P。低熔點金屬111B、112B及113B可為熔點低於連接接墊111P、112P及113P的熔點的金屬，例如焊料或其合金。半導體晶片111、112及113可藉由連接接墊111P、112P及113P及/或低熔點金屬111B、112B及113B連接至中介層120的被暴露的上部配 線層122，且例如焊料等連接構件115可用於將半導體晶片111、112及113連接至被暴露的上部配線層122。可藉由任何已知的底部填充樹脂170將相應半導體晶片111、112及113固定至中介層120上。
第二半導體晶片112可為例如圖形處理單元等應用轉用積體電路。第一半導體晶片111及第三半導體晶片113可為例如高頻寬記憶體等記憶體。亦即，半導體晶片111、112及113中的每一者可為具有數十萬或更多個輸入/輸出(input/output，I/O)的昂貴晶片，但並非僅限於此。舉例而言，作為高頻寬記憶體等的第一半導體晶片111及第三半導體晶片113可與作為例如圖形處理單元等應用專用積體電路的第二半導體晶片112分別並排地配置於第二半導體晶片112的兩側處。
中介層120可對半導體晶片111、112及113的連接接墊111P、112P及113P進行重佈線。半導體晶片111、112及113的具有各種功能的數十至數百個連接接墊111P、112P及113P可藉由中介層120進行重佈線，且可視所述功能而藉由電性連接結構150物理連接或電性連接至外部。中介層120可包括：絕緣層121；配線層122，形成於絕緣層121上或絕緣層121中；以及通孔123，穿透過絕緣層121且將形成於不同層上的配線層122電性連接至彼此。中介層120的層的數目可多於圖式中所示的數目或少於圖式中所示的數目。具有此種形式的中介層120可用作2.5維型有機中介層。
舉例而言，可使用絕緣材料作為絕緣層121中的每一者的材料。在此種情形中，可使用以下材料作為絕緣材料：熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺樹脂；其中將熱固性樹脂及熱塑性樹脂與無機填料混合的樹脂，例如味之素構成膜(Ajinomoto build-up film，ABF)等。或者，可使用例如感光成像介電(photoimagable dielectric，PID)樹脂等感光性絕緣材料作為絕緣材料。亦即，絕緣層121中的每一者可為感光性絕緣層。當絕緣層121具有感光性質時，絕緣層121可被形成為具有較小的厚度，且可更容易地達成通孔123的精細節距。當絕緣層121為多層時，絕緣層121的材料可為彼此相同，且亦可為彼此不同。當絕緣層121為多層時，絕緣層121可視製程而彼此整合於一起，進而使得各絕緣層之間的邊界亦可為不明顯。
配線層122可用於對連接接墊111P、112P及113P實質上進行重佈線。配線層122中的每一者的材料可為導電材料，例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金。配線層122可視對應層的設計而執行各種功能。舉例而言，配線層122可包括接地(GND)圖案、電源(PWR)圖案、訊號(S)圖案等。此處，訊號(S)圖案可包括除了接地(GND)圖案、電源(PWR)圖案等之外的各種訊號圖案，例如資料訊號圖案等。另外，配線層122可包括通孔接墊、連接端子接墊等。可在配線層122中充當用於安裝半導體晶片111、112及113的接墊的最上配線層122的表面上形成表面處 理層P。表面處理層P不受特別限制，只要在相關技術中為已知即可，但表面處理層P可藉由例如電鍍金、無電鍍金、有機可焊性保護劑(organic solderability preservative，OSP)或無電鍍錫、無電鍍銀、無電鍍鎳/置換鍍金、直接浸金(direct immersion gold，DIG)鍍覆、熱空氣焊料均塗(hot air solder leveling，HASL)等而形成，但並非僅限於此。
通孔123可將形成於不同層上的配線層122等電性連接至彼此，從而在包含有機中介層之半導體封裝100A中形成電性通路。通孔123中的每一者的材料可為導電材料，例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金。通孔123可利用導電材料完全填充，但並非僅限於此。通孔123中的每一者的橫截面形狀可為圖式中的近似倒梯形形狀。
鈍化層130可保護中介層120免受外部物理性或化學性損傷。鈍化層130的材料不受特別限制。舉例而言，可使用絕緣材料作為鈍化層130的材料。在此種情形中，所述絕緣材料可為被闡述為上述中介層120的絕緣層121的絕緣材料的材料，例如味之素構成膜。
凸塊下金屬層140可提高電性連接結構150的連接可靠性，以提高包含有機中介層之半導體封裝100A的板級可靠性。凸塊下金屬層140可形成於鈍化層130的開口中，且可電性連接至中介層120的配線層122。可藉由任何已知的金屬化方法來形成凸塊下金屬層140。亦即，凸塊下金屬層140可包含任何已知的金 屬，例如銅(Cu)。
電性連接結構150可將包含有機中介層之半導體封裝100A物理連接或電性連接至外部。舉例而言，包含有機中介層之半導體封裝100A可藉由電性連接結構150安裝於電子裝置的主板上。電性連接結構150中的每一者可由導電材料(例如焊料等)形成。然而，此僅為實例，且電性連接結構150中的每一者的材料並非特別受限於此。電性連接結構150中的每一者可為接腳、球、引腳等。電性連接結構150可形成為多層結構或單層結構。當電性連接結構150形成為多層結構時，電性連接結構150可包含銅(Cu)柱及焊料。當電性連接結構150形成為單層結構時，電性連接結構150可包含錫-銀焊料或銅(Cu)。然而，此僅為實例，且電性連接結構150並非僅限於此。
電性連接結構150的數量、間隔、配置形式等不受特別限制，而是可由熟習此項技術者端視設計特定細節而進行充分地修改。舉例而言，電性連接結構150可根據連接接墊111P、112P及113P的數目而設置為數十至數千的數量，或可設置為數十至數千或更多的數量或是數十至數千或更少的數量。電性連接結構150中的一些電性連接結構可配置在扇出區域中。所述扇出區域指代除配置有半導體晶片111、112及113的區域之外的區域。亦即，根據示例性實施例的包含有機中介層之半導體封裝100A可為扇出型半導體裝置。扇出型封裝相較於扇入型封裝而言可具有優異的可靠性，可實施多個輸入/輸出(I/O)端子，且可有利於三維內 連。另外，相較於球柵陣列(BGA)封裝、接腳柵陣列(land grid array，LGA)封裝等而言，扇出型封裝可被製造成具有小的厚度，且可具有價格競爭力。
障壁層160可配置於半導體晶片111、112及113的側表面上，且可配置於半導體晶片111、112及113與包封體180之間。半導體晶片111、112及113不直接接觸包封體180，而是可藉由障壁層160與包封體180間隔開。障壁層160可沿底部填充樹脂170的側表面延伸，且可在底部填充樹脂170的側表面上被配置成相對於中介層120的上表面傾斜。障壁層160可被配置成障壁層160在相鄰的半導體晶片111、112及113之間直接連接至彼此且在中介層120的上表面上直接連接至彼此的形式，但並非僅限於此。另外，半導體晶片111、112及113的上表面可被暴露至外部以確保散熱特性，且障壁層160亦可被暴露於相同的水平高度上。障壁層160的上表面可配置於與半導體晶片111、112及113的上表面的水平高度相同的水平高度上。障壁層160的厚度並非僅限於圖式中所示的厚度。
障壁層160可由可減少半導體晶片111、112及113的熱膨脹係數與包封體180的熱膨脹係數之間的失配的材料形成。障壁層160可由熱膨脹係數大於半導體晶片111、112及113的熱膨脹係數且小於包封體180的熱膨脹係數的材料形成。舉例而言，構成障壁層160的材料的熱膨脹係數可處於3ppm/K至30ppm/K的範圍內。障壁層160可由絕緣材料(例如，與絕緣層121或鈍 化層130的材料相同的材料)形成，但並非僅限於此。
底部填充樹脂170可將半導體晶片111、112及113固定至中介層120上。可使用包括環氧樹脂等在內的任何已知的材料作為底部填充樹脂170的材料。底部填充樹脂170可被省略。儘管圖式中未示出，然而被動組件亦可與半導體晶片111、112及113並排地配置並封裝於中介層120上。
包封體180可保護半導體晶片111、112及113等。包封體180的包封形式不受特別限制，但可為包封體180環繞半導體晶片111、112及113的至少部分的形式。包封體180的材料不受特別限制。舉例而言，可使用絕緣材料作為包封體180的材料。在此種情形中，可使用以下材料作為絕緣材料：熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺樹脂；其中將熱固性樹脂及熱塑性樹脂與無機填料混合的樹脂，例如味之素構成膜等。然而，包封體180的材料並非僅限於此，而是亦可為包含玻璃纖維的預浸體等。或者，亦可使用任何已知的環氧模製化合物(epoxy molding compound，EMC)等作為包封體180的材料。
圖7A至圖7D為示出形成圖6的包含有機中介層之半導體封裝的製程的實例的示意圖。
參照圖7A，可製備載體210，且可在載體210上形成中介層120。
載體210可包括核心層211以及形成於核心層211上的金屬層212及213。核心層211可由例如包含絕緣樹脂、無機填料 及玻璃纖維的預浸體形成。金屬層212及213可包含例如銅(Cu)、鈦(Ti)等金屬。可在金屬層212與金屬層213之間執行表面處理以使得金屬層212與金屬層213容易地彼此分離開。或者，可在金屬層212與金屬層213之間提供脫模層。載體210可為一般分離核心。亦可在載體210上形成樹脂層220。樹脂層220可用於使載體210與所製造的包含有機中介層之半導體封裝100A之間電性絕緣。亦即，樹脂層220可用於在對中介層120的配線層122執行電性測試時使所製造的包含有機中介層之半導體封裝100A與載體210之間絕緣。可藉由積層膜形式或施用並硬化液相形式來形成樹脂層220。樹脂層220亦可被省略。
可藉由以下方式來形成中介層120：在樹脂層220上形成晶種層，使用乾膜等形成圖案，藉由鍍覆製程填充圖案以形成配線層122，在配線層122上或向配線層122積層或施用感光成像介電質等以形成絕緣層121，在絕緣層121中形成通孔孔洞，且藉由鍍覆製程等填充通孔孔洞以形成通孔123。鍍覆製程可為減成製程(subtractive process)、加成製程(additive process)、半加成製程(semi-additive process，SAP)、經修改半加成製程(modified semi-additive process，MSAP)等，但並非僅限於此。
然後，可在最上配線層122上形成表面處理層P等。另外，可執行四路測試(quad route test)、配線層122的電性測試等。
參照圖7B，可在中介層120上安裝半導體晶片111、112及113。可使用例如焊料等連接構件115將半導體晶片111、112 及113安裝於中介層120上。然後，可藉由底部填充樹脂170來固定半導體晶片111、112及113。
參照圖7C，可形成覆蓋半導體晶片111、112及113的障壁層160。可藉由例如化學氣相沈積(chemical vapor deposition，CVD)、濺鍍、塗佈等製程來形成障壁層160。障壁層160可覆蓋半導體晶片111、112及113的側表面及上表面，且延伸至底部填充樹脂170的側表面以在相鄰的半導體晶片111、112及113之間連接至彼此。障壁層160可在相鄰的半導體晶片111、112及113之間接觸中介層120的上表面，但並非僅限於此。
參照圖7D，可在中介層120上形成包封半導體晶片111、112及113的包封體180。可藉由積層膜形式或施用或硬化液相形式來形成包封體180。
然後，一起參照圖7D及圖6，可研磨包封體180。可藉由所述研磨在相同的水平高度上配置半導體晶片111、112及113的上表面。亦即，半導體晶片111、112及113的厚度可變為實質上彼此相同。另外，半導體晶片111、112及113的上表面以及障壁層160的上表面可被暴露至外部。
然後，可對載體210進行分離。可藉由使金屬層212與金屬層213彼此分離開來分離載體210。在此種情形中，可藉由蝕刻製程來移除金屬層213。在對載體210進行分離之後，可藉由研磨等來移除樹脂層220。然而，當樹脂層220被省略時，亦可省略研磨。然後，可藉由雷射鑽孔在鈍化層130中形成開口。在形成 開口之後，可執行去鑽污製程、形成凸塊下金屬層140的製程、對電性連接結構150進行貼合的製程及回焊(reflow)製程。可藉由一系列製程來製造根據上述示例性實施例的包含有機中介層之半導體封裝100A。
圖8為示出包含有機中介層之半導體封裝的另一實例的剖面示意圖。
參照圖8，在根據本揭露中的另一示例性實施例的包含有機中介層之半導體封裝100B中，可僅在半導體晶片111、112及113的側表面上配置障壁層160a。亦即，障壁層160a不延伸至底部填充樹脂170的側表面。因此，障壁層160a的下表面可配置於與半導體晶片111、112及113的下表面的水平高度相同的水平高度上。另外，障壁層160a可由導電材料以及絕緣材料形成。可藉由以下方式來製造障壁層160a：在安裝半導體晶片111、112及113之前在半導體晶片111、112及113的上表面及側表面上形成障壁層160a，且接著在以上參照圖7B闡述的製程中安裝半導體晶片111、112及113。
其他配置(例如參照圖6至圖7D闡述的內容)可應用於根據另一示例性實施例的包含有機中介層之半導體封裝100B，且因此不再對與上述重疊的其他配置予以贅述。
圖9為示出包含有機中介層之半導體封裝的另一實例的剖面示意圖。
參照圖9，在根據本揭露中的另一示例性實施例的包含 有機中介層之半導體封裝100C中，半導體晶片111、112a及113的厚度可彼此不同。如圖9所示，第二半導體晶片112a的厚度可小於第一半導體晶片111的厚度及第三半導體晶片113的厚度，且第二半導體晶片112a的上表面因此可被包封體180包封。另外，障壁層160b可覆蓋第一半導體晶片111的側表面及第三半導體晶片113的側表面以及第二半導體晶片112a的側表面及上表面。亦即，第一半導體晶片111的上表面及第三半導體晶片113的上表面可被暴露至外部，而第二半導體晶片112a的上表面可被障壁層160b及包封體180覆蓋。當半導體晶片111、112a及113的厚度如上所述彼此不同時，障壁層160b可進一步配置於具有較小厚度的第二半導體晶片112a的上表面上。因此，相較於第二半導體晶片112a的上表面僅被包封體180覆蓋的情形可減少熱膨脹係數之間的失配，因而使得翹曲特性可進一步得到改善。
其他配置(例如參照圖6至圖7D闡述的內容)可應用於根據另一示例性實施例的包含有機中介層之半導體封裝100C，且因此不再對與上述重疊的其他配置予以贅述。
如上所述，根據本揭露中的示例性實施例，可提供一種能夠藉由在包封體與半導體晶片之間形成應力障壁層來提高可靠性的包含有機中介層之半導體封裝。
儘管以上已示出並闡述了示例性實施例，然而對於熟習此項技術者而言將顯而易見的是，在不背離由隨附申請專利範圍所界定的本發明的範圍的條件下，可作出修改及變型。
100A‧‧‧半導體封裝
111、112、113‧‧‧半導體晶片
111B、112B、113B‧‧‧低熔點金屬
111P、112P、113P‧‧‧連接接墊
115‧‧‧連接構件
120‧‧‧中介層
121‧‧‧絕緣層
122‧‧‧配線層
123‧‧‧通孔
130‧‧‧鈍化層
140‧‧‧凸塊下金屬層
150‧‧‧電性連接結構
160‧‧‧障壁層
170‧‧‧底部填充樹脂
180‧‧‧包封體
P‧‧‧表面處理層

Claims (17)

  1. 一種半導體封裝，包括：第一半導體晶片及第二半導體晶片，分別具有主動面，所述主動面上配置有連接接墊；有機中介層，配置於所述第一半導體晶片的所述主動面及所述第二半導體晶片的所述主動面上，且包括電性連接至所述連接接墊的配線層；障壁層，配置於所述第一半導體晶片的側表面及所述第二半導體晶片的側表面上；以及包封體，包封所述第一半導體晶片的至少部分及所述第二半導體晶片的至少部分，其中所述障壁層是由絕緣材料形成。
  2. 如申請專利範圍第1項所述的半導體封裝，其中所述障壁層是由熱膨脹係數(CTE)高於所述第一半導體晶片的熱膨脹係數及所述第二半導體晶片的熱膨脹係數且低於所述包封體的熱膨脹係數的材料形成。
  3. 如申請專利範圍第1項所述的半導體封裝，其中所述障壁層在所述第一半導體晶片與所述第二半導體晶片之間直接連接至彼此。
  4. 如申請專利範圍第3項所述的半導體封裝，其中所述障壁層在所述有機中介層上直接連接至彼此。
  5. 如申請專利範圍第1項所述的半導體封裝，更包括將所 述第一半導體晶片及所述第二半導體晶片固定至所述有機中介層的底部填充樹脂。
  6. 如申請專利範圍第5項所述的半導體封裝，其中所述障壁層延伸至所述底部填充樹脂的側表面。
  7. 如申請專利範圍第1項所述的半導體封裝，其中所述障壁層的上表面被暴露至所述包封體之外。
  8. 如申請專利範圍第7項所述的半導體封裝，其中所述障壁層的上表面配置於與所述第一半導體晶片的上表面及所述第二半導體晶片的上表面的水平高度相同的水平高度上。
  9. 如申請專利範圍第1項所述的半導體封裝，其中所述障壁層的下表面配置於與所述第一半導體晶片的下表面及所述第二半導體晶片的下表面的水平高度相同的水平高度上。
  10. 如申請專利範圍第1項所述的半導體封裝，其中所述第二半導體晶片的厚度小於所述第一半導體晶片的厚度，且所述障壁層覆蓋所述第二半導體晶片的上表面。
  11. 如申請專利範圍第10項所述的半導體封裝，其中所述第一半導體晶片的上表面被暴露至所述包封體之外。
  12. 如申請專利範圍第1項所述的半導體封裝，其中所述第一半導體晶片包括應用專用積體電路(ASIC)，且所述第二半導體晶片包括記憶體。
  13. 如申請專利範圍第1項所述的半導體封裝，其中所述第一半導體晶片包括圖形處理單元(GPU)，且 所述第二半導體晶片包括多個高頻寬記憶體(HBM)。
  14. 如申請專利範圍第1項所述的半導體封裝，其中所述第一半導體晶片與所述第二半導體晶片藉由所述有機中介層電性連接至彼此。
  15. 如申請專利範圍第1項所述的半導體封裝，其中所述障壁層是由改善所述第一半導體晶片及所述第二半導體晶片與所述包封體之間的黏合的材料形成。
  16. 一種半導體封裝，包括：半導體晶片，具有主動面，所述主動面上配置有連接接墊；有機中介層，配置於所述半導體晶片的所述主動面上，且包括電性連接至所述連接接墊的配線層；包封體，包封所述半導體晶片的至少部分；以及障壁層，配置於所述半導體晶片與所述包封體之間，其中所述障壁層是由絕緣材料形成。
  17. 如申請專利範圍第16項所述的半導體封裝，其中所述半導體晶片藉由所述障壁層與所述包封體間隔開以不直接接觸所述包封體。
TW107112200A 2017-11-03 2018-04-10 包含有機中介層之半導體封裝 TWI702699B (zh)

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